{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "bandgap", "name": "Fractional bandgap reference, 0.76 V output", "group": "Mirrors, bias and references", "subgroup": "Voltage references", "title": "Fractional bandgap reference, 0.76 V output", "summary": "Produces about 0.76 V from a 1.2 V supply. It combines a bipolar-derived current that falls with temperature with one that rises, then converts their sum to voltage. Resistor ratios balance the slopes; device errors and curvature leave some temperature drift.", "reference": { "kind": "paper", "authors": "H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi and K. Sakui", "title": "A CMOS bandgap reference circuit with sub-1-V operation", "publisher": "IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 670-674", "year": 1999, "where": "the current-mode bandgap: resistors across the two diodes, their currents summed in a PMOS copy", "takes": "The topology and its result, V_REF = (R3/R1)(V_EB1 + (R1/R0) V_T ln N), which no longer has to be 1.2 V.", "also": [ { "authors": "B. Razavi", "title": "Design of Analog CMOS Integrated Circuits", "edition": "2nd ed.", "year": 2017, "where": "Bandgap References - PTAT and CTAT voltages, the op amp that holds two nodes equal, start-up, and curvature" } ] }, "resources": { "record": "/circuits/bandgap.json", "page": "/index.html#bandgap", "achieved": "/achieved/bandgap.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_hbt_tt.spice", "url": "/sg13g2_hbt_tt.spice", "sha256": "1422d058985b85719ca0c371e119090a4c2a070c9cb01587db35aeee6174f01a" }, { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_hbt_tt.spice", "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "vref", "kind": "output", "note": "the reference voltage; R3 to ground sets its level" }, { "name": "vdd", "kind": "supply" }, { "name": "0", "kind": "ground" } ], "devices": [ { "name": "Q1", "type": "pnp", "sizedBy": [], "role": "the diode whose V_EB falls with temperature: one pnpMPA" }, { "name": "Q2", "type": "pnp", "sizedBy": [ "N" ], "role": "N copies of Q1 at Q1's current: V_T ln N less V_EB" }, { "name": "R0", "type": "resistor", "sizedBy": [ "R0" ], "role": "carries ΔV_EB: the rising current" }, { "name": "R1", "type": "resistor", "sizedBy": [ "R1" ], "role": "across Q1: V_EB1/R1, the falling current" }, { "name": "R2", "type": "resistor", "sizedBy": [ "R1" ], "role": "across Q2 and R0, equal to R1" }, { "name": "R3", "type": "resistor", "sizedBy": [ "R3" ], "role": "turns the summed current into V_REF" }, { "name": "M1", "type": "pmos", "sizedBy": [ "Wp", "Lp" ], "role": "feeds Q1 and R1", "fingers": 4, "copies": 1 }, { "name": "M2", "type": "pmos", "sizedBy": [ "Wp", "Lp" ], "role": "feeds Q2, R0 and R2", "fingers": 4, "copies": 1 }, { "name": "M3", "type": "pmos", "sizedBy": [ "Wp", "Lp" ], "role": "the output copy, into R3", "fingers": 4, "copies": 1 }, { "name": "M5", "type": "pmos", "sizedBy": [ "Wp", "Lp" ], "role": "a fourth copy, biasing the amplifier", "fingers": 4, "copies": 1 }, { "name": "MN", "type": "nmos", "sizedBy": [ "Wn", "Ln" ], "role": "the amplifier's bias diode", "fingers": 1, "copies": 1 }, { "name": "MT", "type": "nmos", "sizedBy": [ "Wn", "Ln" ], "role": "the amplifier's tail, two copies of MN", "fingers": 1, "copies": 2 }, { "name": "MA1", "type": "nmos", "sizedBy": [ "Wn", "Ln" ], "role": "non-inverting input, on vb", "fingers": 1, "copies": 1 }, { "name": "MA2", "type": "nmos", "sizedBy": [ "Wn", "Ln" ], "role": "inverting input, on va", "fingers": 1, "copies": 1 }, { "name": "MA3", "type": "pmos", "sizedBy": [ "Wp", "Lp" ], "role": "the amplifier's load, diode side", "fingers": 4, "copies": 1 }, { "name": "MA4", "type": "pmos", "sizedBy": [ "Wp", "Lp" ], "role": "the amplifier's load, driving the PMOS gates", "fingers": 4, "copies": 1 }, { "name": "CC", "type": "capacitor", "sizedBy": [ "Cc" ], "role": "the dominant pole, on the PMOS gates" }, { "name": "MS1", "type": "nmos", "sizedBy": [ "startup" ], "role": "start-up: pulls the PMOS gates down until the reference runs", "fingers": 1, "copies": 1 }, { "name": "MS2", "type": "nmos", "sizedBy": [ "startup" ], "role": "start-up: watches V_REF and takes MS1's gate away", "fingers": 1, "copies": 1 }, { "name": "MS3", "type": "pmos", "sizedBy": [ "startup" ], "role": "start-up: a weak pull-up on MS1's gate", "fingers": 1, "copies": 1 } ], "intent": [ { "rule": "ptat-plus-ctat", "of": [ "Q1", "Q2", "R0", "R1", "R2" ], "constraint": "I = V_EB1/R1 + ΔV_EB/R0, with R1/R0 set for zero slope", "why": "The amplifier holds va at vb, so R1 and R2 carry equal currents and so do Q1 and Q2; Q2, N copies at Q1's current, then needs ΔV_EB = V_T ln N less, which R0 drops. At 27 °C V_EB1 is 756 mV and falls by 1.41 mV/°C; ΔV_EB is 54.9 mV (V_T ln 8 is 53.8 mV: the PNP's ideality factor is 1.015) and rises by 0.183 mV/°C. R1/R0 weighs the two: equal and opposite slopes need 1.41/0.183 = 7.7, and 8.1 is best here (R1 = 220 kΩ, R0 = 27 kΩ), M3's copy error included. V_EB1 + (R1/R0) ΔV_EB is then 1.20 V - the bandgap voltage - and V_REF is R3/R1 of it: 756 mV, within 0.92 mV from -40 to 125 °C (7.3 ppm/°C)." }, { "rule": "ratios-only", "of": [ "R0", "R1", "R2", "R3" ], "constraint": "V_REF = (R3/R1)(V_EB1 + (R1/R0) ΔV_EB)", "why": "Resistor ratios set the first-order weighting and output scale. Using one material - high-resistance poly - improves ratio tracking. Absolute resistance still sets branch current and changes V_EB, so changing the current requires retuning. R1 and R2 must match to keep the bipolar currents equal." }, { "rule": "unit-devices", "of": [ "Q1", "Q2", "M1", "M2", "M3", "M5", "MA3", "MA4" ], "why": "With equal total bipolar currents, an emitter-area ratio N gives ΔV_EB approximately V_T ln N. Q2 uses N copies of Q1; a symmetric unit layout can reduce gradients. The PMOS branches also use repeated units to reduce geometry-dependent error, but random mismatch remains." }, { "rule": "output-level", "of": [ "M3", "R3" ], "constraint": "V_REF ≈ V_EB1", "why": "Equal drain voltages minimize M3's systematic copy error relative to M1; device mismatch remains. R3 = 138 kΩ puts V_REF on va, both 756 mV at 27 °C, and the output moves about 0.02 mV per volt of supply. At R3 = 120 kΩ, V_REF is 659 mV, M3's drain sits 97 mV below M1's, and the output moves -6.8 mV per volt; its temperature coefficient worsens too, from 7.7 to 12.0 ppm/°C." }, { "rule": "input-polarity", "of": [ "MA1", "MA2" ], "constraint": "vb non-inverting, va inverting", "why": "When the PMOS gates move, vb moves more than va: behind vb is R2 across R0 and Q2, behind va only R1 across Q1's small resistance. So vb goes on the non-inverting input. The inputs sit at V_EB1: 0.76 V at 27 °C, 0.85 V at -40 °C. That is inside an NMOS pair's range down to a supply of about 1.1 V at -40 °C; below it MA1 and MA2 run out of drain voltage - see supply-range." }, { "rule": "supply-range", "of": [ "M1", "M2", "M3", "MA1", "MA2" ], "constraint": "V_DD ≥ 1.15 V over -40 to 125 °C", "why": "V_EB1 is highest at -40 °C, 0.85 V, and what sits above va must fit in the rest of the supply. At 1.2 V M1 and M2 have 0.35 V, the amplifier's input pair - its drains a PMOS V_SG below the supply - is saturated with 0.1 V to spare, and V_REF holds 7.3 ppm/°C. At 1.08 V, the supply 10 % low, M1 and M2 have 0.23 V, only 79 mV above their saturation voltage, and MA1 and MA2 enter triode: the loop gain falls from 31 to 24 dB and M3's copy of M1 moves by 0.4 %. V_REF then rises 4.0 mV at -40 °C, and falls 2.6 mV at 125 °C, where M3 nears its own saturation voltage: 56 ppm/°C. Staying under 20 ppm/°C takes 1.15 V at every process corner. A larger PMOS unit buys much of it back - at 64/8 µm, 21 to 24 ppm/°C at 1.08 V and 4.7 at 1.2 V - but for eight times the area, and its gate capacitance then needs C_c near 16 pF to keep 60° of phase margin." }, { "rule": "start-up", "of": [ "MS1", "MS2", "MS3" ], "constraint": "release between the stuck state's V_REF and the running one", "why": "There are two wrong states: no current at all, and one where Q1 and Q2 are all but off, R1 and R2 carry everything, va = vb = I R1 and the amplifier sees nothing to correct. With the start-up circuit out all three are DC solutions at every temperature - at -40 °C the second has va = vb = 0.62 V and V_REF = 0.39 V - and which one a solver lands in depends on where it starts; a supply ramping up from zero stays in the first. So MS2 watches V_REF, and is a weak 0.15/10 µm device against a weaker pull-up, 0.15/20 µm: it trips at 0.47 to 0.55 V from -40 to 125 °C, above those states and below the running 0.76 V. A 0.5/2 µm MS2 would trip at 0.33 V at -40 °C, inside one. MS1's source is V_REF, so once the reference runs MS1 is reverse-biased and leaks femtoamps; with its source on ground it would move V_REF by 13 mV at 125 °C." }, { "rule": "compensation", "of": [ "CC" ], "constraint": "phase margin > 60°", "why": "The loop has one high-impedance node, the PMOS gates, where C_c sets the dominant pole: 72° of phase margin with 29 dB of loop gain at 27 °C, and 68° at -40 °C, measured by breaking the loop at the amplifier's output (Middlebrook's double injection). With 2 pF it is 57° at -40 °C." } ], "specs": [ { "key": "vref", "label": "Reference voltage", "unit": "V", "direction": "target" }, { "key": "tc", "label": "Temperature coefficient", "unit": "ppm/°C", "direction": "min" }, { "key": "line", "label": "Line regulation", "unit": "V/V", "direction": "min" }, { "key": "vmin", "label": "Lowest supply within 0.1 %", "unit": "V", "direction": "min" }, { "key": "tstart", "label": "Start-up time", "unit": "s", "direction": "min" } ], "explanation": { "idea": "Produces about 0.76 V from a 1.2 V supply. It combines a bipolar-derived current that falls with temperature with one that rises, then converts their sum to voltage. Resistor ratios balance the slopes; device errors and curvature leave some temperature drift.", "detail": "A fractional bandgap reference with about 0.76 V output from a 1.2 V supply. An amplifier holds two branches at one voltage: R1 across the PNP Q1 draws V_EB1/R1, which falls with temperature, while Q2, N copies of Q1 at the same current, needs V_T ln N less, and R0 turns that difference into a current that rises. A third PMOS copy sums both into R3: the current-mode topology of 'A CMOS bandgap reference circuit with sub-1-V operation'.", "lesson": { "relation": 2, "symbols": "V_REF is output voltage; I is summed branch current; R0, R1 and R3 set current weighting and output scale; V_EB1 is Q1's emitter-base voltage; V_T = kT/q is thermal voltage; N is Q2's unit-area ratio.", "assumptions": "First-order matched branches with equal bipolar currents and a high-gain amplifier. V_EB1 depends on branch current: keeping resistor ratios fixed does not make the result invariant.", "exercise": { "param": "R1", "value": 231000, "analysis": "temp", "expect": "Increasing R1 and R2 together should tilt the temperature curve upward relative to the default: the falling-temperature current receives less weight." }, "limits": "The default output is about 0.76 V, not a sub-1 V supply rating. Low drift needs adequate supply headroom, matched layout, and a lightly loaded output." }, "path": [ { "part": "Start-up", "devices": "MS1, MS2, MS3", "does": "While V_REF is low, MS3 holds su high and MS1 pulls the PMOS gates down; once V_REF rises, MS2 pulls su low and MS1 turns off." }, { "part": "PMOS copies", "devices": "M1, M2, M5", "does": "Share the gate g: M1 feeds Q1 and R1 at va, M2 feeds Q2, R0 and R2 at vb, and M5 biases the amplifier." }, { "part": "Q1 branch", "devices": "Q1, R1", "does": "Q1's emitter-base voltage sets va; R1 across it draws V_EB1/R1, a current that falls with temperature." }, { "part": "Q2 branch", "devices": "Q2, R0, R2", "does": "R2 draws the same V_EB1/R1; Q2, N copies at Q1's current, needs V_T ln N less, which R0 turns into a rising current." }, { "part": "Amplifier", "devices": "MN, MT, MA1, MA2, MA3, MA4, CC", "does": "Compares vb, on its non-inverting input, with va and drives the PMOS gates until the two are equal; C_c on g sets the dominant pole." }, { "part": "Output", "devices": "M3, R3", "does": "M3 copies the branch current into R3, turning it into V_REF = R3·I." } ], "bias": "The loop sets its own current: the amplifier drives the PMOS gates until va equals vb, fixing each branch at V_EB1/R1 + (V_T ln N)/R0; M5 and MN copy it into the amplifier's tail, and the start-up devices act only while V_REF is low.", "relations": [ { "what": "Emitter-base difference", "expr": "ΔV_EB = V_EB1 − V_EB2 ≈ V_T ln N", "note": "Q1 and Q2 carry equal currents once va = vb; N = 8 by default" }, { "what": "Branch current", "expr": "I = V_EB1/R1 + (V_T ln N)/R0", "note": "a falling part plus a rising part; R1 = 220 kΩ and R0 = 27 kΩ by default" }, { "what": "Reference voltage", "expr": "V_REF = R3 · I = (R3/R1) (V_EB1 + (R1/R0) V_T ln N)", "note": "ratios set first-order weighting and scale; absolute resistance also changes current and V_EB1, so retuning may be needed" }, { "what": "Zero slope", "expr": "dV_EB1/dT + (R1/R0) (k/q) ln N = 0", "note": "the condition that sets R1/R0; V_EB's own curvature leaves a residual bow" } ], "tradeoffs": [ "R1 = R2 and R0: their ratio balances the two currents' slopes; with R1 too small V_REF falls with temperature, too large and it rises.", "R3: sets the level, V_REF = R3·I; away from V_REF ≈ V_EB1, M3's drain leaves M1's, worsening line regulation and temperature coefficient.", "N (Q2 = N copies of Q1): a larger ΔV_EB = V_T ln N makes the amplifier's offset matter less, but costs area.", "C_c: sets the dominant pole on the PMOS gates; less capacitance costs phase margin, worst at the cold end of the range." ] }, "sizing": [ { "key": "R1", "label": "R1 = R2", "unit": "Ω", "value": 220000, "min": 20000, "max": 1000000, "kind": "si" }, { "key": "R0", "label": "R0", "unit": "Ω", "value": 27000, "min": 2000, "max": 200000, "kind": "si" }, { "key": "R3", "label": "R3", "unit": "Ω", "value": 138000, "min": 20000, "max": 1000000, "kind": "si" }, { "key": "N", "label": "N (Q2 = N copies of Q1)", "unit": "", "value": 8, "min": 2, "max": 24, "kind": "int" }, { "key": "startup", "label": "Start-up circuit", "unit": "", "value": "on", "kind": "choice", "choices": [ [ "on", "on" ], [ "off", "off - to see why it is there" ] ] }, { "key": "Wp", "label": "W (PMOS unit)", "unit": "m", "value": 0.000016, "min": 1.5e-7, "max": 0.0001, "kind": "si" }, { "key": "Lp", "label": "L (PMOS unit)", "unit": "m", "value": 0.000004, "min": 1.3e-7, "max": 0.00001, "kind": "si" }, { "key": "Wn", "label": "W (NMOS unit)", "unit": "m", "value": 0.000004, "min": 1.5e-7, "max": 0.00005, "kind": "si" }, { "key": "Ln", "label": "L (NMOS unit)", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.00001, "kind": "si" }, { "key": "Cc", "label": "C_c", "unit": "F", "value": 4e-12, "min": 0, "max": 2e-11, "kind": "si" } ], "testbenches": [ { "id": "temp", "label": "Against temperature", "note": "", "measures": [ "vref", "tc" ], "metricKeys": [ "vout_27", "spread", "tc_ppm" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice", "sg13g2_hbt_tt.spice" ], "netlist": "* Sub-1-V bandgap reference - the output against temperature\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.include sg13g2_hbt_tt.spice\nVdd vdd 0 1.2\nXM1 va g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXM2 vb g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXM3 vref g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\n* Q1 and Q2 with base and collector on ground; Q2 is N copies of Q1\nXQ1 0 0 va pnpMPA\nXR1 va 0 0 rhigh w=0.5u l=67.842u\nXR0 vb e2 0 rhigh w=0.5u l=8.239u\nXQ2 0 0 e2 pnpMPA m=8\nXR2 vb 0 0 rhigh w=0.5u l=67.842u\nXR3 vref 0 0 rhigh w=0.5u l=42.519u\n* the amplifier: vb on its non-inverting input, va on the inverting one; its\n* tail copies the branch current, through M5 and MN\nXM5 bn g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXMN bn bn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nXMT t bn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=2\nXMA1 x vb t 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nXMA2 g va t 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nXMA3 x x vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXMA4 g x vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXCC g vdd cap_cmim w=29.761u l=29.761u m=3\n* start-up: while vref is low MS2 is off, MS3 pulls su up and MS1 pulls the PMOS\n* gates down; MS1's source is vref, so once the reference runs it is cut off\nXMS3 su 0 vdd vdd sg13_lv_pmos w=150n l=20u ng=1 m=1\nXMS2 su vref 0 0 sg13_lv_nmos w=150n l=10u ng=1 m=1\nXMS1 g su vref 0 sg13_lv_nmos w=1u l=500n ng=1 m=1\n.dc temp -40 125 5\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc vref27 FIND v(vref) AT=27\n.end" }, { "id": "trim", "label": "Trimming R1", "note": "", "measures": [ "tc" ], "metricKeys": [], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice", "sg13g2_hbt_tt.spice" ], "netlist": "* Sub-1-V bandgap reference - the output against temperature\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.include sg13g2_hbt_tt.spice\nVdd vdd 0 1.2\nXM1 va g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXM2 vb g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXM3 vref g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\n* Q1 and Q2 with base and collector on ground; Q2 is N copies of Q1\nXQ1 0 0 va pnpMPA\nXR1 va 0 0 rhigh w=0.5u l=67.842u\nXR0 vb e2 0 rhigh w=0.5u l=8.239u\nXQ2 0 0 e2 pnpMPA m=8\nXR2 vb 0 0 rhigh w=0.5u l=67.842u\nXR3 vref 0 0 rhigh w=0.5u l=42.519u\n* the amplifier: vb on its non-inverting input, va on the inverting one; its\n* tail copies the branch current, through M5 and MN\nXM5 bn g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXMN bn bn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nXMT t bn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=2\nXMA1 x vb t 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nXMA2 g va t 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nXMA3 x x vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXMA4 g x vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXCC g vdd cap_cmim w=29.761u l=29.761u m=3\n* start-up: while vref is low MS2 is off, MS3 pulls su up and MS1 pulls the PMOS\n* gates down; MS1's source is vref, so once the reference runs it is cut off\nXMS3 su 0 vdd vdd sg13_lv_pmos w=150n l=20u ng=1 m=1\nXMS2 su vref 0 0 sg13_lv_nmos w=150n l=10u ng=1 m=1\nXMS1 g su vref 0 sg13_lv_nmos w=1u l=500n ng=1 m=1\n.dc temp -40 125 5\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc vref27 FIND v(vref) AT=27\n.end" }, { "id": "supply", "label": "Against the supply", "note": "", "measures": [ "line", "vmin" ], "metricKeys": [ "line_pct", "vmin", "i_supply" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice", "sg13g2_hbt_tt.spice" ], "netlist": "* Sub-1-V bandgap reference - the output against the supply\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.include sg13g2_hbt_tt.spice\nVdd vdd 0 1.2\nXM1 va g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXM2 vb g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXM3 vref g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\n* Q1 and Q2 with base and collector on ground; Q2 is N copies of Q1\nXQ1 0 0 va pnpMPA\nXR1 va 0 0 rhigh w=0.5u l=67.842u\nXR0 vb e2 0 rhigh w=0.5u l=8.239u\nXQ2 0 0 e2 pnpMPA m=8\nXR2 vb 0 0 rhigh w=0.5u l=67.842u\nXR3 vref 0 0 rhigh w=0.5u l=42.519u\n* the amplifier: vb on its non-inverting input, va on the inverting one; its\n* tail copies the branch current, through M5 and MN\nXM5 bn g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXMN bn bn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nXMT t bn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=2\nXMA1 x vb t 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nXMA2 g va t 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nXMA3 x x vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXMA4 g x vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXCC g vdd cap_cmim w=29.761u l=29.761u m=3\n* start-up: while vref is low MS2 is off, MS3 pulls su up and MS1 pulls the PMOS\n* gates down; MS1's source is vref, so once the reference runs it is cut off\nXMS3 su 0 vdd vdd sg13_lv_pmos w=150n l=20u ng=1 m=1\nXMS2 su vref 0 0 sg13_lv_nmos w=150n l=10u ng=1 m=1\nXMS1 g su vref 0 sg13_lv_nmos w=1u l=500n ng=1 m=1\n.dc Vdd 0 1.32 0.01\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc vref FIND v(vref) AT=1.2\n.end" }, { "id": "powerup", "label": "Power-up", "note": "", "measures": [ "tstart" ], "metricKeys": [ "t_start" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice", "sg13g2_hbt_tt.spice" ], "netlist": "* Sub-1-V bandgap reference - the supply ramping up from zero\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.include sg13g2_hbt_tt.spice\nVdd vdd 0 PWL(0 0 10u 1.2)\nXM1 va g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXM2 vb g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXM3 vref g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\n* Q1 and Q2 with base and collector on ground; Q2 is N copies of Q1\nXQ1 0 0 va pnpMPA\nXR1 va 0 0 rhigh w=0.5u l=67.842u\nXR0 vb e2 0 rhigh w=0.5u l=8.239u\nXQ2 0 0 e2 pnpMPA m=8\nXR2 vb 0 0 rhigh w=0.5u l=67.842u\nXR3 vref 0 0 rhigh w=0.5u l=42.519u\n* the amplifier: vb on its non-inverting input, va on the inverting one; its\n* tail copies the branch current, through M5 and MN\nXM5 bn g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXMN bn bn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nXMT t bn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=2\nXMA1 x vb t 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nXMA2 g va t 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nXMA3 x x vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXMA4 g x vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1\nXCC g vdd cap_cmim w=29.761u l=29.761u m=3\n* start-up: while vref is low MS2 is off, MS3 pulls su up and MS1 pulls the PMOS\n* gates down; MS1's source is vref, so once the reference runs it is cut off\nXMS3 su 0 vdd vdd sg13_lv_pmos w=150n l=20u ng=1 m=1\nXMS2 su vref 0 0 sg13_lv_nmos w=150n l=10u ng=1 m=1\nXMS1 g su vref 0 sg13_lv_nmos w=1u l=500n ng=1 m=1\n.tran 20n 30u\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas tran vref FIND v(vref) AT=30u\n.end" } ], "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "dd0550f29f2b3e549a96ad164a2f50c7fa106418922e2248e4ae0d037cb6a8ff" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/bandgap.js", "sha256": "994bd94ecab8344283c3d8b7b4d7bb8df21c8b4ab5222a28dce5ea391605fa02" }, "simulationFingerprints": { "temp": "15d35247dcc16ab8c40986b90ca13972f968c5d51dbb5b6304e204392a34fe19", "trim": "2950845ab4d8aa29d8eb0dd5a42c39ceeb1cf7eb8ab4d00cb45c112bf410cea5", "supply": "393a899914d7cda4e3a8dc16bb8d02dd2e3299eba44de307cea9047a5fb1478b", "powerup": "c98b505acca7fedbfb37b413943fcaa56be96b52691d544d0e04ce15f53a9f20" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "9f51ca15b2709d35dcbbb4552b2299ff0842328226a3b365344283cc329fd41f", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "bandgap", "parameters": { "R1": 220000, "R0": 27000, "R3": 138000, "N": 8, "startup": "on", "Wp": 0.000016, "Lp": 0.000004, "Wn": 0.000004, "Ln": 0.000002, "Cc": 4e-12 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [ { "key": "startup", "selected": "on", "choices": [ { "value": "on", "label": "on" }, { "value": "off", "label": "off - to see why it is there" } ] } ], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/bandgap/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [], "scopes": [ { "id": "dut", "name": "top", "ports": [ { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vref", "net": "vref", "kind": "output" }, { "name": "gnd", "net": "0", "kind": "ground" } ], "definitions": [], "devices": [ { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=16u l=4u ng=4 m=1", "source": "XM1 va g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1", "pins": [ { "id": "d", "net": "va" }, { "id": "g", "net": "g" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=16u l=4u ng=4 m=1", "source": "XM2 vb g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1", "pins": [ { "id": "d", "net": "vb" }, { "id": "g", "net": "g" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=16u l=4u ng=4 m=1", "source": "XM3 vref g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1", "pins": [ { "id": "d", "net": "vref" }, { "id": "g", "net": "g" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ1", "displayName": "Q1", "spiceType": "X", "model": "pnpMPA", "parametersOrValue": "", "source": "XQ1 0 0 va pnpMPA", "pins": [ { "id": "c", "net": "0" }, { "id": "b", "net": "0" }, { "id": "e", "net": "va" } ], "pinMeaning": "IHP bipolar collector, base, emitter" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=67.842u", "source": "XR1 va 0 0 rhigh w=0.5u l=67.842u", "pins": [ { "id": "p", "net": "va" }, { "id": "n", "net": "0" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR0", "displayName": "R0", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=8.239u", "source": "XR0 vb e2 0 rhigh w=0.5u l=8.239u", "pins": [ { "id": "p", "net": "vb" }, { "id": "n", "net": "e2" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XQ2", "displayName": "Q2", "spiceType": "X", "model": "pnpMPA", "parametersOrValue": "m=8", "source": "XQ2 0 0 e2 pnpMPA m=8", "pins": [ { "id": "c", "net": "0" }, { "id": "b", "net": "0" }, { "id": "e", "net": "e2" } ], "pinMeaning": "IHP bipolar collector, base, emitter" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=67.842u", "source": "XR2 vb 0 0 rhigh w=0.5u l=67.842u", "pins": [ { "id": "p", "net": "vb" }, { "id": "n", "net": "0" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR3", "displayName": "R3", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=42.519u", "source": "XR3 vref 0 0 rhigh w=0.5u l=42.519u", "pins": [ { "id": "p", "net": "vref" }, { "id": "n", "net": "0" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=16u l=4u ng=4 m=1", "source": "XM5 bn g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1", "pins": [ { "id": "d", "net": "bn" }, { "id": "g", "net": "g" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN", "displayName": "MN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XMN bn bn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "bn" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=2", "source": "XMT t bn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=2", "pins": [ { "id": "d", "net": "t" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XMA1 x vb t 0 sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "vb" }, { "id": "s", "net": "t" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XMA2 g va t 0 sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "g" }, { "id": "g", "net": "va" }, { "id": "s", "net": "t" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA3", "displayName": "MA3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=16u l=4u ng=4 m=1", "source": "XMA3 x x vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "x" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA4", "displayName": "MA4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=16u l=4u ng=4 m=1", "source": "XMA4 g x vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1", "pins": [ { "id": "d", "net": "g" }, { "id": "g", "net": "x" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC", "displayName": "CC", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.761u l=29.761u m=3", "source": "XCC g vdd cap_cmim w=29.761u l=29.761u m=3", "pins": [ { "id": "p", "net": "g" }, { "id": "n", "net": "vdd" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMS3", "displayName": "MS3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=150n l=20u ng=1 m=1", "source": "XMS3 su 0 vdd vdd sg13_lv_pmos w=150n l=20u ng=1 m=1", "pins": [ { "id": "d", "net": "su" }, { "id": "g", "net": "0" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS2", "displayName": "MS2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=150n l=10u ng=1 m=1", "source": "XMS2 su vref 0 0 sg13_lv_nmos w=150n l=10u ng=1 m=1", "pins": [ { "id": "d", "net": "su" }, { "id": "g", "net": "vref" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS1", "displayName": "MS1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=500n ng=1 m=1", "source": "XMS1 g su vref 0 sg13_lv_nmos w=1u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "g" }, { "id": "g", "net": "su" }, { "id": "s", "net": "vref" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "va", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XQ1", "pin": "e" }, { "device": "XR1", "pin": "p" }, { "device": "XMA2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "g", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM2", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XMA2", "pin": "d" }, { "device": "XMA4", "pin": "d" }, { "device": "XCC", "pin": "p" }, { "device": "XMS1", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XMA3", "pin": "s" }, { "device": "XMA3", "pin": "b" }, { "device": "XMA4", "pin": "s" }, { "device": "XMA4", "pin": "b" }, { "device": "XCC", "pin": "n" }, { "device": "XMS3", "pin": "s" }, { "device": "XMS3", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vb", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XR0", "pin": "p" }, { "device": "XR2", "pin": "p" }, { "device": "XMA1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vref", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XR3", "pin": "p" }, { "device": "XMS2", "pin": "g" }, { "device": "XMS1", "pin": "s" } ], "ports": [ "vref" ], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "XQ1", "pin": "c" }, { "device": "XQ1", "pin": "b" }, { "device": "XR1", "pin": "n" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR0", "pin": "substrate" }, { "device": "XQ2", "pin": "c" }, { "device": "XQ2", "pin": "b" }, { "device": "XR2", "pin": "n" }, { "device": "XR2", "pin": "substrate" }, { "device": "XR3", "pin": "n" }, { "device": "XR3", "pin": "substrate" }, { "device": "XMN", "pin": "s" }, { "device": "XMN", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "b" }, { "device": "XMS3", "pin": "g" }, { "device": "XMS2", "pin": "s" }, { "device": "XMS2", "pin": "b" }, { "device": "XMS1", "pin": "b" } ], "ports": [ "gnd" ], "voltageReferences": [] }, { "id": "e2", "ground": false, "terminals": [ { "device": "XR0", "pin": "n" }, { "device": "XQ2", "pin": "e" } ], "ports": [], "voltageReferences": [] }, { "id": "bn", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XMN", "pin": "d" }, { "device": "XMN", "pin": "g" }, { "device": "XMT", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "t", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMA1", "pin": "d" }, { "device": "XMA3", "pin": "d" }, { "device": "XMA3", "pin": "g" }, { "device": "XMA4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "su", "ground": false, "terminals": [ { "device": "XMS3", "pin": "d" }, { "device": "XMS2", "pin": "d" }, { "device": "XMS1", "pin": "g" } ], "ports": [], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "1.2", "source": "Vdd vdd 0 1.2", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=16u l=4u ng=4 m=1", "source": "XM1 va g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1", "pins": [ { "id": "d", "net": "va" }, { "id": "g", "net": "g" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=16u l=4u ng=4 m=1", "source": "XM2 vb g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1", "pins": [ { "id": "d", "net": "vb" }, { "id": "g", "net": "g" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=16u l=4u ng=4 m=1", "source": "XM3 vref g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1", "pins": [ { "id": "d", "net": "vref" }, { "id": "g", "net": "g" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ1", "displayName": "Q1", "spiceType": "X", "model": "pnpMPA", "parametersOrValue": "", "source": "XQ1 0 0 va pnpMPA", "pins": [ { "id": "c", "net": "0" }, { "id": "b", "net": "0" }, { "id": "e", "net": "va" } ], "pinMeaning": "IHP bipolar collector, base, emitter" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=67.842u", "source": "XR1 va 0 0 rhigh w=0.5u l=67.842u", "pins": [ { "id": "p", "net": "va" }, { "id": "n", "net": "0" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR0", "displayName": "R0", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=8.239u", "source": "XR0 vb e2 0 rhigh w=0.5u l=8.239u", "pins": [ { "id": "p", "net": "vb" }, { "id": "n", "net": "e2" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XQ2", "displayName": "Q2", "spiceType": "X", "model": "pnpMPA", "parametersOrValue": "m=8", "source": "XQ2 0 0 e2 pnpMPA m=8", "pins": [ { "id": "c", "net": "0" }, { "id": "b", "net": "0" }, { "id": "e", "net": "e2" } ], "pinMeaning": "IHP bipolar collector, base, emitter" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=67.842u", "source": "XR2 vb 0 0 rhigh w=0.5u l=67.842u", "pins": [ { "id": "p", "net": "vb" }, { "id": "n", "net": "0" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR3", "displayName": "R3", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=42.519u", "source": "XR3 vref 0 0 rhigh w=0.5u l=42.519u", "pins": [ { "id": "p", "net": "vref" }, { "id": "n", "net": "0" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=16u l=4u ng=4 m=1", "source": "XM5 bn g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1", "pins": [ { "id": "d", "net": "bn" }, { "id": "g", "net": "g" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN", "displayName": "MN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XMN bn bn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "bn" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=2", "source": "XMT t bn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=2", "pins": [ { "id": "d", "net": "t" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XMA1 x vb t 0 sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "vb" }, { "id": "s", "net": "t" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XMA2 g va t 0 sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "g" }, { "id": "g", "net": "va" }, { "id": "s", "net": "t" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA3", "displayName": "MA3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=16u l=4u ng=4 m=1", "source": "XMA3 x x vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "x" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA4", "displayName": "MA4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=16u l=4u ng=4 m=1", "source": "XMA4 g x vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1", "pins": [ { "id": "d", "net": "g" }, { "id": "g", "net": "x" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC", "displayName": "CC", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.761u l=29.761u m=3", "source": "XCC g vdd cap_cmim w=29.761u l=29.761u m=3", "pins": [ { "id": "p", "net": "g" }, { "id": "n", "net": "vdd" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMS3", "displayName": "MS3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=150n l=20u ng=1 m=1", "source": "XMS3 su 0 vdd vdd sg13_lv_pmos w=150n l=20u ng=1 m=1", "pins": [ { "id": "d", "net": "su" }, { "id": "g", "net": "0" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS2", "displayName": "MS2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=150n l=10u ng=1 m=1", "source": "XMS2 su vref 0 0 sg13_lv_nmos w=150n l=10u ng=1 m=1", "pins": [ { "id": "d", "net": "su" }, { "id": "g", "net": "vref" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS1", "displayName": "MS1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=500n ng=1 m=1", "source": "XMS1 g su vref 0 sg13_lv_nmos w=1u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "g" }, { "id": "g", "net": "su" }, { "id": "s", "net": "vref" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XMA3", "pin": "s" }, { "device": "XMA3", "pin": "b" }, { "device": "XMA4", "pin": "s" }, { "device": "XMA4", "pin": "b" }, { "device": "XCC", "pin": "n" }, { "device": "XMS3", "pin": "s" }, { "device": "XMS3", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "XQ1", "pin": "c" }, { "device": "XQ1", "pin": "b" }, { "device": "XR1", "pin": "n" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR0", "pin": "substrate" }, { "device": "XQ2", "pin": "c" }, { "device": "XQ2", "pin": "b" }, { "device": "XR2", "pin": "n" }, { "device": "XR2", "pin": "substrate" }, { "device": "XR3", "pin": "n" }, { "device": "XR3", "pin": "substrate" }, { "device": "XMN", "pin": "s" }, { "device": "XMN", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "b" }, { "device": "XMS3", "pin": "g" }, { "device": "XMS2", "pin": "s" }, { "device": "XMS2", "pin": "b" }, { "device": "XMS1", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "va", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XQ1", "pin": "e" }, { "device": "XR1", "pin": "p" }, { "device": "XMA2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "g", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM2", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XMA2", "pin": "d" }, { "device": "XMA4", "pin": "d" }, { "device": "XCC", "pin": "p" }, { "device": "XMS1", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "vb", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XR0", "pin": "p" }, { "device": "XR2", "pin": "p" }, { "device": "XMA1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vref", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XR3", "pin": "p" }, { "device": "XMS2", "pin": "g" }, { "device": "XMS1", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "e2", "ground": false, "terminals": [ { "device": "XR0", "pin": "n" }, { "device": "XQ2", "pin": "e" } ], "ports": [], "voltageReferences": [] }, { "id": "bn", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XMN", "pin": "d" }, { "device": "XMN", "pin": "g" }, { "device": "XMT", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "t", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMA1", "pin": "d" }, { "device": "XMA3", "pin": "d" }, { "device": "XMA3", "pin": "g" }, { "device": "XMA4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "su", "ground": false, "terminals": [ { "device": "XMS3", "pin": "d" }, { "device": "XMS2", "pin": "d" }, { "device": "XMS1", "pin": "g" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "top-level-device-set", "scope": "top", "devices": [ "XM1", "XM2", "XM3", "XQ1", "XR1", "XR0", "XQ2", "XR2", "XR3", "XM5", "XMN", "XMT", "XMA1", "XMA2", "XMA3", "XMA4", "XCC", "XMS3", "XMS2", "XMS1" ] } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "The diode whose V_EB falls with temperature: one pnpMPA", "devices": [ { "scope": "dut", "device": "XQ1" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "N copies of Q1 at Q1's current: V_T ln N less V_EB", "devices": [ { "scope": "dut", "device": "XQ2" } ], "inferredStages": [ "bias" ] }, { "id": "block-3", "label": "Carries ΔV_EB: the rising current", "devices": [ { "scope": "dut", "device": "XR0" } ], "inferredStages": [ "bias" ] }, { "id": "block-4", "label": "Across Q1: V_EB1/R1", "devices": [ { "scope": "dut", "device": "XR1" } ], "inferredStages": [ "bias" ] }, { "id": "block-5", "label": "Across Q2 and R0", "devices": [ { "scope": "dut", "device": "XR2" } ], "inferredStages": [ "bias" ] }, { "id": "block-6", "label": "Turns the summed current into V_REF", "devices": [ { "scope": "dut", "device": "XR3" } ], "inferredStages": [ "bias" ] }, { "id": "block-7", "label": "Feeds Q1 and R1", "devices": [ { "scope": "dut", "device": "XM1" } ], "inferredStages": [ "bias" ] }, { "id": "block-8", "label": "Feeds Q2", "devices": [ { "scope": "dut", "device": "XM2" } ], "inferredStages": [ "bias" ] }, { "id": "block-9", "label": "The output copy", "devices": [ { "scope": "dut", "device": "XM3" } ], "inferredStages": [ "bias" ] }, { "id": "block-10", "label": "A fourth copy", "devices": [ { "scope": "dut", "device": "XM5" } ], "inferredStages": [ "bias" ] }, { "id": "block-11", "label": "The amplifier's bias diode", "devices": [ { "scope": "dut", "device": "XMN" } ], "inferredStages": [ "bias" ] }, { "id": "block-12", "label": "The amplifier's tail", "devices": [ { "scope": "dut", "device": "XMT" } ], "inferredStages": [ "bias" ] }, { "id": "block-13", "label": "Non-inverting input", "devices": [ { "scope": "dut", "device": "XMA1" } ], "inferredStages": [ "bias" ] }, { "id": "block-14", "label": "Inverting input", "devices": [ { "scope": "dut", "device": "XMA2" } ], "inferredStages": [ "bias" ] }, { "id": "block-15", "label": "The amplifier's load", "devices": [ { "scope": "dut", "device": "XMA3" }, { "scope": "dut", "device": "XMA4" } ], "inferredStages": [ "bias" ] }, { "id": "block-16", "label": "The dominant pole", "devices": [ { "scope": "dut", "device": "XCC" } ], "inferredStages": [ "bias" ] }, { "id": "block-17", "label": "Start-up: pulls the PMOS gates down until the reference runs", "devices": [ { "scope": "dut", "device": "XMS1" } ], "inferredStages": [ "bias" ] }, { "id": "block-18", "label": "Start-up: watches V_REF and takes MS1's gate away", "devices": [ { "scope": "dut", "device": "XMS2" } ], "inferredStages": [ "bias" ] }, { "id": "block-19", "label": "Start-up: a weak pull-up on MS1's gate", "devices": [ { "scope": "dut", "device": "XMS3" } ], "inferredStages": [ "bias" ] } ], "edges": [ { "id": "net-1", "net": "va", "nodes": [ "block-7", "block-1", "block-4", "block-14" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "g", "nodes": [ "block-7", "block-8", "block-9", "block-10", "block-14", "block-15", "block-16", "block-17" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "vb", "nodes": [ "block-8", "block-3", "block-5", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "vref", "nodes": [ "block-9", "block-6", "block-18", "block-17" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "e2", "nodes": [ "block-3", "block-2" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "bn", "nodes": [ "block-10", "block-11", "block-12" ], "direction": "undirected-shared-net" }, { "id": "net-7", "net": "t", "nodes": [ "block-12", "block-13", "block-14" ], "direction": "undirected-shared-net" }, { "id": "net-8", "net": "x", "nodes": [ "block-13", "block-15" ], "direction": "undirected-shared-net" }, { "id": "net-9", "net": "su", "nodes": [ "block-19", "block-18", "block-17" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vref", "net": "vref", "kind": "output" }, { "name": "gnd", "net": "0", "kind": "ground" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "PWL(0 0 10u 1.2)", "source": "Vdd vdd 0 PWL(0 0 10u 1.2)", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=16u l=4u ng=4 m=1", "source": "XM1 va g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 m=1", "pins": [ { "id": "d", "net": "va" }, { "id": "g", "net": "g" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=16u l=4u ng=4 m=1", "source": "XM2 vb g vdd vdd sg13_lv_pmos w=16u l=4u ng=4 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