{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "beta-multiplier", "name": "Beta-multiplier reference", "group": "Mirrors, bias and references", "subgroup": "Bias generators", "title": "Beta-multiplier reference", "summary": "Generates a bias current from a resistor and a transistor ratio. A feedback loop settles where two gate-source voltages differ by the resistor's voltage drop. An added amplifier reduces supply sensitivity, but needs compensation and a start-up circuit to reach the working state.", "reference": { "kind": "book", "authors": "B. Razavi", "title": "Design of Analog CMOS Integrated Circuits", "edition": "2nd ed.", "publisher": "McGraw-Hill", "year": 2017, "where": "Bandgap References - supply-independent biasing: the self-biased circuit with a resistor in the source of the wider device, and its start-up", "takes": "The topology, the current it settles at, and the zero-current state a start-up circuit removes. The amplifier that holds M2's drain at M1's is the op amp a bandgap uses to hold two nodes equal (same chapter), applied to this loop.", "also": [ { "authors": "R. J. Baker", "title": "CMOS Circuit Design, Layout, and Simulation", "edition": "3rd ed.", "year": 2010, "where": "The beta-multiplier reference and its start-up circuit" } ] }, "resources": { "record": "/circuits/beta-multiplier.json", "page": "/index.html#beta-multiplier", "achieved": "/achieved/beta-multiplier.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "vbn", "kind": "output", "note": "the NMOS bias: a copy of M1 sinks I_ref" }, { "name": "vbp", "kind": "output", "note": "the PMOS bias: a copy of M3 sources I_ref" }, { "name": "vdd", "kind": "supply" }, { "name": "0", "kind": "ground" } ], "devices": [ { "name": "M1", "type": "nmos", "sizedBy": [ "Wn", "Ln" ], "role": "the diode: its drain is V_bn", "fingers": 1, "copies": 1 }, { "name": "M2", "type": "nmos", "sizedBy": [ "Wn", "Ln", "K" ], "role": "K copies of M1, with R1 in its source", "fingers": 1, "copies": 4 }, { "name": "R1", "type": "resistor", "sizedBy": [ "R" ], "role": "sets the current: V_GS1 - V_GS2 drops across it" }, { "name": "M3", "type": "pmos", "sizedBy": [ "Wp", "Lp" ], "role": "copies the current into M1", "fingers": 2, "copies": 1 }, { "name": "M4", "type": "pmos", "sizedBy": [ "Wp", "Lp" ], "role": "supplies M2; the diode, in the basic reference", "fingers": 2, "copies": 1 }, { "name": "MT", "type": "nmos", "sizedBy": [ "Wn", "Ln", "topology" ], "role": "regulated only: the amplifier's tail, two copies of M1", "fingers": 1, "copies": 2 }, { "name": "MA1", "type": "nmos", "sizedBy": [ "Wn", "Ln", "topology" ], "role": "regulated only: non-inverting input, on M2's drain (four copies of M1)", "fingers": 1, "copies": 4 }, { "name": "MA2", "type": "nmos", "sizedBy": [ "Wn", "Ln", "topology" ], "role": "regulated only: inverting input, on M1's drain (four copies of M1)", "fingers": 1, "copies": 4 }, { "name": "MA3", "type": "pmos", "sizedBy": [ "Wp", "Lp", "topology" ], "role": "regulated only: the amplifier's load, diode side", "fingers": 2, "copies": 1 }, { "name": "MA4", "type": "pmos", "sizedBy": [ "Wp", "Lp", "topology" ], "role": "regulated only: the amplifier's load, driving the PMOS gates", "fingers": 2, "copies": 1 }, { "name": "CC", "type": "capacitor", "sizedBy": [ "Cc", "topology" ], "role": "regulated only: the dominant pole, on the PMOS gates" }, { "name": "RZ", "type": "resistor", "sizedBy": [ "Rz", "topology" ], "role": "regulated only: with C_z, M2's drain's impedance at high frequency" }, { "name": "CZ", "type": "capacitor", "sizedBy": [ "Cz", "topology" ], "role": "regulated only: blocks DC, so R_z does not touch the bias" }, { "name": "MS1", "type": "nmos", "sizedBy": [ "startup" ], "role": "start-up: pulls the PMOS gates down while there is no current", "fingers": 1, "copies": 1 }, { "name": "MS2", "type": "nmos", "sizedBy": [ "startup" ], "role": "start-up: takes MS1's gate away once V_bn rises", "fingers": 1, "copies": 1 }, { "name": "MS3", "type": "pmos", "sizedBy": [ "startup" ], "role": "start-up: a long, narrow pull-up on MS1's gate", "fingers": 1, "copies": 1 } ], "intent": [ { "rule": "self-bias", "of": [ "M1", "M2", "R1" ], "constraint": "V_GS1 = V_GS2 + I R1; I = 2 (1 - 1/√K)² / (µC_ox (W/L) R1²) in strong inversion", "why": "M2 is K copies of M1 carrying the same current, so it needs less V_GS; the difference drops across R1, and only one current makes the two agree: 8.46 µA with R1 = 10 kΩ and K = 4. No supply voltage appears in that equation, which is the point of the circuit." }, { "rule": "unit-devices", "of": [ "M1", "M2", "MT", "MA1", "MA2", "M3", "M4", "MA3", "MA4" ], "why": "Every NMOS is a copy of one unit (Wn/Ln) and every PMOS of another (Wp/Lp); K, the tail's 2 and the inputs' 4 are counts of copies. K is what sets the current, and a wider device has a threshold of its own, so a K drawn as one wide M2 would set some other current." }, { "rule": "supply-rejection", "of": [ "MA1", "MA2", "M2", "M3" ], "constraint": "V(M2's drain) = V_bn", "why": "In the basic reference M2's drain sits at V_DD - V_SG and M3's source-drain voltage is V_DD - V_GS1: both follow the supply volt for volt. An SG13G2 NMOS passes about 0.3 of its current more per volt of drain voltage even at L = 2 µm, and the loop's positive feedback multiplies that: the basic reference moves 38 %/V. The amplifier holds M2's drain at M1's, so M3 and M4 see one drain voltage and M2's stops moving: 0.07 %/V, and within 1 % from 0.70 V of supply, where the basic one needs 1.17 V." }, { "rule": "input-range", "of": [ "MA1", "MA2", "MT" ], "constraint": "V_GS(MA1) well below V_GS1", "why": "The amplifier's inputs sit at V_GS1, only 0.37 V. Its input devices are four copies each - wide, so near weak inversion with little V_GS, 0.27 V - which leaves the tail 0.10 V to work in. That is below MT's saturation voltage, 0.18 V: MT is a copy of M1 at M1's gate voltage, so it needs M1's overdrive, and the room under the inputs, V_GS1 - V_GS(MA1), falls short of that while the inputs conduct - sixteen times wider inputs still leave MT only at the edge. So MT works in triode and passes 13.3 µA where two copies of M1 would pass 16.9 µA. It need not be a good current source: both inputs sit at V_GS1 and never part by more than millivolts, and across the process, supply and temperature corners the loop keeps 48 to 57 dB of gain and the reference 0.05 to 0.11 %/V." }, { "rule": "compensation", "of": [ "CC", "RZ", "CZ" ], "constraint": "phase margin > 60°", "why": "The amplifier and M4 make a loop with 53 dB of gain around two high-impedance nodes, the PMOS gates and M2's drain, both with poles well below where the gain reaches unity. C_c alone leaves 1° of phase margin. R_z and C_z across the amplifier's inputs bring M2's drain's impedance down to R_z at high frequency without touching the bias - no DC flows through C_z - for 67°, measured by breaking the loop at the amplifier's output with Middlebrook's double injection." }, { "rule": "start-up", "of": [ "MS1", "MS2", "MS3" ], "constraint": "MS1 off once the reference runs", "why": "Zero current also satisfies the loop, and the regulated reference stays there: its amplifier's tail copies M1, so with no current it has no gain, and C_c holds the PMOS gates at the rising supply. MS1 pulls the gates down until V_bn is high enough for MS2 to take MS1's gate away. MS2 has only V_GS1 = 0.37 V to do that with, so MS3 is a weak pull-up, 0.15/20 µm: it costs 0.29 µA and leaves MS1's gate at 8 mV." } ], "specs": [ { "key": "iref", "label": "Reference current", "unit": "A", "direction": "target" }, { "key": "sens", "label": "Supply sensitivity", "unit": "%/V", "direction": "min" }, { "key": "vmin", "label": "Lowest supply within 1 %", "unit": "V", "direction": "min" }, { "key": "tc", "label": "Temperature coefficient", "unit": "%/°C", "direction": "target" }, { "key": "tstart", "label": "Start-up time", "unit": "s", "direction": "min" }, { "key": "settle", "label": "Settling after a supply step", "unit": "s", "direction": "min" } ], "explanation": { "idea": "Generates a bias current from a resistor and a transistor ratio. A feedback loop settles where two gate-source voltages differ by the resistor's voltage drop. An added amplifier reduces supply sensitivity, but needs compensation and a start-up circuit to reach the working state.", "detail": "A bias current set by a resistor and a ratio of transistors rather than by the supply. M1 is diode-connected; M2, K copies of M1 with R1 in its source, carries the same current at a smaller V_GS, and only one non-zero current makes V_GS1 = V_GS2 + I·R1. The PMOS pair closes the loop. In the regulated topology an amplifier holds M2's drain at M1's reducing the drains' supply dependence, and a start-up circuit removes the other solution, zero current.", "lesson": { "relation": 1, "symbols": "I is branch current; K is M2's unit-copy ratio; µ_n is electron mobility; C_ox is oxide capacitance per area; W/L is M1's width-to-length ratio; R1 is the source resistor.", "assumptions": "Ideal matched strong-inversion square-law devices, with body effect and channel-length modulation neglected. The real regulated circuit only approximates this law.", "exercise": { "param": "R", "value": 20000, "analysis": "supply", "expect": "A larger resistor should reduce the working current. It need not fall by exactly four because the real devices move between inversion regions." }, "limits": "The regulated option needs start-up and compensation. Its bias current still changes with temperature and process; it is not a temperature-independent current standard." }, "path": [ { "part": "Start-up", "devices": "MS1, MS2, MS3", "does": "With no current vbn is low, MS2 is off, MS3 pulls su up and MS1 pulls the PMOS gates down; once vbn rises MS2 turns MS1 off." }, { "part": "Self-biased core", "devices": "M1, M2, R1", "does": "M1 is diode-connected; M2, K copies of M1 at the same current, needs less V_GS, and R1 in its source drops the difference." }, { "part": "PMOS mirror", "devices": "M3, M4", "does": "Share the gate vbp and force one current through both branches: M3 into M1, M4 into M2; in the basic topology M4 is the diode." }, { "part": "Regulating amplifier", "devices": "MT, MA1, MA2, MA3, MA4", "does": "Compares M2's drain (non-inverting) with vbn and drives vbp until they are equal, reducing the drains' supply dependence; its tail copies M1." }, { "part": "Compensation", "devices": "CC, RZ, CZ", "does": "C_c on vbp sets the dominant pole; R_z and C_z across the amplifier's inputs lower M2's drain impedance at high frequency without touching the bias." } ], "bias": "No external reference: the loop settles at the one non-zero current for which V_GS1 = V_GS2 + I·R1, set by R1 (10 kΩ by default) and K (4 by default); vbn and vbp pass copies of it to other circuits.", "relations": [ { "what": "Self-bias condition", "expr": "V_GS1 = V_GS2 + I · R1", "note": "M2 is K copies of M1 at the same current, so it needs less V_GS" }, { "what": "Reference current", "expr": "I = 2 (1 − 1/√K)^2 / (µ_n C_ox (W/L)_1 R1^2)", "note": "strong inversion: no V_DD appears; mobility does, and it falls with temperature, so I rises faster than PTAT" }, { "what": "Loop gain near zero current", "expr": "A_loop(I → 0) ≈ K", "note": "ideal local-loop intuition, not a start-up guarantee; the regulated amplifier has no tail current at zero" }, { "what": "Regulation", "expr": "V_d2 = V_bn", "note": "the amplifier gives M3 and M4 one drain voltage, so the PMOS copy error from unequal drain voltages is reduced" } ], "tradeoffs": [ "R1: current falls with its square in strong inversion; a larger R1 saves power but costs area and edges the devices towards weak inversion.", "K (M2 = K copies of M1): larger K raises the current and the loop's gain near zero current, and costs area.", "Topology: regulation holds M2's drain at M1's and cuts supply sensitivity, but adds a loop to compensate and can remain in its off state without MS1 to MS3.", "C_c, R_z, C_z: C_c alone leaves almost no phase margin; R_z–C_z across the amplifier's inputs restores it; without C_z the loop rings." ] }, "sizing": [ { "key": "topology", "label": "Topology", "unit": "", "value": "regulated", "kind": "choice", "choices": [ [ "basic", "basic (for comparison)" ], [ "regulated", "regulated by an amplifier" ] ] }, { "key": "startup", "label": "Start-up circuit", "unit": "", "value": "on", "kind": "choice", "choices": [ [ "on", "on" ], [ "off", "off - to see why it is there" ] ] }, { "key": "R", "label": "R1", "unit": "Ω", "value": 10000, "min": 1000, "max": 100000, "kind": "si" }, { "key": "K", "label": "K (M2 = K copies of M1)", "unit": "", "value": 4, "min": 2, "max": 16, "kind": "int" }, { "key": "Wn", "label": "W (NMOS unit)", "unit": "m", "value": 0.000004, "min": 1.5e-7, "max": 0.00005, "kind": "si" }, { "key": "Ln", "label": "L (NMOS unit)", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.00001, "kind": "si" }, { "key": "Wp", "label": "W (PMOS unit)", "unit": "m", "value": 0.000008, "min": 1.5e-7, "max": 0.00005, "kind": "si" }, { "key": "Lp", "label": "L (PMOS unit)", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.00001, "kind": "si" }, { "key": "Cc", "label": "C_c", "unit": "F", "value": 2e-12, "min": 0, "max": 2e-11, "kind": "si" }, { "key": "Rz", "label": "R_z", "unit": "Ω", "value": 30000, "min": 1000, "max": 200000, "kind": "si" }, { "key": "Cz", "label": "C_z", "unit": "F", "value": 5e-12, "min": 0, "max": 2e-11, "kind": "si" } ], "testbenches": [ { "id": "supply", "label": "Against the supply", "note": "", "measures": [ "iref", "sens", "vmin" ], "metricKeys": [ "iref", "line_pct", "vmin", "i_supply" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Beta-multiplier reference (regulated) - the reference current against the supply\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\nVdd vdd 0 1.2\nXM3 vbn vbp vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1\nXM4 d2 vbp vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1\nXM1 vbn vbn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nXM2 d2 vbn s 0 sg13_lv_nmos w=4u l=2u ng=1 m=4\nXR1 s sr 0 rppd w=0.5u l=19.417u\n* the amplifier: M2's drain on its non-inverting input, M1's on the inverting\n* one; its tail copies M1, so the reference it regulates is what biases it\nXMT t vbn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=2\nXMA1 x d2 t 0 sg13_lv_nmos w=4u l=2u ng=1 m=4\nXMA2 vbp vbn t 0 sg13_lv_nmos w=4u l=2u ng=1 m=4\nXMA3 x x vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1\nXMA4 vbp x vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1\n* compensation: C_c on the PMOS gates, R_z and C_z across the amplifier's inputs\nXCC vbp vdd cap_cmim w=25.767u l=25.767u m=2\nXRZ vbn z 0 rhigh w=0.5u l=9.166u\nXCZ z d2 cap_cmim w=28.814u l=28.814u m=4\n* start-up: with no current vbn is low, MS2 is off, MS3 pulls su up and MS1\n* pulls the PMOS gates down; once the reference runs, MS2 turns MS1 off\nXMS3 su 0 vdd vdd sg13_lv_pmos w=150n l=20u ng=1 m=1\nXMS2 su vbn 0 0 sg13_lv_nmos w=1u l=1u ng=1 m=1\nXMS1 vbp su 0 0 sg13_lv_nmos w=1u l=500n ng=1 m=1\n* a zero-volt source as the ammeter: I_ref is the current through R1\nVr sr 0 0\n.dc Vdd 0 1.32 0.01\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc iref FIND i(Vr) AT=1.2\n.end" }, { "id": "temp", "label": "Against temperature", "note": "", "measures": [ "tc" ], "metricKeys": [ "tc" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Beta-multiplier reference (regulated) - the reference current against temperature\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\nVdd vdd 0 1.2\nXM3 vbn vbp vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1\nXM4 d2 vbp vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1\nXM1 vbn vbn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nXM2 d2 vbn s 0 sg13_lv_nmos w=4u l=2u ng=1 m=4\nXR1 s sr 0 rppd w=0.5u l=19.417u\n* the amplifier: M2's drain on its non-inverting input, M1's on the inverting\n* one; its tail copies M1, so the reference it regulates is what biases it\nXMT t vbn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=2\nXMA1 x d2 t 0 sg13_lv_nmos w=4u l=2u ng=1 m=4\nXMA2 vbp vbn t 0 sg13_lv_nmos w=4u l=2u ng=1 m=4\nXMA3 x x vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1\nXMA4 vbp x vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1\n* compensation: C_c on the PMOS gates, R_z and C_z across the amplifier's inputs\nXCC vbp vdd cap_cmim w=25.767u l=25.767u m=2\nXRZ vbn z 0 rhigh w=0.5u l=9.166u\nXCZ z d2 cap_cmim w=28.814u l=28.814u m=4\n* start-up: with no current vbn is low, MS2 is off, MS3 pulls su up and MS1\n* pulls the PMOS gates down; once the reference runs, MS2 turns MS1 off\nXMS3 su 0 vdd vdd sg13_lv_pmos w=150n l=20u ng=1 m=1\nXMS2 su vbn 0 0 sg13_lv_nmos w=1u l=1u ng=1 m=1\nXMS1 vbp su 0 0 sg13_lv_nmos w=1u l=500n ng=1 m=1\n* a zero-volt source as the ammeter: I_ref is the current through R1\nVr sr 0 0\n.dc temp -40 125 5\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc iref27 FIND i(Vr) AT=27\n.end" }, { "id": "powerup", "label": "Power-up", "note": "", "measures": [ "tstart" ], "metricKeys": [ "tstart" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Beta-multiplier reference (regulated) - the supply ramping up from zero\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\nVdd vdd 0 PWL(0 0 10u 1.2)\nXM3 vbn vbp vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1\nXM4 d2 vbp vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1\nXM1 vbn vbn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nXM2 d2 vbn s 0 sg13_lv_nmos w=4u l=2u ng=1 m=4\nXR1 s sr 0 rppd w=0.5u l=19.417u\n* the amplifier: M2's drain on its non-inverting input, M1's on the inverting\n* one; its tail copies M1, so the reference it regulates is what biases it\nXMT t vbn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=2\nXMA1 x d2 t 0 sg13_lv_nmos w=4u l=2u ng=1 m=4\nXMA2 vbp vbn t 0 sg13_lv_nmos w=4u l=2u ng=1 m=4\nXMA3 x x vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1\nXMA4 vbp x vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1\n* compensation: C_c on the PMOS gates, R_z and C_z across the amplifier's inputs\nXCC vbp vdd cap_cmim w=25.767u l=25.767u m=2\nXRZ vbn z 0 rhigh w=0.5u l=9.166u\nXCZ z d2 cap_cmim w=28.814u l=28.814u m=4\n* start-up: with no current vbn is low, MS2 is off, MS3 pulls su up and MS1\n* pulls the PMOS gates down; once the reference runs, MS2 turns MS1 off\nXMS3 su 0 vdd vdd sg13_lv_pmos w=150n l=20u ng=1 m=1\nXMS2 su vbn 0 0 sg13_lv_nmos w=1u l=1u ng=1 m=1\nXMS1 vbp su 0 0 sg13_lv_nmos w=1u l=500n ng=1 m=1\n* a zero-volt source as the ammeter: I_ref is the current through R1\nVr sr 0 0\n.tran 20n 30u\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas tran iref FIND i(Vr) AT=30u\n.end" }, { "id": "step", "label": "Supply step", "note": "", "measures": [ "settle" ], "metricKeys": [ "settle" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Beta-multiplier reference (regulated) - a 100 mV step on the supply\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\nVdd vdd 0 PWL(0 1.2 2u 1.2 2.01u 1.3)\nXM3 vbn vbp vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1\nXM4 d2 vbp vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1\nXM1 vbn vbn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nXM2 d2 vbn s 0 sg13_lv_nmos w=4u l=2u ng=1 m=4\nXR1 s sr 0 rppd w=0.5u l=19.417u\n* the amplifier: M2's drain on its non-inverting input, M1's on the inverting\n* one; its tail copies M1, so the reference it regulates is what biases it\nXMT t vbn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=2\nXMA1 x d2 t 0 sg13_lv_nmos w=4u l=2u ng=1 m=4\nXMA2 vbp vbn t 0 sg13_lv_nmos w=4u l=2u ng=1 m=4\nXMA3 x x vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1\nXMA4 vbp x vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1\n* compensation: C_c on the PMOS gates, R_z and C_z across the amplifier's inputs\nXCC vbp vdd cap_cmim w=25.767u l=25.767u m=2\nXRZ vbn z 0 rhigh w=0.5u l=9.166u\nXCZ z d2 cap_cmim w=28.814u l=28.814u m=4\n* start-up: with no current vbn is low, MS2 is off, MS3 pulls su up and MS1\n* pulls the PMOS gates down; once the reference runs, MS2 turns MS1 off\nXMS3 su 0 vdd vdd sg13_lv_pmos w=150n l=20u ng=1 m=1\nXMS2 su vbn 0 0 sg13_lv_nmos w=1u l=1u ng=1 m=1\nXMS1 vbp su 0 0 sg13_lv_nmos w=1u l=500n ng=1 m=1\n* a zero-volt source as the ammeter: I_ref is the current through R1\nVr sr 0 0\n.tran 1n 6u 0 2n\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas tran ibefore FIND i(Vr) AT=1.9u\n.meas tran iafter FIND i(Vr) AT=5.9u\n.end" } ], "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "0a47de6ddc131f56cf1ff71ff0a7313a5a8148025f1805c131f4d79122ab91d0" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/beta-multiplier.js", "sha256": "f1a22b7c1dfc9d317724caf672af3748aee1e565be951edd44641250096337a6" }, "simulationFingerprints": { "supply": "7aa130a10154a14e86e6930e663676ea08f15e3a28078a77e7ca5feac79b0687", "temp": "d6f061d27bd61bcdb3190f75967edc6221a380e3b55fedf516bc232fdc9adbce", "powerup": "48b857593f7242c13326adf048f8d1d9e9f2c744e8c9f89ee79245000fa635e5", "step": "7547f5567a86a5a33f7d0904e87df9bec5e53b9cca9ce55b737082b0c6f4ca65" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "c9a904340c560f0ad9afae87610c19e1d5af7c5e380d200add46e45a5413a2f8", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "beta-multiplier", "parameters": { "topology": "regulated", "startup": "on", "R": 10000, "K": 4, "Wn": 0.000004, "Ln": 0.000002, "Wp": 0.000008, "Lp": 0.000002, "Cc": 2e-12, "Rz": 30000, "Cz": 5e-12 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [ { "key": "topology", "selected": "regulated", "choices": [ { "value": "basic", "label": "basic (for comparison)" }, { "value": "regulated", "label": "regulated by an amplifier" } ] }, { "key": "startup", "selected": "on", "choices": [ { "value": "on", "label": "on" }, { "value": "off", "label": "off - to see why it is there" } ] } ], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/beta-multiplier/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [], "scopes": [ { "id": "dut", "name": "top", "ports": [ { "name": "vbn", "net": "vbn", "kind": "output" }, { "name": "vbp", "net": "vbp", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "gnd", "net": "0", "kind": "ground" }, { "name": "sr", "net": "sr", "kind": "signal" } ], "definitions": [], "devices": [ { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XM3 vbn vbp vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XM4 d2 vbp vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "vbp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XM1 vbn vbn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=4", "source": "XM2 d2 vbn s 0 sg13_lv_nmos w=4u l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "s" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR1 s sr 0 rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "s" }, { "id": "n", "net": "sr" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=2", "source": "XMT t vbn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=2", "pins": [ { "id": "d", "net": "t" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=4", "source": "XMA1 x d2 t 0 sg13_lv_nmos w=4u l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "t" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=4", "source": "XMA2 vbp vbn t 0 sg13_lv_nmos w=4u l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "vbp" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "t" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA3", "displayName": "MA3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMA3 x x vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "x" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA4", "displayName": "MA4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMA4 vbp x vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vbp" }, { "id": "g", "net": "x" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC", "displayName": "CC", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC vbp vdd cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "vbp" }, { "id": "n", "net": "vdd" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ", "displayName": "RZ", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=9.166u", "source": "XRZ vbn z 0 rhigh w=0.5u l=9.166u", "pins": [ { "id": "p", "net": "vbn" }, { "id": "n", "net": "z" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCZ", "displayName": "CZ", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=4", "source": "XCZ z d2 cap_cmim w=28.814u l=28.814u m=4", "pins": [ { "id": "p", "net": "z" }, { "id": "n", "net": "d2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMS3", "displayName": "MS3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=150n l=20u ng=1 m=1", "source": "XMS3 su 0 vdd vdd sg13_lv_pmos w=150n l=20u ng=1 m=1", "pins": [ { "id": "d", "net": "su" }, { "id": "g", "net": "0" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS2", "displayName": "MS2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=1u ng=1 m=1", "source": "XMS2 su vbn 0 0 sg13_lv_nmos w=1u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "su" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS1", "displayName": "MS1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=500n ng=1 m=1", "source": "XMS1 vbp su 0 0 sg13_lv_nmos w=1u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "vbp" }, { "id": "g", "net": "su" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "vbn", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM1", "pin": "d" }, { "device": "XM1", "pin": "g" }, { "device": "XM2", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMA2", "pin": "g" }, { "device": "XRZ", "pin": "p" }, { "device": "XMS2", "pin": "g" } ], "ports": [ "vbn" ], "voltageReferences": [] }, { "id": "vbp", "ground": false, "terminals": [ { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XMA2", "pin": "d" }, { "device": "XMA4", "pin": "d" }, { "device": "XCC", "pin": "p" }, { "device": "XMS1", "pin": "d" } ], "ports": [ "vbp" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMA3", "pin": "s" }, { "device": "XMA3", "pin": "b" }, { "device": "XMA4", "pin": "s" }, { "device": "XMA4", "pin": "b" }, { "device": "XCC", "pin": "n" }, { "device": "XMS3", "pin": "s" }, { "device": "XMS3", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM2", "pin": "d" }, { "device": "XMA1", "pin": "g" }, { "device": "XCZ", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XR1", "pin": "substrate" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "b" }, { "device": "XRZ", "pin": "substrate" }, { "device": "XMS3", "pin": "g" }, { "device": "XMS2", "pin": "s" }, { "device": "XMS2", "pin": "b" }, { "device": "XMS1", "pin": "s" }, { "device": "XMS1", "pin": "b" } ], "ports": [ "gnd" ], "voltageReferences": [] }, { "id": "s", "ground": false, "terminals": [ { "device": "XM2", "pin": "s" }, { "device": "XR1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "sr", "ground": false, "terminals": [ { "device": "XR1", "pin": "n" } ], "ports": [ "sr" ], "voltageReferences": [] }, { "id": "t", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMA1", "pin": "d" }, { "device": "XMA3", "pin": "d" }, { "device": "XMA3", "pin": "g" }, { "device": "XMA4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "z", "ground": false, "terminals": [ { "device": "XRZ", "pin": "n" }, { "device": "XCZ", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "su", "ground": false, "terminals": [ { "device": "XMS3", "pin": "d" }, { "device": "XMS2", "pin": "d" }, { "device": "XMS1", "pin": "g" } ], "ports": [], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "1.2", "source": "Vdd vdd 0 1.2", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XM3 vbn vbp vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XM4 d2 vbp vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "vbp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XM1 vbn vbn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=4", "source": "XM2 d2 vbn s 0 sg13_lv_nmos w=4u l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "s" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR1 s sr 0 rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "s" }, { "id": "n", "net": "sr" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=2", "source": "XMT t vbn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=2", "pins": [ { "id": "d", "net": "t" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=4", "source": "XMA1 x d2 t 0 sg13_lv_nmos w=4u l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "t" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=4", "source": "XMA2 vbp vbn t 0 sg13_lv_nmos w=4u l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "vbp" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "t" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA3", "displayName": "MA3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMA3 x x vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "x" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA4", "displayName": "MA4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMA4 vbp x vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vbp" }, { "id": "g", "net": "x" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC", "displayName": "CC", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC vbp vdd cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "vbp" }, { "id": "n", "net": "vdd" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ", "displayName": "RZ", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=9.166u", "source": "XRZ vbn z 0 rhigh w=0.5u l=9.166u", "pins": [ { "id": "p", "net": "vbn" }, { "id": "n", "net": "z" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCZ", "displayName": "CZ", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=4", "source": "XCZ z d2 cap_cmim w=28.814u l=28.814u m=4", "pins": [ { "id": "p", "net": "z" }, { "id": "n", "net": "d2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMS3", "displayName": "MS3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=150n l=20u ng=1 m=1", "source": "XMS3 su 0 vdd vdd sg13_lv_pmos w=150n l=20u ng=1 m=1", "pins": [ { "id": "d", "net": "su" }, { "id": "g", "net": "0" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS2", "displayName": "MS2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=1u ng=1 m=1", "source": "XMS2 su vbn 0 0 sg13_lv_nmos w=1u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "su" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS1", "displayName": "MS1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=500n ng=1 m=1", "source": "XMS1 vbp su 0 0 sg13_lv_nmos w=1u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "vbp" }, { "id": "g", "net": "su" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "Vr", "displayName": "Vr", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vr sr 0 0", "pins": [ { "id": "p", "net": "sr" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMA3", "pin": "s" }, { "device": "XMA3", "pin": "b" }, { "device": "XMA4", "pin": "s" }, { "device": "XMA4", "pin": "b" }, { "device": "XCC", "pin": "n" }, { "device": "XMS3", "pin": "s" }, { "device": "XMS3", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XR1", "pin": "substrate" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "b" }, { "device": "XRZ", "pin": "substrate" }, { "device": "XMS3", "pin": "g" }, { "device": "XMS2", "pin": "s" }, { "device": "XMS2", "pin": "b" }, { "device": "XMS1", "pin": "s" }, { "device": "XMS1", "pin": "b" }, { "device": "Vr", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM1", "pin": "d" }, { "device": "XM1", "pin": "g" }, { "device": "XM2", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMA2", "pin": "g" }, { "device": "XRZ", "pin": "p" }, { "device": "XMS2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbp", "ground": false, "terminals": [ { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XMA2", "pin": "d" }, { "device": "XMA4", "pin": "d" }, { "device": "XCC", "pin": "p" }, { "device": "XMS1", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM2", "pin": "d" }, { "device": "XMA1", "pin": "g" }, { "device": "XCZ", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "s", "ground": false, "terminals": [ { "device": "XM2", "pin": "s" }, { "device": "XR1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "sr", "ground": false, "terminals": [ { "device": "XR1", "pin": "n" }, { "device": "Vr", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "t", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMA1", "pin": "d" }, { "device": "XMA3", "pin": "d" }, { "device": "XMA3", "pin": "g" }, { "device": "XMA4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "z", "ground": false, "terminals": [ { "device": "XRZ", "pin": "n" }, { "device": "XCZ", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "su", "ground": false, "terminals": [ { "device": "XMS3", "pin": "d" }, { "device": "XMS2", "pin": "d" }, { "device": "XMS1", "pin": "g" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "top-level-device-set", "scope": "top", "devices": [ "XM3", "XM4", "XM1", "XM2", "XR1", "XMT", "XMA1", "XMA2", "XMA3", "XMA4", "XCC", "XRZ", "XCZ", "XMS3", "XMS2", "XMS1" ] } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "The diode: its drain is V_bn", "devices": [ { "scope": "dut", "device": "XM1" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "K copies of M1", "devices": [ { "scope": "dut", "device": "XM2" } ], "inferredStages": [ "bias" ] }, { "id": "block-3", "label": "Sets the current: V_GS1 - V_GS2 drops across it", "devices": [ { "scope": "dut", "device": "XR1" } ], "inferredStages": [ "bias" ] }, { "id": "block-4", "label": "Copies the current into M1", "devices": [ { "scope": "dut", "device": "XM3" } ], "inferredStages": [ "bias" ] }, { "id": "block-5", "label": "Supplies M2; the diode", "devices": [ { "scope": "dut", "device": "XM4" } ], "inferredStages": [ "bias" ] }, { "id": "block-6", "label": "Regulated only: the amplifier's tail", "devices": [ { "scope": "dut", "device": "XMT" } ], "inferredStages": [ "bias" ] }, { "id": "block-7", "label": "Regulated only: non-inverting input", "devices": [ { "scope": "dut", "device": "XMA1" } ], "inferredStages": [ "bias" ] }, { "id": "block-8", "label": "Regulated only: inverting input", "devices": [ { "scope": "dut", "device": "XMA2" } ], "inferredStages": [ "bias" ] }, { "id": "block-9", "label": "Regulated only: the amplifier's load", "devices": [ { "scope": "dut", "device": "XMA3" }, { "scope": "dut", "device": "XMA4" } ], "inferredStages": [ "bias" ] }, { "id": "block-10", "label": "Regulated only: the dominant pole", "devices": [ { "scope": "dut", "device": "XCC" } ], "inferredStages": [ "bias" ] }, { "id": "block-11", "label": "Regulated only: with C_z", "devices": [ { "scope": "dut", "device": "XRZ" } ], "inferredStages": [ "bias" ] }, { "id": "block-12", "label": "Regulated only: blocks DC", "devices": [ { "scope": "dut", "device": "XCZ" } ], "inferredStages": [ "bias" ] }, { "id": "block-13", "label": "Start-up: pulls the PMOS gates down while there is no current", "devices": [ { "scope": "dut", "device": "XMS1" } ], "inferredStages": [ "bias" ] }, { "id": "block-14", "label": "Start-up: takes MS1's gate away once V_bn rises", "devices": [ { "scope": "dut", "device": "XMS2" } ], "inferredStages": [ "bias" ] }, { "id": "block-15", "label": "Start-up: a long", "devices": [ { "scope": "dut", "device": "XMS3" } ], "inferredStages": [ "bias" ] } ], "edges": [ { "id": "net-1", "net": "vbn", "nodes": [ "block-4", "block-1", "block-2", "block-6", "block-8", "block-11", "block-14" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "vbp", "nodes": [ "block-4", "block-5", "block-8", "block-9", "block-10", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "d2", "nodes": [ "block-5", "block-2", "block-7", "block-12" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "s", "nodes": [ "block-2", "block-3" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "t", "nodes": [ "block-6", "block-7", "block-8" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "x", "nodes": [ "block-7", "block-9" ], "direction": "undirected-shared-net" }, { "id": "net-7", "net": "z", "nodes": [ "block-11", "block-12" ], "direction": "undirected-shared-net" }, { "id": "net-8", "net": "su", "nodes": [ "block-15", "block-14", "block-13" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "vbn", "net": "vbn", "kind": "output" }, { "name": "vbp", "net": "vbp", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "gnd", "net": "0", "kind": "ground" }, { "name": "sr", "net": "sr", "kind": "signal" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "PWL(0 0 10u 1.2)", "source": "Vdd vdd 0 PWL(0 0 10u 1.2)", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XM3 vbn vbp vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XM4 d2 vbp vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "vbp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XM1 vbn vbn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=4", "source": "XM2 d2 vbn s 0 sg13_lv_nmos w=4u l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "s" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR1 s sr 0 rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "s" }, { "id": "n", "net": "sr" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=2", "source": "XMT t vbn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=2", "pins": [ { "id": "d", "net": "t" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=4", "source": "XMA1 x d2 t 0 sg13_lv_nmos w=4u l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "t" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=4", "source": "XMA2 vbp vbn t 0 sg13_lv_nmos w=4u l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "vbp" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "t" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA3", "displayName": "MA3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMA3 x x vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "x" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA4", "displayName": "MA4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMA4 vbp x vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vbp" }, { "id": "g", "net": "x" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC", "displayName": "CC", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC vbp vdd cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "vbp" }, { "id": "n", "net": "vdd" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ", "displayName": "RZ", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=9.166u", "source": "XRZ vbn z 0 rhigh w=0.5u l=9.166u", "pins": [ { "id": "p", "net": "vbn" }, { "id": "n", "net": "z" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCZ", "displayName": "CZ", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=4", "source": "XCZ z d2 cap_cmim w=28.814u l=28.814u m=4", "pins": [ { "id": "p", "net": "z" }, { "id": "n", "net": "d2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMS3", "displayName": "MS3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=150n l=20u ng=1 m=1", "source": "XMS3 su 0 vdd vdd sg13_lv_pmos w=150n l=20u ng=1 m=1", "pins": [ { "id": "d", "net": "su" }, { "id": "g", "net": "0" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS2", "displayName": "MS2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=1u ng=1 m=1", "source": "XMS2 su vbn 0 0 sg13_lv_nmos w=1u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "su" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS1", "displayName": "MS1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=500n ng=1 m=1", "source": "XMS1 vbp su 0 0 sg13_lv_nmos w=1u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "vbp" }, { "id": "g", "net": "su" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "Vr", "displayName": "Vr", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vr sr 0 0", "pins": [ { "id": "p", "net": "sr" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMA3", "pin": "s" }, { "device": "XMA3", "pin": "b" }, { "device": "XMA4", "pin": "s" }, { "device": "XMA4", "pin": "b" }, { "device": "XCC", "pin": "n" }, { "device": "XMS3", "pin": "s" }, { "device": "XMS3", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XR1", "pin": "substrate" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "b" }, { "device": "XRZ", "pin": "substrate" }, { "device": "XMS3", "pin": "g" }, { "device": "XMS2", "pin": "s" }, { "device": "XMS2", "pin": "b" }, { "device": "XMS1", "pin": "s" }, { "device": "XMS1", "pin": "b" }, { "device": "Vr", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM1", "pin": "d" }, { "device": "XM1", "pin": "g" }, { "device": "XM2", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMA2", "pin": "g" }, { "device": "XRZ", "pin": "p" }, { "device": "XMS2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbp", "ground": false, "terminals": [ { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XMA2", "pin": "d" }, { "device": "XMA4", "pin": "d" }, { "device": "XCC", "pin": "p" }, { "device": "XMS1", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM2", "pin": "d" }, { "device": "XMA1", "pin": "g" }, { "device": "XCZ", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "s", "ground": false, "terminals": [ { "device": "XM2", "pin": "s" }, { "device": "XR1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "sr", "ground": false, "terminals": [ { "device": "XR1", "pin": "n" }, { "device": "Vr", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "t", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMA1", "pin": "d" }, { "device": "XMA3", "pin": "d" }, { "device": "XMA3", "pin": "g" }, { "device": "XMA4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "z", "ground": false, "terminals": [ { "device": "XRZ", "pin": "n" }, { "device": "XCZ", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "su", "ground": false, "terminals": [ { "device": "XMS3", "pin": "d" }, { "device": "XMS2", "pin": "d" }, { "device": "XMS1", "pin": "g" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "top-level-device-set", "scope": "top", "devices": [ "XM3", "XM4", "XM1", "XM2", "XR1", "XMT", "XMA1", "XMA2", "XMA3", "XMA4", "XCC", "XRZ", "XCZ", "XMS3", "XMS2", "XMS1" ] } }, { "id": "graph-5", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "PWL(0 1.2 2u 1.2 2.01u 1.3)", "source": "Vdd vdd 0 PWL(0 1.2 2u 1.2 2.01u 1.3)", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XM3 vbn vbp vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XM4 d2 vbp vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "vbp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XM1 vbn vbn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=4", "source": "XM2 d2 vbn s 0 sg13_lv_nmos w=4u l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "s" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR1 s sr 0 rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "s" }, { "id": "n", "net": "sr" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=2", "source": "XMT t vbn 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=2", "pins": [ { "id": "d", "net": "t" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=4", "source": "XMA1 x d2 t 0 sg13_lv_nmos w=4u l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "t" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=4", "source": "XMA2 vbp vbn t 0 sg13_lv_nmos w=4u l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "vbp" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "t" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA3", "displayName": "MA3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMA3 x x vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "x" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA4", "displayName": "MA4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMA4 vbp x vdd vdd sg13_lv_pmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vbp" }, { "id": "g", "net": "x" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC", "displayName": "CC", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC vbp vdd cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "vbp" }, { "id": "n", "net": "vdd" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ", "displayName": "RZ", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=9.166u", "source": "XRZ vbn z 0 rhigh w=0.5u l=9.166u", "pins": [ { "id": "p", "net": "vbn" }, { "id": "n", "net": "z" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCZ", "displayName": "CZ", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=4", "source": "XCZ z d2 cap_cmim w=28.814u l=28.814u m=4", "pins": [ { "id": "p", "net": "z" }, { "id": "n", "net": "d2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMS3", "displayName": "MS3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=150n l=20u ng=1 m=1", "source": "XMS3 su 0 vdd vdd sg13_lv_pmos w=150n l=20u ng=1 m=1", "pins": [ { "id": "d", "net": "su" }, { "id": "g", "net": "0" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS2", "displayName": "MS2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=1u ng=1 m=1", "source": "XMS2 su vbn 0 0 sg13_lv_nmos w=1u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "su" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS1", "displayName": "MS1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=500n ng=1 m=1", "source": "XMS1 vbp su 0 0 sg13_lv_nmos w=1u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "vbp" }, { "id": "g", "net": "su" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "Vr", "displayName": "Vr", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vr sr 0 0", "pins": [ { "id": "p", "net": "sr" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMA3", "pin": "s" }, { "device": "XMA3", "pin": "b" }, { "device": "XMA4", "pin": "s" }, { "device": "XMA4", "pin": "b" }, { "device": "XCC", "pin": "n" }, { "device": "XMS3", "pin": "s" }, { "device": "XMS3", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XR1", "pin": "substrate" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "b" }, { "device": "XRZ", "pin": "substrate" }, { "device": "XMS3", "pin": "g" }, { "device": "XMS2", "pin": "s" }, { "device": "XMS2", "pin": "b" }, { "device": "XMS1", "pin": "s" }, { "device": "XMS1", "pin": "b" }, { "device": "Vr", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM1", "pin": "d" }, { "device": "XM1", "pin": "g" }, { "device": "XM2", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMA2", "pin": "g" }, { "device": "XRZ", "pin": "p" }, { "device": "XMS2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbp", "ground": false, "terminals": [ { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XMA2", "pin": "d" }, { "device": "XMA4", "pin": "d" }, { "device": "XCC", "pin": "p" }, { "device": "XMS1", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM2", "pin": "d" }, { "device": "XMA1", "pin": "g" }, { "device": "XCZ", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "s", "ground": false, "terminals": [ { "device": "XM2", "pin": "s" }, { "device": "XR1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "sr", "ground": false, "terminals": [ { "device": "XR1", "pin": "n" }, { "device": "Vr", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "t", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMA1", "pin": "d" }, { "device": "XMA3", "pin": "d" }, { "device": "XMA3", "pin": "g" }, { "device": "XMA4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "z", "ground": false, "terminals": [ { "device": "XRZ", "pin": "n" }, { "device": "XCZ", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "su", "ground": false, "terminals": [ { "device": "XMS3", "pin": "d" }, { "device": "XMS2", "pin": "d" }, { "device": "XMS1", "pin": "g" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "top-level-device-set", "scope": "top", "devices": [ "XM3", "XM4", "XM1", "XM2", "XR1", "XMT", "XMA1", "XMA2", "XMA3", "XMA4", "XCC", "XRZ", "XCZ", "XMS3", "XMS2", "XMS1" ] } } ], "views": [ { "bench": "supply", "source": { "recordField": "testbenches", "id": "supply", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/beta-multiplier/supply-schematic.svg", "asset": "supply-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Beta-multiplier reference", "instances": [] } ] }, "benchDiagram": { "graph": "graph-2", "svg": { "url": "/circuits/beta-multiplier/supply-bench.svg", "asset": "supply-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/beta-multiplier/supply-block.svg", "asset": "supply-block.svg" } } }, { "bench": "temp", "source": { "recordField": "testbenches", "id": "temp", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/beta-multiplier/supply-schematic.svg", "asset": "supply-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Beta-multiplier reference", "instances": [] } ] }, "benchDiagram": { "graph": "graph-2", "svg": { "url": "/circuits/beta-multiplier/supply-bench.svg", "asset": "supply-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/beta-multiplier/supply-block.svg", "asset": "supply-block.svg" } } }, { "bench": "powerup", "source": { "recordField": "testbenches", "id": "powerup", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/beta-multiplier/supply-schematic.svg", "asset": "supply-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Beta-multiplier reference", "instances": [] } ] }, "benchDiagram": { "graph": "graph-4", "svg": { "url": "/circuits/beta-multiplier/powerup-bench.svg", "asset": "powerup-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/beta-multiplier/supply-block.svg", "asset": "supply-block.svg" } } }, { "bench": "step", "source": { "recordField": "testbenches", "id": "step", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/beta-multiplier/supply-schematic.svg", "asset": "supply-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Beta-multiplier reference", "instances": [] } ] }, "benchDiagram": { "graph": "graph-5", "svg": { "url": "/circuits/beta-multiplier/powerup-bench.svg", "asset": "powerup-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/beta-multiplier/supply-block.svg", "asset": "supply-block.svg" } } } ] } }