{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "mixed-signal", "id": "capdac", "name": "Charge-redistribution DAC", "group": "Data converters", "subgroup": "DACs", "title": "Charge-redistribution DAC", "summary": "This DAC converts a binary number into a voltage by sharing charge between capacitors. Each bit controls a different capacitor weight. Capacitor mismatch makes the steps unequal; a fixed capacitance on the shared output mainly reduces the voltage scale.", "reference": { "kind": "paper", "authors": "J. L. McCreary and P. R. Gray", "title": "All-MOS charge redistribution analog-to-digital conversion techniques - Part I", "publisher": "IEEE Journal of Solid-State Circuits, vol. SC-10, no. 6", "year": 1975, "where": "the binary-weighted array, its termination capacitor and the effect of top-plate parasitic", "takes": "The array itself, and the separation this bench measures: parasitic costs full scale, mismatch costs linearity." }, "resources": { "record": "/circuits/capdac.json", "page": "/index.html#capdac", "achieved": "/achieved/capdac.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_passive_tt.spice" ], "ports": [ { "name": "top", "kind": "output", "note": "common top plate" }, { "name": "b0..bN-1", "kind": "control", "note": "bottom plates, driven to V_ref or ground" }, { "name": "0", "kind": "ground", "note": "termination capacitor and substrate reference" } ], "devices": [ { "name": "C0..CN-1", "type": "capacitor", "sizedBy": [ "Cu", "bits" ], "role": "binary-weighted array, C_k = 2^k * C_u" }, { "name": "Cterm", "type": "capacitor", "sizedBy": [ "Cu" ], "role": "termination, makes the total 2^N * C_u" }, { "name": "Cpar", "type": "capacitor", "sizedBy": [ "Cpar" ], "role": "top-plate parasitic" } ], "intent": [ { "rule": "unit-cells", "of": [ "C0..CN-1" ], "constraint": "C_k = 2^k * C_u; identical unit cells are a physical-layout recommendation", "why": "The user-added mismatch model assumes independent unit errors, so relative sigma falls as 1/sqrt(2^k). The generated deck represents each weight with equivalent square MIM capacitance, not an implemented unit-cell layout. A physical unit-cell array needs its own placement, routing, matching and extracted-parasitic checks; larger area alone does not remove systematic gradients." }, { "rule": "termination", "of": [ "Cterm" ], "constraint": "C_term = C_u, making the total 2^N * C_u", "why": "Without it the full scale is V_ref*(2^N-1)/(2^N-1) rather than a clean binary fraction, and the LSB step is wrong." }, { "rule": "gain-vs-linearity", "of": [ "Cpar" ], "constraint": "a linear, code-independent top-plate capacitance attenuates every code equally", "why": "It reduces full scale without changing endpoint-fit DNL and INL after gain error is removed. This approximation does not cover voltage-dependent or code-dependent parasitics." } ], "specs": [ { "key": "lsb", "label": "LSB size", "unit": "V", "direction": "target" }, { "key": "dnl", "label": "Max |DNL|", "unit": "LSB", "direction": "min" }, { "key": "inl", "label": "Max |INL|", "unit": "LSB", "direction": "min" }, { "key": "ctot", "label": "Total array capacitance", "unit": "F", "direction": "min" } ], "explanation": { "idea": "This DAC converts a binary number into a voltage by sharing charge between capacitors. Each bit controls a different capacitor weight. Capacitor mismatch makes the steps unequal; a fixed capacitance on the shared output mainly reduces the voltage scale.", "detail": "Turns a digital code into a voltage by charge sharing: the array at the heart of a SAR converter. Each bit drives the bottom plate of a binary-weighted capacitor to V_ref or ground, and the common top plate settles at the capacitance-weighted average of the bottom plates, ideally V_ref·code/2^N. Exact linear capacitors give equal ideal steps. Mismatch changes their relative sizes; a linear, code-independent top-plate capacitance mainly scales the transfer, without changing endpoint-fit linearity after gain error is removed. The deck represents equivalent square MIM capacitors; an identical-unit physical array remains a layout recommendation, not an implemented layout.", "lesson": { "relation": 1, "symbols": "LSB is the ideal voltage step; V_ref is the reference level; C_u is unit capacitance; N is the number of bits; C_par is a fixed capacitance from the top plate to ground.", "assumptions": "The equation assumes exact binary weights, a fixed linear C_par, known initial charge and fully settled ideal bottom-plate drives. Real capacitor ratios and voltage-dependent parasitics can change the result.", "exercise": { "param": "Cpar", "value": 2e-13, "analysis": "transfer", "expect": "Full scale and the voltage step should shrink. Endpoint-fit DNL and INL should remain small in LSB because their calculation removes the common gain error; numerical and physical residuals can still change." }, "limits": "The bench supplies ideal bit drivers. Its 10 GΩ output resistor is a numerical DC path, not a validated physical device. A usable DAC or ADC also needs initialization, switches, reference drive and extracted-layout checks; Unit-cap σ is additional user-controlled mismatch, not a layout certification." }, "path": [ { "part": "Bit drivers", "devices": "Vb0..VbN-1", "does": "The bench's sources count in binary, one code per nanosecond, switching each bottom plate b_k between ground and V_ref, so one transient walks every code." }, { "part": "Binary array", "devices": "C0..CN-1", "does": "Capacitor k is 2^k·C_unit, its mismatch drawn as for 2^k unit cells; moving its bottom plate by V_ref moves the top plate by V_ref·C_k/C_total." }, { "part": "Termination", "devices": "Cterm", "does": "One more unit to ground makes the ideal array total 2^N·C_unit. With exact ratios and negligible extra top-plate capacitance, each step is V_ref/2^N and full scale is V_ref·(2^N − 1)/2^N." }, { "part": "Top plate", "devices": "Cpar, Rt", "does": "The shared top plate is the output; Cpar, zero by default, is an ideal surrogate for capacitance to ground, and Rt, 10 GΩ, only gives the simulator a DC path. Neither is a separately validated physical device to copy into a layout." } ], "bias": "Nothing is biased: charge sharing alone sets the output, with V_ref (1.2 V by default) the only reference, applied by the bench's drivers. Rt holds the floating top plate at 0 V at DC, and its time constant, milliseconds, is far longer than the sweep.", "relations": [ { "what": "Output", "expr": "v_top = V_ref·Σ b_k·C_k/(C_total + C_par)", "note": "ideal linear charge sharing; with exact units and C_par = 0, V_ref·code/2^N. Physical parasitics and transient measurement can leave residual error." }, { "what": "LSB", "expr": "LSB = V_ref·C_u/(2^N·C_u + C_par)", "note": "18.75 mV at the defaults; C_par shrinks every step alike, a gain error" }, { "what": "Unit-cell spread", "expr": "σ_C,k/C_k = σ_u/√(2^k)", "note": "σ_u is Unit-cap σ; 2^k cells average, yet the MSB has the largest absolute error" }, { "what": "DNL at mid-scale", "expr": "σ_DNL ≈ σ_u·√(2^N − 1)", "note": "in LSB: at the MSB transition the largest capacitor is exchanged for all the others" }, { "what": "Total capacitance", "expr": "C_total = 2^N·C_u", "note": "1.28 pF at the defaults; it doubles per bit, in area and drive energy" } ], "tradeoffs": [ "Resolution: each extra bit halves the LSB and doubles C_total, while the DNL spread at the MSB step grows as √(2^N).", "C_unit: alone it cancels from the ratio; a larger unit shrinks the top-plate parasitic's gain error and, on silicon, mismatch, at the cost of area.", "Fixed linear top-plate capacitance: scales every code by 2^N·C_u/(2^N·C_u + C_par), costing full scale while leaving endpoint-fit DNL and INL approximately unchanged after gain error is removed. Voltage-dependent or code-dependent parasitics need separate analysis.", "Unit-cap σ: DNL and INL scale with it; the worst DNL is at the MSB transition, and below −1 LSB a step runs backwards." ] }, "sizing": [ { "key": "bits", "label": "Resolution", "unit": "bit", "value": 6, "min": 3, "max": 9, "kind": "int" }, { "key": "Cu", "label": "C_unit", "unit": "F", "value": 2e-14, "min": 1e-14, "max": 1e-13, "kind": "si" }, { "key": "Cpar", "label": "Top-plate parasitic", "unit": "F", "value": 0, "min": 0, "max": 1e-12, "kind": "si" }, { "key": "mismatch", "label": "Unit-cap σ", "unit": "%", "value": 0, "min": 0, "max": 10, "kind": "si" }, { "key": "seed", "label": "Mismatch seed", "unit": "", "value": 1, "min": 1, "max": 999, "kind": "int" }, { "key": "vref", "label": "V_ref", "unit": "V", "value": 1.2, "min": 0.2, "max": 1.2, "kind": "si" } ], "testbenches": [ { "id": "transfer", "label": "Transfer and linearity", "note": "", "measures": [ "lsb", "dnl", "inl", "ctot" ], "metricKeys": [ "fs", "lsb", "ctot", "dnl", "inl" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_passive_tt.spice" ], "netlist": "* Binary-weighted charge-redistribution DAC, 6 bits\n.include sg13g2_passive_tt.spice\n* One transient walks every code: the bit drivers are a binary counter.\nVb0 b0 0 pulse(0 1.2 1n 10p 10p 1n 2n)\nVb1 b1 0 pulse(0 1.2 2n 10p 10p 2n 4n)\nVb2 b2 0 pulse(0 1.2 4n 10p 10p 4n 8n)\nVb3 b3 0 pulse(0 1.2 8n 10p 10p 8n 16n)\nVb4 b4 0 pulse(0 1.2 16n 10p 10p 16n 32n)\nVb5 b5 0 pulse(0 1.2 32n 10p 10p 32n 64n)\n* the array - bottom plates driven, top plate common\nXC0 b0 top cap_cmim w=3.599u l=3.599u\nXC1 b1 top cap_cmim w=5.111u l=5.111u\nXC2 b2 top cap_cmim w=7.25u l=7.25u\nXC3 b3 top cap_cmim w=10.275u l=10.275u\nXC4 b4 top cap_cmim w=14.553u l=14.553u\nXC5 b5 top cap_cmim w=20.603u l=20.603u\nXCterm top 0 cap_cmim w=3.599u l=3.599u\n* the top plate is otherwise floating; ngspice needs a DC path to it. 10 G,\n* not more: 1 T is a conductance the size of ngspice's own current tolerance,\n* and the MIM model's internal nodes then move the operating point by 15 mV.\n* 10 G pins it to 0.1 mV and is still 10 ms of time constant against the sweep.\nRt top 0 10g\n.tran 50p 64n\n.end" } ], "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "6e7b6badd528807dacffd1d1eee209814d7354b4b5210e5fb8bef212c8d649ad" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/capdac.js", "sha256": "b6639405f90475f0b722fd0a2b69e3c42c0fff0ff255a348821f613f60a4aca5" }, "simulationFingerprints": { "transfer": "31dc0616df37aca81a99c670c06954076fd3a65a8b22f73c6ee1b1be0e10a792" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "9afe79ceb8367eacbbc0af652db654c7510c98a58047b641bc783ab0f970ab46", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "capdac", "parameters": { "bits": 6, "Cu": 2e-14, "Cpar": 0, "mismatch": 0, "seed": 1, "vref": 1.2 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/capdac/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [], "scopes": [ { "id": "dut", "name": "top", "ports": [ { "name": "b0", "net": "b0", "kind": "control" }, { "name": "top", "net": "top", "kind": "output" }, { "name": "b1", "net": "b1", "kind": "control" }, { "name": "b2", "net": "b2", "kind": "control" }, { "name": "b3", "net": "b3", "kind": "control" }, { "name": "b4", "net": "b4", "kind": "control" }, { "name": "b5", "net": "b5", "kind": "control" }, { "name": "gnd", "net": "0", "kind": "ground" } ], "definitions": [], "devices": [ { "id": "XC0", "displayName": "C0", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=3.599u l=3.599u", "source": "XC0 b0 top cap_cmim w=3.599u l=3.599u", "pins": [ { "id": "p", "net": "b0" }, { "id": "n", "net": "top" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC1", "displayName": "C1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=5.111u l=5.111u", "source": "XC1 b1 top cap_cmim w=5.111u l=5.111u", "pins": [ { "id": "p", "net": "b1" }, { "id": "n", "net": "top" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC2", "displayName": "C2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=7.25u l=7.25u", "source": "XC2 b2 top cap_cmim w=7.25u l=7.25u", "pins": [ { "id": "p", "net": "b2" }, { "id": "n", "net": "top" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC3", "displayName": "C3", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=10.275u l=10.275u", "source": "XC3 b3 top cap_cmim w=10.275u l=10.275u", "pins": [ { "id": "p", "net": "b3" }, { "id": "n", "net": "top" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC4", "displayName": "C4", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=14.553u l=14.553u", "source": "XC4 b4 top cap_cmim w=14.553u l=14.553u", "pins": [ { "id": "p", "net": "b4" }, { "id": "n", "net": "top" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC5", "displayName": "C5", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=20.603u l=20.603u", "source": "XC5 b5 top cap_cmim w=20.603u l=20.603u", "pins": [ { "id": "p", "net": "b5" }, { "id": "n", "net": "top" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCterm", "displayName": "Cterm", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=3.599u l=3.599u", "source": "XCterm top 0 cap_cmim w=3.599u l=3.599u", "pins": [ { "id": "p", "net": "top" }, { "id": "n", "net": "0" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "b0", "ground": false, "terminals": [ { "device": "XC0", "pin": "p" } ], "ports": [ "b0" ], "voltageReferences": [] }, { "id": "top", "ground": false, "terminals": [ { "device": "XC0", "pin": "n" }, { "device": "XC1", "pin": "n" }, { "device": "XC2", "pin": "n" }, { "device": "XC3", "pin": "n" }, { "device": "XC4", "pin": "n" }, { "device": "XC5", "pin": "n" }, { "device": "XCterm", "pin": "p" } ], "ports": [ "top" ], "voltageReferences": [] }, { "id": "b1", "ground": false, "terminals": [ { "device": "XC1", "pin": "p" } ], "ports": [ "b1" ], "voltageReferences": [] }, { "id": "b2", "ground": false, "terminals": [ { "device": "XC2", "pin": "p" } ], "ports": [ "b2" ], "voltageReferences": [] }, { "id": "b3", "ground": false, "terminals": [ { "device": "XC3", "pin": "p" } ], "ports": [ "b3" ], "voltageReferences": [] }, { "id": "b4", "ground": false, "terminals": [ { "device": "XC4", "pin": "p" } ], "ports": [ "b4" ], "voltageReferences": [] }, { "id": "b5", "ground": false, "terminals": [ { "device": "XC5", "pin": "p" } ], "ports": [ "b5" ], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "XCterm", "pin": "n" } ], "ports": [ "gnd" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vb0", "displayName": "Vb0", "spiceType": "V", "model": null, "parametersOrValue": "pulse(0 1.2 1n 10p 10p 1n 2n)", "source": "Vb0 b0 0 pulse(0 1.2 1n 10p 10p 1n 2n)", "pins": [ { "id": "p", "net": "b0" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vb1", "displayName": "Vb1", "spiceType": "V", "model": null, "parametersOrValue": "pulse(0 1.2 2n 10p 10p 2n 4n)", "source": "Vb1 b1 0 pulse(0 1.2 2n 10p 10p 2n 4n)", "pins": [ { "id": "p", "net": "b1" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vb2", "displayName": "Vb2", "spiceType": "V", "model": null, "parametersOrValue": "pulse(0 1.2 4n 10p 10p 4n 8n)", "source": "Vb2 b2 0 pulse(0 1.2 4n 10p 10p 4n 8n)", "pins": [ { "id": "p", "net": "b2" }, { "id": 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