{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "cascode-mirror", "name": "Cascode current mirrors", "group": "Mirrors, bias and references", "subgroup": "Current mirrors", "title": "Cascode current mirrors", "summary": "Copies a current more accurately as the output voltage changes. A transistor stacked above the output device keeps its drain voltage nearly constant. This improves output resistance but needs extra voltage; the wide-swing option recovers some range using a second reference current.", "reference": { "kind": "book", "authors": "B. Razavi", "title": "Design of Analog CMOS Integrated Circuits", "edition": "2nd ed.", "publisher": "McGraw-Hill", "year": 2017, "where": "Current Mirrors - cascode current mirrors, and the low-voltage cascode that biases the cascodes separately", "takes": "The two topologies, the output resistance a cascode gives (about g_m r_o times the output device's r_o), and the headroom each needs.", "also": [ { "authors": "T. Chan Carusone, D. A. Johns and K. W. Martin", "title": "Analog Integrated Circuit Design", "edition": "2nd ed.", "year": 2012, "where": "Current mirrors - the wide-swing cascode mirror and the choice of its bias transistor" } ] }, "resources": { "record": "/circuits/cascode-mirror.json", "page": "/index.html#cascode-mirror", "achieved": "/achieved/cascode-mirror.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice" ], "ports": [ { "name": "ref", "kind": "input", "note": "carries I_ref" }, { "name": "out", "kind": "output" }, { "name": "vb", "kind": "bias", "note": "wide-swing option only: inject a second I_ref into the Mb1..MbK cascode-bias stack; unused in the simple and cascode options" }, { "name": "vdd", "kind": "supply" }, { "name": "0", "kind": "ground" } ], "devices": [ { "name": "M1", "type": "nmos", "sizedBy": [ "W", "L" ], "role": "reference device", "fingers": 1, "copies": 1 }, { "name": "M2", "type": "nmos", "sizedBy": [ "W", "L" ], "role": "output device, a copy of M1", "fingers": 1, "copies": 1 }, { "name": "M3", "type": "nmos", "sizedBy": [ "W", "L", "topology" ], "role": "reference-side cascode (cascode and wide-swing only)", "fingers": 1, "copies": 1 }, { "name": "M4", "type": "nmos", "sizedBy": [ "W", "L", "topology" ], "role": "output cascode, shielding M2's drain (cascode and wide-swing only)", "fingers": 1, "copies": 1 }, { "name": "Mb1..MbK", "type": "nmos", "sizedBy": [ "W", "L", "K" ], "role": "wide-swing only: the cascode bias, K unit devices in series fed a second I_ref" } ], "intent": [ { "rule": "unit-devices", "of": [ "M1", "M2", "M3", "M4", "Mb1..MbK" ], "why": "Repeated unit devices avoid changing nominal threshold through different geometry; mismatch and unequal drain voltages still cause copy error. This wide-swing design uses K units in series to approximate a longer bias device. The stack retains unit geometry but body effect and finite drain voltage make the equivalence approximate." }, { "rule": "cascode", "of": [ "M4", "M2" ], "constraint": "R_out ~ g_m4 r_o4 r_o2", "why": "The cascode holds M2's drain still while the output moves, so M2's current no longer follows the output voltage: at V_out = 1.0 V the cascode's output resistance is 13 MΩ against the simple mirror's 0.49 MΩ, and it copies 10 µA to within 0.2 % where the simple mirror is 16 % high." }, { "rule": "headroom", "of": [ "M3", "M4" ], "constraint": "cascode: V_out,min ~ 2 V_GS - V_th; wide-swing: ~ 2 V_ov", "why": "The cascode mirror stacks two diodes: its reference input sits at 0.82 V, leaving the source that feeds it 0.38 V, and its output resistance only reaches half its full value above 0.59 V. That is why the unit is 4 µm wide: at 2 µm its overdrive is 0.24 V, the reference input sits at 1.0 V, and at the slow corner with the supply 10 % low it rises to 1.10 V, above the 1.08 V supply - no real current source could feed it. The wide-swing mirror biases the cascodes from a separate stack instead: its reference input sits at 0.39 V and its knee at 0.47 V - 0.12 V more swing, for a second reference current." }, { "rule": "bias-margin", "of": [ "Mb1..MbK", "M1", "M3" ], "constraint": "K = 4 in the square law; more in moderate inversion", "why": "In the square law a bias device four times longer puts M2 exactly at the edge of saturation. At 10 µA these 4/2 µm devices are in moderate inversion, where the saturation voltage exceeds the overdrive, and M4's source sits above ground, which raises its threshold: four is too few. The output resistance is 4.9 MΩ with K = 4, 9.6 MΩ with 5 and 11.8 MΩ with 6, for knees at 0.51, 0.49 and 0.47 V; 7 and 8 add at most 1.1 MΩ and move the knee back up. Six leaves M2 49 mV above its saturation voltage. The reference side cannot do as well: M1's margin and M3's add up to V_GS1 - V_DSAT1 - V_DSAT3, only 17 mV, so K = 6 leaves M1 32 mV in and M3 16 mV into triode. M3 only holds M1's drain level with M2's, and still does to 17 mV: a 0.8 % copy error." } ], "specs": [ { "key": "iout", "label": "Output current", "unit": "A", "direction": "target" }, { "key": "rout", "label": "Output resistance", "unit": "Ω", "direction": "max" }, { "key": "vmin", "label": "Compliance voltage", "unit": "V", "direction": "min" } ], "explanation": { "idea": "Copies a current more accurately as the output voltage changes. A transistor stacked above the output device keeps its drain voltage nearly constant. This improves output resistance but needs extra voltage; the wide-swing option recovers some range using a second reference current.", "detail": "A current mirror with a second transistor stacked on the output device. The cascode M4 holds M2's drain nearly still while the output moves, so M2's current changes less with the output and the output resistance rises by M4's intrinsic gain, g_m4 r_o4. The price is headroom: two stacked diodes put the reference input two V_GS up. The wide-swing topology biases the cascodes from a separate stack instead, buying most of that swing back for a second reference current.", "lesson": { "relation": 0, "symbols": "R_out is output resistance; g_m4 is M4's small-signal transconductance; r_o4 and r_o2 are the devices' small-signal output resistances.", "assumptions": "Low-frequency approximation with M2 and M4 saturated and g_m4 r_o4 much larger than one. Bias, body effect and mismatch cause departures.", "exercise": { "param": "topology", "value": "simple", "analysis": "dc", "expect": "Removing the cascode should lower output resistance and allow operation at a lower output voltage. Compare both plots, not just the current at one point." }, "limits": "Cascode operation needs output and reference-source headroom. The wide-swing option also needs a second externally supplied reference current." }, "path": [ { "part": "Reference stack", "devices": "M1, M3", "does": "I_ref flows through M3 into M1, setting M1's V_GS; in the cascode topology both are diodes, which puts ref two V_GS above ground." }, { "part": "Output device", "devices": "M2", "does": "Shares M1's gate, so it approximately copies I_ref; matching drain voltages reduces systematic error." }, { "part": "Output cascode", "devices": "M4", "does": "Its gate tied to M3's, it holds M2's drain at M1's while the output moves, multiplying M2's r_o by g_m4 r_o4." }, { "part": "Wide-swing bias", "devices": "Mb1..MbK", "does": "Wide-swing only: a second I_ref through K unit devices in series sets vb, a V_GS plus about one overdrive, for both cascode gates." } ], "bias": "One I_ref (10 µA by default) sets every gate, and every device is a copy of one unit, 4 µm/2 µm by default, so equal drain voltages improve its nominal copy accuracy; the wide-swing topology draws a second I_ref for its bias stack. Feed that additional reference current into vb in the wide-swing option; it is supplied by the bench, not generated inside the mirror.", "relations": [ { "what": "Output resistance", "expr": "R_out ≈ g_m4 r_o4 · r_o2", "note": "against r_o2 for the simple mirror; holds only while M2 and M4 are both saturated" }, { "what": "Compliance, cascode", "expr": "V_out,min ≈ V_GS1 + V_GS3 − V_TH4 ≈ V_TH + 2 V_ov", "note": "the reference input sits two V_GS up, a threshold more than the devices need" }, { "what": "Compliance, wide-swing", "expr": "V_out,min ≈ √K · V_ov", "note": "square law, with M2 left at V_DS2 ≈ (√K − 1) V_ov: K = 4 is the edge of saturation" }, { "what": "Bias stack", "expr": "V_b ≈ V_TH + √K · V_ov", "note": "K units in series approximate a longer device; body effect and finite drain voltages modify the result; moderate inversion needs K above 4 (6 by default)" } ], "tradeoffs": [ "Topology: cascode multiplies R_out by about g_m r_o over simple but costs a threshold of headroom; wide-swing buys most back for a second I_ref.", "Bias stack, units in series: fewer units lower the knee but push M2 out of saturation, so R_out falls; more units waste swing.", "L (unit): longer raises r_o, which enters the cascode's R_out twice, but raises V_ov and every knee with it, and costs area.", "I_ref: more current raises V_ov, moving every knee up, and lowers r_o, so R_out falls." ] }, "sizing": [ { "key": "topology", "label": "Topology", "unit": "", "value": "cascode", "kind": "choice", "choices": [ [ "simple", "simple (for comparison)" ], [ "cascode", "cascode" ], [ "wide", "wide-swing cascode" ] ] }, { "key": "Iref", "label": "I_ref", "unit": "A", "value": 0.00001, "min": 1e-7, "max": 0.001, "kind": "si" }, { "key": "W", "label": "W (unit)", "unit": "m", "value": 0.000004, "min": 1.5e-7, "max": 0.0001, "kind": "si" }, { "key": "L", "label": "L (unit)", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.00001, "kind": "si" }, { "key": "K", "label": "Bias stack, units in series", "unit": "", "value": 6, "min": 2, "max": 10, "kind": "int" } ], "testbenches": [ { "id": "dc", "label": "Output characteristic", "note": "", "measures": [ "iout", "rout", "vmin" ], "metricKeys": [ "iout", "err", "rout", "vmin", "vin" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Cascode NMOS current mirror - output current against output voltage\n.include sg13g2_lv_tt.spice\nVdd vdd 0 1.2\nIref vdd ref 10u\n* the cascode mirror: a diode on a diode, the reference input two V_GS up\nXM1 a a 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nXM3 ref ref a 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nXM2 b a 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nXM4 out ref b 0 sg13_lv_nmos w=4u l=2u ng=1 m=1\nVout out 0 0\n.dc Vout 0 1.2 0.005\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc iout FIND i(Vout) AT=1\n.end" } ], "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "fa940e3318281c451c2223758f4f094e32510775868446fffdf17629853cdda8" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/cascode-mirror.js", "sha256": "b2b051ec5c94cdc01cbd9e51bcffffde0441cd6cd8bfef7e471e380aeed3cfbf" }, "simulationFingerprints": { "dc": "3c6c44475f0759bc4e9675ade5ff8db5af5f9dbcfa758c1eeb2d1761d90462c5" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "20c75f8faa3c3a25e3cd00b21b34d94e4f426ea72357327155d784a02daf0cb2", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "cascode-mirror", "parameters": { "topology": "cascode", "Iref": 0.00001, "W": 0.000004, "L": 0.000002, "K": 6 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [ { "key": "topology", "selected": "cascode", "choices": [ { "value": "simple", "label": "simple (for comparison)" }, { "value": "cascode", "label": "cascode" }, { "value": "wide", "label": "wide-swing cascode" } ] } ], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/cascode-mirror/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [], "scopes": [ { "id": "dut", "name": "top", "ports": [ { "name": "gnd", "net": "0", "kind": "ground" }, { "name": "ref", "net": "ref", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" } ], "definitions": [], "devices": [ { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XM1 a a 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "a" }, { "id": "g", "net": "a" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XM3 ref ref a 0 sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "ref" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "a" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XM2 b a 0 0 sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "b" }, { "id": "g", "net": "a" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XM4 out ref b 0 sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "b" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "a", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM1", "pin": "g" }, { "device": "XM3", "pin": "s" }, { "device": "XM2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM3", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" }, { "device": "XM4", "pin": "b" } ], "ports": [ "gnd" ], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "b", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. 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Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. 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