{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "chopper-ota-core", "name": "Chopper OTA core, common mode set from outside", "group": "Fully differential", "subgroup": "Op amps and OTA cores", "title": "Chopper OTA core, common mode set from outside", "summary": "This is the amplifier core used inside a chopper amplifier. Two gain stages are separated by switches that can reverse the signal polarity. Here the switches stay in one position, and an ideal testbench loop sets the output average; a complete design needs real common-mode control.", "reference": { "kind": "paper", "authors": "Q. Fan, F. Sebastiano, J. H. Huijsing, K. A. A. Makinwa", "title": "A 1.8 uW 60 nV/sqrt(Hz) Capacitively-Coupled Chopper Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor Nodes", "year": 2011, "where": "IEEE Journal of Solid-State Circuits, 46(7):1534-1543", "doi": "10.1109/JSSC.2011.2143610", "takes": "The OTA's architecture: a PMOS-input folded-cascode first stage, the output chopper placed between the two stages, a Miller-compensated second stage. The sizing, the bias network and the cascode biasing are this library's, for SG13G2 at 1.2 V." }, "resources": { "record": "/circuits/chopper-ota-core.json", "page": "/index.html#chopper-ota-core", "achieved": "/achieved/chopper-ota-core.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "inp", "kind": "input" }, { "name": "inn", "kind": "input" }, { "name": "outp", "kind": "output" }, { "name": "outn", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the reference current, drawn out of this pin" }, { "name": "cmc", "kind": "bias", "note": "common-mode control: the diode ML that the first-stage loads M7, M8 copy; a CMFB draws Ib from it, plus its correction - here the bench's ideal one" }, { "name": "clk", "kind": "clock", "note": "high: the output chopper straight" }, { "name": "clkb", "kind": "clock", "note": "high: the output chopper crossed" } ], "devices": [ { "name": "MB", "type": "pmos", "nodes": "ib ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "bias reference, diode-connected: Ib flows out of pin ib through it", "fingers": 2, "copies": 1 }, { "name": "MB1", "type": "pmos", "nodes": "nb ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "bias, a copy of Ib into the NMOS reference", "fingers": 2, "copies": 1 }, { "name": "MB2", "type": "nmos", "nodes": "nb nb vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "bias, the NMOS reference diode", "fingers": 2, "copies": 1 }, { "name": "MB3", "type": "pmos", "nodes": "vcp vcp vdd vdd", "sizedBy": [ "Wdp", "Ldp" ], "role": "bias, long diode setting the PMOS cascode gate", "fingers": 1, "copies": 1 }, { "name": "MB4", "type": "nmos", "nodes": "vcp nb vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "bias, the current through MB3", "fingers": 2, "copies": 1 }, { "name": "MB5", "type": "pmos", "nodes": "vcn ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "bias, the current through MB6", "fingers": 2, "copies": 1 }, { "name": "MB6", "type": "nmos", "nodes": "vcn vcn vss vss", "sizedBy": [ "Wdn", "Ldn" ], "role": "bias, long diode setting the NMOS cascode gate", "fingers": 1, "copies": 1 }, { "name": "MT", "type": "pmos", "nodes": "tail ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "tail current source, two copies of MB", "fingers": 2, "copies": 2 }, { "name": "M1", "type": "pmos", "nodes": "f1 inp tail vdd", "sizedBy": [ "W1", "L1" ], "role": "input pair, non-inverting side", "fingers": 4, "copies": 1 }, { "name": "M2", "type": "pmos", "nodes": "f2 inn tail vdd", "sizedBy": [ "W1", "L1" ], "role": "input pair, inverting side", "fingers": 4, "copies": 1 }, { "name": "M3", "type": "nmos", "nodes": "f1 nb vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "fold current sink, two NMOS units", "fingers": 2, "copies": 2 }, { "name": "M4", "type": "nmos", "nodes": "f2 nb vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "fold current sink, two NMOS units", "fingers": 2, "copies": 2 }, { "name": "M5", "type": "nmos", "nodes": "o1 vcn f1 vss", "sizedBy": [ "Wcn", "Lcn" ], "role": "NMOS cascode", "fingers": 2, "copies": 1 }, { "name": "M6", "type": "nmos", "nodes": "o2 vcn f2 vss", "sizedBy": [ "Wcn", "Lcn" ], "role": "NMOS cascode", "fingers": 2, "copies": 1 }, { "name": "M7", "type": "pmos", "nodes": "k1 cmc vdd vdd", "sizedBy": [ "Wl", "Ll" ], "role": "first-stage load, its gate the common-mode control", "fingers": 4, "copies": 1 }, { "name": "M8", "type": "pmos", "nodes": "k2 cmc vdd vdd", "sizedBy": [ "Wl", "Ll" ], "role": "first-stage load, its gate the common-mode control", "fingers": 4, "copies": 1 }, { "name": "M9", "type": "pmos", "nodes": "o1 vcp k1 vdd", "sizedBy": [ "Wcp", "Lcp" ], "role": "PMOS cascode", "fingers": 2, "copies": 1 }, { "name": "M10", "type": "pmos", "nodes": "o2 vcp k2 vdd", "sizedBy": [ "Wcp", "Lcp" ], "role": "PMOS cascode", "fingers": 2, "copies": 1 }, { "name": "ML", "type": "pmos", "nodes": "cmc cmc vdd vdd", "sizedBy": [ "Wl", "Ll" ], "role": "the diode M7 and M8 copy: a CMFB draws its current", "fingers": 4, "copies": 1 }, { "name": "SO1", "type": "nmos", "nodes": "o1 clk g1 vss", "sizedBy": [ "Wso", "Lso" ], "role": "output chopper, straight while clk is high", "fingers": 1, "copies": 1 }, { "name": "SO2", "type": "nmos", "nodes": "o2 clk g2 vss", "sizedBy": [ "Wso", "Lso" ], "role": "output chopper, straight while clk is high", "fingers": 1, "copies": 1 }, { "name": "SO3", "type": "nmos", "nodes": "o1 clkb g2 vss", "sizedBy": [ "Wso", "Lso" ], "role": "output chopper, crossed while clkb is high", "fingers": 1, "copies": 1 }, { "name": "SO4", "type": "nmos", "nodes": "o2 clkb g1 vss", "sizedBy": [ "Wso", "Lso" ], "role": "output chopper, crossed while clkb is high", "fingers": 1, "copies": 1 }, { "name": "M11", "type": "nmos", "nodes": "outp g1 vss vss", "sizedBy": [ "W2", "L2", "N2" ], "role": "second stage, common source; N2 copies of its unit", "fingers": 1, "copies": 4 }, { "name": "M12", "type": "nmos", "nodes": "outn g2 vss vss", "sizedBy": [ "W2", "L2", "N2" ], "role": "second stage, common source; N2 copies of its unit", "fingers": 1, "copies": 4 }, { "name": "M13", "type": "pmos", "nodes": "outp ib vdd vdd", "sizedBy": [ "Wp", "Lp", "N2" ], "role": "second-stage current source, N2 copies of MB", "fingers": 2, "copies": 4 }, { "name": "M14", "type": "pmos", "nodes": "outn ib vdd vdd", "sizedBy": [ "Wp", "Lp", "N2" ], "role": "second-stage current source, N2 copies of MB", "fingers": 2, "copies": 4 }, { "name": "CC1", "type": "capacitor", "nodes": "g1 z1", "sizedBy": [ "Cc" ], "role": "Miller compensation" }, { "name": "CC2", "type": "capacitor", "nodes": "g2 z2", "sizedBy": [ "Cc" ], "role": "Miller compensation" }, { "name": "RZ1", "type": "resistor", "nodes": "z1 outp", "sizedBy": [ "Rz" ], "role": "nulling resistor" }, { "name": "RZ2", "type": "resistor", "nodes": "z2 outn", "sizedBy": [ "Rz" ], "role": "nulling resistor" } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "The input pair: any difference is input offset - the offset the chopper moves when clocked." }, { "rule": "match", "of": [ "M3", "M4", "M7", "M8" ], "why": "The fold sinks and the loads set the first stage's currents; a mismatch between the sides is offset too, referred to the input through g_m1." }, { "rule": "unit-copies", "of": [ "MB", "MT", "M13", "M14", "M3", "M4" ], "constraint": "MT = 2 PMOS units, M13, M14 = N2 units; M3, M4 = 2 NMOS units", "why": "Repeated unit geometry preserves the nominal ratio; random mismatch and unequal drain voltages still cause errors. The fold sinks nominally carry the tail's half plus the load's current, 2 Ib each." }, { "rule": "headroom", "of": [ "M3", "M5", "M11" ], "constraint": "V_GS,M11 >= V_DS,M3 + V_DS,M5 at every corner", "why": "The first stage's outputs sit at the gate voltage of M11, and the fold sink and its cascode must both saturate under it. M11 is sized for a V_GS near its temperature-flat point (about 0.5 V), and M3, M5 run in weak inversion, whose V_DSAT is about 4 kT/q." }, { "rule": "cascode-bias", "of": [ "MB6", "M5", "MB3", "M9" ], "constraint": "MB6, MB3 long and narrow: one V_GS plus the room the device below needs", "why": "A long diode at the same current stands higher than the wide cascode by roughly the V_DS the sink below it needs - and that difference grows with temperature, as V_DSAT does. A resistor would do the opposite: high-resistance poly loses about a fifth of its value by 125 °C." }, { "rule": "chopper-placement", "of": [ "SO1", "SO2", "SO3", "SO4" ], "constraint": "between the first stage's outputs and the second stage's gates", "why": "The chopper must sit after the first stage, whose offset and 1/f noise it moves, and before the Miller integrator, whose input it feeds; at o1, o2 it switches a node near 0.5 V, where an NMOS switch has 0.7 V of drive." }, { "rule": "zero", "of": [ "RZ1", "M11" ], "constraint": "R_z > 1/g_m11", "why": "C_c feeds the second stage's input forward to its output: a right-half-plane zero at g_m11/C_c. A series resistor above 1/g_m11 moves it into the left half-plane." }, { "rule": "needs-cmfb", "of": [ "ML", "M7", "M8" ], "constraint": "cmc must be driven by a common-mode loop", "why": "Both stages' outputs are high-impedance nodes: without a loop setting the loads' current, the balance of fixed currents leaves them wherever a millivolt of mismatch pushes them - a rail. The loop acts as a current into ML: balanced it draws Ib, so ML stands at the gate voltage the loads need at every corner and only the correction depends on the loop's gain." } ], "specs": [ { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.00011 A", "min": null, "max": 0.00011, "why": "Two stages and the bias from one 5 µA reference: 20 µA in the first stage, 2 x N2 Ib in the second, the rest bias." }, { "key": "vocm_out", "label": "Output common mode", "unit": "V", "direction": "target", "constraint": ">= 0.58 V, <= 0.62 V", "min": 0.58, "max": 0.62, "why": "The bench's ideal loop holds the output common mode at 0.6 V; a core that could not be held there would show it here." }, { "key": "dc_gain_db", "label": "DC open-loop gain", "unit": "dB", "direction": "max", "constraint": ">= 70 dB", "min": 70, "max": null, "why": "A folded cascode and a common-source stage: enough that a 20x capacitive-feedback loop around it errs by well under 1 %." }, { "key": "ugf_hz", "label": "Unity-gain frequency", "unit": "Hz", "direction": "max", "constraint": ">= 2500000 Hz", "min": 2500000, "max": null, "why": "The closed-loop response is slower than the OTA's unity-gain frequency. The clocked amplifier must settle within each half-period at its chosen capacitor ratio and chopping frequency." }, { "key": "pm_deg", "label": "Phase margin", "unit": "deg", "direction": "max", "constraint": ">= 60 deg", "min": 60, "max": null, "why": "The follower must settle without ringing; 60° leaves room for the load a feedback network adds." }, { "key": "t_settle", "label": "Settling time, 1 %", "unit": "s", "direction": "min", "constraint": "<= 5e-7 s", "min": null, "max": 5e-7, "why": "The follower settles within 2 % of a 25 µs half period of a 20 kHz chopper, at every corner." }, { "key": "cm_overshoot_pct", "label": "Common-mode overshoot", "unit": "%", "direction": "min", "constraint": "<= 25 %", "min": null, "max": 25, "why": "The common-mode loop must be as well damped as the differential one; a large overshoot is a loop near oscillation." }, { "key": "vn_int", "label": "Input noise, 1 Hz to 1 MHz, chopper held", "unit": "V", "direction": "min", "constraint": "<= 0.0001 V", "min": null, "max": 0.0001, "why": "Held, the input pair's and the loads' thermal noise plus their 1/f noise: about 55 µV from 1 Hz to 1 MHz, 70 µV when hot. Clocked, the chopper moves the 1/f part away." } ], "explanation": { "idea": "This is the amplifier core used inside a chopper amplifier. Two gain stages are separated by switches that can reverse the signal polarity. Here the switches stay in one position, and an ideal testbench loop sets the output average; a complete design needs real common-mode control.", "detail": "The OTA of a capacitively coupled chopper amplifier, on its own. A PMOS pair feeds a folded cascode whose outputs o1, o2 are its high-resistance nodes; a chopper between the stages - held straight in every bench here - would swap o1 and o2 at the chopping frequency, and a Miller-compensated common-source stage gives the gain and the swing. The core has no common-mode loop of its own: its loads copy the diode ML on pin cmc, and the benches close an ideal loop that draws Ib from ML and 50 µA more per volt the output common mode stands above vocm.", "lesson": { "relation": 1, "symbols": "ω_u is angular unity-gain frequency in rad/s; g_m1 is input-pair device transconductance in S; C_c is compensation capacitance per side in F. Divide ω_u by 2π for Hz.", "assumptions": "Small signals around the default bias point, with the intended dominant pole and the other internal poles above crossover. Device and load parasitics make the relation approximate.", "exercise": { "param": "Cc", "value": 6e-12, "analysis": "open_loop", "expect": "Increasing the compensation capacitance should lower the unity-gain frequency. Compare the phase margin as well; a slower crossover does not by itself prove every internal loop is stable." }, "limits": "These benches hold the chopper straight; they do not measure chopping suppression. Provide bias and common-mode references, and verify clocked settling in the complete instrumentation amplifier. This core additionally needs real common-mode feedback; its bench supplies an ideal loop." }, "path": [ { "part": "Input pair", "devices": "M1, M2, MT", "does": "MT's 10 µA divides between M1 and M2 as the inputs differ; a rise on inp takes current away from the fold node f1." }, { "part": "Folded cascode", "devices": "M3, M4, M5, M6, M7, M8, M9, M10", "does": "M3, M4 sink 2·Ib each; what the pair does not supply there is drawn through the NMOS cascodes M5, M6 from o1, o2, where the loads M7, M8 under the PMOS cascodes M9, M10 source Ib. Cascoded on both sides, o1 and o2 are the amplifier's high-resistance nodes, and a rise on inp pulls o1 down." }, { "part": "Output chopper", "devices": "SO1, SO2, SO3, SO4", "does": "With clk high, SO1 and SO2 join o1 to g1 and o2 to g2; clocked, SO3 and SO4 cross them every other half period, so a chopped signal returns to baseband at g1, g2 while the first stage's offset and 1/f noise leave at the chopping frequency. Every bench of this OTA holds it straight." }, { "part": "Second stage", "devices": "M11, M12, M13, M14, CC1, CC2, RZ1, RZ2", "does": "M11, M12 invert g1, g2 onto outp, outn against the sources M13, M14, so outp follows inp. CC1, CC2 across them, in series with RZ1, RZ2, make g1, g2 the dominant pole." }, { "part": "Common-mode control", "devices": "ML, M7, M8", "does": "M7, M8 copy the current drawn out of ML. The bench's ideal loop draws Ib and more as the output common mode rises: the loads then source more, o1, o2 rise, and M11, M12 pull the outputs back down." } ], "bias": "The testbench draws Ib = 5 µA out of the diode MB. MT is two copies of it (10 µA); MB1 copies Ib into the NMOS diode MB2, which M3 and M4 copy twice (10 µA each). The cascode gates come from long, narrow diodes carrying Ib: MB6 stands one cascode V_GS plus about 0.2 V above ground, the room M3 needs under M5, and MB3 likewise leaves M7 room under M9 - differences that grow with temperature, as V_DSAT does, where a poly resistor's drop would shrink. o1 and o2 settle at the gate voltage M11 needs for N2·Ib = 20 µA, about 0.5 V, close to where its V_GS stops moving with temperature. Drawn at Ib, ML stands at the gate voltage the loads need, so the ideal loop only supplies the few-percent correction and the output common mode stays within about 15 mV of vocm at every corner.", "relations": [ { "what": "Differential gain", "expr": "A_d ≈ g_m1·R_o1·g_m11·(r_o11 ∥ r_o13)", "note": "R_o1 is the cascoded resistance at o1, set mostly by the NMOS side (g_m5·r_o5·r_o3); about 78 dB with the chopper held." }, { "what": "Unity-gain frequency", "expr": "ω_u ≈ g_m1/C_c", "note": "About 4.5 MHz: g_m1 ≈ 92 µS, C_c = 3 pF. The closed-loop response depends on the feedback network; the complete clocked amplifier must settle within each half-period at its selected gain and chopping frequency." }, { "what": "Compensation zero", "expr": "ω_z = 1/[C_c·(R_z − 1/g_m11)]", "note": "R_z = 12 kΩ is above 1/g_m11 ≈ 7 kΩ, so the zero lies in the left half-plane, near 11 MHz, and adds phase at ω_u: the margin is close to 90°." }, { "what": "Headroom under o1", "expr": "V_GS,11 ≥ V_DS,3 + V_DS,5", "note": "About 0.5 V against 0.2 V for M3 and 0.3 V for M5, both near weak inversion, where V_DSAT is about 4kT/q." }, { "what": "Common-mode loop", "expr": "ω_u,cm ≈ (g_cm/g_m,ML)·g_m7/C_c", "note": "g_cm = 50 µS is the bench loop's; the loop runs through both stages and the Miller capacitors, like the differential path, and settles in about 230 ns without overshoot." } ], "tradeoffs": [ "Miller capacitor (Cc): larger adds margin for a heavier feedback network, but slows the OTA and its recovery after each chopper edge.", "Second-stage current (N2): more raises g_m11, the output pole and the slew rate into the load, at the supply's cost; o1, o2 do not move, since M11's unit sets them.", "Second-stage unit (W2, L2): a lower V_GS, from a wider or shorter unit, leaves less room for M3 and M5 under o1, o2; a higher one crowds M7 and M9 above them.", "Cascode-bias diodes (Wdn, Wdp): they share the room between each current source and its cascode; a narrower diode gives the source more and the cascode less." ] }, "sizing": [ { "key": "Ib", "label": "Reference current", "unit": "A", "value": 0.000005, "min": 0.000001, "max": 0.00002, "kind": "si" }, { "key": "Wp", "label": "W PMOS source unit (MB, MT, M13, M14)", "unit": "m", "value": 0.00001, "min": 0.000001, "max": 0.00004, "kind": "si" }, { "key": "Lp", "label": "L PMOS source unit", "unit": "m", "value": 0.000002, "min": 5e-7, "max": 0.000008, "kind": "si" }, { "key": "Wn", "label": "W NMOS unit (MB2, M3, M4, the CMFB tail)", "unit": "m", "value": 0.000008, "min": 0.000001, "max": 0.00004, "kind": "si" }, { "key": "Ln", "label": "L NMOS unit", "unit": "m", "value": 0.000002, "min": 5e-7, "max": 0.000008, "kind": "si" }, { "key": "Wl", "label": "W PMOS load unit (M7, M8 and the diode they copy)", "unit": "m", "value": 0.00002, "min": 0.000002, "max": 0.00006, "kind": "si" }, { "key": "Ll", "label": "L PMOS load unit", "unit": "m", "value": 0.000002, "min": 5e-7, "max": 0.000008, "kind": "si" }, { "key": "W1", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.00002, "min": 0.000002, "max": 0.00008, "kind": "si" }, { "key": "L1", "label": "L input pair", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wcn", "label": "W NMOS cascode (M5, M6)", "unit": "m", "value": 0.000008, "min": 0.000001, "max": 0.00004, "kind": "si" }, { "key": "Lcn", "label": "L NMOS cascode", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.000002, "kind": "si" }, { "key": "Wcp", "label": "W PMOS cascode (M9, M10)", "unit": "m", "value": 0.000006, "min": 0.000001, "max": 0.00004, "kind": "si" }, { "key": "Lcp", "label": "L PMOS cascode", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.000002, "kind": "si" }, { "key": "Wdn", "label": "W diode setting the NMOS cascode gate (MB6)", "unit": "m", "value": 0.0000016, "min": 5e-7, "max": 0.000008, "kind": "si" }, { "key": "Ldn", "label": "L diode setting the NMOS cascode gate", "unit": "m", "value": 0.000004, "min": 0.000001, "max": 0.00001, "kind": "si" }, { "key": "Wdp", "label": "W diode setting the PMOS cascode gate (MB3)", "unit": "m", "value": 0.000004, "min": 5e-7, "max": 0.00001, "kind": "si" }, { "key": "Ldp", "label": "L diode setting the PMOS cascode gate", "unit": "m", "value": 0.000004, "min": 0.000001, "max": 0.00001, "kind": "si" }, { "key": "W2", "label": "W second-stage NMOS unit (M11, M12)", "unit": "m", "value": 8e-7, "min": 3e-7, "max": 0.000004, "kind": "si" }, { "key": "L2", "label": "L second-stage NMOS unit", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.000006, "kind": "si" }, { "key": "N2", "label": "Second-stage current, in Ib", "unit": "", "value": 4, "min": 2, "max": 12, "kind": "int" }, { "key": "Cc", "label": "Miller capacitor, each side", "unit": "F", "value": 3e-12, "min": 5e-13, "max": 1.2e-11, "kind": "si" }, { "key": "Rz", "label": "Nulling resistor, each side", "unit": "Ω", "value": 12000, "min": 2000, "max": 60000, "kind": "si" }, { "key": "Wso", "label": "W output-chopper switch (SO1-SO4)", "unit": "m", "value": 0.000001, "min": 1.5e-7, "max": 0.00001, "kind": "si" }, { "key": "Lso", "label": "L output-chopper switch", "unit": "m", "value": 1.3e-7, "min": 1.3e-7, "max": 0.000001, "kind": "si" }, { "key": "CL", "label": "Load capacitance, each output", "unit": "F", "value": 2e-12, "min": 2e-13, "max": 2e-11, "kind": "si" }, { "key": "VICM", "label": "Input common mode", "unit": "V", "value": 0.35, "min": 0.1, "max": 0.6, "kind": "si" }, { "key": "VOCM", "label": "Output common mode the bench's loop asks for", "unit": "V", "value": 0.6, "min": 0.4, "max": 0.8, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point, chopper held", "note": "The amplifier as a fully differential follower at its input common mode, its chopper held straight: the current it draws, where its outputs sit, and the difference they settle at with no input.", "measures": [], "metricKeys": [ "i_supply", "vocm_out", "vod_dc" ], "acceptance": [ "i_supply", "vocm_out" ], "acceptanceRules": [ { "key": "i_supply", "unit": "A", "min": null, "max": 0.00011, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "vocm_out", "unit": "V", "min": 0.58, "max": 0.62, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Chopper OTA core, common mode set from outside - operating point, chopper held\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n* the clocks held: clk high, clkb low - every chopper straight\nVclk clk 0 dc {VDD}\nVclkb clkb 0 dc 0\nIb ib 0 5u\n* an ideal common-mode loop, the bench's: it draws Ib out of the loads'\n* diode ML, and 50 uA more per volt the output common mode stands above\n* vocm - the loads then source more, and the second stage pulls it back\nBcm cmc 0 I=5u+50u*((v(outp)+v(outn))/2-v(vocm))\n* the output common mode the amplifier is asked for\nVocm vocm 0 dc 600m\n.subckt chopota inp inn outp outn vdd vss ib cmc clk clkb\nXMB ib ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB1 nb ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB2 nb nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1\nXMB3 vcp vcp vdd vdd sg13_lv_pmos w=4u l=4u ng=1 m=1\nXMB4 vcp nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1\nXMB5 vcn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB6 vcn vcn vss vss sg13_lv_nmos w=1.6u l=4u ng=1 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=2\nXM1 f1 inp tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM2 f2 inn tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM3 f1 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2\nXM4 f2 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2\nXM5 o1 vcn f1 vss sg13_lv_nmos w=8u l=500n ng=2 m=1\nXM6 o2 vcn f2 vss sg13_lv_nmos w=8u l=500n ng=2 m=1\nXM7 k1 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXM8 k2 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXM9 o1 vcp k1 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1\nXM10 o2 vcp k2 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1\nXML cmc cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXSO1 o1 clk g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO2 o2 clk g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO3 o1 clkb g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO4 o2 clkb g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXM11 outp g1 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4\nXM12 outn g2 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4\nXM13 outp ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4\nXM14 outn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4\nXCC1 g1 z1 cap_cmim w=25.767u l=25.767u m=3\nXCC2 g2 z2 cap_cmim w=25.767u l=25.767u m=3\nXRZ1 z1 outp vss rppd w=0.5u l=23.355u\nXRZ2 z2 outn vss rppd w=0.5u l=23.355u\n.ends\nXdut inp inn outp outn vdd 0 ib cmc clk clkb chopota\nClp outp 0 2p\nCln outn 0 2p\n* a fully differential follower: inp, inn = VICM +- (vid - vod)/2\nVicm icm 0 dc 350m\nEod od 0 outp outn 1\nEer er 0 vid od 1\nEinp inp icm er 0 0.5\nEinn inn icm er 0 -0.5\nVid vid 0 dc 0\n.op\n.end" }, { "id": "open_loop", "label": "Open-loop gain, chopper held", "note": "Differential gain and phase with the follower's loop closed only at DC, through a 1 TH coil: every frequency the sweep visits sees the open loop, and the operating point is the follower's. The chopper is held straight.", "measures": [], "metricKeys": [ "dc_gain_db", "ugf_hz", "pm_deg", "gm_db" ], "acceptance": [ "dc_gain_db", "ugf_hz", "pm_deg" ], "acceptanceRules": [ { "key": "dc_gain_db", "unit": "dB", "min": 70, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "ugf_hz", "unit": "Hz", "min": 2500000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "pm_deg", "unit": "deg", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Chopper OTA core, common mode set from outside - open-loop differential gain and phase, chopper held\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n* the clocks held: clk high, clkb low - every chopper straight\nVclk clk 0 dc {VDD}\nVclkb clkb 0 dc 0\nIb ib 0 5u\n* an ideal common-mode loop, the bench's: it draws Ib out of the loads'\n* diode ML, and 50 uA more per volt the output common mode stands above\n* vocm - the loads then source more, and the second stage pulls it back\nBcm cmc 0 I=5u+50u*((v(outp)+v(outn))/2-v(vocm))\n* the output common mode the amplifier is asked for\nVocm vocm 0 dc 600m\n.subckt chopota inp inn outp outn vdd vss ib cmc clk clkb\nXMB ib ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB1 nb ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB2 nb nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1\nXMB3 vcp vcp vdd vdd sg13_lv_pmos w=4u l=4u ng=1 m=1\nXMB4 vcp nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1\nXMB5 vcn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB6 vcn vcn vss vss sg13_lv_nmos w=1.6u l=4u ng=1 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=2\nXM1 f1 inp tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM2 f2 inn tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM3 f1 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2\nXM4 f2 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2\nXM5 o1 vcn f1 vss sg13_lv_nmos w=8u l=500n ng=2 m=1\nXM6 o2 vcn f2 vss sg13_lv_nmos w=8u l=500n ng=2 m=1\nXM7 k1 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXM8 k2 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXM9 o1 vcp k1 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1\nXM10 o2 vcp k2 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1\nXML cmc cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXSO1 o1 clk g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO2 o2 clk g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO3 o1 clkb g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO4 o2 clkb g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXM11 outp g1 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4\nXM12 outn g2 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4\nXM13 outp ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4\nXM14 outn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4\nXCC1 g1 z1 cap_cmim w=25.767u l=25.767u m=3\nXCC2 g2 z2 cap_cmim w=25.767u l=25.767u m=3\nXRZ1 z1 outp vss rppd w=0.5u l=23.355u\nXRZ2 z2 outn vss rppd w=0.5u l=23.355u\n.ends\nXdut inp inn outp outn vdd 0 ib cmc clk clkb chopota\nClp outp 0 2p\nCln outn 0 2p\n* a fully differential follower: inp, inn = VICM +- (vid - vod)/2\nVicm icm 0 dc 350m\nEod od 0 outp outn 1\nEer er 0 vid odl 1\nEinp inp icm er 0 0.5\nEinn inn icm er 0 -0.5\n* the loop closed at DC and open at every frequency the sweep visits\nLod od odl 1t\nCod odl 0 1t\nVid vid 0 dc 0 ac 1\n.ac dec 25 1 10g\n.end" }, { "id": "step", "label": "Step response, chopper held", "note": "A 200mV differential step into the follower, its chopper held: how fast the output difference follows and whether it rings - the test that finds a local loop an open-loop phase margin hides.", "measures": [], "metricKeys": [ "sr", "t_settle", "overshoot_pct" ], "acceptance": [ "t_settle" ], "acceptanceRules": [ { "key": "t_settle", "unit": "s", "min": null, "max": 5e-7, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Chopper OTA core, common mode set from outside - differential step into the follower, chopper held\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n* the clocks held: clk high, clkb low - every chopper straight\nVclk clk 0 dc {VDD}\nVclkb clkb 0 dc 0\nIb ib 0 5u\n* an ideal common-mode loop, the bench's: it draws Ib out of the loads'\n* diode ML, and 50 uA more per volt the output common mode stands above\n* vocm - the loads then source more, and the second stage pulls it back\nBcm cmc 0 I=5u+50u*((v(outp)+v(outn))/2-v(vocm))\n* the output common mode the amplifier is asked for\nVocm vocm 0 dc 600m\n.subckt chopota inp inn outp outn vdd vss ib cmc clk clkb\nXMB ib ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB1 nb ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB2 nb nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1\nXMB3 vcp vcp vdd vdd sg13_lv_pmos w=4u l=4u ng=1 m=1\nXMB4 vcp nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1\nXMB5 vcn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB6 vcn vcn vss vss sg13_lv_nmos w=1.6u l=4u ng=1 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=2\nXM1 f1 inp tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM2 f2 inn tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM3 f1 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2\nXM4 f2 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2\nXM5 o1 vcn f1 vss sg13_lv_nmos w=8u l=500n ng=2 m=1\nXM6 o2 vcn f2 vss sg13_lv_nmos w=8u l=500n ng=2 m=1\nXM7 k1 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXM8 k2 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXM9 o1 vcp k1 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1\nXM10 o2 vcp k2 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1\nXML cmc cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXSO1 o1 clk g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO2 o2 clk g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO3 o1 clkb g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO4 o2 clkb g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXM11 outp g1 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4\nXM12 outn g2 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4\nXM13 outp ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4\nXM14 outn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4\nXCC1 g1 z1 cap_cmim w=25.767u l=25.767u m=3\nXCC2 g2 z2 cap_cmim w=25.767u l=25.767u m=3\nXRZ1 z1 outp vss rppd w=0.5u l=23.355u\nXRZ2 z2 outn vss rppd w=0.5u l=23.355u\n.ends\nXdut inp inn outp outn vdd 0 ib cmc clk clkb chopota\nClp outp 0 2p\nCln outn 0 2p\n* a fully differential follower: inp, inn = VICM +- (vid - vod)/2\nVicm icm 0 dc 350m\nEod od 0 outp outn 1\nEer er 0 vid od 1\nEinp inp icm er 0 0.5\nEinn inn icm er 0 -0.5\nVid vid 0 pulse(-100m 100m 400n 1n 1n 2u 8u)\n.tran 1000p 4u\n.end" }, { "id": "cm", "label": "Common-mode loop, chopper held", "note": "A 50 mV step on the common-mode reference: the output common mode has to follow it, and how it gets there - its settling and its overshoot - is the common-mode loop's phase margin, a loop the differential benches never see.", "measures": [], "metricKeys": [ "cm_settle", "cm_overshoot_pct" ], "acceptance": [ "cm_overshoot_pct" ], "acceptanceRules": [ { "key": "cm_overshoot_pct", "unit": "%", "min": null, "max": 25, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Chopper OTA core, common mode set from outside - a step on the common-mode reference, chopper held\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n* the clocks held: clk high, clkb low - every chopper straight\nVclk clk 0 dc {VDD}\nVclkb clkb 0 dc 0\nIb ib 0 5u\n* an ideal common-mode loop, the bench's: it draws Ib out of the loads'\n* diode ML, and 50 uA more per volt the output common mode stands above\n* vocm - the loads then source more, and the second stage pulls it back\nBcm cmc 0 I=5u+50u*((v(outp)+v(outn))/2-v(vocm))\n* the output common mode the amplifier is asked for\nVocm vocm 0 pulse(600m 650m 400n 1n 1n 4u 16u)\n.subckt chopota inp inn outp outn vdd vss ib cmc clk clkb\nXMB ib ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB1 nb ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB2 nb nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1\nXMB3 vcp vcp vdd vdd sg13_lv_pmos w=4u l=4u ng=1 m=1\nXMB4 vcp nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1\nXMB5 vcn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB6 vcn vcn vss vss sg13_lv_nmos w=1.6u l=4u ng=1 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=2\nXM1 f1 inp tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM2 f2 inn tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM3 f1 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2\nXM4 f2 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2\nXM5 o1 vcn f1 vss sg13_lv_nmos w=8u l=500n ng=2 m=1\nXM6 o2 vcn f2 vss sg13_lv_nmos w=8u l=500n ng=2 m=1\nXM7 k1 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXM8 k2 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXM9 o1 vcp k1 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1\nXM10 o2 vcp k2 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1\nXML cmc cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXSO1 o1 clk g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO2 o2 clk g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO3 o1 clkb g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO4 o2 clkb g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXM11 outp g1 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4\nXM12 outn g2 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4\nXM13 outp ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4\nXM14 outn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4\nXCC1 g1 z1 cap_cmim w=25.767u l=25.767u m=3\nXCC2 g2 z2 cap_cmim w=25.767u l=25.767u m=3\nXRZ1 z1 outp vss rppd w=0.5u l=23.355u\nXRZ2 z2 outn vss rppd w=0.5u l=23.355u\n.ends\nXdut inp inn outp outn vdd 0 ib cmc clk clkb chopota\nClp outp 0 2p\nCln outn 0 2p\n* a fully differential follower: inp, inn = VICM +- (vid - vod)/2\nVicm icm 0 dc 350m\nEod od 0 outp outn 1\nEer er 0 vid od 1\nEinp inp icm er 0 0.5\nEinn inn icm er 0 -0.5\nVid vid 0 dc 0\n.tran 1000p 4u\n.end" }, { "id": "noise", "label": "Noise, chopper held", "note": "Noise referred to the differential input of the follower, its chopper held: the density at 1 kHz and the total from 1 Hz to 1 MHz. Held, the first stage's 1/f noise is all here; clocked, the chopper moves it up to the chopping frequency.", "measures": [], "metricKeys": [ "vn_1k", "vn_int" ], "acceptance": [ "vn_int" ], "acceptanceRules": [ { "key": "vn_int", "unit": "V", "min": null, "max": 0.0001, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Chopper OTA core, common mode set from outside - input-referred noise, chopper held\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n* the clocks held: clk high, clkb low - every chopper straight\nVclk clk 0 dc {VDD}\nVclkb clkb 0 dc 0\nIb ib 0 5u\n* an ideal common-mode loop, the bench's: it draws Ib out of the loads'\n* diode ML, and 50 uA more per volt the output common mode stands above\n* vocm - the loads then source more, and the second stage pulls it back\nBcm cmc 0 I=5u+50u*((v(outp)+v(outn))/2-v(vocm))\n* the output common mode the amplifier is asked for\nVocm vocm 0 dc 600m\n.subckt chopota inp inn outp outn vdd vss ib cmc clk clkb\nXMB ib ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB1 nb ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB2 nb nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1\nXMB3 vcp vcp vdd vdd sg13_lv_pmos w=4u l=4u ng=1 m=1\nXMB4 vcp nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1\nXMB5 vcn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB6 vcn vcn vss vss sg13_lv_nmos w=1.6u l=4u ng=1 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=2\nXM1 f1 inp tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM2 f2 inn tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM3 f1 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2\nXM4 f2 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2\nXM5 o1 vcn f1 vss sg13_lv_nmos w=8u l=500n ng=2 m=1\nXM6 o2 vcn f2 vss sg13_lv_nmos w=8u l=500n ng=2 m=1\nXM7 k1 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXM8 k2 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXM9 o1 vcp k1 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1\nXM10 o2 vcp k2 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1\nXML cmc cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXSO1 o1 clk g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO2 o2 clk g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO3 o1 clkb g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO4 o2 clkb g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXM11 outp g1 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4\nXM12 outn g2 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4\nXM13 outp ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4\nXM14 outn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4\nXCC1 g1 z1 cap_cmim w=25.767u l=25.767u m=3\nXCC2 g2 z2 cap_cmim w=25.767u l=25.767u m=3\nXRZ1 z1 outp vss rppd w=0.5u l=23.355u\nXRZ2 z2 outn vss rppd w=0.5u l=23.355u\n.ends\nXdut inp inn outp outn vdd 0 ib cmc clk clkb chopota\nClp outp 0 2p\nCln outn 0 2p\n* a fully differential follower: inp, inn = VICM +- (vid - vod)/2\nVicm icm 0 dc 350m\nEod od 0 outp outn 1\nEer er 0 vid od 1\nEinp inp icm er 0 0.5\nEinn inn icm er 0 -0.5\nVid vid 0 dc 0 ac 1\n.control\nnoise v(od) Vid dec 20 1 1meg\nsetplot noise1\n* 20 points a decade from 1 Hz: point 60 is 1 kHz\nlet vn_1k = inoise_spectrum[60]\nprint vn_1k\nsetplot noise2\nprint inoise_total\n.endc\n.op\n.end" } ], "measurements": { "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.00011 } }, "vocm_out": { "label": "Output common mode", "unit": "V", "spec": { "min": 0.58, "max": 0.62 } }, "dc_gain_db": { "label": "DC open-loop gain", "unit": "dB", "spec": { "min": 70, "max": null } }, "ugf_hz": { "label": "Unity-gain frequency", "unit": "Hz", "spec": { "min": 2500000, "max": null } }, "pm_deg": { "label": "Phase margin", "unit": "deg", "spec": { "min": 60, "max": null } }, "t_settle": { "label": "Settling time, 1 %", "unit": "s", "spec": { "min": null, "max": 5e-7 } }, "cm_overshoot_pct": { "label": "Common-mode overshoot", "unit": "%", "spec": { "min": null, "max": 25 } }, "vn_int": { "label": "Input noise, 1 Hz to 1 MHz, chopper held", "unit": "V", "spec": { "min": null, "max": 0.0001 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "181a759ca2081cab0ada7f1fc27fb14a8c37575e74a70cbc3aef4dca8f10eb22" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/chopper-ota-core.js", "sha256": "61a0914b9002e978e65124ca857e63d35892e66f81a87b2e049a7036f11dbeb8" }, "simulationFingerprints": { "op": "096d0caa23acb3e1e5987be8f159bd2ff591018fc33b9070f0b8692f6aeff79f", "open_loop": "7ba7d5c6134a78636fb2d4074ec68a51582cfb0ed04af0e0052504bc3a607677", "step": "cb39a2359bb332e94a7725ba44cb3843e8c2e72e1bc823ea28e4011645faac8a", "cm": "be8130a8c80c552cddfc69dd93d58fbcfdec260e567b4def2462fb95a9b93c31", "noise": "312d6d2645961928ed58b24e4c4a07bd0d804276d3c83468a94f03dcabbc3d0b" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "8f478dcaba882871b249c5b1603f5b6b2d1998f98717ff77f3d256976c3dc5c9", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "chopper-ota-core", "parameters": { "Ib": 0.000005, "Wp": 0.00001, "Lp": 0.000002, "Wn": 0.000008, "Ln": 0.000002, "Wl": 0.00002, "Ll": 0.000002, "W1": 0.00002, "L1": 0.000001, "Wcn": 0.000008, "Lcn": 5e-7, "Wcp": 0.000006, "Lcp": 5e-7, "Wdn": 0.0000016, "Ldn": 0.000004, "Wdp": 0.000004, "Ldp": 0.000004, "W2": 8e-7, "L2": 0.000002, "N2": 4, "Cc": 3e-12, "Rz": 12000, "Wso": 0.000001, "Lso": 1.3e-7, "CL": 2e-12, "VICM": 0.35, "VOCM": 0.6 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/chopper-ota-core/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "chopota", "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "outp", "net": "outp", "kind": "output" }, { "name": "outn", "net": "outn", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" }, { "name": "cmc", "net": "cmc", "kind": "bias" }, { "name": "clk", "net": "clk", "kind": "clock" }, { "name": "clkb", "net": "clkb", "kind": "clock" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB2 nb nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMB3 vcp vcp vdd vdd sg13_lv_pmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB4", "displayName": "MB4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB4 vcp nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB5", "displayName": "MB5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB5 vcn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB6", "displayName": "MB6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.6u l=4u ng=1 m=1", "source": "XMB6 vcn vcn vss vss sg13_lv_nmos w=1.6u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM1 f1 inp tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM2 f2 inn tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM5 o1 vcn f1 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM6 o2 vcn f2 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM7 k1 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "cmc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM8 k2 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "cmc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM9 o1 vcp k1 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM10 o2 vcp k2 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML", "displayName": "ML", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XML cmc cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "cmc" }, { "id": "g", "net": "cmc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO1", "displayName": "SO1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO1 o1 clk g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO2", "displayName": "SO2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO2 o2 clk g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO3", "displayName": "SO3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO3 o1 clkb g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO4", "displayName": "SO4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO4 o2 clkb g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM11 outp g1 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "g1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM12 outn g2 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "g2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM13 outp ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM14 outn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC1 g1 z1 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC2 g2 z2 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB5", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM13", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XMB5", "pin": "s" }, { "device": "XMB5", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" }, { "device": "XML", "pin": "s" }, { "device": "XML", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMB2", "pin": "d" }, { "device": "XMB2", "pin": "g" }, { "device": "XMB4", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMB4", "pin": "s" }, { "device": "XMB4", "pin": "b" }, { "device": "XMB6", "pin": "s" }, { "device": "XMB6", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XSO1", "pin": "b" }, { "device": "XSO2", "pin": "b" }, { "device": "XSO3", "pin": "b" }, { "device": "XSO4", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XRZ1", "pin": "substrate" }, { "device": "XRZ2", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" }, { "device": "XMB4", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB5", "pin": "d" }, { "device": "XMB6", "pin": "d" }, { "device": "XMB6", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM9", "pin": "d" }, { "device": "XSO1", "pin": "d" }, { "device": "XSO3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XSO2", "pin": "d" }, { "device": "XSO4", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "cmc", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XML", "pin": "d" }, { "device": "XML", "pin": "g" } ], "ports": [ "cmc" ], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "XSO1", "pin": "g" }, { "device": "XSO2", "pin": "g" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "g1", "ground": false, "terminals": [ { "device": "XSO1", "pin": "s" }, { "device": "XSO4", "pin": "s" }, { "device": "XM11", "pin": "g" }, { "device": "XCC1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "g2", "ground": false, "terminals": [ { "device": "XSO2", "pin": "s" }, { "device": "XSO3", "pin": "s" }, { "device": "XM12", "pin": "g" }, { "device": "XCC2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "XSO3", "pin": "g" }, { "device": "XSO4", "pin": "g" } ], "ports": [ "clkb" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XRZ1", "pin": "n" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XRZ2", "pin": "n" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "z1", "ground": false, "terminals": [ { "device": "XCC1", "pin": "n" }, { "device": "XRZ1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z2", "ground": false, "terminals": [ { "device": "XCC2", "pin": "n" }, { "device": "XRZ2", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclk", "displayName": "Vclk", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vclk clk 0 dc {VDD}", "pins": [ { "id": "p", "net": "clk" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclkb", "displayName": "Vclkb", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vclkb clkb 0 dc 0", "pins": [ { "id": "p", "net": "clkb" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ib ib 0 5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bcm", "displayName": "Bcm", "spiceType": "B", "model": null, "parametersOrValue": "I=5u+50u*((v(outp)+v(outn))/2-v(vocm))", "source": "Bcm cmc 0 I=5u+50u*((v(outp)+v(outn))/2-v(vocm))", "pins": [ { "id": "p", "net": "cmc" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "outp", "outn", "vocm" ], "currentDevices": [] } }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vocm vocm 0 dc 600m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "chopota", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 ib cmc clk clkb chopota", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" }, { "id": "cmc", "net": "cmc" }, { "id": "clk", "net": "clk" }, { "id": "clkb", "net": "clkb" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/chopota" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 350m", "source": "Vicm icm 0 dc 350m", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Eod", "displayName": "Eod", "spiceType": "E", "model": null, "parametersOrValue": "1", "source": "Eod od 0 outp outn 1", "pins": [ { "id": "p", "net": "od" }, { "id": "n", "net": "0" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Eer", "displayName": "Eer", "spiceType": "E", "model": null, "parametersOrValue": "1", "source": "Eer er 0 vid od 1", "pins": [ { "id": "p", "net": "er" }, { "id": "n", "net": "0" }, { "id": "cp", "net": "vid" }, { "id": "cn", "net": "od" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Einp", "displayName": "Einp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Einp inp icm er 0 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "er" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Einn", "displayName": "Einn", "spiceType": "E", "model": null, "parametersOrValue": "-0.5", "source": "Einn inn icm er 0 -0.5", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "er" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vid", "displayName": "Vid", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vid vid 0 dc 0", "pins": [ { "id": "p", "net": "vid" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vclk", "pin": "n" }, { "device": "Vclkb", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Bcm", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" }, { "device": "Eod", "pin": "n" }, { "device": "Eer", "pin": "n" }, { "device": "Einp", "pin": "cn" }, { "device": "Einn", "pin": "cn" }, { "device": "Vid", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "Vclk", "pin": "p" }, { "device": "Xdut", "pin": "clk" } ], "ports": [], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "Vclkb", "pin": "p" }, { "device": "Xdut", "pin": "clkb" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "cmc", "ground": false, "terminals": [ { "device": "Bcm", "pin": "p" }, { "device": "Xdut", "pin": "cmc" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Eod", "pin": "cp" } ], "ports": [], "voltageReferences": [ "Bcm" ] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Eod", "pin": "cn" } ], "ports": [], "voltageReferences": [ "Bcm" ] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bcm" ] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Einp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Einn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Einp", "pin": "n" }, { "device": "Einn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "od", "ground": false, "terminals": [ { "device": "Eod", "pin": "p" }, { "device": "Eer", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "er", "ground": false, "terminals": [ { "device": "Eer", "pin": "p" }, { "device": "Einp", "pin": "cp" }, { "device": "Einn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "vid", "ground": false, "terminals": [ { "device": "Eer", "pin": "cp" }, { "device": "Vid", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/chopota", "name": "chopota", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" }, { "name": "cmc", "net": "cmc" }, { "name": "clk", "net": "clk" }, { "name": "clkb", "net": "clkb" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB2 nb nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMB3 vcp vcp vdd vdd sg13_lv_pmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB4", "displayName": "MB4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB4 vcp nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB5", "displayName": "MB5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB5 vcn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB6", "displayName": "MB6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.6u l=4u ng=1 m=1", "source": "XMB6 vcn vcn vss vss sg13_lv_nmos w=1.6u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM1 f1 inp tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM2 f2 inn tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM5 o1 vcn f1 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM6 o2 vcn f2 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM7 k1 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "cmc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM8 k2 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "cmc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM9 o1 vcp k1 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM10 o2 vcp k2 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML", "displayName": "ML", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XML cmc cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "cmc" }, { "id": "g", "net": "cmc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO1", "displayName": "SO1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO1 o1 clk g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO2", "displayName": "SO2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO2 o2 clk g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO3", "displayName": "SO3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO3 o1 clkb g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO4", "displayName": "SO4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO4 o2 clkb g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM11 outp g1 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "g1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM12 outn g2 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "g2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM13 outp ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM14 outn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC1 g1 z1 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC2 g2 z2 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB5", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM13", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XMB5", "pin": "s" }, { "device": "XMB5", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" }, { "device": "XML", "pin": "s" }, { "device": "XML", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMB2", "pin": "d" }, { "device": "XMB2", "pin": "g" }, { "device": "XMB4", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMB4", "pin": "s" }, { "device": "XMB4", "pin": "b" }, { "device": "XMB6", "pin": "s" }, { "device": "XMB6", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XSO1", "pin": "b" }, { "device": "XSO2", "pin": "b" }, { "device": "XSO3", "pin": "b" }, { "device": "XSO4", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XRZ1", "pin": "substrate" }, { "device": "XRZ2", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" }, { "device": "XMB4", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB5", "pin": "d" }, { "device": "XMB6", "pin": "d" }, { "device": "XMB6", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM9", "pin": "d" }, { "device": "XSO1", "pin": "d" }, { "device": "XSO3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XSO2", "pin": "d" }, { "device": "XSO4", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "cmc", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XML", "pin": "d" }, { "device": "XML", "pin": "g" } ], "ports": [ "cmc" ], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "XSO1", "pin": "g" }, { "device": "XSO2", "pin": "g" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "g1", "ground": false, "terminals": [ { "device": "XSO1", "pin": "s" }, { "device": "XSO4", "pin": "s" }, { "device": "XM11", "pin": "g" }, { "device": "XCC1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "g2", "ground": false, "terminals": [ { "device": "XSO2", "pin": "s" }, { "device": "XSO3", "pin": "s" }, { "device": "XM12", "pin": "g" }, { "device": "XCC2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "XSO3", "pin": "g" }, { "device": "XSO4", "pin": "g" } ], "ports": [ "clkb" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XRZ1", "pin": "n" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XRZ2", "pin": "n" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "z1", "ground": false, "terminals": [ { "device": "XCC1", "pin": "n" }, { "device": "XRZ1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z2", "ground": false, "terminals": [ { "device": "XCC2", "pin": "n" }, { "device": "XRZ2", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/chopota" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Bias reference", "devices": [ { "scope": "dut", "device": "XMB" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "Bias", "devices": [ { "scope": "dut", "device": "XMB1" }, { "scope": "dut", "device": "XMB2" }, { "scope": "dut", "device": "XMB3" }, { "scope": "dut", "device": "XMB4" }, { "scope": "dut", "device": "XMB5" }, { "scope": "dut", "device": "XMB6" } ], "inferredStages": [ "bias" ] }, { "id": "block-3", "label": "Tail current source", "devices": [ { "scope": "dut", "device": "XMT" } ], "inferredStages": [ 1 ] }, { "id": "block-4", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 1 ] }, { "id": "block-5", "label": "Fold current sink", "devices": [ { "scope": "dut", "device": "XM3" }, { "scope": "dut", "device": "XM4" } ], "inferredStages": [ 1 ] }, { "id": "block-6", "label": "NMOS cascode", "devices": [ { "scope": "dut", "device": "XM5" }, { "scope": "dut", "device": "XM6" } ], "inferredStages": [ 2 ] }, { "id": "block-7", "label": "First-stage load", "devices": [ { "scope": "dut", "device": "XM7" }, { "scope": "dut", "device": "XM8" } ], "inferredStages": [ "bias" ] }, { "id": "block-8", "label": "PMOS cascode", "devices": [ { "scope": "dut", "device": "XM9" }, { "scope": "dut", "device": "XM10" } ], "inferredStages": [ 2 ] }, { "id": "block-9", "label": "The diode M7 and M8 copy: a CMFB draws its current", "devices": [ { "scope": "dut", "device": "XML" } ], "inferredStages": [ "bias" ] }, { "id": "block-10", "label": "Output chopper", "devices": [ { "scope": "dut", "device": "XSO1" }, { "scope": "dut", "device": "XSO2" }, { "scope": "dut", "device": "XSO3" }, { "scope": "dut", "device": "XSO4" } ], "inferredStages": [ 2 ] }, { "id": "block-11", "label": "Second stage", "devices": [ { "scope": "dut", "device": "XM11" }, { "scope": "dut", "device": "XM12" } ], "inferredStages": [ "bias" ] }, { "id": "block-12", "label": "Second-stage current source", "devices": [ { "scope": "dut", "device": "XM13" }, { "scope": "dut", "device": "XM14" } ], "inferredStages": [ "bias" ] }, { "id": "block-13", "label": "Miller compensation", "devices": [ { "scope": "dut", "device": "XCC1" }, { "scope": "dut", "device": "XCC2" } ], "inferredStages": [ "bias" ] }, { "id": "block-14", "label": "Nulling resistor", "devices": [ { "scope": "dut", "device": "XRZ1" }, { "scope": "dut", "device": "XRZ2" } ], "inferredStages": [ "bias" ] } ], "edges": [ { "id": "net-1", "net": "ib", "nodes": [ "block-1", "block-2", "block-3", "block-12" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "nb", "nodes": [ "block-2", "block-5" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "vcp", "nodes": [ "block-2", "block-8" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "vcn", "nodes": [ "block-2", "block-6" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "tail", "nodes": [ "block-3", "block-4" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "f1", "nodes": [ "block-4", "block-5", "block-6" ], "direction": "undirected-shared-net" }, { "id": "net-7", "net": "f2", "nodes": [ "block-4", "block-5", "block-6" ], "direction": "undirected-shared-net" }, { "id": "net-8", "net": "o1", "nodes": [ "block-6", "block-8", "block-10" ], "direction": "undirected-shared-net" }, { "id": "net-9", "net": "o2", "nodes": [ "block-6", "block-8", "block-10" ], "direction": "undirected-shared-net" }, { "id": "net-10", "net": "k1", "nodes": [ "block-7", "block-8" ], "direction": "undirected-shared-net" }, { "id": "net-11", "net": "cmc", "nodes": [ "block-7", "block-9" ], "direction": "undirected-shared-net" }, { "id": "net-12", "net": "k2", "nodes": [ "block-7", "block-8" ], "direction": "undirected-shared-net" }, { "id": "net-13", "net": "g1", "nodes": [ "block-10", "block-11", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-14", "net": "g2", "nodes": [ "block-10", "block-11", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-15", "net": "outp", "nodes": [ "block-11", "block-12", "block-14" ], "direction": "undirected-shared-net" }, { "id": "net-16", "net": "outn", "nodes": [ "block-11", "block-12", "block-14" ], "direction": "undirected-shared-net" }, { "id": "net-17", "net": "z1", "nodes": [ "block-13", "block-14" ], "direction": "undirected-shared-net" }, { "id": "net-18", "net": "z2", "nodes": [ "block-13", "block-14" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "outp", "net": "outp", "kind": "output" }, { "name": "outn", "net": "outn", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" }, { "name": "cmc", "net": "cmc", "kind": "bias" }, { "name": "clk", "net": "clk", "kind": "clock" }, { "name": "clkb", "net": "clkb", "kind": "clock" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclk", "displayName": "Vclk", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vclk clk 0 dc {VDD}", "pins": [ { "id": "p", "net": "clk" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclkb", "displayName": "Vclkb", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vclkb clkb 0 dc 0", "pins": [ { "id": "p", "net": "clkb" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ib ib 0 5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bcm", "displayName": "Bcm", "spiceType": "B", "model": null, "parametersOrValue": "I=5u+50u*((v(outp)+v(outn))/2-v(vocm))", "source": "Bcm cmc 0 I=5u+50u*((v(outp)+v(outn))/2-v(vocm))", "pins": [ { "id": "p", "net": "cmc" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "outp", "outn", "vocm" ], "currentDevices": [] } }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vocm vocm 0 dc 600m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "chopota", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 ib cmc clk clkb chopota", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" }, { "id": "cmc", "net": "cmc" }, { "id": "clk", "net": "clk" }, { "id": "clkb", "net": "clkb" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/chopota" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 350m", "source": "Vicm icm 0 dc 350m", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Eod", "displayName": "Eod", "spiceType": "E", "model": null, "parametersOrValue": "1", "source": "Eod od 0 outp outn 1", "pins": [ { "id": "p", "net": "od" }, { "id": "n", "net": "0" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Eer", "displayName": "Eer", "spiceType": "E", "model": null, "parametersOrValue": "1", "source": "Eer er 0 vid odl 1", "pins": [ { "id": "p", "net": "er" }, { "id": "n", "net": "0" }, { "id": "cp", "net": "vid" }, { "id": "cn", "net": "odl" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Einp", "displayName": "Einp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Einp inp icm er 0 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "er" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Einn", "displayName": "Einn", "spiceType": "E", "model": null, "parametersOrValue": "-0.5", "source": "Einn inn icm er 0 -0.5", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "er" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lod", "displayName": "Lod", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lod od odl 1t", "pins": [ { "id": "p", "net": "od" }, { "id": "n", "net": "odl" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cod", "displayName": "Cod", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cod odl 0 1t", "pins": [ { "id": "p", "net": "odl" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vid", "displayName": "Vid", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Vid vid 0 dc 0 ac 1", "pins": [ { "id": "p", "net": "vid" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vclk", "pin": "n" }, { "device": "Vclkb", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Bcm", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" }, { "device": "Eod", "pin": "n" }, { "device": "Eer", "pin": "n" }, { "device": "Einp", "pin": "cn" }, { "device": "Einn", "pin": "cn" }, { "device": "Cod", "pin": "n" }, { "device": "Vid", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "Vclk", "pin": "p" }, { "device": "Xdut", "pin": "clk" } ], "ports": [], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "Vclkb", "pin": "p" }, { "device": "Xdut", "pin": "clkb" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "cmc", "ground": false, "terminals": [ { "device": "Bcm", "pin": "p" }, { "device": "Xdut", "pin": "cmc" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Eod", "pin": "cp" } ], "ports": [], "voltageReferences": [ "Bcm" ] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Eod", "pin": "cn" } ], "ports": [], "voltageReferences": [ "Bcm" ] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bcm" ] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Einp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Einn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Einp", "pin": "n" }, { "device": "Einn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "od", "ground": false, "terminals": [ { "device": "Eod", "pin": "p" }, { "device": "Lod", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "er", "ground": false, "terminals": [ { "device": "Eer", "pin": "p" }, { "device": "Einp", "pin": "cp" }, { "device": "Einn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "vid", "ground": false, "terminals": [ { "device": "Eer", "pin": "cp" }, { "device": "Vid", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "odl", "ground": false, "terminals": [ { "device": "Eer", "pin": "cn" }, { "device": "Lod", "pin": "n" }, { "device": "Cod", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/chopota", "name": "chopota", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" }, { "name": "cmc", "net": "cmc" }, { "name": "clk", "net": "clk" }, { "name": "clkb", "net": "clkb" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB2 nb nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMB3 vcp vcp vdd vdd sg13_lv_pmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB4", "displayName": "MB4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB4 vcp nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB5", "displayName": "MB5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB5 vcn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB6", "displayName": "MB6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.6u l=4u ng=1 m=1", "source": "XMB6 vcn vcn vss vss sg13_lv_nmos w=1.6u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM1 f1 inp tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM2 f2 inn tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM5 o1 vcn f1 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM6 o2 vcn f2 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM7 k1 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "cmc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM8 k2 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "cmc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM9 o1 vcp k1 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM10 o2 vcp k2 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML", "displayName": "ML", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XML cmc cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "cmc" }, { "id": "g", "net": "cmc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO1", "displayName": "SO1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO1 o1 clk g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO2", "displayName": "SO2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO2 o2 clk g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO3", "displayName": "SO3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO3 o1 clkb g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO4", "displayName": "SO4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO4 o2 clkb g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM11 outp g1 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "g1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM12 outn g2 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "g2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM13 outp ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM14 outn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC1 g1 z1 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC2 g2 z2 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB5", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM13", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XMB5", "pin": "s" }, { "device": "XMB5", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" }, { "device": "XML", "pin": "s" }, { "device": "XML", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMB2", "pin": "d" }, { "device": "XMB2", "pin": "g" }, { "device": "XMB4", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMB4", "pin": "s" }, { "device": "XMB4", "pin": "b" }, { "device": "XMB6", "pin": "s" }, { "device": "XMB6", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XSO1", "pin": "b" }, { "device": "XSO2", "pin": "b" }, { "device": "XSO3", "pin": "b" }, { "device": "XSO4", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XRZ1", "pin": "substrate" }, { "device": "XRZ2", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" }, { "device": "XMB4", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB5", "pin": "d" }, { "device": "XMB6", "pin": "d" }, { "device": "XMB6", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM9", "pin": "d" }, { "device": "XSO1", "pin": "d" }, { "device": "XSO3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XSO2", "pin": "d" }, { "device": "XSO4", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "cmc", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XML", "pin": "d" }, { "device": "XML", "pin": "g" } ], "ports": [ "cmc" ], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "XSO1", "pin": "g" }, { "device": "XSO2", "pin": "g" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "g1", "ground": false, "terminals": [ { "device": "XSO1", "pin": "s" }, { "device": "XSO4", "pin": "s" }, { "device": "XM11", "pin": "g" }, { "device": "XCC1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "g2", "ground": false, "terminals": [ { "device": "XSO2", "pin": "s" }, { "device": "XSO3", "pin": "s" }, { "device": "XM12", "pin": "g" }, { "device": "XCC2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "XSO3", "pin": "g" }, { "device": "XSO4", "pin": "g" } ], "ports": [ "clkb" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XRZ1", "pin": "n" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XRZ2", "pin": "n" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "z1", "ground": false, "terminals": [ { "device": "XCC1", "pin": "n" }, { "device": "XRZ1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z2", "ground": false, "terminals": [ { "device": "XCC2", "pin": "n" }, { "device": "XRZ2", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/chopota" } }, { "id": "graph-5", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclk", "displayName": "Vclk", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vclk clk 0 dc {VDD}", "pins": [ { "id": "p", "net": "clk" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclkb", "displayName": "Vclkb", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vclkb clkb 0 dc 0", "pins": [ { "id": "p", "net": "clkb" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ib ib 0 5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bcm", "displayName": "Bcm", "spiceType": "B", "model": null, "parametersOrValue": "I=5u+50u*((v(outp)+v(outn))/2-v(vocm))", "source": "Bcm cmc 0 I=5u+50u*((v(outp)+v(outn))/2-v(vocm))", "pins": [ { "id": "p", "net": "cmc" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "outp", "outn", "vocm" ], "currentDevices": [] } }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vocm vocm 0 dc 600m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "chopota", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 ib cmc clk clkb chopota", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" }, { "id": "cmc", "net": "cmc" }, { "id": "clk", "net": "clk" }, { "id": "clkb", "net": "clkb" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/chopota" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 350m", "source": "Vicm icm 0 dc 350m", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Eod", "displayName": "Eod", "spiceType": "E", "model": null, "parametersOrValue": "1", "source": "Eod od 0 outp outn 1", "pins": [ { "id": "p", "net": "od" }, { "id": "n", "net": "0" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Eer", "displayName": "Eer", "spiceType": "E", "model": null, "parametersOrValue": "1", "source": "Eer er 0 vid od 1", "pins": [ { "id": "p", "net": "er" }, { "id": "n", "net": "0" }, { "id": "cp", "net": "vid" }, { "id": "cn", "net": "od" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Einp", "displayName": "Einp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Einp inp icm er 0 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "er" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Einn", "displayName": "Einn", "spiceType": "E", "model": null, "parametersOrValue": "-0.5", "source": "Einn inn icm er 0 -0.5", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "er" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vid", "displayName": "Vid", "spiceType": "V", "model": null, "parametersOrValue": "pulse(-100m 100m 400n 1n 1n 2u 8u)", "source": "Vid vid 0 pulse(-100m 100m 400n 1n 1n 2u 8u)", "pins": [ { "id": "p", "net": "vid" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vclk", "pin": "n" }, { "device": "Vclkb", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Bcm", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" }, { "device": "Eod", "pin": "n" }, { "device": "Eer", "pin": "n" }, { "device": "Einp", "pin": "cn" }, { "device": "Einn", "pin": "cn" }, { "device": "Vid", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "Vclk", "pin": "p" }, { "device": "Xdut", "pin": "clk" } ], "ports": [], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "Vclkb", "pin": "p" }, { "device": "Xdut", "pin": "clkb" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "cmc", "ground": false, "terminals": [ { "device": "Bcm", "pin": "p" }, { "device": "Xdut", "pin": "cmc" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Eod", "pin": "cp" } ], "ports": [], "voltageReferences": [ "Bcm" ] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Eod", "pin": "cn" } ], "ports": [], "voltageReferences": [ "Bcm" ] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bcm" ] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Einp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Einn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Einp", "pin": "n" }, { "device": "Einn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "od", "ground": false, "terminals": [ { "device": "Eod", "pin": "p" }, { "device": "Eer", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "er", "ground": false, "terminals": [ { "device": "Eer", "pin": "p" }, { "device": "Einp", "pin": "cp" }, { "device": "Einn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "vid", "ground": false, "terminals": [ { "device": "Eer", "pin": "cp" }, { "device": "Vid", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/chopota", "name": "chopota", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" }, { "name": "cmc", "net": "cmc" }, { "name": "clk", "net": "clk" }, { "name": "clkb", "net": "clkb" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB2 nb nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMB3 vcp vcp vdd vdd sg13_lv_pmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB4", "displayName": "MB4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB4 vcp nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB5", "displayName": "MB5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB5 vcn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB6", "displayName": "MB6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.6u l=4u ng=1 m=1", "source": "XMB6 vcn vcn vss vss sg13_lv_nmos w=1.6u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM1 f1 inp tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM2 f2 inn tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM5 o1 vcn f1 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM6 o2 vcn f2 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM7 k1 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "cmc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM8 k2 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "cmc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM9 o1 vcp k1 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM10 o2 vcp k2 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML", "displayName": "ML", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XML cmc cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "cmc" }, { "id": "g", "net": "cmc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO1", "displayName": "SO1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO1 o1 clk g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO2", "displayName": "SO2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO2 o2 clk g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO3", "displayName": "SO3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO3 o1 clkb g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO4", "displayName": "SO4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO4 o2 clkb g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM11 outp g1 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "g1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM12 outn g2 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "g2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM13 outp ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM14 outn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC1 g1 z1 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC2 g2 z2 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB5", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM13", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XMB5", "pin": "s" }, { "device": "XMB5", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" }, { "device": "XML", "pin": "s" }, { "device": "XML", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMB2", "pin": "d" }, { "device": "XMB2", "pin": "g" }, { "device": "XMB4", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMB4", "pin": "s" }, { "device": "XMB4", "pin": "b" }, { "device": "XMB6", "pin": "s" }, { "device": "XMB6", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XSO1", "pin": "b" }, { "device": "XSO2", "pin": "b" }, { "device": "XSO3", "pin": "b" }, { "device": "XSO4", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XRZ1", "pin": "substrate" }, { "device": "XRZ2", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" }, { "device": "XMB4", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB5", "pin": "d" }, { "device": "XMB6", "pin": "d" }, { "device": "XMB6", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM9", "pin": "d" }, { "device": "XSO1", "pin": "d" }, { "device": "XSO3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XSO2", "pin": "d" }, { "device": "XSO4", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "cmc", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XML", "pin": "d" }, { "device": "XML", "pin": "g" } ], "ports": [ "cmc" ], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "XSO1", "pin": "g" }, { "device": "XSO2", "pin": "g" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "g1", "ground": false, "terminals": [ { "device": "XSO1", "pin": "s" }, { "device": "XSO4", "pin": "s" }, { "device": "XM11", "pin": "g" }, { "device": "XCC1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "g2", "ground": false, "terminals": [ { "device": "XSO2", "pin": "s" }, { "device": "XSO3", "pin": "s" }, { "device": "XM12", "pin": "g" }, { "device": "XCC2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "XSO3", "pin": "g" }, { "device": "XSO4", "pin": "g" } ], "ports": [ "clkb" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XRZ1", "pin": "n" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XRZ2", "pin": "n" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "z1", "ground": false, "terminals": [ { "device": "XCC1", "pin": "n" }, { "device": "XRZ1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z2", "ground": false, "terminals": [ { "device": "XCC2", "pin": "n" }, { "device": "XRZ2", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/chopota" } }, { "id": "graph-6", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclk", "displayName": "Vclk", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vclk clk 0 dc {VDD}", "pins": [ { "id": "p", "net": "clk" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclkb", "displayName": "Vclkb", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vclkb clkb 0 dc 0", "pins": [ { "id": "p", "net": "clkb" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ib ib 0 5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bcm", "displayName": "Bcm", "spiceType": "B", "model": null, "parametersOrValue": "I=5u+50u*((v(outp)+v(outn))/2-v(vocm))", "source": "Bcm cmc 0 I=5u+50u*((v(outp)+v(outn))/2-v(vocm))", "pins": [ { "id": "p", "net": "cmc" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "outp", "outn", "vocm" ], "currentDevices": [] } }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "pulse(600m 650m 400n 1n 1n 4u 16u)", "source": "Vocm vocm 0 pulse(600m 650m 400n 1n 1n 4u 16u)", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "chopota", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 ib cmc clk clkb chopota", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" }, { "id": "cmc", "net": "cmc" }, { "id": "clk", "net": "clk" }, { "id": "clkb", "net": "clkb" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/chopota" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 350m", "source": "Vicm icm 0 dc 350m", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Eod", "displayName": "Eod", "spiceType": "E", "model": null, "parametersOrValue": "1", "source": "Eod od 0 outp outn 1", "pins": [ { "id": "p", "net": "od" }, { "id": "n", "net": "0" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Eer", "displayName": "Eer", "spiceType": "E", "model": null, "parametersOrValue": "1", "source": "Eer er 0 vid od 1", "pins": [ { "id": "p", "net": "er" }, { "id": "n", "net": "0" }, { "id": "cp", "net": "vid" }, { "id": "cn", "net": "od" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Einp", "displayName": "Einp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Einp inp icm er 0 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "er" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Einn", "displayName": "Einn", "spiceType": "E", "model": null, "parametersOrValue": "-0.5", "source": "Einn inn icm er 0 -0.5", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "er" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vid", "displayName": "Vid", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vid vid 0 dc 0", "pins": [ { "id": "p", "net": "vid" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vclk", "pin": "n" }, { "device": "Vclkb", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Bcm", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" }, { "device": "Eod", "pin": "n" }, { "device": "Eer", "pin": "n" }, { "device": "Einp", "pin": "cn" }, { "device": "Einn", "pin": "cn" }, { "device": "Vid", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "Vclk", "pin": "p" }, { "device": "Xdut", "pin": "clk" } ], "ports": [], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "Vclkb", "pin": "p" }, { "device": "Xdut", "pin": "clkb" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "cmc", "ground": false, "terminals": [ { "device": "Bcm", "pin": "p" }, { "device": "Xdut", "pin": "cmc" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Eod", "pin": "cp" } ], "ports": [], "voltageReferences": [ "Bcm" ] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Eod", "pin": "cn" } ], "ports": [], "voltageReferences": [ "Bcm" ] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bcm" ] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Einp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Einn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Einp", "pin": "n" }, { "device": "Einn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "od", "ground": false, "terminals": [ { "device": "Eod", "pin": "p" }, { "device": "Eer", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "er", "ground": false, "terminals": [ { "device": "Eer", "pin": "p" }, { "device": "Einp", "pin": "cp" }, { "device": "Einn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "vid", "ground": false, "terminals": [ { "device": "Eer", "pin": "cp" }, { "device": "Vid", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/chopota", "name": "chopota", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" }, { "name": "cmc", "net": "cmc" }, { "name": "clk", "net": "clk" }, { "name": "clkb", "net": "clkb" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB2 nb nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMB3 vcp vcp vdd vdd sg13_lv_pmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB4", "displayName": "MB4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB4 vcp nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB5", "displayName": "MB5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB5 vcn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB6", "displayName": "MB6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.6u l=4u ng=1 m=1", "source": "XMB6 vcn vcn vss vss sg13_lv_nmos w=1.6u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM1 f1 inp tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM2 f2 inn tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM5 o1 vcn f1 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM6 o2 vcn f2 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM7 k1 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "cmc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM8 k2 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "cmc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM9 o1 vcp k1 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM10 o2 vcp k2 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML", "displayName": "ML", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XML cmc cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "cmc" }, { "id": "g", "net": "cmc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO1", "displayName": "SO1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO1 o1 clk g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO2", "displayName": "SO2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO2 o2 clk g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO3", "displayName": "SO3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO3 o1 clkb g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO4", "displayName": "SO4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO4 o2 clkb g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM11 outp g1 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "g1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM12 outn g2 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "g2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM13 outp ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM14 outn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC1 g1 z1 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC2 g2 z2 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB5", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM13", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XMB5", "pin": "s" }, { "device": "XMB5", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" }, { "device": "XML", "pin": "s" }, { "device": "XML", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMB2", "pin": "d" }, { "device": "XMB2", "pin": "g" }, { "device": "XMB4", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMB4", "pin": "s" }, { "device": "XMB4", "pin": "b" }, { "device": "XMB6", "pin": "s" }, { "device": "XMB6", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XSO1", "pin": "b" }, { "device": "XSO2", "pin": "b" }, { "device": "XSO3", "pin": "b" }, { "device": "XSO4", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XRZ1", "pin": "substrate" }, { "device": "XRZ2", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" }, { "device": "XMB4", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB5", "pin": "d" }, { "device": "XMB6", "pin": "d" }, { "device": "XMB6", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM9", "pin": "d" }, { "device": "XSO1", "pin": "d" }, { "device": "XSO3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XSO2", "pin": "d" }, { "device": "XSO4", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "cmc", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XML", "pin": "d" }, { "device": "XML", "pin": "g" } ], "ports": [ "cmc" ], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "XSO1", "pin": "g" }, { "device": "XSO2", "pin": "g" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "g1", "ground": false, "terminals": [ { "device": "XSO1", "pin": "s" }, { "device": "XSO4", "pin": "s" }, { "device": "XM11", "pin": "g" }, { "device": "XCC1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "g2", "ground": false, "terminals": [ { "device": "XSO2", "pin": "s" }, { "device": "XSO3", "pin": "s" }, { "device": "XM12", "pin": "g" }, { "device": "XCC2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "XSO3", "pin": "g" }, { "device": "XSO4", "pin": "g" } ], "ports": [ "clkb" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XRZ1", "pin": "n" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XRZ2", "pin": "n" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "z1", "ground": false, "terminals": [ { "device": "XCC1", "pin": "n" }, { "device": "XRZ1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z2", "ground": false, "terminals": [ { "device": "XCC2", "pin": "n" }, { "device": "XRZ2", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/chopota" } }, { "id": "graph-7", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclk", "displayName": "Vclk", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vclk clk 0 dc {VDD}", "pins": [ { "id": "p", "net": "clk" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclkb", "displayName": "Vclkb", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vclkb clkb 0 dc 0", "pins": [ { "id": "p", "net": "clkb" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ib ib 0 5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bcm", "displayName": "Bcm", "spiceType": "B", "model": null, "parametersOrValue": "I=5u+50u*((v(outp)+v(outn))/2-v(vocm))", "source": "Bcm cmc 0 I=5u+50u*((v(outp)+v(outn))/2-v(vocm))", "pins": [ { "id": "p", "net": "cmc" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "outp", "outn", "vocm" ], "currentDevices": [] } }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vocm vocm 0 dc 600m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "chopota", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 ib cmc clk clkb chopota", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" }, { "id": "cmc", "net": "cmc" }, { "id": "clk", "net": "clk" }, { "id": "clkb", "net": "clkb" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/chopota" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 350m", "source": "Vicm icm 0 dc 350m", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Eod", "displayName": "Eod", "spiceType": "E", "model": null, "parametersOrValue": "1", "source": "Eod od 0 outp outn 1", "pins": [ { "id": "p", "net": "od" }, { "id": "n", "net": "0" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Eer", "displayName": "Eer", "spiceType": "E", "model": null, "parametersOrValue": "1", "source": "Eer er 0 vid od 1", "pins": [ { "id": "p", "net": "er" }, { "id": "n", "net": "0" }, { "id": "cp", "net": "vid" }, { "id": "cn", "net": "od" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Einp", "displayName": "Einp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Einp inp icm er 0 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "er" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Einn", "displayName": "Einn", "spiceType": "E", "model": null, "parametersOrValue": "-0.5", "source": "Einn inn icm er 0 -0.5", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "er" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vid", "displayName": "Vid", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Vid vid 0 dc 0 ac 1", "pins": [ { "id": "p", "net": "vid" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vclk", "pin": "n" }, { "device": "Vclkb", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Bcm", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" }, { "device": "Eod", "pin": "n" }, { "device": "Eer", "pin": "n" }, { "device": "Einp", "pin": "cn" }, { "device": "Einn", "pin": "cn" }, { "device": "Vid", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "Vclk", "pin": "p" }, { "device": "Xdut", "pin": "clk" } ], "ports": [], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "Vclkb", "pin": "p" }, { "device": "Xdut", "pin": "clkb" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "cmc", "ground": false, "terminals": [ { "device": "Bcm", "pin": "p" }, { "device": "Xdut", "pin": "cmc" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Eod", "pin": "cp" } ], "ports": [], "voltageReferences": [ "Bcm" ] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Eod", "pin": "cn" } ], "ports": [], "voltageReferences": [ "Bcm" ] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bcm" ] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Einp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Einn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Einp", "pin": "n" }, { "device": "Einn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "od", "ground": false, "terminals": [ { "device": "Eod", "pin": "p" }, { "device": "Eer", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "er", "ground": false, "terminals": [ { "device": "Eer", "pin": "p" }, { "device": "Einp", "pin": "cp" }, { "device": "Einn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "vid", "ground": false, "terminals": [ { "device": "Eer", "pin": "cp" }, { "device": "Vid", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/chopota", "name": "chopota", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" }, { "name": "cmc", "net": "cmc" }, { "name": "clk", "net": "clk" }, { "name": "clkb", "net": "clkb" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB2 nb nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMB3 vcp vcp vdd vdd sg13_lv_pmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB4", "displayName": "MB4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB4 vcp nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB5", "displayName": "MB5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB5 vcn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB6", "displayName": "MB6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.6u l=4u ng=1 m=1", "source": "XMB6 vcn vcn vss vss sg13_lv_nmos w=1.6u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM1 f1 inp tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM2 f2 inn tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM5 o1 vcn f1 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM6 o2 vcn f2 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM7 k1 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "cmc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM8 k2 cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "cmc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM9 o1 vcp k1 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM10 o2 vcp k2 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML", "displayName": "ML", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XML cmc cmc vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "cmc" }, { "id": "g", "net": "cmc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO1", "displayName": "SO1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO1 o1 clk g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO2", "displayName": "SO2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO2 o2 clk g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO3", "displayName": "SO3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO3 o1 clkb g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO4", "displayName": "SO4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO4 o2 clkb g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM11 outp g1 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "g1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM12 outn g2 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "g2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM13 outp ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM14 outn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC1 g1 z1 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC2 g2 z2 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB5", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM13", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XMB5", "pin": "s" }, { "device": "XMB5", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" }, { "device": "XML", "pin": "s" }, { "device": "XML", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMB2", "pin": "d" }, { "device": "XMB2", "pin": "g" }, { "device": "XMB4", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMB4", "pin": "s" }, { "device": "XMB4", "pin": "b" }, { "device": "XMB6", "pin": "s" }, { "device": "XMB6", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XSO1", "pin": "b" }, { "device": "XSO2", "pin": "b" }, { "device": "XSO3", "pin": "b" }, { "device": "XSO4", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XRZ1", "pin": "substrate" }, { "device": "XRZ2", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" }, { "device": "XMB4", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB5", "pin": "d" }, { "device": "XMB6", "pin": "d" }, { "device": "XMB6", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM9", "pin": "d" }, { "device": "XSO1", "pin": "d" }, { "device": "XSO3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XSO2", "pin": "d" }, { "device": "XSO4", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "cmc", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XML", "pin": "d" }, { "device": "XML", "pin": "g" } ], "ports": [ "cmc" ], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "XSO1", "pin": "g" }, { "device": "XSO2", "pin": "g" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "g1", "ground": false, "terminals": [ { "device": "XSO1", "pin": "s" }, { "device": "XSO4", "pin": "s" }, { "device": "XM11", "pin": "g" }, { "device": "XCC1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "g2", "ground": false, "terminals": [ { "device": "XSO2", "pin": "s" }, { "device": "XSO3", "pin": "s" }, { "device": "XM12", "pin": "g" }, { "device": "XCC2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "XSO3", "pin": "g" }, { "device": "XSO4", "pin": "g" } ], "ports": [ "clkb" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XRZ1", "pin": "n" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XRZ2", "pin": "n" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "z1", "ground": false, "terminals": [ { "device": "XCC1", "pin": "n" }, { "device": "XRZ1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z2", "ground": false, "terminals": [ { "device": "XCC2", "pin": "n" }, { "device": "XRZ2", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/chopota" } } ], "views": [ { "bench": "op", "source": { "recordField": "testbenches", "id": "op", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/chopper-ota-core/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Chopper OTA core, common mode set from outside", "instances": [] } ] }, "benchDiagram": { "graph": "graph-2", "svg": { "url": "/circuits/chopper-ota-core/op-bench.svg", "asset": "op-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/chopper-ota-core/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "open_loop", "source": { "recordField": "testbenches", "id": "open_loop", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/chopper-ota-core/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Chopper OTA core, common mode set from outside", "instances": [] } ] }, "benchDiagram": { "graph": "graph-4", "svg": { "url": "/circuits/chopper-ota-core/open_loop-bench.svg", "asset": "open_loop-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/chopper-ota-core/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "step", "source": { "recordField": "testbenches", "id": "step", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/chopper-ota-core/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Chopper OTA core, common mode set from outside", "instances": [] } ] }, "benchDiagram": { "graph": "graph-5", "svg": { "url": "/circuits/chopper-ota-core/step-bench.svg", "asset": "step-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/chopper-ota-core/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "cm", "source": { "recordField": "testbenches", "id": "cm", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/chopper-ota-core/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Chopper OTA core, common mode set from outside", "instances": [] } ] }, "benchDiagram": { "graph": "graph-6", "svg": { "url": "/circuits/chopper-ota-core/cm-bench.svg", "asset": "cm-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/chopper-ota-core/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "noise", "source": { "recordField": "testbenches", "id": "noise", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/chopper-ota-core/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Chopper OTA core, common mode set from outside", "instances": [] } ] }, "benchDiagram": { "graph": "graph-7", "svg": { "url": "/circuits/chopper-ota-core/noise-bench.svg", "asset": "noise-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/chopper-ota-core/op-block.svg", "asset": "op-block.svg" } } } ] } }