{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "chopper-tg", "name": "Differential chopper, transmission gates", "group": "Switches and sampling", "subgroup": "Switches", "title": "Differential chopper, transmission gates", "summary": "This switch network repeatedly swaps two signal wires. Straight connections preserve the input difference; crossed connections reverse it, moving a slow signal around the clock frequency. A second synchronized chopper can recover the signal, while switch resistance and clock edges introduce errors.", "reference": { "kind": "paper", "authors": "C. C. Enz, G. C. Temes", "title": "Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization", "year": 1996, "where": "Proceedings of the IEEE, 84(11):1584-1614", "doi": "10.1109/5.542410", "takes": "The chopper as a multiplier by a ±1 square wave, and why its residual offset comes from the charge its switches release at the edges. The transmission-gate cell, its sizing and its benches are this library's, for SG13G2 at 1.2 V.", "also": [ { "authors": "Q. Fan, F. Sebastiano, J. H. Huijsing, K. A. A. Makinwa", "title": "A 1.8 uW 60 nV/sqrt(Hz) Capacitively-Coupled Chopper Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor Nodes", "year": 2011, "where": "IEEE Journal of Solid-State Circuits, 46(7):1534-1543", "doi": "10.1109/JSSC.2011.2143610" } ] }, "resources": { "record": "/circuits/chopper-tg.json", "page": "/index.html#chopper-tg", "achieved": "/achieved/chopper-tg.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice" ], "ports": [ { "name": "inp", "kind": "input" }, { "name": "inn", "kind": "input" }, { "name": "outp", "kind": "output" }, { "name": "outn", "kind": "output" }, { "name": "clk", "kind": "clock", "note": "high: straight, inp to outp and inn to outn" }, { "name": "clkb", "kind": "clock", "note": "high: crossed, inp to outn and inn to outp" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" } ], "devices": [ { "name": "S1n", "type": "nmos", "nodes": "inp clk outp vss", "sizedBy": [ "Wsw", "Lsw" ], "role": "chopper, straight while clk is high (NMOS half)", "fingers": 1, "copies": 1 }, { "name": "S1p", "type": "pmos", "nodes": "inp clkb outp vdd", "sizedBy": [ "Wsw", "Lsw" ], "role": "chopper, straight while clk is high (PMOS half, twice the NMOS width)", "fingers": 1, "copies": 1 }, { "name": "S2n", "type": "nmos", "nodes": "inn clk outn vss", "sizedBy": [ "Wsw", "Lsw" ], "role": "chopper, straight while clk is high (NMOS half)", "fingers": 1, "copies": 1 }, { "name": "S2p", "type": "pmos", "nodes": "inn clkb outn vdd", "sizedBy": [ "Wsw", "Lsw" ], "role": "chopper, straight while clk is high (PMOS half, twice the NMOS width)", "fingers": 1, "copies": 1 }, { "name": "S3n", "type": "nmos", "nodes": "inp clkb outn vss", "sizedBy": [ "Wsw", "Lsw" ], "role": "chopper, crossed while clkb is high (NMOS half)", "fingers": 1, "copies": 1 }, { "name": "S3p", "type": "pmos", "nodes": "inp clk outn vdd", "sizedBy": [ "Wsw", "Lsw" ], "role": "chopper, crossed while clkb is high (PMOS half, twice the NMOS width)", "fingers": 1, "copies": 1 }, { "name": "S4n", "type": "nmos", "nodes": "inn clkb outp vss", "sizedBy": [ "Wsw", "Lsw" ], "role": "chopper, crossed while clkb is high (NMOS half)", "fingers": 1, "copies": 1 }, { "name": "S4p", "type": "pmos", "nodes": "inn clk outp vdd", "sizedBy": [ "Wsw", "Lsw" ], "role": "chopper, crossed while clkb is high (PMOS half, twice the NMOS width)", "fingers": 1, "copies": 1 } ], "intent": [ { "rule": "match", "of": [ "S1n", "S2n", "S3n", "S4n" ], "why": "The four NMOS halves: a chopper's gain is the same in both phases only when its straight and crossed paths match, and the charge they release at an edge cancels in the difference only when they do." }, { "rule": "match", "of": [ "S1p", "S2p", "S3p", "S4p" ], "why": "The four PMOS halves, for the same reasons." }, { "rule": "complementary", "of": [ "S1n", "S1p" ], "constraint": "PMOS half twice the NMOS half", "why": "An NMOS stops conducting a threshold below its gate, a PMOS a threshold above ground: together they conduct across the supply, and the PMOS's lower mobility is met by twice the width." }, { "rule": "break-before-make", "of": [ "S1n", "S3n" ], "constraint": "check simultaneous conduction and clock skew over the intended signal range", "why": "Complementary clocks illustrate operation at the default mid-supply point, but do not guarantee non-overlap across the whole signal range. Near either rail, straight and crossed paths can conduct together during an edge and temporarily connect the inputs. Physical reuse needs edge and skew verification, with explicit break-before-make control where required." }, { "rule": "trade", "of": [ "S1n", "S1p" ], "constraint": "R_on against charge per edge", "why": "A wider gate conducts better and releases more channel charge at every edge; minimum length gives the least of both, a longer one only adds." } ], "specs": [ { "key": "ron", "label": "On-resistance at mid-supply", "unit": "Ω", "direction": "min", "constraint": "<= 5000 Ω", "min": null, "max": 5000, "why": "Small beside the 10 pF an amplifier's input chopper charges in a 25 µs half period: 5 kΩ is a 50 ns time constant, five hundred times shorter." }, { "key": "ron_max", "label": "Highest on-resistance over the range", "unit": "Ω", "direction": "min", "constraint": "<= 8000 Ω", "min": null, "max": 8000, "why": "Across the whole signal range, not only at mid-supply: where the NMOS half fades the PMOS half carries." }, { "key": "swap", "label": "Crossed over straight", "unit": "V/V", "direction": "target", "constraint": ">= -1.01 V/V, <= -0.99 V/V", "min": -1.01, "max": -0.99, "why": "A chopper multiplies by +1 and -1: the crossed phase must give the straight phase's output, inverted, to within the four gates' match." }, { "key": "loss_pct", "label": "Loss into the load", "unit": "%", "direction": "min", "constraint": "<= 5 %", "min": null, "max": 5, "why": "Into 100 kΩ the gates lose R_on/(R_L + R_on), a few percent at most, the same in both phases." }, { "key": "spike", "label": "Common-mode spike at a clock edge", "unit": "V", "direction": "min", "constraint": "<= 0.005 V", "min": null, "max": 0.005, "why": "A minimum-length gate releases about a femtocoulomb of channel charge at an edge: on a 1 pF load, a millivolt or two, on both outputs alike." } ], "explanation": { "idea": "This switch network repeatedly swaps two signal wires. Straight connections preserve the input difference; crossed connections reverse it, moving a slow signal around the clock frequency. A second synchronized chopper can recover the signal, while switch resistance and clock edges introduce errors.", "detail": "Multiplies a differential signal approximately by a square wave of +1 and −1: the modulator at each end of a chopper amplifier. While clk is high the straight transmission gates pass inp to outp and inn to outn; while clkb is high the crossed gates swap them, so the output difference changes sign every half period. Each gate combines NMOS and PMOS devices to improve conduction across the supply range. Complementary clocks alone do not guarantee non-overlap throughout that range: simultaneous straight and crossed conduction near an edge can temporarily connect the inputs.", "lesson": { "relation": 2, "symbols": "A is the settled signal-voltage gain magnitude; R_L is the load resistance on each output; R_on is the transmission-gate resistance; R_on,n and R_on,p are its NMOS and PMOS resistances, whose parallel combination is denoted by ∥.", "assumptions": "The resistive-divider estimate describes a settled phase with matched paths and approximately constant switch resistance. It excludes clock-edge charge injection, overlap conduction and incomplete capacitive settling.", "exercise": { "param": "RL", "value": 200000, "analysis": "chop", "expect": "A lighter resistive load should reduce the settled amplitude loss. The crossed-to-straight ratio should remain close to minus one; inspect clock-edge spikes separately from that settled ratio." }, "limits": "Supply the clock pair externally. Check simultaneous conduction and clock skew over the intended signal range; explicit break-before-make control may be needed. The default ideal sources do not establish input disturbance on a high-impedance source or a complete chopper amplifier's noise performance." }, "path": [ { "part": "Straight gates", "devices": "S1n, S1p, S2n, S2p", "does": "On while clk is high: inp to outp and inn to outn, so the output difference is the input's, less what R_on drops into the load." }, { "part": "Crossed gates", "devices": "S3n, S3p, S4n, S4p", "does": "On while clkb is high: inp to outn and inn to outp, so the output difference is the input's, inverted." }, { "part": "Edges", "devices": "S1n, S1p, S3n, S3p", "does": "At each edge the outgoing gates release channel charge and couple the clock into the signal nodes. Matching helps make the disturbance common to both outputs, but signal dependence, mismatch, skew and overlap can leave a differential error." } ], "bias": "Nothing is biased: clk and clkb, complementary between 0 and V_DD, choose which gates conduct. At mid-supply, the worst place, each half has about 0.1 V of overdrive past its threshold and body effect; the benches chop at 20 kHz into 100 kΩ and 1 pF returned to 0.6 V.", "relations": [ { "what": "Modulation", "expr": "v_out,d(t) = m(t)·v_in,d(t), m = ±1", "note": "The clocked bench reads the crossed phase over the straight one: −1.000." }, { "what": "Chopping spectrum", "expr": "m(t) = (4/π)·Σ sin(n·ω_ch·t)/n, n odd", "note": "A signal moves to f_ch ± f, 3f_ch ± f and on; a second chopper in step brings it back." }, { "what": "Loss into a load", "expr": "A = R_L/(R_L + R_on), R_on = R_on,n ∥ R_on,p", "note": "About 2.3 kΩ at mid-supply: 2 % into 100 kΩ, the same in both phases when the four gates match." }, { "what": "Residual offset", "expr": "V_os,res ≈ 2·f_ch·τ·ΔV_spike", "note": "Only the difference between the two sides' edge spikes survives demodulation: a matter of the gates' match." } ], "tradeoffs": [ "Switch width (Wsw): wider lowers R_on and the loss into a load, but releases more channel charge at every edge and loads the clock more.", "Switch length (Lsw): minimum length gives the least R_on for the least channel charge; a longer gate only adds both.", "PMOS-to-NMOS ratio (fixed at 2): it sets where across the range R_on peaks and how the two halves' charges cancel." ] }, "sizing": [ { "key": "Wsw", "label": "W switch, NMOS half (PMOS twice)", "unit": "m", "value": 0.000002, "min": 1.5e-7, "max": 0.00002, "kind": "si" }, { "key": "Lsw", "label": "L switch", "unit": "m", "value": 1.3e-7, "min": 1.3e-7, "max": 0.000001, "kind": "si" }, { "key": "VCM", "label": "Signal common mode", "unit": "V", "value": 0.6, "min": 0.1, "max": 1.1, "kind": "si" }, { "key": "fch", "label": "Chopping frequency", "unit": "Hz", "value": 20000, "min": 1000, "max": 1000000, "kind": "si" }, { "key": "Vid", "label": "Input difference the clocked bench applies", "unit": "V", "value": 0.1, "min": 0.001, "max": 0.5, "kind": "si" }, { "key": "RL", "label": "Load resistance, each output", "unit": "Ω", "value": 100000, "min": 1000, "max": 10000000, "kind": "si" }, { "key": "CL", "label": "Load capacitance, each output", "unit": "F", "value": 1e-12, "min": 1e-13, "max": 2e-11, "kind": "si" } ], "testbenches": [ { "id": "ron", "label": "On-resistance, one phase held", "note": "The clocks held straight, a 10uA current drawn through the switch from inp to outp while inp is swept across the supply: its on-resistance at every level a signal can take. The other input sits at mid-supply.", "measures": [], "metricKeys": [ "ron", "ron_max" ], "acceptance": [ "ron", "ron_max" ], "acceptanceRules": [ { "key": "ron", "unit": "Ω", "min": null, "max": 5000, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "ron_max", "unit": "Ω", "min": null, "max": 8000, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Differential chopper, transmission gates - on-resistance across the signal range\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n* the clocks held: clk high, clkb low - every chopper straight\nVclk clk 0 dc {VDD}\nVclkb clkb 0 dc 0\n.subckt chop inp inn outp outn clk clkb vdd vss\nXS1n inp clk outp vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXS1p inp clkb outp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXS2n inn clk outn vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXS2p inn clkb outn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXS3n inp clkb outn vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXS3p inp clk outn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXS4n inn clkb outp vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXS4p inn clk outp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\n.ends\nXdut inp inn outp outn clk clkb vdd 0 chop\nVin inp 0 dc 0\nVn inn 0 dc 600m\nIload outp 0 dc 10u\nRn outn 0 1meg\n.dc Vin 0.05 1.15 0.01\n.end" }, { "id": "chop", "label": "Clocked into a load", "note": "The clocks running, a DC difference on the inputs, each output loaded by a resistor and a capacitor to mid-supply: the output difference must swap sign every half period with the same size, less only what the switches drop into the load.", "measures": [], "metricKeys": [ "swap", "loss_pct", "spike" ], "acceptance": [ "swap", "loss_pct", "spike" ], "acceptanceRules": [ { "key": "swap", "unit": "V/V", "min": -1.01, "max": -0.99, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "loss_pct", "unit": "%", "min": null, "max": 5, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "spike", "unit": "V", "min": null, "max": 0.005, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Differential chopper, transmission gates - clocked into a load\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n* the clocks: 20kHz, clk high (straight) for the first half period, 20ns edges\nVclk clk 0 pulse({VDD} 0 25u 20n 20n 24.98u 50u)\nVclkb clkb 0 pulse(0 {VDD} 25u 20n 20n 24.98u 50u)\n.subckt chop inp inn outp outn clk clkb vdd vss\nXS1n inp clk outp vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXS1p inp clkb outp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXS2n inn clk outn vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXS2p inn clkb outn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXS3n inp clkb outn vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXS3p inp clk outn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXS4n inn clkb outp vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXS4p inn clk outp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\n.ends\nXdut inp inn outp outn clk clkb vdd 0 chop\nVinp inp 0 dc 650m\nVinn inn 0 dc 550m\nVmid mid 0 dc 600m\nRlp outp mid 100k\nRln outn mid 100k\nClp outp mid 1p\nCln outn mid 1p\n.tran 25n 100u 0 100n\n.end" } ], "measurements": { "ron": { "label": "On-resistance at mid-supply", "unit": "Ω", "spec": { "min": null, "max": 5000 } }, "ron_max": { "label": "Highest on-resistance over the range", "unit": "Ω", "spec": { "min": null, "max": 8000 } }, "swap": { "label": "Crossed over straight", "unit": "V/V", "spec": { "min": -1.01, "max": -0.99 } }, "loss_pct": { "label": "Loss into the load", "unit": "%", "spec": { "min": null, "max": 5 } }, "spike": { "label": "Common-mode spike at a clock edge", "unit": "V", "spec": { "min": null, "max": 0.005 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "66e8b27c1b707ccc895df33a1e27b5b1934f54a3e1827d6dd15d6523aeaae391" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/chopper-tg.js", "sha256": "0cf5b7682b99e61605f1164aab148179605f58bbdb4e38f5b0376632784a769e" }, "simulationFingerprints": { "ron": "43a280630ee4a21ad163c1c57d9c8fa6ef195e8b5241911ac082601a5a59d41b", "chop": "8eb64ac38ef5c98a41616e57d6d8f22091478af55c3e21ec599df0ce30d422cc" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "16f2c5f7d6820df73b361a73aed2b0210871286f6d69f92936989ccbad1056dd", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "chopper-tg", "parameters": { "Wsw": 0.000002, "Lsw": 1.3e-7, "VCM": 0.6, "fch": 20000, "Vid": 0.1, "RL": 100000, "CL": 1e-12 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/chopper-tg/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "chop", "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "outp", "net": "outp", "kind": "output" }, { "name": "outn", "net": "outn", "kind": "output" }, { "name": "clk", "net": "clk", "kind": "clock" }, { "name": "clkb", "net": "clkb", "kind": "clock" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" } ], "definitions": [], "devices": [ { "id": "XS1n", "displayName": "S1n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS1n inp clk outp vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "outp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS1p", "displayName": "S1p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XS1p inp clkb outp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "outp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS2n", "displayName": "S2n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS2n inn clk outn vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "outn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS2p", "displayName": "S2p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XS2p inn clkb outn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "outn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS3n", "displayName": "S3n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS3n inp clkb outn vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "outn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS3p", "displayName": "S3p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XS3p inp clk outn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "outn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS4n", "displayName": "S4n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS4n inn clkb outp vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "outp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS4p", "displayName": "S4p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XS4p inn clk outp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "outp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "inp", "ground": false, "terminals": [ { "device": "XS1n", "pin": "d" }, { "device": "XS1p", "pin": "d" }, { "device": "XS3n", "pin": "d" }, { "device": "XS3p", "pin": "d" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "XS1n", "pin": "g" }, { "device": "XS2n", "pin": "g" }, { "device": "XS3p", "pin": "g" }, { "device": "XS4p", "pin": "g" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XS1n", "pin": "s" }, { "device": "XS1p", "pin": "s" }, { "device": "XS4n", "pin": "s" }, { "device": "XS4p", "pin": "s" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XS1n", "pin": "b" }, { "device": "XS2n", "pin": "b" }, { "device": "XS3n", "pin": "b" }, { "device": "XS4n", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "XS1p", "pin": "g" }, { "device": "XS2p", "pin": "g" }, { "device": "XS3n", "pin": "g" }, { "device": "XS4n", "pin": "g" } ], "ports": [ "clkb" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XS1p", "pin": "b" }, { "device": "XS2p", "pin": "b" }, { "device": "XS3p", "pin": "b" }, { "device": "XS4p", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XS2n", "pin": "d" }, { "device": "XS2p", "pin": "d" }, { "device": "XS4n", "pin": "d" }, { "device": "XS4p", "pin": "d" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XS2n", "pin": "s" }, { "device": "XS2p", "pin": "s" }, { "device": "XS3n", "pin": "s" }, { "device": "XS3p", "pin": "s" } ], "ports": [ "outn" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclk", "displayName": "Vclk", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vclk clk 0 dc {VDD}", "pins": [ { "id": "p", "net": "clk" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclkb", "displayName": "Vclkb", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vclkb clkb 0 dc 0", "pins": [ { "id": "p", "net": "clkb" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "chop", "parametersOrValue": "", "source": "Xdut inp inn outp outn clk clkb vdd 0 chop", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "clk", "net": "clk" }, { "id": "clkb", "net": "clkb" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/chop" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vin inp 0 dc 0", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vn", "displayName": "Vn", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vn inn 0 dc 600m", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Iload", "displayName": "Iload", "spiceType": "I", "model": null, "parametersOrValue": "dc 10u", "source": "Iload outp 0 dc 10u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Rn", "displayName": "Rn", "spiceType": "R", "model": null, "parametersOrValue": "1meg", "source": "Rn outn 0 1meg", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vclk", "pin": "n" }, { "device": "Vclkb", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Vin", "pin": "n" }, { "device": "Vn", "pin": "n" }, { "device": "Iload", "pin": "n" }, { "device": "Rn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "Vclk", "pin": "p" }, { "device": "Xdut", "pin": "clk" } ], "ports": [], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "Vclkb", "pin": "p" }, { "device": "Xdut", "pin": "clkb" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Iload", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Rn", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/chop", "name": "chop", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "clk", "net": "clk" }, { "name": "clkb", "net": "clkb" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" } ], "definitions": [], "devices": [ { "id": "XS1n", "displayName": "S1n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS1n inp clk outp vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "outp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS1p", "displayName": "S1p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XS1p inp clkb outp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "outp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS2n", "displayName": "S2n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS2n inn clk outn vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "outn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS2p", "displayName": "S2p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XS2p inn clkb outn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "outn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS3n", "displayName": "S3n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS3n inp clkb outn vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "outn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS3p", "displayName": "S3p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XS3p inp clk outn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "outn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS4n", "displayName": "S4n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS4n inn clkb outp vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "outp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS4p", "displayName": "S4p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XS4p inn clk outp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "outp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "inp", "ground": false, "terminals": [ { "device": "XS1n", "pin": "d" }, { "device": "XS1p", "pin": "d" }, { "device": "XS3n", "pin": "d" }, { "device": "XS3p", "pin": "d" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "XS1n", "pin": "g" }, { "device": "XS2n", "pin": "g" }, { "device": "XS3p", "pin": "g" }, { "device": "XS4p", "pin": "g" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XS1n", "pin": "s" }, { "device": "XS1p", "pin": "s" }, { "device": "XS4n", "pin": "s" }, { "device": "XS4p", "pin": "s" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XS1n", "pin": "b" }, { "device": "XS2n", "pin": "b" }, { "device": "XS3n", "pin": "b" }, { "device": "XS4n", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "XS1p", "pin": "g" }, { "device": "XS2p", "pin": "g" }, { "device": "XS3n", "pin": "g" }, { "device": "XS4n", "pin": "g" } ], "ports": [ "clkb" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XS1p", "pin": "b" }, { "device": "XS2p", "pin": "b" }, { "device": "XS3p", "pin": "b" }, { "device": "XS4p", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XS2n", "pin": "d" }, { "device": "XS2p", "pin": "d" }, { "device": "XS4n", "pin": "d" }, { "device": "XS4p", "pin": "d" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XS2n", "pin": "s" }, { "device": "XS2p", "pin": "s" }, { "device": "XS3n", "pin": "s" }, { "device": "XS3p", "pin": "s" } ], "ports": [ "outn" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/chop" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Chopper", "devices": [ { "scope": "dut", "device": "XS1n" }, { "scope": "dut", "device": "XS1p" }, { "scope": "dut", "device": "XS2n" }, { "scope": "dut", "device": "XS2p" }, { "scope": "dut", "device": "XS3n" }, { "scope": "dut", "device": "XS3p" }, { "scope": "dut", "device": "XS4n" }, { "scope": "dut", "device": "XS4p" } ], "inferredStages": [ 1 ] } ], "edges": [], "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "outp", "net": "outp", "kind": "output" }, { "name": "outn", "net": "outn", "kind": "output" }, { "name": "clk", "net": "clk", "kind": "clock" }, { "name": "clkb", "net": "clkb", "kind": "clock" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclk", "displayName": "Vclk", "spiceType": "V", "model": null, "parametersOrValue": "pulse({VDD} 0 25u 20n 20n 24.98u 50u)", "source": "Vclk clk 0 pulse({VDD} 0 25u 20n 20n 24.98u 50u)", "pins": [ { "id": "p", "net": "clk" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclkb", "displayName": "Vclkb", "spiceType": "V", "model": null, "parametersOrValue": "pulse(0 {VDD} 25u 20n 20n 24.98u 50u)", "source": "Vclkb clkb 0 pulse(0 {VDD} 25u 20n 20n 24.98u 50u)", "pins": [ { "id": "p", "net": "clkb" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "chop", "parametersOrValue": "", "source": "Xdut inp inn outp outn clk clkb vdd 0 chop", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "clk", "net": "clk" }, { "id": "clkb", "net": "clkb" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/chop" }, { "id": "Vinp", "displayName": "Vinp", "spiceType": "V", "model": null, "parametersOrValue": "dc 650m", "source": "Vinp inp 0 dc 650m", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vinn", "displayName": "Vinn", "spiceType": "V", "model": null, "parametersOrValue": "dc 550m", "source": "Vinn inn 0 dc 550m", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vmid", "displayName": "Vmid", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vmid mid 0 dc 600m", "pins": [ { "id": "p", "net": "mid" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Rlp", "displayName": "Rlp", "spiceType": "R", "model": null, "parametersOrValue": "100k", "source": "Rlp outp mid 100k", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "mid" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Rln", "displayName": "Rln", "spiceType": "R", "model": null, "parametersOrValue": "100k", "source": "Rln outn mid 100k", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "mid" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "1p", "source": "Clp outp mid 1p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "mid" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "1p", "source": "Cln outn mid 1p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "mid" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vclk", "pin": "n" }, { "device": "Vclkb", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Vinp", "pin": "n" }, { "device": "Vinn", "pin": "n" }, { "device": "Vmid", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "Vclk", "pin": "p" }, { "device": "Xdut", "pin": "clk" } ], "ports": [], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "Vclkb", "pin": "p" }, { "device": "Xdut", "pin": "clkb" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vinp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vinn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Rlp", "pin": "p" }, { "device": "Clp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Rln", "pin": "p" }, { "device": "Cln", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "mid", "ground": false, "terminals": [ { "device": "Vmid", "pin": "p" }, { "device": "Rlp", "pin": "n" }, { "device": "Rln", "pin": "n" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/chop", "name": "chop", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "clk", "net": "clk" }, { "name": "clkb", "net": "clkb" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" } ], "definitions": [], "devices": [ { "id": "XS1n", "displayName": "S1n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS1n inp clk outp vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "outp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS1p", "displayName": "S1p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XS1p inp clkb outp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "outp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS2n", "displayName": "S2n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS2n inn clk outn vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "outn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS2p", "displayName": "S2p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XS2p inn clkb outn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "outn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS3n", "displayName": "S3n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS3n inp clkb outn vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "outn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS3p", "displayName": "S3p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XS3p inp clk outn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "outn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS4n", "displayName": "S4n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS4n inn clkb outp vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "outp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS4p", "displayName": "S4p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XS4p inn clk outp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "outp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "inp", "ground": false, "terminals": [ { "device": "XS1n", "pin": "d" }, { "device": "XS1p", "pin": "d" }, { "device": "XS3n", "pin": "d" }, { "device": "XS3p", "pin": "d" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "XS1n", "pin": "g" }, { "device": "XS2n", "pin": "g" }, { "device": "XS3p", "pin": "g" }, { "device": "XS4p", "pin": "g" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XS1n", "pin": "s" }, { "device": "XS1p", "pin": "s" }, { "device": "XS4n", "pin": "s" }, { "device": "XS4p", "pin": "s" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XS1n", "pin": "b" }, { "device": "XS2n", "pin": "b" }, { "device": "XS3n", "pin": "b" }, { "device": "XS4n", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "XS1p", "pin": "g" }, { "device": "XS2p", "pin": "g" }, { "device": "XS3n", "pin": "g" }, { "device": "XS4n", "pin": "g" } ], "ports": [ "clkb" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XS1p", "pin": "b" }, { "device": "XS2p", "pin": "b" }, { "device": "XS3p", "pin": "b" }, { "device": "XS4p", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XS2n", "pin": "d" }, { "device": "XS2p", "pin": "d" }, { "device": "XS4n", "pin": "d" }, { "device": "XS4p", "pin": "d" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XS2n", "pin": "s" }, { "device": "XS2p", "pin": "s" }, { "device": "XS3n", "pin": "s" }, { "device": "XS3p", "pin": "s" } ], "ports": [ "outn" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/chop" } } ], "views": [ { "bench": "ron", "source": { "recordField": "testbenches", "id": "ron", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/chopper-tg/ron-schematic.svg", "asset": "ron-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Differential chopper, transmission gates", "instances": [] } ] }, "benchDiagram": { "graph": "graph-2", "svg": { "url": "/circuits/chopper-tg/ron-bench.svg", "asset": "ron-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/chopper-tg/ron-block.svg", "asset": "ron-block.svg" } } }, { "bench": "chop", "source": { "recordField": "testbenches", "id": "chop", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/chopper-tg/ron-schematic.svg", "asset": "ron-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Differential chopper, transmission gates", "instances": [] } ] }, "benchDiagram": { "graph": "graph-4", "svg": { "url": "/circuits/chopper-tg/chop-bench.svg", "asset": "chop-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/chopper-tg/ron-block.svg", "asset": "ron-block.svg" } } } ] } }