{
  "schema": "aisic.circuit/1",
  "entryType": "library-block",
  "domain": "analog",
  "id": "cm-detector",
  "name": "Resistive common-mode detector",
  "group": "Fully differential",
  "subgroup": "Common-mode feedback",
  "title": "Resistive common-mode detector",
  "summary": "This block measures the average of two voltages without amplifying it. Equal resistors provide the average at low frequency, and parallel capacitors help it follow faster changes. Mismatch lets some differential signal through, while the connected load causes error and attenuation.",
  "reference": {
    "kind": "book",
    "authors": "B. Razavi",
    "title": "Design of Analog CMOS Integrated Circuits",
    "edition": "2nd",
    "publisher": "McGraw-Hill",
    "year": 2016,
    "where": "Sec. 9.7 (common-mode feedback: resistive sensing, and capacitors across the sensing resistors)",
    "takes": "The technique: resistive averaging of the two outputs, with capacitors in parallel with the resistors to reduce the attenuation and phase lag caused by the error amplifier's input capacitance. The values, the choice of high-resistance poly and MIM, and the targets are this library's, for SG13G2."
  },
  "resources": {
    "record": "/circuits/cm-detector.json",
    "page": "/index.html#cm-detector",
    "achieved": "/achieved/cm-detector.json",
    "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.",
    "modelCards": [
      {
        "name": "sg13g2_passive_tt.spice",
        "url": "/sg13g2_passive_tt.spice",
        "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc"
      }
    ],
    "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.",
    "schema": "/schemas/circuit.schema.json"
  },
  "specificationPolicy": {
    "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.",
    "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.",
    "scopes": {
      "nominal": {
        "corner": "tt",
        "temp": 27,
        "vdd": 1,
        "temperatureUnit": "degC",
        "supplyMeaning": "scale of the bench's nominal supply"
      }
    },
    "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim."
  },
  "corners": {
    "cards": "a deck's sg13g2_<family>_tt.spice (family lv, hv, passive, hbt) becomes sg13g2_<family>_<corner>.spice",
    "process": [
      "tt",
      "ss",
      "ff",
      "sf",
      "fs"
    ],
    "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise",
    "temperatures": [
      -40,
      27,
      125
    ],
    "supplyScale": [
      0.9,
      1,
      1.1
    ],
    "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it",
    "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw",
    "sets": {
      "essential": [
        {
          "corner": "tt",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "ss",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "ff",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "sf",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "fs",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "tt",
          "temp": -40,
          "vdd": 1
        },
        {
          "corner": "tt",
          "temp": 125,
          "vdd": 1
        },
        {
          "corner": "tt",
          "temp": 27,
          "vdd": 0.9
        },
        {
          "corner": "tt",
          "temp": 27,
          "vdd": 1.1
        },
        {
          "corner": "ss",
          "temp": 125,
          "vdd": 0.9
        },
        {
          "corner": "ff",
          "temp": -40,
          "vdd": 1.1
        }
      ],
      "full": "all 45 combinations"
    },
    "montecarlo": {
      "cards": {
        "mc": "process and mismatch",
        "mcmm": "mismatch only",
        "mcproc": "process only"
      },
      "seed": "draw k adds .options seed=k, so draws are reproducible"
    }
  },
  "technology": {
    "id": "sg13g2",
    "name": "IHP SG13G2",
    "node": "130 nm",
    "corner": "tt",
    "vdd": 1.2,
    "lmin": 1.3e-7,
    "wmin": 1.5e-7,
    "models": "sg13g2_lv_tt.spice",
    "devices": {
      "nmos": "sg13_lv_nmos",
      "pmos": "sg13_lv_pmos",
      "resistor": "rppd, rhigh",
      "capacitor": "cap_cmim"
    },
    "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.",
    "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF."
  },
  "implementation": {
    "kind": "physical-device-reference",
    "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.",
    "evidence": "schematic-simulation",
    "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.",
    "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.",
    "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification."
  },
  "cards": [
    "sg13g2_passive_tt.spice"
  ],
  "ports": [
    {
      "name": "inp",
      "kind": "input",
      "note": "one of the two outputs it senses"
    },
    {
      "name": "inn",
      "kind": "input",
      "note": "the other"
    },
    {
      "name": "out",
      "kind": "output",
      "note": "their average: the sensed common mode"
    },
    {
      "name": "vss",
      "kind": "ground",
      "note": "the substrate under the resistors"
    }
  ],
  "devices": [
    {
      "name": "R1",
      "type": "resistor",
      "nodes": "inp out",
      "sizedBy": [
        "R"
      ],
      "role": "averaging resistor"
    },
    {
      "name": "R2",
      "type": "resistor",
      "nodes": "inn out",
      "sizedBy": [
        "R"
      ],
      "role": "averaging resistor"
    },
    {
      "name": "C1",
      "type": "capacitor",
      "nodes": "inp out",
      "sizedBy": [
        "C"
      ],
      "role": "averaging capacitor, the fast path across R1"
    },
    {
      "name": "C2",
      "type": "capacitor",
      "nodes": "inn out",
      "sizedBy": [
        "C"
      ],
      "role": "averaging capacitor, the fast path across R2"
    }
  ],
  "intent": [
    {
      "rule": "match",
      "of": [
        "R1",
        "R2"
      ],
      "why": "The output is the average only if the two resistors are equal: their mismatch passes a fraction of the differential signal into the sensed common mode. Long, identical strips match best."
    },
    {
      "rule": "match",
      "of": [
        "C1",
        "C2"
      ],
      "why": "The same at high frequency, where the capacitors carry the signal."
    },
    {
      "rule": "time-constant",
      "of": [
        "R1",
        "C1"
      ],
      "constraint": "C well above the load's capacitance",
      "why": "Across each resistor, the capacitor makes the divider capacitive as well as resistive: matched capacitors preserve averaging, but the load leaves a pole-zero shelf with high-frequency gain 2C/(2C + C_L)."
    },
    {
      "rule": "loading",
      "of": [
        "R1",
        "R2"
      ],
      "constraint": "R1 + R2 well above the stage's output resistance",
      "why": "The two resistors in series load the stage's outputs differentially: large enough to limit gain loss, but not so large that sensing becomes too slow."
    }
  ],
  "specs": [
    {
      "key": "slope",
      "label": "Slope at the reference",
      "unit": "V/V",
      "direction": "target",
      "constraint": ">= 0.999 V/V, <= 1.001 V/V",
      "min": 0.999,
      "max": 1.001,
      "why": "Equal resistors: the output is the average, to within their mismatch."
    },
    {
      "key": "sense_err",
      "label": "Sensed less true common mode",
      "unit": "V",
      "direction": "target",
      "constraint": ">= -0.001 V, <= 0.001 V",
      "min": -0.001,
      "max": 0.001,
      "why": "With negligible DC input current and matched resistors, the output is the average. Leakage or loading at the sensing node adds error."
    },
    {
      "key": "dm_err",
      "label": "Error from a differential input",
      "unit": "V",
      "direction": "min",
      "constraint": "<= 0.002 V",
      "min": null,
      "max": 0.002,
      "why": "The mismatch between R1 and R2 lets a fraction of the difference through: a magnitude |R1 - R2|/(4R) of it, under 1 mV for 0.2 V over Monte Carlo."
    },
    {
      "key": "r_in",
      "label": "Differential input resistance",
      "unit": "Ω",
      "direction": "max",
      "constraint": ">= 500000 Ω",
      "min": 500000,
      "max": null,
      "why": "R1 + R2 across the two outputs: 1 MΩ typical; high-resistance poly loses a quarter of its value at the fast corner and a fifth at 125 °C, 750 and 795 kΩ."
    },
    {
      "key": "gain_db",
      "label": "Gain at DC",
      "unit": "dB",
      "direction": "target",
      "constraint": ">= -0.1 dB, <= 0.1 dB",
      "min": -0.1,
      "max": 0.1
    },
    {
      "key": "bw_hz",
      "label": "Bandwidth, -3 dB",
      "unit": "Hz",
      "direction": "max",
      "constraint": ">= 100000000 Hz",
      "min": 100000000,
      "max": null,
      "why": "The parallel capacitors limit high-frequency attenuation from the sensing-node load. Bandwidth here uses a 3 dB drop, not a 1 dB flatness guarantee."
    }
  ],
  "explanation": {
    "idea": "This block measures the average of two voltages without amplifying it. Equal resistors provide the average at low frequency, and parallel capacitors help it follow faster changes. Mismatch lets some differential signal through, while the connected load causes error and attenuation.",
    "detail": "R1 and R2 form a weighted average of the two input voltages. Equal realized resistors give the arithmetic mean; mismatch allows differential signal into the sensed common mode. C1 and C2 bypass the resistors at high frequency, reducing the load capacitance's effect rather than eliminating it. For equal R and C and a load C_L, the ideal common-mode transfer is (1 + sRC)/(1 + sR(C + C_L/2)); it has a pole-zero shelf, not a perfectly flat response.",
    "lesson": {
      "relation": 0,
      "symbols": "V_out is sensed average voltage; V_inp and V_inn are the two sensed voltages; R1 connects inp to out and R2 connects inn to out, in Ω.",
      "assumptions": "DC or sufficiently low frequency, with negligible current drawn from the sensing node. Equal resistors give the arithmetic mean; mismatch creates differential-to-common-mode error.",
      "exercise": {
        "param": "R",
        "value": 1000000,
        "analysis": "transfer",
        "expect": "Doubling both sensing resistors should double the differential input resistance while leaving the nominal DC average nearly unchanged. It also makes leakage and capacitive loading more important."
      },
      "limits": "This passive block senses common mode but does not regulate it. The following error amplifier loads the sensing node, and resistor/capacitor mismatch limits rejection of differential signals."
    },
    "path": [
      {
        "part": "Averaging divider",
        "devices": "R1, R2",
        "does": "R1 from inp and R2 from inn meet at out; with equal values out settles at the mean of the two inputs."
      },
      {
        "part": "Fast path",
        "devices": "C1, C2",
        "does": "The capacitors across the resistors average at high frequency too, so out follows the common mode past the corner the resistors would make with the load."
      }
    ],
    "bias": "At DC, neglecting leakage and sensing-node loading, only the differential input drives current through the two series resistors. Changing voltages also move charge through the capacitors. out reports whatever common mode the inputs carry; holding it at a target is the job of the error amplifier it feeds.",
    "relations": [
      {
        "what": "Sensed common mode",
        "expr": "V_out = (V_inp·R2 + V_inn·R1)/(R1 + R2)",
        "note": "The arithmetic mean for equal realized resistors. A shared nominal value does not remove random mismatch."
      },
      {
        "what": "Mismatch error",
        "expr": "ΔV_cm = V_out − (V_inp + V_inn)/2 = (R2 − R1)·(V_inp − V_inn)/(2·(R1 + R2))",
        "note": "Resistor mismatch lets a fraction of the differential signal into the sensed common mode."
      },
      {
        "what": "High-frequency division",
        "expr": "V_out/V_cm → 2C/(2C + C_L)",
        "note": "The load leaves a pole-zero shelf: the ideal response changes from one at DC to 2C/(2C + C_L) at high frequency. The recorded bandwidth uses a 3 dB criterion, not a 1 dB flatness guarantee."
      },
      {
        "what": "Differential load",
        "expr": "R_in,d = R1 + R2",
        "note": "Seen between the two outputs: 1 MΩ by default."
      }
    ],
    "tradeoffs": [
      "Resistor value: larger loads the stage's outputs less, but takes more area, and without the capacitors would lower the sensing bandwidth.",
      "Resistor length: longer strips match better, so less of the differential signal leaks into the sensed common mode.",
      "Capacitor value: larger keeps the division by the load closer to one, and adds capacitance to the outputs."
    ]
  },
  "sizing": [
    {
      "key": "R",
      "label": "Averaging resistor, per side",
      "unit": "Ω",
      "value": 500000,
      "min": 20000,
      "max": 2000000,
      "kind": "si"
    },
    {
      "key": "C",
      "label": "Averaging capacitor, per side",
      "unit": "F",
      "value": 2e-13,
      "min": 2e-14,
      "max": 2e-12,
      "kind": "si"
    },
    {
      "key": "CL",
      "label": "Load on the output: the error amplifier's input",
      "unit": "F",
      "value": 5e-14,
      "min": 1e-15,
      "max": 1e-12,
      "kind": "si"
    },
    {
      "key": "VCM",
      "label": "Common mode of the sensed outputs",
      "unit": "V",
      "value": 0.6,
      "min": 0.2,
      "max": 1,
      "kind": "si"
    }
  ],
  "testbenches": [
    {
      "id": "transfer",
      "label": "Transfer",
      "note": "The sensed common mode swept from 0 to 1.2 V, with the two inputs equal and then 200m V apart either way: the output against it, its slope where the inputs sit at the reference, and whether a difference between them moves it.",
      "measures": [],
      "metricKeys": [
        "slope",
        "sense_err",
        "dm_err",
        "r_in"
      ],
      "acceptance": [
        "slope",
        "sense_err",
        "dm_err",
        "r_in"
      ],
      "acceptanceRules": [
        {
          "key": "slope",
          "unit": "V/V",
          "min": 0.999,
          "max": 1.001,
          "classification": "simulation-limit",
          "conditions": "all requested testbench conditions",
          "outsideScope": "characterization; the measurement must still be present, unique and finite"
        },
        {
          "key": "sense_err",
          "unit": "V",
          "min": -0.001,
          "max": 0.001,
          "classification": "simulation-limit",
          "conditions": "all requested testbench conditions",
          "outsideScope": "characterization; the measurement must still be present, unique and finite"
        },
        {
          "key": "dm_err",
          "unit": "V",
          "min": null,
          "max": 0.002,
          "classification": "simulation-limit",
          "conditions": "all requested testbench conditions",
          "outsideScope": "characterization; the measurement must still be present, unique and finite"
        },
        {
          "key": "r_in",
          "unit": "Ω",
          "min": 500000,
          "max": null,
          "classification": "simulation-limit",
          "conditions": "all requested testbench conditions",
          "outsideScope": "characterization; the measurement must still be present, unique and finite"
        }
      ],
      "cards": [
        "sg13g2_passive_tt.spice"
      ],
      "netlist": "* Resistive common-mode detector - transfer, sensed common mode swept\n.include sg13g2_passive_tt.spice\n.subckt cmdet inp inn out vss\nXR1 inp out vss rhigh w=0.5u l=154.313u\nXR2 inn out vss rhigh w=0.5u l=154.313u\nXC1 inp out cap_cmim w=11.494u l=11.494u\nXC2 inn out cap_cmim w=11.494u l=11.494u\n.ends\nXdut inp inn out 0 cmdet\nCl out 0 50f\n* the two sensed nodes: the common mode on cm, the difference on vd\nVcm cm 0 dc 600m\nVd vd 0 dc 0\nEp inp cm vd 0 0.5\nEn inn cm vd 0 -0.5\n.dc Vcm 0 1.2 5m Vd -200m 200m 200m\n.end"
    },
    {
      "id": "servo",
      "label": "Bandwidth",
      "note": "A small common-mode signal on both inputs and the output driving its load: how fast the sensed common mode follows.",
      "measures": [],
      "metricKeys": [
        "gain_db",
        "bw_hz"
      ],
      "acceptance": [
        "gain_db",
        "bw_hz"
      ],
      "acceptanceRules": [
        {
          "key": "gain_db",
          "unit": "dB",
          "min": -0.1,
          "max": 0.1,
          "classification": "simulation-limit",
          "conditions": "all requested testbench conditions",
          "outsideScope": "characterization; the measurement must still be present, unique and finite"
        },
        {
          "key": "bw_hz",
          "unit": "Hz",
          "min": 100000000,
          "max": null,
          "classification": "simulation-limit",
          "conditions": "all requested testbench conditions",
          "outsideScope": "characterization; the measurement must still be present, unique and finite"
        }
      ],
      "cards": [
        "sg13g2_passive_tt.spice"
      ],
      "netlist": "* Resistive common-mode detector - common-mode signal to the output\n.include sg13g2_passive_tt.spice\n.subckt cmdet inp inn out vss\nXR1 inp out vss rhigh w=0.5u l=154.313u\nXR2 inn out vss rhigh w=0.5u l=154.313u\nXC1 inp out cap_cmim w=11.494u l=11.494u\nXC2 inn out cap_cmim w=11.494u l=11.494u\n.ends\nXdut inp inn out 0 cmdet\nCl out 0 50f\n* the two sensed nodes: the common mode on cm, the difference on vd\nVcm cm 0 dc 600m ac 1\nVd vd 0 dc 0\nEp inp cm vd 0 0.5\nEn inn cm vd 0 -0.5\n.ac dec 25 1 10g\n.end"
    }
  ],
  "measurements": {
    "slope": {
      "label": "Slope at the reference",
      "unit": "V/V",
      "spec": {
        "min": 0.999,
        "max": 1.001
      }
    },
    "sense_err": {
      "label": "Sensed less true common mode",
      "unit": "V",
      "spec": {
        "min": -0.001,
        "max": 0.001
      }
    },
    "dm_err": {
      "label": "Error from a differential input",
      "unit": "V",
      "spec": {
        "min": null,
        "max": 0.002
      }
    },
    "r_in": {
      "label": "Differential input resistance",
      "unit": "Ω",
      "spec": {
        "min": 500000,
        "max": null
      }
    },
    "gain_db": {
      "label": "Gain at DC",
      "unit": "dB",
      "spec": {
        "min": -0.1,
        "max": 0.1
      }
    },
    "bw_hz": {
      "label": "Bandwidth, -3 dB",
      "unit": "Hz",
      "spec": {
        "min": 100000000,
        "max": null
      }
    }
  },
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      "devices[].copies"
    ],
    "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.",
    "sha256": "91438d46a4975a439d36ca4cc9c07238c5ac256ad461c6854f09a416e467957a"
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      "url": "/library/cm-detector.js",
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    "simulationFingerprints": {
      "transfer": "48123d6c55f52058ef858754891a9c3dfb1bf089b3bd3cff792c2541a89f4d50",
      "servo": "da2d3b2f7350fa7eee36b8ddad283ff7168fc4e45f21115e35c28adddabdbc34"
    },
    "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification."
  },
  "revision": "9d859de5d4cafa9cd9bcc8bd163ad879110cfedb5970047a16eb4d38642c0ff3",
  "diagrams": {
    "schema": "aisic.diagrams/1",
    "circuit": "cm-detector",
    "parameters": {
      "R": 500000,
      "C": 2e-13,
      "CL": 5e-14,
      "VCM": 0.6
    },
    "parameterScope": "published-defaults",
    "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.",
    "variants": {
      "choiceParameters": [],
      "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation."
    },
    "resourceBase": "/circuits/cm-detector/",
    "graphs": [
      {
        "id": "graph-1",
        "kind": "electrical-connectivity",
        "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.",
        "root": "dut",
        "globalDefinitions": [],
        "scopes": [
          {
            "id": "dut",
            "name": "cmdet",
            "ports": [
              {
                "name": "inp",
                "net": "inp",
                "kind": "input"
              },
              {
                "name": "inn",
                "net": "inn",
                "kind": "input"
              },
              {
                "name": "out",
                "net": "out",
                "kind": "output"
              },
              {
                "name": "vss",
                "net": "vss",
                "kind": "ground"
              }
            ],
            "definitions": [],
            "devices": [
              {
                "id": "XR1",
                "displayName": "R1",
                "spiceType": "X",
                "model": "rhigh",
                "parametersOrValue": "w=0.5u l=154.313u",
                "source": "XR1 inp out vss rhigh w=0.5u l=154.313u",
                "pins": [
                  {
                    "id": "p",
                    "net": "inp"
                  },
                  {
                    "id": "n",
                    "net": "out"
                  },
                  {
                    "id": "substrate",
                    "net": "vss"
                  }
                ],
                "pinMeaning": "IHP resistor model terminal order"
              },
              {
                "id": "XR2",
                "displayName": "R2",
                "spiceType": "X",
                "model": "rhigh",
                "parametersOrValue": "w=0.5u l=154.313u",
                "source": "XR2 inn out vss rhigh w=0.5u l=154.313u",
                "pins": [
                  {
                    "id": "p",
                    "net": "inn"
                  },
                  {
                    "id": "n",
                    "net": "out"
                  },
                  {
                    "id": "substrate",
                    "net": "vss"
                  }
                ],
                "pinMeaning": "IHP resistor model terminal order"
              },
              {
                "id": "XC1",
                "displayName": "C1",
                "spiceType": "X",
                "model": "cap_cmim",
                "parametersOrValue": "w=11.494u l=11.494u",
                "source": "XC1 inp out cap_cmim w=11.494u l=11.494u",
                "pins": [
                  {
                    "id": "p",
                    "net": "inp"
                  },
                  {
                    "id": "n",
                    "net": "out"
                  }
                ],
                "pinMeaning": "IHP MIM model terminal order"
              },
              {
                "id": "XC2",
                "displayName": "C2",
                "spiceType": "X",
                "model": "cap_cmim",
                "parametersOrValue": "w=11.494u l=11.494u",
                "source": "XC2 inn out cap_cmim w=11.494u l=11.494u",
                "pins": [
                  {
                    "id": "p",
                    "net": "inn"
                  },
                  {
                    "id": "n",
                    "net": "out"
                  }
                ],
                "pinMeaning": "IHP MIM model terminal order"
              }
            ],
            "nets": [
              {
                "id": "inp",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR1",
                    "pin": "p"
                  },
                  {
                    "device": "XC1",
                    "pin": "p"
                  }
                ],
                "ports": [
                  "inp"
                ],
                "voltageReferences": []
              },
              {
                "id": "out",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR1",
                    "pin": "n"
                  },
                  {
                    "device": "XR2",
                    "pin": "n"
                  },
                  {
                    "device": "XC1",
                    "pin": "n"
                  },
                  {
                    "device": "XC2",
                    "pin": "n"
                  }
                ],
                "ports": [
                  "out"
                ],
                "voltageReferences": []
              },
              {
                "id": "vss",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR1",
                    "pin": "substrate"
                  },
                  {
                    "device": "XR2",
                    "pin": "substrate"
                  }
                ],
                "ports": [
                  "vss"
                ],
                "voltageReferences": []
              },
              {
                "id": "inn",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR2",
                    "pin": "p"
                  },
                  {
                    "device": "XC2",
                    "pin": "p"
                  }
                ],
                "ports": [
                  "inn"
                ],
                "voltageReferences": []
              }
            ]
          }
        ]
      },
      {
        "id": "graph-2",
        "kind": "electrical-connectivity",
        "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.",
        "root": "top",
        "globalDefinitions": [],
        "scopes": [
          {
            "id": "top",
            "name": "top",
            "ports": [],
            "definitions": [],
            "devices": [
              {
                "id": "Xdut",
                "displayName": "Xdut",
                "spiceType": "X",
                "model": "cmdet",
                "parametersOrValue": "",
                "source": "Xdut inp inn out 0 cmdet",
                "pins": [
                  {
                    "id": "inp",
                    "net": "inp"
                  },
                  {
                    "id": "inn",
                    "net": "inn"
                  },
                  {
                    "id": "out",
                    "net": "out"
                  },
                  {
                    "id": "vss",
                    "net": "0"
                  }
                ],
                "pinMeaning": "Declared .subckt port order",
                "subcircuit": "subckt/cmdet"
              },
              {
                "id": "Cl",
                "displayName": "Cl",
                "spiceType": "C",
                "model": null,
                "parametersOrValue": "50f",
                "source": "Cl out 0 50f",
                "pins": [
                  {
                    "id": "p",
                    "net": "out"
                  },
                  {
                    "id": "n",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              },
              {
                "id": "Vcm",
                "displayName": "Vcm",
                "spiceType": "V",
                "model": null,
                "parametersOrValue": "dc 600m",
                "source": "Vcm cm 0 dc 600m",
                "pins": [
                  {
                    "id": "p",
                    "net": "cm"
                  },
                  {
                    "id": "n",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              },
              {
                "id": "Vd",
                "displayName": "Vd",
                "spiceType": "V",
                "model": null,
                "parametersOrValue": "dc 0",
                "source": "Vd vd 0 dc 0",
                "pins": [
                  {
                    "id": "p",
                    "net": "vd"
                  },
                  {
                    "id": "n",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              },
              {
                "id": "Ep",
                "displayName": "Ep",
                "spiceType": "E",
                "model": null,
                "parametersOrValue": "0.5",
                "source": "Ep inp cm vd 0 0.5",
                "pins": [
                  {
                    "id": "p",
                    "net": "inp"
                  },
                  {
                    "id": "n",
                    "net": "cm"
                  },
                  {
                    "id": "cp",
                    "net": "vd"
                  },
                  {
                    "id": "cn",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              },
              {
                "id": "En",
                "displayName": "En",
                "spiceType": "E",
                "model": null,
                "parametersOrValue": "-0.5",
                "source": "En inn cm vd 0 -0.5",
                "pins": [
                  {
                    "id": "p",
                    "net": "inn"
                  },
                  {
                    "id": "n",
                    "net": "cm"
                  },
                  {
                    "id": "cp",
                    "net": "vd"
                  },
                  {
                    "id": "cn",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              }
            ],
            "nets": [
              {
                "id": "inp",
                "ground": false,
                "terminals": [
                  {
                    "device": "Xdut",
                    "pin": "inp"
                  },
                  {
                    "device": "Ep",
                    "pin": "p"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "inn",
                "ground": false,
                "terminals": [
                  {
                    "device": "Xdut",
                    "pin": "inn"
                  },
                  {
                    "device": "En",
                    "pin": "p"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "out",
                "ground": false,
                "terminals": [
                  {
                    "device": "Xdut",
                    "pin": "out"
                  },
                  {
                    "device": "Cl",
                    "pin": "p"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "0",
                "ground": true,
                "terminals": [
                  {
                    "device": "Xdut",
                    "pin": "vss"
                  },
                  {
                    "device": "Cl",
                    "pin": "n"
                  },
                  {
                    "device": "Vcm",
                    "pin": "n"
                  },
                  {
                    "device": "Vd",
                    "pin": "n"
                  },
                  {
                    "device": "Ep",
                    "pin": "cn"
                  },
                  {
                    "device": "En",
                    "pin": "cn"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "cm",
                "ground": false,
                "terminals": [
                  {
                    "device": "Vcm",
                    "pin": "p"
                  },
                  {
                    "device": "Ep",
                    "pin": "n"
                  },
                  {
                    "device": "En",
                    "pin": "n"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "vd",
                "ground": false,
                "terminals": [
                  {
                    "device": "Vd",
                    "pin": "p"
                  },
                  {
                    "device": "Ep",
                    "pin": "cp"
                  },
                  {
                    "device": "En",
                    "pin": "cp"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              }
            ]
          },
          {
            "id": "subckt/cmdet",
            "name": "cmdet",
            "ports": [
              {
                "name": "inp",
                "net": "inp"
              },
              {
                "name": "inn",
                "net": "inn"
              },
              {
                "name": "out",
                "net": "out"
              },
              {
                "name": "vss",
                "net": "vss"
              }
            ],
            "definitions": [],
            "devices": [
              {
                "id": "XR1",
                "displayName": "R1",
                "spiceType": "X",
                "model": "rhigh",
                "parametersOrValue": "w=0.5u l=154.313u",
                "source": "XR1 inp out vss rhigh w=0.5u l=154.313u",
                "pins": [
                  {
                    "id": "p",
                    "net": "inp"
                  },
                  {
                    "id": "n",
                    "net": "out"
                  },
                  {
                    "id": "substrate",
                    "net": "vss"
                  }
                ],
                "pinMeaning": "IHP resistor model terminal order"
              },
              {
                "id": "XR2",
                "displayName": "R2",
                "spiceType": "X",
                "model": "rhigh",
                "parametersOrValue": "w=0.5u l=154.313u",
                "source": "XR2 inn out vss rhigh w=0.5u l=154.313u",
                "pins": [
                  {
                    "id": "p",
                    "net": "inn"
                  },
                  {
                    "id": "n",
                    "net": "out"
                  },
                  {
                    "id": "substrate",
                    "net": "vss"
                  }
                ],
                "pinMeaning": "IHP resistor model terminal order"
              },
              {
                "id": "XC1",
                "displayName": "C1",
                "spiceType": "X",
                "model": "cap_cmim",
                "parametersOrValue": "w=11.494u l=11.494u",
                "source": "XC1 inp out cap_cmim w=11.494u l=11.494u",
                "pins": [
                  {
                    "id": "p",
                    "net": "inp"
                  },
                  {
                    "id": "n",
                    "net": "out"
                  }
                ],
                "pinMeaning": "IHP MIM model terminal order"
              },
              {
                "id": "XC2",
                "displayName": "C2",
                "spiceType": "X",
                "model": "cap_cmim",
                "parametersOrValue": "w=11.494u l=11.494u",
                "source": "XC2 inn out cap_cmim w=11.494u l=11.494u",
                "pins": [
                  {
                    "id": "p",
                    "net": "inn"
                  },
                  {
                    "id": "n",
                    "net": "out"
                  }
                ],
                "pinMeaning": "IHP MIM model terminal order"
              }
            ],
            "nets": [
              {
                "id": "inp",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR1",
                    "pin": "p"
                  },
                  {
                    "device": "XC1",
                    "pin": "p"
                  }
                ],
                "ports": [
                  "inp"
                ],
                "voltageReferences": []
              },
              {
                "id": "out",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR1",
                    "pin": "n"
                  },
                  {
                    "device": "XR2",
                    "pin": "n"
                  },
                  {
                    "device": "XC1",
                    "pin": "n"
                  },
                  {
                    "device": "XC2",
                    "pin": "n"
                  }
                ],
                "ports": [
                  "out"
                ],
                "voltageReferences": []
              },
              {
                "id": "vss",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR1",
                    "pin": "substrate"
                  },
                  {
                    "device": "XR2",
                    "pin": "substrate"
                  }
                ],
                "ports": [
                  "vss"
                ],
                "voltageReferences": []
              },
              {
                "id": "inn",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR2",
                    "pin": "p"
                  },
                  {
                    "device": "XC2",
                    "pin": "p"
                  }
                ],
                "ports": [
                  "inn"
                ],
                "voltageReferences": []
              }
            ]
          }
        ],
        "uninstantiatedDefinitions": [],
        "dut": {
          "kind": "subcircuit-instance",
          "scope": "top",
          "device": "Xdut",
          "definition": "subckt/cmdet"
        }
      },
      {
        "id": "graph-3",
        "kind": "functional-graph",
        "classification": "heuristic-device-grouping",
        "electricalScope": "dut",
        "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.",
        "nodes": [
          {
            "id": "block-1",
            "label": "Averaging resistor",
            "devices": [
              {
                "scope": "dut",
                "device": "XR1"
              },
              {
                "scope": "dut",
                "device": "XR2"
              }
            ],
            "inferredStages": [
              1
            ]
          },
          {
            "id": "block-2",
            "label": "Averaging capacitor",
            "devices": [
              {
                "scope": "dut",
                "device": "XC1"
              },
              {
                "scope": "dut",
                "device": "XC2"
              }
            ],
            "inferredStages": [
              1
            ]
          }
        ],
        "edges": [
          {
            "id": "net-1",
            "net": "inp",
            "nodes": [
              "block-1",
              "block-2"
            ],
            "direction": "undirected-shared-net"
          },
          {
            "id": "net-2",
            "net": "out",
            "nodes": [
              "block-1",
              "block-2"
            ],
            "direction": "undirected-shared-net"
          },
          {
            "id": "net-3",
            "net": "inn",
            "nodes": [
              "block-1",
              "block-2"
            ],
            "direction": "undirected-shared-net"
          }
        ],
        "ports": [
          {
            "name": "inp",
            "net": "inp",
            "kind": "input"
          },
          {
            "name": "inn",
            "net": "inn",
            "kind": "input"
          },
          {
            "name": "out",
            "net": "out",
            "kind": "output"
          },
          {
            "name": "vss",
            "net": "vss",
            "kind": "ground"
          }
        ],
        "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes."
      },
      {
        "id": "graph-4",
        "kind": "electrical-connectivity",
        "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.",
        "root": "top",
        "globalDefinitions": [],
        "scopes": [
          {
            "id": "top",
            "name": "top",
            "ports": [],
            "definitions": [],
            "devices": [
              {
                "id": "Xdut",
                "displayName": "Xdut",
                "spiceType": "X",
                "model": "cmdet",
                "parametersOrValue": "",
                "source": "Xdut inp inn out 0 cmdet",
                "pins": [
                  {
                    "id": "inp",
                    "net": "inp"
                  },
                  {
                    "id": "inn",
                    "net": "inn"
                  },
                  {
                    "id": "out",
                    "net": "out"
                  },
                  {
                    "id": "vss",
                    "net": "0"
                  }
                ],
                "pinMeaning": "Declared .subckt port order",
                "subcircuit": "subckt/cmdet"
              },
              {
                "id": "Cl",
                "displayName": "Cl",
                "spiceType": "C",
                "model": null,
                "parametersOrValue": "50f",
                "source": "Cl out 0 50f",
                "pins": [
                  {
                    "id": "p",
                    "net": "out"
                  },
                  {
                    "id": "n",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              },
              {
                "id": "Vcm",
                "displayName": "Vcm",
                "spiceType": "V",
                "model": null,
                "parametersOrValue": "dc 600m ac 1",
                "source": "Vcm cm 0 dc 600m ac 1",
                "pins": [
                  {
                    "id": "p",
                    "net": "cm"
                  },
                  {
                    "id": "n",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              },
              {
                "id": "Vd",
                "displayName": "Vd",
                "spiceType": "V",
                "model": null,
                "parametersOrValue": "dc 0",
                "source": "Vd vd 0 dc 0",
                "pins": [
                  {
                    "id": "p",
                    "net": "vd"
                  },
                  {
                    "id": "n",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              },
              {
                "id": "Ep",
                "displayName": "Ep",
                "spiceType": "E",
                "model": null,
                "parametersOrValue": "0.5",
                "source": "Ep inp cm vd 0 0.5",
                "pins": [
                  {
                    "id": "p",
                    "net": "inp"
                  },
                  {
                    "id": "n",
                    "net": "cm"
                  },
                  {
                    "id": "cp",
                    "net": "vd"
                  },
                  {
                    "id": "cn",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              },
              {
                "id": "En",
                "displayName": "En",
                "spiceType": "E",
                "model": null,
                "parametersOrValue": "-0.5",
                "source": "En inn cm vd 0 -0.5",
                "pins": [
                  {
                    "id": "p",
                    "net": "inn"
                  },
                  {
                    "id": "n",
                    "net": "cm"
                  },
                  {
                    "id": "cp",
                    "net": "vd"
                  },
                  {
                    "id": "cn",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              }
            ],
            "nets": [
              {
                "id": "inp",
                "ground": false,
                "terminals": [
                  {
                    "device": "Xdut",
                    "pin": "inp"
                  },
                  {
                    "device": "Ep",
                    "pin": "p"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "inn",
                "ground": false,
                "terminals": [
                  {
                    "device": "Xdut",
                    "pin": "inn"
                  },
                  {
                    "device": "En",
                    "pin": "p"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "out",
                "ground": false,
                "terminals": [
                  {
                    "device": "Xdut",
                    "pin": "out"
                  },
                  {
                    "device": "Cl",
                    "pin": "p"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "0",
                "ground": true,
                "terminals": [
                  {
                    "device": "Xdut",
                    "pin": "vss"
                  },
                  {
                    "device": "Cl",
                    "pin": "n"
                  },
                  {
                    "device": "Vcm",
                    "pin": "n"
                  },
                  {
                    "device": "Vd",
                    "pin": "n"
                  },
                  {
                    "device": "Ep",
                    "pin": "cn"
                  },
                  {
                    "device": "En",
                    "pin": "cn"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "cm",
                "ground": false,
                "terminals": [
                  {
                    "device": "Vcm",
                    "pin": "p"
                  },
                  {
                    "device": "Ep",
                    "pin": "n"
                  },
                  {
                    "device": "En",
                    "pin": "n"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "vd",
                "ground": false,
                "terminals": [
                  {
                    "device": "Vd",
                    "pin": "p"
                  },
                  {
                    "device": "Ep",
                    "pin": "cp"
                  },
                  {
                    "device": "En",
                    "pin": "cp"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              }
            ]
          },
          {
            "id": "subckt/cmdet",
            "name": "cmdet",
            "ports": [
              {
                "name": "inp",
                "net": "inp"
              },
              {
                "name": "inn",
                "net": "inn"
              },
              {
                "name": "out",
                "net": "out"
              },
              {
                "name": "vss",
                "net": "vss"
              }
            ],
            "definitions": [],
            "devices": [
              {
                "id": "XR1",
                "displayName": "R1",
                "spiceType": "X",
                "model": "rhigh",
                "parametersOrValue": "w=0.5u l=154.313u",
                "source": "XR1 inp out vss rhigh w=0.5u l=154.313u",
                "pins": [
                  {
                    "id": "p",
                    "net": "inp"
                  },
                  {
                    "id": "n",
                    "net": "out"
                  },
                  {
                    "id": "substrate",
                    "net": "vss"
                  }
                ],
                "pinMeaning": "IHP resistor model terminal order"
              },
              {
                "id": "XR2",
                "displayName": "R2",
                "spiceType": "X",
                "model": "rhigh",
                "parametersOrValue": "w=0.5u l=154.313u",
                "source": "XR2 inn out vss rhigh w=0.5u l=154.313u",
                "pins": [
                  {
                    "id": "p",
                    "net": "inn"
                  },
                  {
                    "id": "n",
                    "net": "out"
                  },
                  {
                    "id": "substrate",
                    "net": "vss"
                  }
                ],
                "pinMeaning": "IHP resistor model terminal order"
              },
              {
                "id": "XC1",
                "displayName": "C1",
                "spiceType": "X",
                "model": "cap_cmim",
                "parametersOrValue": "w=11.494u l=11.494u",
                "source": "XC1 inp out cap_cmim w=11.494u l=11.494u",
                "pins": [
                  {
                    "id": "p",
                    "net": "inp"
                  },
                  {
                    "id": "n",
                    "net": "out"
                  }
                ],
                "pinMeaning": "IHP MIM model terminal order"
              },
              {
                "id": "XC2",
                "displayName": "C2",
                "spiceType": "X",
                "model": "cap_cmim",
                "parametersOrValue": "w=11.494u l=11.494u",
                "source": "XC2 inn out cap_cmim w=11.494u l=11.494u",
                "pins": [
                  {
                    "id": "p",
                    "net": "inn"
                  },
                  {
                    "id": "n",
                    "net": "out"
                  }
                ],
                "pinMeaning": "IHP MIM model terminal order"
              }
            ],
            "nets": [
              {
                "id": "inp",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR1",
                    "pin": "p"
                  },
                  {
                    "device": "XC1",
                    "pin": "p"
                  }
                ],
                "ports": [
                  "inp"
                ],
                "voltageReferences": []
              },
              {
                "id": "out",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR1",
                    "pin": "n"
                  },
                  {
                    "device": "XR2",
                    "pin": "n"
                  },
                  {
                    "device": "XC1",
                    "pin": "n"
                  },
                  {
                    "device": "XC2",
                    "pin": "n"
                  }
                ],
                "ports": [
                  "out"
                ],
                "voltageReferences": []
              },
              {
                "id": "vss",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR1",
                    "pin": "substrate"
                  },
                  {
                    "device": "XR2",
                    "pin": "substrate"
                  }
                ],
                "ports": [
                  "vss"
                ],
                "voltageReferences": []
              },
              {
                "id": "inn",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR2",
                    "pin": "p"
                  },
                  {
                    "device": "XC2",
                    "pin": "p"
                  }
                ],
                "ports": [
                  "inn"
                ],
                "voltageReferences": []
              }
            ]
          }
        ],
        "uninstantiatedDefinitions": [],
        "dut": {
          "kind": "subcircuit-instance",
          "scope": "top",
          "device": "Xdut",
          "definition": "subckt/cmdet"
        }
      }
    ],
    "views": [
      {
        "bench": "transfer",
        "source": {
          "recordField": "testbenches",
          "id": "transfer",
          "field": "netlist"
        },
        "schematic": {
          "graph": "graph-1",
          "svg": {
            "url": "/circuits/cm-detector/transfer-schematic.svg",
            "asset": "transfer-schematic.svg"
          },
          "drawingCheck": {
            "method": "checkSchematic",
            "problems": []
          },
          "sheets": [
            {
              "name": "Resistive common-mode detector",
              "instances": []
            }
          ]
        },
        "benchDiagram": {
          "graph": "graph-2",
          "svg": {
            "url": "/circuits/cm-detector/transfer-bench.svg",
            "asset": "transfer-bench.svg"
          }
        },
        "blockDiagram": {
          "graph": "graph-3",
          "electricalGraph": "graph-1",
          "svg": {
            "url": "/circuits/cm-detector/transfer-block.svg",
            "asset": "transfer-block.svg"
          }
        }
      },
      {
        "bench": "servo",
        "source": {
          "recordField": "testbenches",
          "id": "servo",
          "field": "netlist"
        },
        "schematic": {
          "graph": "graph-1",
          "svg": {
            "url": "/circuits/cm-detector/transfer-schematic.svg",
            "asset": "transfer-schematic.svg"
          },
          "drawingCheck": {
            "method": "checkSchematic",
            "problems": []
          },
          "sheets": [
            {
              "name": "Resistive common-mode detector",
              "instances": []
            }
          ]
        },
        "benchDiagram": {
          "graph": "graph-4",
          "svg": {
            "url": "/circuits/cm-detector/servo-bench.svg",
            "asset": "servo-bench.svg"
          }
        },
        "blockDiagram": {
          "graph": "graph-3",
          "electricalGraph": "graph-1",
          "svg": {
            "url": "/circuits/cm-detector/transfer-block.svg",
            "asset": "transfer-block.svg"
          }
        }
      }
    ]
  }
}