{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "cmfb-5t-pmos", "name": "Common-mode feedback block, five-transistor amplifier, PMOS input", "group": "Fully differential", "subgroup": "Common-mode feedback", "title": "Five-transistor CMFB, PMOS input", "summary": "This block helps a differential amplifier keep its two outputs centred on a reference voltage. Two resistors sense their average, and a small amplifier turns the error into a control voltage. The stage it drives must respond in the opposite direction to close negative feedback.", "reference": { "kind": "book", "authors": "B. Razavi", "title": "Design of Analog CMOS Integrated Circuits", "edition": "2nd", "publisher": "McGraw-Hill", "year": 2016, "where": "Sec. 9.7 (common-mode feedback: resistive sensing and the error amplifier)", "takes": "The technique: resistive common-mode sensing, which averages the outputs without responding to their difference, and a differential-pair error amplifier comparing the average with a reference to set a stage's current sources. The PMOS-input five-transistor amplifier, its sizing, the plant it is tested around and the targets are this library's, for SG13G2 at 1.2 V." }, "resources": { "record": "/circuits/cmfb-5t-pmos.json", "page": "/index.html#cmfb-5t-pmos", "achieved": "/achieved/cmfb-5t-pmos.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "inp", "kind": "input", "note": "one of the two outputs it senses" }, { "name": "inn", "kind": "input", "note": "the other" }, { "name": "out", "kind": "output", "note": "the control voltage: rises with the sensed common mode" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" }, { "name": "ref", "kind": "bias", "note": "the common mode to hold" }, { "name": "ib", "kind": "bias", "note": "the reference current, drawn out of this pin" } ], "devices": [ { "name": "RS1", "type": "resistor", "nodes": "inp sen", "sizedBy": [ "Rs" ], "role": "detector" }, { "name": "RS2", "type": "resistor", "nodes": "inn sen", "sizedBy": [ "Rs" ], "role": "detector" }, { "name": "MB", "type": "pmos", "nodes": "ib ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "bias reference, diode-connected", "fingers": 2, "copies": 1 }, { "name": "MT", "type": "pmos", "nodes": "tail ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "tail, 2 copies of MB", "fingers": 2, "copies": 2 }, { "name": "M1", "type": "pmos", "nodes": "d1 sen tail tail", "sizedBy": [ "W1", "L1" ], "role": "pair, sensing side, n-well on its source", "fingers": 2, "copies": 1 }, { "name": "M2", "type": "pmos", "nodes": "out ref tail tail", "sizedBy": [ "W1", "L1" ], "role": "pair, reference side, n-well on its source", "fingers": 2, "copies": 1 }, { "name": "M3", "type": "nmos", "nodes": "d1 d1 vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "mirror, diode", "fingers": 1, "copies": 1 }, { "name": "M4", "type": "nmos", "nodes": "out d1 vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "mirror output", "fingers": 1, "copies": 1 } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "The pair: its offset is the common-mode error the block leaves in a loop." }, { "rule": "match", "of": [ "M3", "M4" ], "why": "The mirror: a mismatch shifts the balance, as offset." }, { "rule": "match", "of": [ "RS1", "RS2" ], "why": "Equal resistors average away the differential signal; a mismatch lets it into the sensed common mode." }, { "rule": "unit-copies", "of": [ "MB", "MT" ], "constraint": "MT = 2 copies of MB", "why": "The tail is a count of the reference unit." }, { "rule": "well", "of": [ "M1", "M2" ], "constraint": "n-well on the source", "why": "No body effect: the pair's V_SG stays small, and the tail keeps its saturation with the sensed common mode near 0.6 V at 1.08 V." }, { "rule": "level", "of": [ "M3", "M4" ], "constraint": "out at balance = V_GS3 at half the tail current", "why": "The control voltage sits at an NMOS diode's level: made to set NMOS sinks, best by driving a diode whose copies they are - into a diode the block is a transconductance, and the loop keeps a single slow pole." }, { "rule": "detector-pole", "of": [ "RS1", "RS2", "M1" ], "constraint": "1/(2π·(RS/2)·C_gs1) well above the loop's crossover", "why": "The averaging resistors and the pair's gate capacitance make a pole in the loop; a small pair and moderate resistors keep it out of the way." } ], "specs": [ { "key": "slope", "label": "Slope at the reference", "unit": "V/V", "direction": "max", "constraint": ">= 15 V/V", "min": 15, "max": null, "why": "The servo's gain, g_m1 times the output resistance of M2 and M4: about 25 V/V at every corner." }, { "key": "dm_err", "label": "Error from a differential input", "unit": "V", "direction": "min", "constraint": "<= 0.005 V", "min": null, "max": 0.005, "why": "Equal resistors average a differential signal away exactly; only their mismatch lets it through, up to 2 mV for a 0.2 V difference over Monte Carlo." }, { "key": "gain_db", "label": "Gain at DC", "unit": "dB", "direction": "max", "constraint": ">= 20 dB", "min": 20, "max": null }, { "key": "bw_hz", "label": "Bandwidth, -3 dB", "unit": "Hz", "direction": "max", "constraint": ">= 2000000 Hz", "min": 2000000, "max": null, "why": "The output pole, M2's and M4's output resistance with the gates the block drives: about 4.7 MHz into 0.1 pF." }, { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.00002 A", "min": null, "max": 0.00002, "why": "2 Ib in the tail and Ib in the reference." }, { "key": "cm_err", "label": "Held common mode less its reference", "unit": "V", "direction": "target", "constraint": ">= -0.015 V, <= 0.015 V", "min": -0.015, "max": 0.015, "why": "Closed around its plant, the block holds the common mode to within its pair's offset and the copy error of the plant's sinks, which see a higher V_DS than the diode they copy: -3 to -6 mV at every corner, and -12 to +3 mV over 20 Monte Carlo draws." }, { "key": "loop_pm_deg", "label": "Loop phase margin", "unit": "deg", "direction": "max", "constraint": ">= 60 deg", "min": 60, "max": null, "why": "Into a diode its current sets, the block is a transconductor: the plant's load is the loop's only slow pole, and the detector's pole - RS/2 with the pair's gate capacitance - sits well above the crossover." }, { "key": "kick_recover", "label": "Recovery from the kick, 5 %", "unit": "s", "direction": "min", "constraint": "<= 5e-8 s", "min": null, "max": 5e-8, "why": "About 25 ns into the 2 pF plant, a single-pole recovery." }, { "key": "kick_under_pct", "label": "Swing past on the way back", "unit": "%", "direction": "min", "constraint": "<= 10 %", "min": null, "max": 10 } ], "explanation": { "idea": "This block helps a differential amplifier keep its two outputs centred on a reference voltage. Two resistors sense their average, and a small amplifier turns the error into a control voltage. The stage it drives must respond in the opposite direction to close negative feedback.", "detail": "A common-mode feedback block for a fully differential stage: it senses the average of two outputs and returns a control voltage that rises when that average rises above ref. Two equal resistors form the average without responding to the outputs' difference, and a five-transistor amplifier with a PMOS pair on an NMOS mirror amplifies the error. At balance its output rests at the mirror diode's gate voltage, the level of an NMOS current sink's gate.", "lesson": { "relation": 0, "symbols": "V_sen is the sensed common-mode voltage; V_inp and V_inn are the two stage-output voltages being averaged. All voltages are in V.", "assumptions": "Equal sensing resistors, negligible detector input current and low-frequency operation. The following amplifier and controlled stage must close negative feedback.", "exercise": { "param": "Rs", "value": 400000, "analysis": "transfer", "expect": "Larger sensing resistors should leave the nominal DC average nearly unchanged while reducing resistive loading. Check the common-mode response separately because the larger resistance can slow sensing." }, "limits": "The control voltage rises when the sensed average rises. Connect it to devices that then pull the stage outputs down, and verify common-mode range and loop stability with the actual stage." }, "path": [ { "part": "Detector", "devices": "RS1, RS2", "does": "The equal resistors put the average of inp and inn on sen; a purely differential swing leaves sen still." }, { "part": "Error amplifier", "devices": "M1, M2, M3, M4", "does": "M1, gate on sen, and M2, gate on ref, split the tail; the mirror M3, M4 subtracts the halves at out, which rises as sen rises above ref." }, { "part": "Tail", "devices": "MB, MT", "does": "The bench draws Ib out of the diode MB, and MT, two copies, feeds the pair." } ], "bias": "MT carries 2 Ib, so each side of the pair carries Ib at balance and out rests at M3's gate voltage at that current, about 0.36 V. The pair's n-wells sit on their sources, which keeps its V_SG small and the tail saturated with the sensed common mode near 0.5 V. Built to set NMOS sinks, the block works best into a diode whose copies they are: its output current then sets their current directly, and its benches close the loop that way.", "relations": [ { "what": "Sensed common mode", "expr": "V_sen = (V_inp + V_inn)/2", "note": "Each input sees one resistor to a node that stays still for differential signals." }, { "what": "Servo gain", "expr": "A_s = ΔV_out/ΔV_sen ≈ g_m1·(r_o2 ∥ r_o4)", "note": "Positive: out follows the sensed common mode, so the devices it drives must pull the outputs down as it rises." }, { "what": "Balanced output", "expr": "V_out,bal ≈ V_GS3(I_T/2)", "note": "At zero error the halves match and M4 copies M3." }, { "what": "Detector pole", "expr": "f_s ≈ 1/(2π·(RS/2)·C_gs1)", "note": "Must sit well above a closed loop's crossover: a small pair and 200 kΩ resistors put it near 30 MHz." } ], "tradeoffs": [ "Detector resistors: larger load the sensed outputs less, but pull the detector pole down with the pair's gate capacitance.", "Pair width: wider lowers offset and raises the gain, but loads sen and narrows the linear window.", "Mirror length: longer raises the servo gain, but slows its output pole and adds capacitance.", "Tail current: more speeds the servo for more supply current." ] }, "sizing": [ { "key": "Ib", "label": "Reference current", "unit": "A", "value": 0.000005, "min": 0.000001, "max": 0.00002, "kind": "si" }, { "key": "W1", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.000008, "min": 0.000001, "max": 0.00006, "kind": "si" }, { "key": "L1", "label": "L input pair", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wn", "label": "W NMOS mirror unit (M3, M4)", "unit": "m", "value": 0.000002, "min": 5e-7, "max": 0.00002, "kind": "si" }, { "key": "Ln", "label": "L NMOS mirror unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wp", "label": "W PMOS unit (MB, MT)", "unit": "m", "value": 0.000008, "min": 0.000001, "max": 0.00004, "kind": "si" }, { "key": "Lp", "label": "L PMOS unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Rs", "label": "Detector resistor, per side", "unit": "Ω", "value": 200000, "min": 50000, "max": 2000000, "kind": "si" }, { "key": "CL", "label": "Load on the output: the gates it drives", "unit": "F", "value": 1e-13, "min": 1e-14, "max": 2e-12, "kind": "si" }, { "key": "K", "label": "Plant: sinks, in copies of its diode", "unit": "", "value": 2, "min": 1, "max": 8, "kind": "int" }, { "key": "Cp", "label": "Plant: load capacitance on each output", "unit": "F", "value": 2e-12, "min": 2e-13, "max": 2e-11, "kind": "si" }, { "key": "VCM", "label": "Common mode held (the reference)", "unit": "V", "value": 0.5, "min": 0.35, "max": 0.6, "kind": "si" } ], "testbenches": [ { "id": "transfer", "label": "Transfer", "note": "The sensed common mode swept from 0 to 1.2 V, with the two inputs equal and then 200m V apart either way: the output against it, its slope where the inputs sit at the reference, and whether a difference between them moves it.", "measures": [], "metricKeys": [ "slope", "out_bal", "cm_lo", "cm_hi", "dm_err", "i_supply" ], "acceptance": [ "slope", "dm_err", "i_supply" ], "acceptanceRules": [ { "key": "slope", "unit": "V/V", "min": 15, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "dm_err", "unit": "V", "min": null, "max": 0.005, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "i_supply", "unit": "A", "min": null, "max": 0.00002, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Common-mode feedback block, PMOS input - transfer, sensed common mode swept\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 500m\nIb ib 0 5u\n.subckt cmfb5p inp inn out vdd vss ref ib\n* the detector: equal resistors put the average of inp and inn on sen\nXRS1 inp sen vss rhigh w=0.5u l=61.666u\nXRS2 inn sen vss rhigh w=0.5u l=61.666u\n* the tail, two copies of the reference diode MB\nXMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\n* the pair, its n-well on its sources, on an NMOS mirror; out rises with sen\nXM1 d1 sen tail tail sg13_lv_pmos w=8u l=500n ng=2 m=1\nXM2 out ref tail tail sg13_lv_pmos w=8u l=500n ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=2u l=1u ng=1 m=1\nXM4 out d1 vss vss sg13_lv_nmos w=2u l=1u ng=1 m=1\n.ends\nXdut inp inn out vdd 0 ref ib cmfb5p\nCl out 0 100f\n* the two sensed nodes: the common mode on cm, the difference on vd\nVcm cm 0 dc 500m\nVd vd 0 dc 0\nEp inp cm vd 0 0.5\nEn inn cm vd 0 -0.5\n.dc Vcm 0 1.2 5m Vd -200m 200m 200m\n.end" }, { "id": "servo", "label": "Servo response", "note": "A small common-mode signal on both inputs and the output driving its load: the servo's gain at DC, its bandwidth and its unity-gain frequency.", "measures": [], "metricKeys": [ "gain_db", "bw_hz", "ugf_hz" ], "acceptance": [ "gain_db", "bw_hz" ], "acceptanceRules": [ { "key": "gain_db", "unit": "dB", "min": 20, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "bw_hz", "unit": "Hz", "min": 2000000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Common-mode feedback block, PMOS input - common-mode signal to the output\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 500m\nIb ib 0 5u\n.subckt cmfb5p inp inn out vdd vss ref ib\n* the detector: equal resistors put the average of inp and inn on sen\nXRS1 inp sen vss rhigh w=0.5u l=61.666u\nXRS2 inn sen vss rhigh w=0.5u l=61.666u\n* the tail, two copies of the reference diode MB\nXMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\n* the pair, its n-well on its sources, on an NMOS mirror; out rises with sen\nXM1 d1 sen tail tail sg13_lv_pmos w=8u l=500n ng=2 m=1\nXM2 out ref tail tail sg13_lv_pmos w=8u l=500n ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=2u l=1u ng=1 m=1\nXM4 out d1 vss vss sg13_lv_nmos w=2u l=1u ng=1 m=1\n.ends\nXdut inp inn out vdd 0 ref ib cmfb5p\nCl out 0 100f\n* the two sensed nodes: the common mode on cm, the difference on vd\nVcm cm 0 dc 500m ac 1\nVd vd 0 dc 0\nEp inp cm vd 0 0.5\nEn inn cm vd 0 -0.5\n.ac dec 25 1 10g\n.end" }, { "id": "loop", "label": "Common-mode loop", "note": "The block holding the common mode of its plant: where that common mode lands against the reference, and the loop's gain and phase margin, measured by Middlebrook's double injection - a voltage, then a current - where the block's output meets the plant.", "measures": [], "metricKeys": [ "cm_level", "cm_err", "loop_gain_db", "loop_ugf_hz", "loop_pm_deg" ], "acceptance": [ "cm_err", "loop_pm_deg" ], "acceptanceRules": [ { "key": "cm_err", "unit": "V", "min": -0.015, "max": 0.015, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "loop_pm_deg", "unit": "deg", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Common-mode feedback block, PMOS input - common-mode loop, operating point\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 500m\nIb ib 0 5u\n.subckt cmfb5p inp inn out vdd vss ref ib\n* the detector: equal resistors put the average of inp and inn on sen\nXRS1 inp sen vss rhigh w=0.5u l=61.666u\nXRS2 inn sen vss rhigh w=0.5u l=61.666u\n* the tail, two copies of the reference diode MB\nXMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\n* the pair, its n-well on its sources, on an NMOS mirror; out rises with sen\nXM1 d1 sen tail tail sg13_lv_pmos w=8u l=500n ng=2 m=1\nXM2 out ref tail tail sg13_lv_pmos w=8u l=500n ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=2u l=1u ng=1 m=1\nXM4 out d1 vss vss sg13_lv_nmos w=2u l=1u ng=1 m=1\n.ends\nXdut inp inn out vdd 0 ref ib cmfb5p\n* the plant: the stage whose common mode the block holds\nIsp vdd inp 10u\nIsn vdd inn 10u\nIpd vdd ctl 5u\nXMPD ctl ctl 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1\nXMSP inp ctl 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=2\nXMSN inn ctl 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=2\nCpp inp 0 2p\nCpn inn 0 2p\n* the loop joined where the block's output meets the plant\nVbrk ctl out 0\n.op\n.end" }, { "id": "kick", "label": "Common-mode kick", "note": "The loop kicked: 2uA into each of the plant's outputs for 50ns, and how the common mode comes back.", "measures": [], "metricKeys": [ "kick_dev", "kick_recover", "kick_under_pct" ], "acceptance": [ "kick_recover", "kick_under_pct" ], "acceptanceRules": [ { "key": "kick_recover", "unit": "s", "min": null, "max": 5e-8, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "kick_under_pct", "unit": "%", "min": null, "max": 10, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Common-mode feedback block, PMOS input - common-mode kick\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 500m\nIb ib 0 5u\n.subckt cmfb5p inp inn out vdd vss ref ib\n* the detector: equal resistors put the average of inp and inn on sen\nXRS1 inp sen vss rhigh w=0.5u l=61.666u\nXRS2 inn sen vss rhigh w=0.5u l=61.666u\n* the tail, two copies of the reference diode MB\nXMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\n* the pair, its n-well on its sources, on an NMOS mirror; out rises with sen\nXM1 d1 sen tail tail sg13_lv_pmos w=8u l=500n ng=2 m=1\nXM2 out ref tail tail sg13_lv_pmos w=8u l=500n ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=2u l=1u ng=1 m=1\nXM4 out d1 vss vss sg13_lv_nmos w=2u l=1u ng=1 m=1\n.ends\nXdut inp inn out vdd 0 ref ib cmfb5p\n* the plant: the stage whose common mode the block holds\nIsp vdd inp 10u\nIsn vdd inn 10u\nIpd vdd ctl 5u\nXMPD ctl ctl 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1\nXMSP inp ctl 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=2\nXMSN inn ctl 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=2\nCpp inp 0 2p\nCpn inn 0 2p\n* the loop joined where the block's output meets the plant\nVbrk ctl out 0\n* the kick: the same current pulse into both outputs\nIkp 0 inp dc 0 pulse(0 2u 100n 1n 1n 50n 2u)\nIkn 0 inn dc 0 pulse(0 2u 100n 1n 1n 50n 2u)\n.tran 250p 1u\n.end" } ], "measurements": { "slope": { "label": "Slope at the reference", "unit": "V/V", "spec": { "min": 15, "max": null } }, "dm_err": { "label": "Error from a differential input", "unit": "V", "spec": { "min": null, "max": 0.005 } }, "gain_db": { "label": "Gain at DC", "unit": "dB", "spec": { "min": 20, "max": null } }, "bw_hz": { "label": "Bandwidth, -3 dB", "unit": "Hz", "spec": { "min": 2000000, "max": null } }, "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.00002 } }, "cm_err": { "label": "Held common mode less its reference", "unit": "V", "spec": { "min": -0.015, "max": 0.015 } }, "loop_pm_deg": { "label": "Loop phase margin", "unit": "deg", "spec": { "min": 60, "max": null } }, "kick_recover": { "label": "Recovery from the kick, 5 %", "unit": "s", "spec": { "min": null, "max": 5e-8 } }, "kick_under_pct": { "label": "Swing past on the way back", "unit": "%", "spec": { "min": null, "max": 10 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "b69ccd1724ef706630c047864a3b0b9d0103f1fcce5926134edb453cf977fefe" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/cmfb-5t-pmos.js", "sha256": "e5e586298cc26b49070ad4665cd06e49a1b4522796ba1b2f71c8340d9b635844" }, "simulationFingerprints": { "transfer": "ad81866cd39f524d6cb649f304f8a5bc7c6e9218789057ee794f32c90c3af37b", "servo": "aa59bc06a709f0d8803d1ba3f5472be6d22f60efff20bc37fe9585427390bc19", "loop": "0b65e5ef363d67eabd9e291e00bb6e7b2fb40239de9676b64ff5347bc1deb277", "kick": "72f4a4cd1a8720127a7ca16cfe67f76466697af3e833769c748f7f76dfd9c496" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "334807d4dfd63cfdbcfbda53ea1e40cc64864df51fabdbffa1e9d0a598c68317", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "cmfb-5t-pmos", "parameters": { "Ib": 0.000005, "W1": 0.000008, "L1": 5e-7, "Wn": 0.000002, "Ln": 0.000001, "Wp": 0.000008, "Lp": 0.000001, "Rs": 200000, "CL": 1e-13, "K": 2, "Cp": 2e-12, "VCM": 0.5 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/cmfb-5t-pmos/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "cmfb5p", "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ref", "net": "ref", "kind": "bias" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XRS1", "displayName": "RS1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRS1 inp sen vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "sen" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRS2", "displayName": "RS2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRS2 inn sen vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "sen" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM1 d1 sen tail tail sg13_lv_pmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "sen" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM2 out ref tail tail sg13_lv_pmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XM3 d1 d1 vss vss sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XM4 out d1 vss vss sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "inp", "ground": false, "terminals": [ { "device": "XRS1", "pin": "p" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "sen", "ground": false, "terminals": [ { "device": "XRS1", "pin": "n" }, { "device": "XRS2", "pin": "n" }, { "device": "XM1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRS1", "pin": "substrate" }, { "device": "XRS2", "pin": "substrate" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XRS2", "pin": "p" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 500m", "source": "Vref ref 0 dc 500m", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ib ib 0 5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "cmfb5p", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ref ib cmfb5p", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ref", "net": "ref" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/cmfb5p" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "100f", "source": "Cl out 0 100f", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vcm", "displayName": "Vcm", "spiceType": "V", "model": null, "parametersOrValue": "dc 500m", "source": "Vcm cm 0 dc 500m", "pins": [ { "id": "p", "net": "cm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vd", "displayName": "Vd", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vd vd 0 dc 0", "pins": [ { "id": "p", "net": "vd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ep", "displayName": "Ep", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Ep inp cm vd 0 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "cm" }, { "id": "cp", "net": "vd" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "En", "displayName": "En", "spiceType": "E", "model": null, "parametersOrValue": "-0.5", "source": "En inn cm vd 0 -0.5", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "cm" }, { "id": "cp", "net": "vd" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vcm", "pin": "n" }, { "device": "Vd", "pin": "n" }, { "device": "Ep", "pin": "cn" }, { "device": "En", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Ep", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "En", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cm", "ground": false, "terminals": [ { "device": "Vcm", "pin": "p" }, { "device": "Ep", "pin": "n" }, { "device": "En", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vd", "ground": false, "terminals": [ { "device": "Vd", "pin": "p" }, { "device": "Ep", "pin": "cp" }, { "device": "En", "pin": "cp" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/cmfb5p", "name": "cmfb5p", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ref", "net": "ref" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XRS1", "displayName": "RS1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRS1 inp sen vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "sen" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRS2", "displayName": "RS2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRS2 inn sen vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "sen" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMT tail ib vdd vdd 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PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 500m", "source": "Vref ref 0 dc 500m", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ib ib 0 5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "cmfb5p", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ref ib cmfb5p", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ref", "net": "ref" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/cmfb5p" }, { "id": "Isp", "displayName": "Isp", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Isp vdd inp 10u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "inp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Isn", "displayName": "Isn", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Isn vdd inn 10u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ipd", "displayName": "Ipd", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ipd vdd ctl 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ctl" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "XMPD", "displayName": "MPD", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMPD ctl ctl 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "ctl" }, { "id": "g", "net": "ctl" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSP", "displayName": "MSP", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=2", "source": "XMSP inp ctl 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "ctl" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSN", "displayName": "MSN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=2", "source": "XMSN inn ctl 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "ctl" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "Cpp", "displayName": "Cpp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cpp inp 0 2p", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cpn", "displayName": "Cpn", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cpn inn 0 2p", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk", "displayName": "Vbrk", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk ctl out 0", "pins": [ { "id": "p", "net": "ctl" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" }, { "device": "Isp", "pin": "p" }, { "device": "Isn", "pin": "p" }, { "device": "Ipd", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "XMPD", "pin": "s" }, { "device": "XMPD", "pin": "b" }, { "device": "XMSP", "pin": "s" }, { "device": "XMSP", "pin": "b" }, { "device": "XMSN", "pin": "s" }, { "device": "XMSN", "pin": "b" }, { "device": "Cpp", "pin": "n" }, { "device": "Cpn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Isp", "pin": "n" }, { "device": "XMSP", "pin": "d" }, { "device": "Cpp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Isn", "pin": "n" }, { "device": "XMSN", "pin": "d" }, { "device": "Cpn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vbrk", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ctl", "ground": false, "terminals": [ { "device": "Ipd", "pin": "n" }, { "device": "XMPD", "pin": "d" }, { "device": "XMPD", "pin": "g" }, { "device": "XMSP", "pin": "g" }, { "device": "XMSN", "pin": "g" }, { "device": "Vbrk", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/cmfb5p", "name": "cmfb5p", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ref", "net": "ref" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XRS1", "displayName": "RS1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRS1 inp sen vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "sen" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRS2", "displayName": "RS2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRS2 inn sen vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "sen" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM1 d1 sen tail tail sg13_lv_pmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "sen" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM2 out ref tail tail sg13_lv_pmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XM3 d1 d1 vss vss sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XM4 out d1 vss vss sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "inp", "ground": false, "terminals": [ { "device": "XRS1", "pin": "p" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "sen", "ground": false, "terminals": [ { "device": "XRS1", "pin": "n" }, { "device": "XRS2", "pin": "n" }, { "device": "XM1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRS1", "pin": "substrate" }, { "device": "XRS2", "pin": "substrate" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XRS2", "pin": "p" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/cmfb5p" } }, { "id": "graph-6", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 500m", "source": "Vref ref 0 dc 500m", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ib ib 0 5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "cmfb5p", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ref ib cmfb5p", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ref", "net": "ref" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/cmfb5p" }, { "id": "Isp", "displayName": "Isp", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Isp vdd inp 10u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "inp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Isn", "displayName": "Isn", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Isn vdd inn 10u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ipd", "displayName": "Ipd", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ipd vdd ctl 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ctl" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "XMPD", "displayName": "MPD", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMPD ctl ctl 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "ctl" }, { "id": "g", "net": "ctl" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSP", "displayName": "MSP", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=2", "source": "XMSP inp ctl 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "ctl" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSN", "displayName": "MSN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=2", "source": "XMSN inn ctl 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "ctl" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "Cpp", "displayName": "Cpp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cpp inp 0 2p", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cpn", "displayName": "Cpn", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cpn inn 0 2p", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk", "displayName": "Vbrk", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk ctl out 0", "pins": [ { "id": "p", "net": "ctl" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ikp", "displayName": "Ikp", "spiceType": "I", "model": null, "parametersOrValue": "dc 0 pulse(0 2u 100n 1n 1n 50n 2u)", "source": "Ikp 0 inp dc 0 pulse(0 2u 100n 1n 1n 50n 2u)", "pins": [ { "id": "p", "net": "0" }, { "id": "n", "net": "inp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ikn", "displayName": "Ikn", "spiceType": "I", "model": null, "parametersOrValue": "dc 0 pulse(0 2u 100n 1n 1n 50n 2u)", "source": "Ikn 0 inn dc 0 pulse(0 2u 100n 1n 1n 50n 2u)", "pins": [ { "id": "p", "net": "0" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" }, { "device": "Isp", "pin": "p" }, { "device": "Isn", "pin": "p" }, { "device": "Ipd", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Ib", "pin": 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