{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "cmfb-sc", "name": "Switched-capacitor common-mode feedback", "group": "Fully differential", "subgroup": "Common-mode feedback", "title": "Switched-capacitor CMFB", "summary": "This block controls the average output voltage of a differential amplifier using stored charge. Sensing capacitors pass changes immediately, while clocked capacitors refresh the control level. It avoids an intentional static bias path, but needs clock phases that do not overlap and a suitable bias reference.", "reference": { "kind": "book", "authors": "T. Chan Carusone, D. A. Johns, K. W. Martin", "title": "Analog Integrated Circuit Design", "edition": "2nd", "publisher": "Wiley", "year": 2012, "where": "Sec. 7.6 (common-mode feedback circuits: the switched-capacitor detector)", "takes": "The circuit: capacitors from the outputs to the control node that sense the common mode, and capacitors switched on two non-overlapping phases between the reference and the bias and across the sensing capacitors, which set the charge on them. The switch types, the sizing, the stage it is tested around, the bias replica and the targets are this library's, for SG13G2 at 1.2 V." }, "resources": { "record": "/circuits/cmfb-sc.json", "page": "/index.html#cmfb-sc", "achieved": "/achieved/cmfb-sc.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "inp", "kind": "input", "note": "one of the two outputs it senses" }, { "name": "inn", "kind": "input", "note": "the other" }, { "name": "out", "kind": "output", "note": "the control voltage: vbias plus the common mode's distance from ref" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" }, { "name": "ref", "kind": "bias", "note": "the common mode to hold" }, { "name": "vbias", "kind": "bias", "note": "the control voltage the stage needs with its common mode at ref" }, { "name": "p1", "kind": "clock", "note": "phase 1: the switched capacitors recharge" }, { "name": "p1b", "kind": "clock", "note": "phase 1, inverted, for the PMOS halves" }, { "name": "p2", "kind": "clock", "note": "phase 2, not overlapping phase 1: the switched capacitors across the sensing ones" }, { "name": "p2b", "kind": "clock", "note": "phase 2, inverted" } ], "devices": [ { "name": "CC1", "type": "capacitor", "nodes": "inp out", "sizedBy": [ "Cc" ], "role": "sensing capacitor" }, { "name": "CC2", "type": "capacitor", "nodes": "inn out", "sizedBy": [ "Cc" ], "role": "sensing capacitor" }, { "name": "CS1", "type": "capacitor", "nodes": "a1 b1", "sizedBy": [ "Cs" ], "role": "switched capacitor" }, { "name": "CS2", "type": "capacitor", "nodes": "a2 b2", "sizedBy": [ "Cs" ], "role": "switched capacitor" }, { "name": "M1", "type": "nmos", "nodes": "a1 p1 ref vss", "sizedBy": [ "Wsn", "Ls" ], "role": "phase 1: CS1 to ref, NMOS half", "fingers": 1, "copies": 1 }, { "name": "M2", "type": "pmos", "nodes": "a1 p1b ref vdd", "sizedBy": [ "Wsp", "Ls" ], "role": "phase 1: CS1 to ref, PMOS half", "fingers": 1, "copies": 1 }, { "name": "M3", "type": "nmos", "nodes": "b1 p1 vbias vss", "sizedBy": [ "Wsn", "Ls" ], "role": "phase 1: CS1 to vbias", "fingers": 1, "copies": 1 }, { "name": "M4", "type": "nmos", "nodes": "a1 p2 inp vss", "sizedBy": [ "Wsn", "Ls" ], "role": "phase 2: CS1 to inp, NMOS half", "fingers": 1, "copies": 1 }, { "name": "M5", "type": "pmos", "nodes": "a1 p2b inp vdd", "sizedBy": [ "Wsp", "Ls" ], "role": "phase 2: CS1 to inp, PMOS half", "fingers": 1, "copies": 1 }, { "name": "M6", "type": "nmos", "nodes": "b1 p2 out vss", "sizedBy": [ "Wsn", "Ls" ], "role": "phase 2: CS1 to out", "fingers": 1, "copies": 1 }, { "name": "M7", "type": "nmos", "nodes": "a2 p1 ref vss", "sizedBy": [ "Wsn", "Ls" ], "role": "phase 1: CS2 to ref, NMOS half", "fingers": 1, "copies": 1 }, { "name": "M8", "type": "pmos", "nodes": "a2 p1b ref vdd", "sizedBy": [ "Wsp", "Ls" ], "role": "phase 1: CS2 to ref, PMOS half", "fingers": 1, "copies": 1 }, { "name": "M9", "type": "nmos", "nodes": "b2 p1 vbias vss", "sizedBy": [ "Wsn", "Ls" ], "role": "phase 1: CS2 to vbias", "fingers": 1, "copies": 1 }, { "name": "M10", "type": "nmos", "nodes": "a2 p2 inn vss", "sizedBy": [ "Wsn", "Ls" ], "role": "phase 2: CS2 to inn, NMOS half", "fingers": 1, "copies": 1 }, { "name": "M11", "type": "pmos", "nodes": "a2 p2b inn vdd", "sizedBy": [ "Wsp", "Ls" ], "role": "phase 2: CS2 to inn, PMOS half", "fingers": 1, "copies": 1 }, { "name": "M12", "type": "nmos", "nodes": "b2 p2 out vss", "sizedBy": [ "Wsn", "Ls" ], "role": "phase 2: CS2 to out", "fingers": 1, "copies": 1 } ], "intent": [ { "rule": "match", "of": [ "CC1", "CC2", "CS1", "CS2" ], "why": "The two halves must be equal, or a differential output leaks into out and the charge each side sets differs." }, { "rule": "ratio", "of": [ "CS1", "CC1" ], "constraint": "CS = CC/2", "why": "In the ideal charge-sharing model, each cycle closes CS/(CC + CS) of the remaining error. A larger CS can settle in fewer cycles but changes both switched charge and total node capacitance; clock ripple need not increase monotonically. Check the measured waveform for the chosen load and switches." }, { "rule": "switch-type", "of": [ "M3", "M6", "M9", "M12" ], "constraint": "NMOS only on the vbias and out side", "why": "out and vbias sit near 0.3 V, where an NMOS conducts well and a PMOS barely; a PMOS half would add only its n-well's leakage into out, which grows a hundredfold by 125 °C." }, { "rule": "switch-type", "of": [ "M1", "M2", "M4", "M5" ], "constraint": "transmission gates on the outputs' side", "why": "The outputs and ref swing around mid-supply, where either half alone would be weak over part of the swing." }, { "rule": "non-overlap", "of": [ "M1", "M4" ], "constraint": "phase 1 and phase 2 never high together", "why": "Overlapping phases would short ref to an output and vbias to out through the capacitor's switches, for as long as they overlap." }, { "rule": "vbias", "of": [ "M6", "M12" ], "constraint": "vbias = the gate voltage the stage's devices need at their operating point", "why": "The block has a slope of one and no gain: whatever distance lies between vbias and the gate voltage the stage needs appears as common-mode error, one for one." } ], "specs": [ { "key": "slope", "label": "Slope at the reference", "unit": "V/V", "direction": "target", "constraint": ">= 0.95 V/V, <= 1.05 V/V", "min": 0.95, "max": 1.05, "why": "The switched capacitors carry the common-mode error across one for one: the slope is one, less what the capacitors on out divide away." }, { "key": "bal_err", "label": "Output at balance less vbias", "unit": "V", "direction": "target", "constraint": ">= -0.005 V, <= 0.005 V", "min": -0.005, "max": 0.005, "why": "With the outputs at ref, out rests at vbias less the charge the NMOS switches inject into it each cycle: about 1 mV." }, { "key": "settle_clk", "label": "Settling, 1 %", "unit": "cycles", "direction": "min", "constraint": "<= 15 cycles", "min": null, "max": 15, "why": "Ignoring load and parasitics, each refresh removes one third of stored-charge error at CS = CC/2. Settling is the first cycle after the last 1% miss, with at least two observed in-band cycles, not a temporary first crossing." }, { "key": "ripple", "label": "Clock ripple on the output", "unit": "V", "direction": "min", "constraint": "<= 0.005 V", "min": null, "max": 0.005 }, { "key": "cm_err", "label": "Held common mode less its reference", "unit": "V", "direction": "target", "constraint": ">= -0.01 V, <= 0.01 V", "min": -0.01, "max": 0.01, "why": "With a slope of one the block adds no gain: the common mode lands where the stage's sinks need out to be, so the mismatch between them and the vbias replica passes straight through - within 4 mV at every corner, 6 mV over 20 Monte Carlo draws." }, { "key": "cm_ripple", "label": "Clock ripple on the common mode", "unit": "V", "direction": "min", "constraint": "<= 0.002 V", "min": null, "max": 0.002, "why": "Each cycle's charge injection and CS's reconnection, seen through the stage's gain." }, { "key": "t_hold", "label": "Settling to 1 mV", "unit": "s", "direction": "min", "constraint": "<= 0.00002 s", "min": null, "max": 0.00002 } ], "explanation": { "idea": "This block controls the average output voltage of a differential amplifier using stored charge. Sensing capacitors pass changes immediately, while clocked capacitors refresh the control level. It avoids an intentional static bias path, but needs clock phases that do not overlap and a suitable bias reference.", "detail": "CC1 and CC2 continuously couple the sensed outputs to the control node, but they do not provide a DC conductive path: stored charge sets the control level. During phase 1, CS1 and CS2 charge to ref − vbias. During phase 2, they share that charge with the sensing capacitors. With ideal switches, negligible loading and settled clocking, out approaches vbias plus the sensed common mode minus ref. Leakage, charge injection and load capacitance cause departures from that approximation.", "lesson": { "relation": 1, "symbols": "e_k is the remaining voltage error stored on the sensing capacitors after refresh number k, in V; C_C is the always-connected sensing capacitance per side in F; C_S is the switched refresh capacitance per side in F.", "assumptions": "Ideal charge sharing with negligible control-node load and parasitics, and complete settling within each clock phase. The bench measures 1 % of an applied step, not 1 % of initial stored-charge error.", "exercise": { "param": "Cs", "value": 5e-13, "analysis": "clocked", "expect": "Doubling the switched capacitor should remove more stored-charge error per refresh and usually shorten settling. Compare clock ripple as well: larger refresh capacitors move more charge." }, "limits": "Use non-overlapping phases and a bias reference matched to the controlled stage. The control node stores charge rather than having a DC conductive path; leakage, startup and clock failure need separate checks." }, "path": [ { "part": "Sensing capacitors", "devices": "CC1, CC2", "does": "Each connects an output to out at every instant: out moves with the outputs' common mode, and their difference cancels." }, { "part": "Recharge, phase 1", "devices": "M1, M2, M3, M7, M8, M9, CS1, CS2", "does": "Transmission gates M1, M2 and M7, M8 tie one plate of each switched capacitor to ref; M3 and M9 tie the other to vbias, so each holds ref less vbias." }, { "part": "Refresh, phase 2", "devices": "M4, M5, M6, M10, M11, M12", "does": "M4, M5 and M10, M11 tie the capacitors to inp and inn, M6 and M12 to out: each switched capacitor sits across a sensing one and shares its charge, pulling it towards ref less vbias." } ], "bias": "There is no intentional static bias path in the sensing block. Clock switching moves charge, device leakage remains, and the two clock phases must not overlap. ref is the common mode to hold and vbias the control voltage the stage needs at that point: here the gate voltage at which one unit of the stage's sinks carries its current with its drain near the reference, which the bench makes with a replica. The switches on out and vbias are NMOS only, since those nodes sit a few hundred millivolts above ground.", "relations": [ { "what": "Steady state", "expr": "V_out → V_bias + (V_inp + V_inn)/2 − V_ref", "note": "A slope of one; with the common mode at ref, out rests at vbias." }, { "what": "Settling per cycle", "expr": "e_(k+1)/e_k ≈ C_C/(C_C + C_S)", "note": "Ignoring load and parasitics, C_S = C_C/2 leaves two thirds of the stored-charge error after each refresh: twelve refreshes reduce it below 1 % of its initial value. The default step bench measures six cycles to 1 % of the full applied step because capacitive feedthrough supplies most of the change immediately." }, { "what": "Common-mode error in a loop", "expr": "ΔV_oc ≈ V_GS,needed − V_bias", "note": "The block adds no gain: the distance between vbias and the gate voltage the stage needs appears as common-mode error one for one." }, { "what": "Load on the outputs", "expr": "R_eq ≈ 1/(f_clk·C_S)", "note": "Only for differential signals and common-mode errors: a settled common mode moves no charge." } ], "tradeoffs": [ "Switched capacitor: larger closes more of the ideal stored error each cycle. It changes both switched charge and node capacitance, so clock ripple need not rise; inspect the measured waveform.", "Sensing capacitor: larger divides the switches' charge injection down, and loads the outputs more.", "Switch width: wider settles faster within each phase but injects more charge onto out.", "vbias: must be the stage's own operating gate voltage, since the block cannot correct a wrong one." ] }, "sizing": [ { "key": "Ib", "label": "Bias current (the vbias replica, the plant)", "unit": "A", "value": 0.000005, "min": 0.000001, "max": 0.00002, "kind": "si" }, { "key": "Cc", "label": "Sensing capacitor, per side (CC1, CC2)", "unit": "F", "value": 5e-13, "min": 5e-14, "max": 5e-12, "kind": "si" }, { "key": "Cs", "label": "Switched capacitor, per side (CS1, CS2)", "unit": "F", "value": 2.5e-13, "min": 2e-14, "max": 5e-12, "kind": "si" }, { "key": "Wsn", "label": "W NMOS switches", "unit": "m", "value": 5e-7, "min": 1.5e-7, "max": 0.000005, "kind": "si" }, { "key": "Wsp", "label": "W PMOS switches", "unit": "m", "value": 0.000001, "min": 1.5e-7, "max": 0.00001, "kind": "si" }, { "key": "Ls", "label": "L switches", "unit": "m", "value": 1.3e-7, "min": 1.3e-7, "max": 0.000001, "kind": "si" }, { "key": "Wn", "label": "W NMOS unit (the vbias replica, the plant's sinks)", "unit": "m", "value": 0.000004, "min": 5e-7, "max": 0.00004, "kind": "si" }, { "key": "Ln", "label": "L NMOS unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wp", "label": "W PMOS unit (the plant's sources)", "unit": "m", "value": 0.000008, "min": 0.000001, "max": 0.00004, "kind": "si" }, { "key": "Lp", "label": "L PMOS unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "CL", "label": "Load on the output: the gates it drives", "unit": "F", "value": 1e-13, "min": 1e-14, "max": 2e-12, "kind": "si" }, { "key": "K", "label": "Plant: sinks, in copies of the vbias replica", "unit": "", "value": 2, "min": 1, "max": 8, "kind": "int" }, { "key": "Cp", "label": "Plant: load capacitance on each output", "unit": "F", "value": 2e-12, "min": 2e-13, "max": 2e-11, "kind": "si" }, { "key": "VCM", "label": "Common mode held (the reference)", "unit": "V", "value": 0.6, "min": 0.4, "max": 0.8, "kind": "si" } ], "testbenches": [ { "id": "clocked", "label": "Clocked settling", "note": "The block is clocked on its own, first at balance then after a 50 mV common-mode step. Settling requires every remaining cycle sample to stay within 1%, with at least two observed in-band cycles.", "measures": [], "metricKeys": [ "out_bal", "bal_err", "slope", "settle_clk", "ripple" ], "acceptance": [ "bal_err", "slope", "settle_clk", "ripple" ], "acceptanceRules": [ { "key": "bal_err", "unit": "V", "min": -0.005, "max": 0.005, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "slope", "unit": "V/V", "min": 0.95, "max": 1.05, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "settle_clk", "unit": "cycles", "min": null, "max": 15, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "ripple", "unit": "V", "min": null, "max": 0.005, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Switched-capacitor common-mode feedback - clocked settling\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 600m\n* vbias: the gate voltage at which one NMOS unit carries Ib with its drain a\n* follower's V_GS above it - near the reference, where the stage's sinks sit\nIvb vdd dvb 5u\nXMVB dvb vbias 0 0 sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMVF vdd dvb vbias 0 sg13_lv_nmos w=4u l=1u ng=1 m=1\nIvf vbias 0 5u\n.subckt cmfbsc inp inn out vdd vss ref vbias p1 p1b p2 p2b\n* the sensing capacitors, always between each output and out\nXCC1 inp out cap_cmim w=18.204u l=18.204u\nXCC2 inn out cap_cmim w=18.204u l=18.204u\n* the switched capacitors: charged to ref - vbias on phase 1, across CC1, CC2 on phase 2\nXCS1 a1 b1 cap_cmim w=12.857u l=12.857u\nXCS2 a2 b2 cap_cmim w=12.857u l=12.857u\n* phase 1: each a to ref through a transmission gate, each b to vbias through an NMOS\nXM1 a1 p1 ref vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXM2 a1 p1b ref vdd sg13_lv_pmos w=1u l=130n ng=1 m=1\nXM3 b1 p1 vbias vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXM7 a2 p1 ref vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXM8 a2 p1b ref vdd sg13_lv_pmos w=1u l=130n ng=1 m=1\nXM9 b2 p1 vbias vss sg13_lv_nmos w=500n l=130n ng=1 m=1\n* phase 2: each a to its output through a transmission gate, each b to out through an NMOS\nXM4 a1 p2 inp vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXM5 a1 p2b inp vdd sg13_lv_pmos w=1u l=130n ng=1 m=1\nXM6 b1 p2 out vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXM10 a2 p2 inn vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXM11 a2 p2b inn vdd sg13_lv_pmos w=1u l=130n ng=1 m=1\nXM12 b2 p2 out vss sg13_lv_nmos w=500n l=130n ng=1 m=1\n.ends\nXdut inp inn out vdd 0 ref vbias p1 p1b p2 p2b cmfbsc\nCl out 0 100f\n* two non-overlapping phases, 1us period\nVp1 p1 0 dc 0 pulse(0 {VDD} 25n 2.5n 2.5n 447.5n 1u)\nVp1b p1b 0 dc {VDD} pulse({VDD} 0 25n 2.5n 2.5n 447.5n 1u)\nVp2 p2 0 dc 0 pulse(0 {VDD} 525n 2.5n 2.5n 447.5n 1u)\nVp2b p2b 0 dc {VDD} pulse({VDD} 0 525n 2.5n 2.5n 447.5n 1u)\n* the two sensed nodes: the common mode on cm, the difference on vd\nVcm cm 0 dc 600m pulse(600m 650m 25u 2.5n 2.5n 100u 200u)\nVd vd 0 dc 0\nEp inp cm vd 0 0.5\nEn inn cm vd 0 -0.5\n.ic v(out)=0.3\n.tran 5n 50u\n.end" }, { "id": "clocked_loop", "label": "Clocked loop", "note": "The block holding its plant's common mode, clocked, from a start with that common mode away from the reference: where it lands, how soon it is within 1 mV, and the ripple the clock leaves on it.", "measures": [], "metricKeys": [ "cm_level", "cm_err", "cm_ripple", "t_hold" ], "acceptance": [ "cm_err", "cm_ripple", "t_hold" ], "acceptanceRules": [ { "key": "cm_err", "unit": "V", "min": -0.01, "max": 0.01, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "cm_ripple", "unit": "V", "min": null, "max": 0.002, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "t_hold", "unit": "s", "min": null, "max": 0.00002, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Switched-capacitor common-mode feedback - clocked common-mode loop\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 600m\n* vbias: the gate voltage at which one NMOS unit carries Ib with its drain a\n* follower's V_GS above it - near the reference, where the stage's sinks sit\nIvb vdd dvb 5u\nXMVB dvb vbias 0 0 sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMVF vdd dvb vbias 0 sg13_lv_nmos w=4u l=1u ng=1 m=1\nIvf vbias 0 5u\n.subckt cmfbsc inp inn out vdd vss ref vbias p1 p1b p2 p2b\n* the sensing capacitors, always between each output and out\nXCC1 inp out cap_cmim w=18.204u l=18.204u\nXCC2 inn out cap_cmim w=18.204u l=18.204u\n* the switched capacitors: charged to ref - vbias on phase 1, across CC1, CC2 on phase 2\nXCS1 a1 b1 cap_cmim w=12.857u l=12.857u\nXCS2 a2 b2 cap_cmim w=12.857u l=12.857u\n* phase 1: each a to ref through a transmission gate, each b to vbias through an NMOS\nXM1 a1 p1 ref vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXM2 a1 p1b ref vdd sg13_lv_pmos w=1u l=130n ng=1 m=1\nXM3 b1 p1 vbias vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXM7 a2 p1 ref vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXM8 a2 p1b ref vdd sg13_lv_pmos w=1u l=130n ng=1 m=1\nXM9 b2 p1 vbias vss sg13_lv_nmos w=500n l=130n ng=1 m=1\n* phase 2: each a to its output through a transmission gate, each b to out through an NMOS\nXM4 a1 p2 inp vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXM5 a1 p2b inp vdd sg13_lv_pmos w=1u l=130n ng=1 m=1\nXM6 b1 p2 out vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXM10 a2 p2 inn vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXM11 a2 p2b inn vdd sg13_lv_pmos w=1u l=130n ng=1 m=1\nXM12 b2 p2 out vss sg13_lv_nmos w=500n l=130n ng=1 m=1\n.ends\nXdut inp inn out vdd 0 ref vbias p1 p1b p2 p2b cmfbsc\n* two non-overlapping phases, 1us period\nVp1 p1 0 dc 0 pulse(0 {VDD} 25n 2.5n 2.5n 447.5n 1u)\nVp1b p1b 0 dc {VDD} pulse({VDD} 0 25n 2.5n 2.5n 447.5n 1u)\nVp2 p2 0 dc 0 pulse(0 {VDD} 525n 2.5n 2.5n 447.5n 1u)\nVp2b p2b 0 dc {VDD} pulse({VDD} 0 525n 2.5n 2.5n 447.5n 1u)\n* the plant: the stage whose common mode the block holds\nIpb pb 0 5u\nXMPB pb pb vdd vdd sg13_lv_pmos w=32u l=4u ng=8 m=1\nXMPP inp pb vdd vdd sg13_lv_pmos w=32u l=4u ng=8 m=2\nXMPN inn pb vdd vdd sg13_lv_pmos w=32u l=4u ng=8 m=2\nXMSP inp ctl 0 0 sg13_lv_nmos w=4u l=1u ng=1 m=2\nXMSN inn ctl 0 0 sg13_lv_nmos w=4u l=1u ng=1 m=2\nCpp inp 0 2p\nCpn inn 0 2p\n* the loop joined where the block's output meets the plant\nVbrk ctl out 0\n.ic v(out)=0.3 v(inp)=700m v(inn)=700m\n.tran 5n 50u\n.end" } ], "measurements": { "slope": { "label": "Slope at the reference", "unit": "V/V", "spec": { "min": 0.95, "max": 1.05 } }, "bal_err": { "label": "Output at balance less vbias", "unit": "V", "spec": { "min": -0.005, "max": 0.005 } }, "settle_clk": { "label": "Settling, 1 %", "unit": "cycles", "spec": { "min": null, "max": 15 } }, "ripple": { "label": "Clock ripple on the output", "unit": "V", "spec": { "min": null, "max": 0.005 } }, "cm_err": { "label": "Held common mode less its reference", "unit": "V", "spec": { "min": -0.01, "max": 0.01 } }, "cm_ripple": { "label": "Clock ripple on the common mode", "unit": "V", "spec": { "min": null, "max": 0.002 } }, "t_hold": { "label": "Settling to 1 mV", "unit": "s", "spec": { "min": null, "max": 0.00002 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "ac3c4a49e979393aa505630bfa36f583b1bd00fe357e16f9ba86e23588ea4bba" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/cmfb-sc.js", "sha256": "eb71f2d4ca266c72f04f82c09340be7ce61eabbd3e818afd72848049e4bea7f8" }, "simulationFingerprints": { "clocked": "9f2d8c6f82b3a3d187def7ad30d2c174289379cd30bc4a3be851653b8e63ab29", "clocked_loop": "82b01275de3152af6df3e3f675b7fe568081d64862bb28f1fc416c15efa9157a" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "a5e09d48773c7d3c566e0075a3de0b4479814c899c6ab4ab3ac1120669b72ad7", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "cmfb-sc", "parameters": { "Ib": 0.000005, "Cc": 5e-13, "Cs": 2.5e-13, "Wsn": 5e-7, "Wsp": 0.000001, "Ls": 1.3e-7, "Wn": 0.000004, "Ln": 0.000001, "Wp": 0.000008, "Lp": 0.000001, "CL": 1e-13, "K": 2, "Cp": 2e-12, "VCM": 0.6 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/cmfb-sc/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "cmfbsc", "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ref", "net": "ref", "kind": "bias" }, { "name": "vbias", "net": "vbias", "kind": "bias" }, { "name": "p1", "net": "p1", "kind": "clock" }, { "name": "p1b", "net": "p1b", "kind": "clock" }, { "name": "p2", "net": "p2", "kind": "clock" }, { "name": "p2b", "net": "p2b", "kind": "clock" } ], "definitions": [], "devices": [ { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=18.204u l=18.204u", "source": "XCC1 inp out cap_cmim w=18.204u l=18.204u", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=18.204u l=18.204u", "source": "XCC2 inn out cap_cmim w=18.204u l=18.204u", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCS1", "displayName": "CS1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=12.857u l=12.857u", "source": "XCS1 a1 b1 cap_cmim w=12.857u l=12.857u", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "b1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCS2", "displayName": "CS2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=12.857u l=12.857u", "source": "XCS2 a2 b2 cap_cmim w=12.857u l=12.857u", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "b2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM1 a1 p1 ref vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "p1" }, { "id": "s", "net": "ref" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XM2 a1 p1b ref vdd sg13_lv_pmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "p1b" }, { "id": "s", "net": "ref" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM3 b1 p1 vbias vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "b1" }, { "id": "g", "net": "p1" }, { "id": "s", "net": "vbias" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM7 a2 p1 ref vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "p1" }, { "id": "s", "net": "ref" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XM8 a2 p1b ref vdd sg13_lv_pmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "p1b" }, { "id": "s", "net": "ref" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM9 b2 p1 vbias vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "b2" }, { "id": "g", "net": "p1" }, { "id": "s", "net": "vbias" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM4 a1 p2 inp vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "p2" }, { "id": "s", "net": "inp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XM5 a1 p2b inp vdd sg13_lv_pmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "p2b" }, { "id": "s", "net": "inp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM6 b1 p2 out vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "b1" }, { "id": "g", "net": "p2" }, { "id": "s", "net": "out" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM10 a2 p2 inn vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "p2" }, { "id": "s", "net": "inn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XM11 a2 p2b inn vdd sg13_lv_pmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "p2b" }, { "id": "s", "net": "inn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM12 b2 p2 out vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "b2" }, { "id": "g", "net": "p2" }, { "id": "s", "net": "out" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "inp", "ground": false, "terminals": [ { "device": "XCC1", "pin": "p" }, { "device": "XM4", "pin": "s" }, { "device": "XM5", "pin": "s" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XCC1", "pin": "n" }, { "device": "XCC2", "pin": "n" }, { "device": "XM6", "pin": "s" }, { "device": "XM12", "pin": "s" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XCC2", "pin": "p" }, { "device": "XM10", "pin": "s" }, { "device": "XM11", "pin": "s" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "a1", "ground": false, "terminals": [ { "device": "XCS1", "pin": "p" }, { "device": "XM1", "pin": "d" }, { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM5", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "b1", "ground": false, "terminals": [ { "device": "XCS1", "pin": "n" }, { "device": "XM3", "pin": "d" }, { "device": "XM6", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "a2", "ground": false, "terminals": [ { "device": "XCS2", "pin": "p" }, { "device": "XM7", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XM11", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "b2", "ground": false, "terminals": [ { "device": "XCS2", "pin": "n" }, { "device": "XM9", "pin": "d" }, { "device": "XM12", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "p1", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM7", "pin": "g" }, { "device": "XM9", "pin": "g" } ], "ports": [ "p1" ], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" }, { "device": "XM7", "pin": "s" }, { "device": "XM8", "pin": "s" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM1", "pin": "b" }, { "device": "XM3", "pin": "b" }, { "device": "XM7", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM4", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM10", "pin": "b" }, { "device": "XM12", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "p1b", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [ "p1b" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XM2", "pin": "b" }, { "device": "XM8", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM11", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbias", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM9", "pin": "s" } ], "ports": [ "vbias" ], "voltageReferences": [] }, { "id": "p2", "ground": false, "terminals": [ { "device": "XM4", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XM10", "pin": "g" }, { "device": "XM12", "pin": "g" } ], "ports": [ "p2" ], "voltageReferences": [] }, { "id": "p2b", "ground": false, "terminals": [ { "device": "XM5", "pin": "g" }, { "device": "XM11", "pin": "g" } ], "ports": [ "p2b" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vref ref 0 dc 600m", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ivb", "displayName": "Ivb", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ivb vdd dvb 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "dvb" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "XMVB", "displayName": "MVB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMVB dvb vbias 0 0 sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "dvb" }, { "id": "g", "net": "vbias" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMVF", "displayName": "MVF", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMVF vdd dvb vbias 0 sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vdd" }, { "id": "g", "net": "dvb" }, { "id": "s", "net": "vbias" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "Ivf", "displayName": "Ivf", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ivf vbias 0 5u", "pins": [ { "id": "p", "net": "vbias" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "cmfbsc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ref vbias p1 p1b p2 p2b cmfbsc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ref", "net": "ref" }, { "id": "vbias", "net": "vbias" }, { "id": "p1", "net": "p1" }, { "id": "p1b", "net": "p1b" }, { "id": "p2", "net": "p2" }, { "id": "p2b", "net": "p2b" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/cmfbsc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "100f", "source": "Cl out 0 100f", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vp1", "displayName": "Vp1", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 pulse(0 {VDD} 25n 2.5n 2.5n 447.5n 1u)", "source": "Vp1 p1 0 dc 0 pulse(0 {VDD} 25n 2.5n 2.5n 447.5n 1u)", "pins": [ { "id": "p", "net": "p1" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vp1b", "displayName": "Vp1b", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD} pulse({VDD} 0 25n 2.5n 2.5n 447.5n 1u)", "source": "Vp1b p1b 0 dc {VDD} pulse({VDD} 0 25n 2.5n 2.5n 447.5n 1u)", "pins": [ { "id": "p", "net": "p1b" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vp2", "displayName": "Vp2", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 pulse(0 {VDD} 525n 2.5n 2.5n 447.5n 1u)", "source": "Vp2 p2 0 dc 0 pulse(0 {VDD} 525n 2.5n 2.5n 447.5n 1u)", "pins": [ { "id": "p", "net": "p2" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vp2b", "displayName": "Vp2b", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD} pulse({VDD} 0 525n 2.5n 2.5n 447.5n 1u)", "source": "Vp2b p2b 0 dc {VDD} pulse({VDD} 0 525n 2.5n 2.5n 447.5n 1u)", "pins": [ { "id": "p", "net": "p2b" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vcm", "displayName": "Vcm", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m pulse(600m 650m 25u 2.5n 2.5n 100u 200u)", "source": "Vcm cm 0 dc 600m pulse(600m 650m 25u 2.5n 2.5n 100u 200u)", "pins": [ { "id": "p", "net": "cm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vd", "displayName": "Vd", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vd vd 0 dc 0", "pins": [ { "id": "p", "net": "vd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ep", "displayName": "Ep", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Ep inp cm vd 0 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "cm" }, { "id": "cp", "net": "vd" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "En", "displayName": "En", "spiceType": "E", "model": null, "parametersOrValue": "-0.5", "source": "En inn cm vd 0 -0.5", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "cm" }, { "id": "cp", "net": "vd" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ivb", "pin": "p" }, { "device": "XMVF", "pin": "d" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "XMVB", "pin": "s" }, { "device": "XMVB", "pin": "b" }, { "device": "XMVF", "pin": "b" }, { "device": "Ivf", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vp1", "pin": "n" }, { "device": "Vp1b", "pin": "n" }, { "device": "Vp2", "pin": "n" }, { "device": "Vp2b", "pin": "n" }, { "device": "Vcm", "pin": "n" }, { "device": "Vd", "pin": "n" }, { "device": "Ep", "pin": "cn" }, { "device": "En", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "dvb", "ground": false, "terminals": [ { "device": "Ivb", "pin": "n" }, { "device": "XMVB", "pin": "d" }, { "device": "XMVF", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbias", "ground": false, "terminals": [ { "device": "XMVB", "pin": "g" }, { "device": "XMVF", "pin": "s" }, { "device": "Ivf", "pin": "p" }, { "device": "Xdut", "pin": "vbias" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Ep", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "En", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "p1", "ground": false, "terminals": [ { "device": "Xdut", "pin": "p1" }, { "device": "Vp1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "p1b", "ground": false, "terminals": [ { "device": "Xdut", "pin": "p1b" }, { "device": "Vp1b", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "p2", "ground": false, "terminals": [ { "device": "Xdut", "pin": "p2" }, { "device": "Vp2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "p2b", "ground": false, "terminals": [ { "device": "Xdut", "pin": "p2b" }, { "device": "Vp2b", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cm", "ground": false, "terminals": [ { "device": "Vcm", "pin": "p" }, { "device": "Ep", "pin": "n" }, { "device": "En", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vd", "ground": false, "terminals": [ { "device": "Vd", "pin": "p" }, { "device": "Ep", "pin": "cp" }, { "device": "En", "pin": "cp" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/cmfbsc", "name": "cmfbsc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ref", "net": "ref" }, { "name": "vbias", "net": "vbias" }, { "name": "p1", "net": "p1" }, { "name": "p1b", "net": "p1b" }, { "name": "p2", "net": "p2" }, { "name": "p2b", "net": "p2b" } ], "definitions": [], "devices": [ { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=18.204u l=18.204u", "source": "XCC1 inp out cap_cmim w=18.204u l=18.204u", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=18.204u l=18.204u", "source": "XCC2 inn out cap_cmim w=18.204u l=18.204u", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCS1", "displayName": "CS1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=12.857u l=12.857u", "source": "XCS1 a1 b1 cap_cmim w=12.857u l=12.857u", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "b1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCS2", "displayName": "CS2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=12.857u l=12.857u", "source": "XCS2 a2 b2 cap_cmim w=12.857u l=12.857u", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "b2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM1 a1 p1 ref vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "p1" }, { "id": "s", "net": "ref" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XM2 a1 p1b ref vdd sg13_lv_pmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "p1b" }, { "id": "s", "net": "ref" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM3 b1 p1 vbias vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "b1" }, { "id": "g", "net": "p1" }, { "id": "s", "net": "vbias" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM7 a2 p1 ref vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "p1" }, { "id": "s", "net": "ref" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XM8 a2 p1b ref vdd sg13_lv_pmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "p1b" }, { "id": "s", "net": "ref" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM9 b2 p1 vbias vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "b2" }, { "id": "g", "net": "p1" }, { "id": "s", "net": "vbias" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM4 a1 p2 inp vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "p2" }, { "id": "s", "net": "inp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XM5 a1 p2b inp vdd sg13_lv_pmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "p2b" }, { "id": "s", "net": "inp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM6 b1 p2 out vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "b1" }, { "id": "g", "net": "p2" }, { "id": "s", "net": "out" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM10 a2 p2 inn vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "p2" }, { "id": "s", "net": "inn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XM11 a2 p2b inn vdd sg13_lv_pmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "p2b" }, { "id": "s", "net": "inn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM12 b2 p2 out vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "b2" }, { "id": "g", "net": "p2" }, { "id": "s", "net": "out" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "inp", "ground": false, "terminals": [ { "device": "XCC1", "pin": "p" }, { "device": "XM4", "pin": "s" }, { "device": "XM5", "pin": "s" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XCC1", "pin": "n" }, { "device": "XCC2", "pin": "n" }, { "device": "XM6", "pin": "s" }, { "device": "XM12", "pin": "s" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XCC2", "pin": "p" }, { "device": "XM10", "pin": "s" }, { "device": "XM11", "pin": "s" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "a1", "ground": false, "terminals": [ { "device": "XCS1", "pin": "p" }, { "device": "XM1", "pin": "d" }, { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM5", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "b1", "ground": false, "terminals": [ { "device": "XCS1", "pin": "n" }, { "device": "XM3", "pin": "d" }, { "device": "XM6", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "a2", "ground": false, "terminals": [ { "device": "XCS2", "pin": "p" }, { "device": "XM7", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XM11", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "b2", "ground": false, "terminals": [ { "device": "XCS2", "pin": "n" }, { "device": "XM9", "pin": "d" }, { "device": "XM12", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "p1", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM7", "pin": "g" }, { "device": "XM9", "pin": "g" } ], "ports": [ "p1" ], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" }, { "device": "XM7", "pin": "s" }, { "device": "XM8", "pin": "s" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM1", "pin": "b" }, { "device": "XM3", "pin": "b" }, { "device": "XM7", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM4", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM10", "pin": "b" }, { "device": "XM12", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "p1b", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [ "p1b" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XM2", "pin": "b" }, { "device": "XM8", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM11", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbias", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM9", "pin": "s" } ], "ports": [ "vbias" ], "voltageReferences": [] }, { "id": "p2", "ground": false, "terminals": [ { "device": "XM4", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XM10", "pin": "g" }, { "device": "XM12", "pin": "g" } ], "ports": [ "p2" ], "voltageReferences": [] }, { "id": "p2b", "ground": false, "terminals": [ { "device": "XM5", "pin": "g" }, { "device": "XM11", "pin": "g" } ], "ports": [ "p2b" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/cmfbsc" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Sensing capacitor", "devices": [ { "scope": "dut", "device": "XCC1" }, { "scope": "dut", "device": "XCC2" } ], "inferredStages": [ 1 ] }, { "id": "block-2", "label": "Switched capacitor", "devices": [ { "scope": "dut", "device": "XCS1" }, { "scope": "dut", "device": "XCS2" } ], "inferredStages": [ 1 ] }, { "id": "block-3", "label": "Phase 1: CS1 to ref", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 1 ] }, { "id": "block-4", "label": "Phase 1: CS1 to vbias", "devices": [ { "scope": "dut", "device": "XM3" } ], "inferredStages": [ "bias" ] }, { "id": "block-5", "label": "Phase 2: CS1 to inp", "devices": [ { "scope": "dut", "device": "XM4" }, { "scope": "dut", "device": "XM5" } ], "inferredStages": [ 1 ] }, { "id": "block-6", "label": "Phase 2: CS1 to out", "devices": [ { "scope": "dut", "device": "XM6" } ], "inferredStages": [ "bias" ] }, { "id": "block-7", "label": "Phase 1: CS2 to ref", "devices": [ { "scope": "dut", "device": "XM7" }, { "scope": "dut", "device": "XM8" } ], "inferredStages": [ 1 ] }, { "id": "block-8", "label": "Phase 1: CS2 to vbias", "devices": [ { "scope": "dut", "device": "XM9" } ], "inferredStages": [ "bias" ] }, { "id": "block-9", "label": "Phase 2: CS2 to inn", "devices": [ { "scope": "dut", "device": "XM10" }, { "scope": "dut", "device": "XM11" } ], "inferredStages": [ 1 ] }, { "id": "block-10", "label": "Phase 2: CS2 to out", "devices": [ { "scope": "dut", "device": "XM12" } ], "inferredStages": [ "bias" ] } ], "edges": [ { "id": "net-1", "net": "inp", "nodes": [ "block-1", "block-5" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "out", "nodes": [ "block-1", "block-6", "block-10" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "inn", "nodes": [ "block-1", "block-9" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "a1", "nodes": [ "block-2", "block-3", "block-5" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "b1", "nodes": [ "block-2", "block-4", "block-6" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "a2", "nodes": [ "block-2", "block-7", "block-9" ], "direction": "undirected-shared-net" }, { "id": "net-7", "net": "b2", "nodes": [ "block-2", "block-8", "block-10" ], "direction": "undirected-shared-net" }, { "id": "net-8", "net": "p1", "nodes": [ "block-3", "block-4", "block-7", "block-8" ], "direction": "undirected-shared-net" }, { "id": "net-9", "net": "ref", "nodes": [ "block-3", "block-7" ], "direction": "undirected-shared-net" }, { "id": "net-10", "net": "p1b", "nodes": [ "block-3", "block-7" ], "direction": "undirected-shared-net" }, { "id": "net-11", "net": "vbias", "nodes": [ "block-4", "block-8" ], "direction": "undirected-shared-net" }, { "id": "net-12", "net": "p2", "nodes": [ "block-5", "block-6", "block-9", "block-10" ], "direction": "undirected-shared-net" }, { "id": "net-13", "net": "p2b", "nodes": [ "block-5", "block-9" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ref", "net": "ref", "kind": "bias" }, { "name": "vbias", "net": "vbias", "kind": "bias" }, { "name": "p1", "net": "p1", "kind": "clock" }, { "name": "p1b", "net": "p1b", "kind": "clock" }, { "name": "p2", "net": "p2", "kind": "clock" }, { "name": "p2b", "net": "p2b", "kind": "clock" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vref ref 0 dc 600m", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ivb", "displayName": "Ivb", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ivb vdd dvb 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "dvb" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "XMVB", "displayName": "MVB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMVB dvb vbias 0 0 sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "dvb" }, { "id": "g", "net": "vbias" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMVF", "displayName": "MVF", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMVF vdd dvb vbias 0 sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vdd" }, { "id": "g", "net": "dvb" }, { "id": "s", "net": "vbias" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "Ivf", "displayName": "Ivf", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ivf vbias 0 5u", "pins": [ { "id": "p", "net": "vbias" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "cmfbsc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ref vbias p1 p1b p2 p2b cmfbsc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ref", "net": "ref" }, { "id": "vbias", "net": "vbias" }, { "id": "p1", "net": "p1" }, { "id": "p1b", "net": "p1b" }, { "id": "p2", "net": "p2" }, { "id": "p2b", "net": "p2b" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/cmfbsc" }, { "id": "Vp1", "displayName": "Vp1", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 pulse(0 {VDD} 25n 2.5n 2.5n 447.5n 1u)", "source": "Vp1 p1 0 dc 0 pulse(0 {VDD} 25n 2.5n 2.5n 447.5n 1u)", "pins": [ { "id": "p", "net": "p1" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vp1b", "displayName": "Vp1b", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD} pulse({VDD} 0 25n 2.5n 2.5n 447.5n 1u)", "source": "Vp1b p1b 0 dc {VDD} pulse({VDD} 0 25n 2.5n 2.5n 447.5n 1u)", "pins": [ { "id": "p", "net": "p1b" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vp2", "displayName": "Vp2", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 pulse(0 {VDD} 525n 2.5n 2.5n 447.5n 1u)", "source": "Vp2 p2 0 dc 0 pulse(0 {VDD} 525n 2.5n 2.5n 447.5n 1u)", "pins": [ { "id": "p", "net": "p2" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vp2b", "displayName": "Vp2b", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD} pulse({VDD} 0 525n 2.5n 2.5n 447.5n 1u)", "source": "Vp2b p2b 0 dc {VDD} pulse({VDD} 0 525n 2.5n 2.5n 447.5n 1u)", "pins": [ { "id": "p", "net": "p2b" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ipb", "displayName": "Ipb", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ipb pb 0 5u", "pins": [ { "id": "p", "net": "pb" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "XMPB", "displayName": "MPB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=32u l=4u ng=8 m=1", "source": "XMPB pb pb vdd vdd sg13_lv_pmos w=32u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "pb" }, { "id": "g", "net": "pb" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMPP", "displayName": "MPP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=32u l=4u ng=8 m=2", "source": "XMPP inp pb vdd vdd sg13_lv_pmos w=32u l=4u ng=8 m=2", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "pb" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMPN", "displayName": "MPN", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=32u l=4u ng=8 m=2", "source": "XMPN inn pb vdd vdd sg13_lv_pmos w=32u l=4u ng=8 m=2", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "pb" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSP", "displayName": "MSP", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMSP inp ctl 0 0 sg13_lv_nmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "ctl" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSN", "displayName": "MSN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMSN inn ctl 0 0 sg13_lv_nmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "ctl" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "Cpp", "displayName": "Cpp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cpp inp 0 2p", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cpn", "displayName": "Cpn", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cpn inn 0 2p", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk", "displayName": "Vbrk", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk ctl out 0", "pins": [ { "id": "p", "net": "ctl" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ivb", "pin": "p" }, { "device": "XMVF", "pin": "d" }, { "device": "Xdut", "pin": "vdd" }, { "device": "XMPB", "pin": "s" }, { "device": "XMPB", "pin": "b" }, { "device": "XMPP", "pin": "s" }, { "device": "XMPP", "pin": "b" }, { "device": "XMPN", "pin": "s" }, { "device": "XMPN", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "XMVB", "pin": "s" }, { "device": "XMVB", "pin": "b" }, { "device": "XMVF", "pin": "b" }, { "device": "Ivf", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Vp1", "pin": "n" }, { "device": "Vp1b", "pin": "n" }, { "device": "Vp2", "pin": "n" }, { "device": "Vp2b", "pin": "n" }, { "device": "Ipb", "pin": "n" }, { "device": "XMSP", "pin": "s" }, { "device": "XMSP", "pin": "b" }, { "device": "XMSN", "pin": "s" }, { "device": "XMSN", "pin": "b" }, { "device": "Cpp", "pin": "n" }, { "device": "Cpn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "dvb", "ground": false, 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