{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "comparator-hysteresis", "name": "Comparator with hysteresis", "group": "Comparators", "subgroup": "Continuous-time", "title": "Comparator with hysteresis", "summary": "This comparator uses different thresholds for rising and falling inputs. Feedback reinforces the current output state, so small input fluctuations do not repeatedly switch it. A wider threshold gap rejects more noise but requires a larger input change to reverse the output.", "reference": { "kind": "book", "authors": "P. E. Allen, D. R. Holberg", "title": "CMOS Analog Circuit Design", "edition": "2nd ed.", "publisher": "Oxford University Press", "year": 2002, "where": "Ch. 8 'Comparators' (Secs. 8.1 Characterization, 8.2 Two-Stage Open-Loop Comparators, 8.4 Improving the Performance of Open-Loop Comparators)", "takes": "The comparator's characterization - thresholds, hysteresis, propagation delay against overdrive - and its structure: a differential pair on a current-mirror load, gain stages to a logic swing, and positive feedback that splits one threshold into two. The feedback through output-switched resistors into the first stage's output, the bias and the sizing are this library's, for SG13G2 at 1.2 V." }, "resources": { "record": "/circuits/comparator-hysteresis.json", "page": "/index.html#comparator-hysteresis", "achieved": "/achieved/comparator-hysteresis.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "inp", "kind": "input", "polarity": "+" }, { "name": "inn", "kind": "input", "polarity": "-" }, { "name": "out", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the reference current, fed into this pin" } ], "devices": [ { "name": "MB", "type": "nmos", "nodes": "ib ib vss vss", "sizedBy": [ "Wt", "Lt" ], "role": "bias reference, diode-connected", "fingers": 2, "copies": 1 }, { "name": "MT", "type": "nmos", "nodes": "tail ib vss vss", "sizedBy": [ "Wt", "Lt", "N" ], "role": "tail current source, N copies of MB", "fingers": 2, "copies": 2 }, { "name": "M1", "type": "nmos", "nodes": "d1 inp tail vss", "sizedBy": [ "W1", "L1" ], "role": "input pair, non-inverting input", "fingers": 2, "copies": 1 }, { "name": "M2", "type": "nmos", "nodes": "d2 inn tail vss", "sizedBy": [ "W1", "L1" ], "role": "input pair, inverting input", "fingers": 2, "copies": 1 }, { "name": "M3", "type": "pmos", "nodes": "d2 d2 vdd vdd", "sizedBy": [ "W3", "L3" ], "role": "mirror load, diode-connected", "fingers": 1, "copies": 1 }, { "name": "M4", "type": "pmos", "nodes": "d1 d2 vdd vdd", "sizedBy": [ "W3", "L3" ], "role": "mirror load, onto d1", "fingers": 1, "copies": 1 }, { "name": "M5", "type": "nmos", "nodes": "a1 d1 vss vss", "sizedBy": [ "Wn", "Li" ], "role": "first inverter", "fingers": 1, "copies": 1 }, { "name": "M6", "type": "pmos", "nodes": "a1 d1 vdd vdd", "sizedBy": [ "Wp", "Li" ], "role": "first inverter", "fingers": 1, "copies": 1 }, { "name": "M7", "type": "nmos", "nodes": "a2 a1 vss vss", "sizedBy": [ "Wn", "Li", "F" ], "role": "second inverter, F copies", "fingers": 1, "copies": 3 }, { "name": "M8", "type": "pmos", "nodes": "a2 a1 vdd vdd", "sizedBy": [ "Wp", "Li", "F" ], "role": "second inverter, F copies", "fingers": 1, "copies": 3 }, { "name": "M9", "type": "nmos", "nodes": "out a2 vss vss", "sizedBy": [ "Wn", "Li", "F" ], "role": "output inverter, F² copies", "fingers": 1, "copies": 9 }, { "name": "M10", "type": "pmos", "nodes": "out a2 vdd vdd", "sizedBy": [ "Wp", "Li", "F" ], "role": "output inverter, F² copies", "fingers": 1, "copies": 9 }, { "name": "RH1", "type": "resistor", "nodes": "d1 h1", "sizedBy": [ "RH" ], "role": "hysteresis, sinking" }, { "name": "M11", "type": "nmos", "nodes": "h1 out vss vss", "sizedBy": [ "Ws", "Li" ], "role": "hysteresis switch, on with the output high", "fingers": 1, "copies": 1 }, { "name": "RH2", "type": "resistor", "nodes": "h2 d1", "sizedBy": [ "RH" ], "role": "hysteresis, sourcing" }, { "name": "M12", "type": "pmos", "nodes": "h2 out vdd vdd", "sizedBy": [ "Ws", "Li" ], "role": "hysteresis switch, on with the output low; two copies", "fingers": 1, "copies": 2 } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "The input pair: its mismatch is the comparator's offset, on top of whatever the hysteresis is centred on." }, { "rule": "match", "of": [ "M3", "M4" ], "why": "The mirror: a copy error lands on d1 as a current the pair must cancel, and shifts both thresholds the same way." }, { "rule": "match", "of": [ "RH1", "RH2" ], "why": "The two feedback resistors set the two thresholds; unequal, the hysteresis is not centred on the offset." }, { "rule": "unit-copies", "of": [ "MB", "MT" ], "constraint": "MT = N copies of MB", "why": "The tail is a copy of the reference, not a resistor: the pair's g_m, and with it the hysteresis, does not move with the input common mode." }, { "rule": "hysteresis", "of": [ "RH1", "RH2", "M1", "M2" ], "constraint": "V_hyst ≈ V_DD/(g_m1 R_H)", "why": "To turn the output over, the pair's current g_m1·V_id must cancel what the switched resistor feeds into d1, V_DD - V_M or V_M over R_H: the two add to V_DD/R_H across the two thresholds." }, { "rule": "centring", "of": [ "M3", "M5", "M6" ], "constraint": "V_SG,3 = V_DD - V_M,1 = V_DD/2", "why": "At balance d1 sits at the mirror's gate, V_DD - V_SG,3; the first inverter turns at V_M,1. With both at mid-supply the two thresholds sit symmetrically either side of zero." }, { "rule": "taper", "of": [ "M5", "M7", "M9" ], "constraint": "each inverter F times the last", "why": "A small first inverter loads d1 lightly; each stage then drives the next F times larger, the fastest way to the load." } ], "specs": [ { "key": "v_hyst", "label": "Hysteresis", "unit": "V", "direction": "target", "constraint": ">= 0.01 V, <= 0.04 V", "min": 0.01, "max": 0.04, "why": "About 20 mV at tt, V_DD/(g_m1 R_H): enough to ignore tens of millivolts of noise on a slow input. It widens when hot, where both g_m1 and the high-resistance poly fall, and narrows when cold; it stays inside this window at every corner." }, { "key": "vos", "label": "Offset", "unit": "V", "direction": "target", "constraint": ">= -0.01 V, <= 0.01 V", "min": -0.01, "max": 0.01, "why": "The midpoint of the two thresholds. Centred at tt by the mirror's V_SG; it moves with the supply, because d1 balances at V_DD - V_SG3 while the first inverter turns at about V_DD/2, and mismatch adds 2 to 3 mV σ." }, { "key": "t_dec", "label": "Decision time", "unit": "s", "direction": "min", "constraint": "<= 1e-8 s", "min": null, "max": 1e-8, "why": "10 mV past a threshold, into 20 fF: g_m1 times the overdrive, less what the feedback holds against it, must move d1 to the first inverter's threshold." }, { "key": "t_dec_small", "label": "Decision time, smallest overdrive", "unit": "s", "direction": "min", "constraint": "<= 2.5e-8 s", "min": null, "max": 2.5e-8, "why": "1 mV past a threshold: the current left to move d1 is a tenth, and the decision about twice as slow - the feedback, once the output starts to turn, finishes it." }, { "key": "v_band", "label": "Transition width, 10-90 %", "unit": "V", "direction": "min", "constraint": "<= 0.001 V", "min": null, "max": 0.001, "why": "The positive feedback makes the output snap: once it starts to turn it completes, so no input holds it between the logic levels." }, { "key": "voh", "label": "Output high level", "unit": "V", "direction": "max", "constraint": ">= 1.05 V", "min": 1.05, "max": null, "why": "A logic level at every supply the corners take it to." }, { "key": "vol", "label": "Output low level", "unit": "V", "direction": "min", "constraint": "<= 0.05 V", "min": null, "max": 0.05, "why": "And ground." }, { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.00004 A", "min": null, "max": 0.00004, "why": "(N + 1)·Ib, the reference and the tail; the inverters draw only while the output turns." } ], "explanation": { "idea": "This comparator uses different thresholds for rising and falling inputs. Feedback reinforces the current output state, so small input fluctuations do not repeatedly switch it. A wider threshold gap rejects more noise but requires a larger input change to reverse the output.", "detail": "A continuous-time comparator with two thresholds. Once its output has turned, it feeds a current back into its first stage that reinforces that state, and it turns back only past the other threshold. A slow or noisy input may cross the pair's balance point repeatedly. The gap between thresholds prevents repeated switching only while those fluctuations are too small to cross both thresholds; larger noise can still make the output chatter.", "lesson": { "relation": 0, "symbols": "V_hyst is the difference between rising and falling input thresholds; V_DD is supply voltage; g_m1 is the input transistor's transconductance, or change in drain current per input-voltage change; R_H is each feedback resistor.", "assumptions": "The estimate treats the pair transconductance as constant near switching, neglects feedback-switch resistance and assumes roughly symmetric thresholds. Input headroom and device mismatch can change the thresholds.", "exercise": { "param": "RH", "value": 600000, "analysis": "sweep", "expect": "Doubling both feedback resistors should weaken the feedback and narrow the gap between rising and falling thresholds. Compare the two sweep directions and their midpoint." }, "limits": "Supply the reference current externally and keep the input common mode in the amplifier's usable range. Hysteresis suppresses small fluctuations, not arbitrarily large noise. Thresholds, offset and decision delay change with conditions and load." }, "path": [ { "part": "Input pair", "devices": "M1, M2, MT", "does": "MT's tail current divides between M1, on inp, and M2, on inn: inp rising past inn takes current from M2." }, { "part": "Mirror load", "devices": "M3, M4", "does": "M3 turns M2's current into a gate voltage and M4 copies it onto d1, where M1's current meets it: d1 falls as inp rises past inn." }, { "part": "Inverter chain", "devices": "M5, M6, M7, M8, M9, M10", "does": "Three inverters, each F times the last, turn d1's swing into a full logic swing at out, high when inp wins." }, { "part": "Hysteresis", "devices": "M11, RH1, M12, RH2", "does": "With out high M11 connects RH1 from d1 to ground and sinks current; with out low M12 connects RH2 from vdd and feeds it: either way the present state is reinforced." } ], "bias": "Ib, 10 µA, is fed into the diode MB, and the tail MT, two copies, gives the pair approximately 20 µA. A current-source tail reduces the dependence of g_m1 and hysteresis on input common mode while the source remains saturated; it does not remove headroom or mismatch errors. With the inputs at 0.6 V the tail node sits near 0.30 V. M3 is sized to balance d1 near mid-supply, where the first inverter turns: the nominal thresholds are about +10 and −10 mV, with about 30 µA supply current.", "relations": [ { "what": "Hysteresis", "expr": "V_hyst ≈ V_DD/(g_m1 R_H)", "note": "R_H = RH1 = RH2: the pair must cancel (V_DD − V_M,1)/R_H at one threshold and V_M,1/R_H at the other; about 20 mV at tt" }, { "what": "Thresholds", "expr": "V_T+ ≈ (V_DD − V_M,1)/(g_m1 R_H), V_T− ≈ −V_M,1/(g_m1 R_H)", "note": "symmetric about zero when the first inverter turns at V_DD/2" }, { "what": "Systematic offset", "expr": "V_os ≈ (V_DD − V_SG3 − V_M,1)/A_1, A_1 = g_m1 (r_o1 ∥ r_o4 ∥ R_H)", "note": "zero at tt by the size of M3; the supply moves d1's balance twice as fast as V_M,1, about ±4 mV per 10 % of V_DD" }, { "what": "Decision time", "expr": "t_d ≈ C_d1 ΔV_d1/(g_m1 V_od)", "note": "V_od past the threshold; once the output starts to turn, the feedback completes it" }, { "what": "Temperature", "expr": "V_hyst ∝ T/R_H(T)", "note": "g_m1 falls as 1/T in weak inversion, and the high-resistance poly falls too: the hysteresis grows by half from 27 °C to 125 °C" } ], "tradeoffs": [ "Hysteresis resistors (RH): smaller widens the hysteresis, V_DD/(g_m1 R_H), and rejects more noise, but needs more overdrive to turn the output and draws more current through the switches.", "Tail current (N): more raises g_m1, which narrows the hysteresis for the same RH and speeds the decision, at more supply current.", "Mirror width (W3): sets d1's balance, and so centres the thresholds - at one supply only, since the balance follows V_DD one for one and the inverter's threshold half as fast.", "Input pair (W1, L1): larger lowers the random offset, 2 to 3 mV σ, but adds capacitance at d1 and slows every decision." ] }, "sizing": [ { "key": "Ib", "label": "Reference current", "unit": "A", "value": 0.00001, "min": 0.000001, "max": 0.00005, "kind": "si" }, { "key": "N", "label": "Tail current, in Ib", "unit": "", "value": 2, "min": 1, "max": 8, "kind": "int" }, { "key": "Wt", "label": "W tail unit (MB, MT)", "unit": "m", "value": 0.000008, "min": 5e-7, "max": 0.00002, "kind": "si" }, { "key": "Lt", "label": "L tail unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "W1", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.00001, "min": 5e-7, "max": 0.00005, "kind": "si" }, { "key": "L1", "label": "L input pair", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "W3", "label": "W mirror (M3, M4)", "unit": "m", "value": 0.000004, "min": 3e-7, "max": 0.00002, "kind": "si" }, { "key": "L3", "label": "L mirror", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wn", "label": "W inverter NMOS unit (M5, M7, M9)", "unit": "m", "value": 5e-7, "min": 1.5e-7, "max": 0.000005, "kind": "si" }, { "key": "Wp", "label": "W inverter PMOS unit (M6, M8, M10)", "unit": "m", "value": 7e-7, "min": 1.5e-7, "max": 0.00001, "kind": "si" }, { "key": "Li", "label": "L inverters and switches", "unit": "m", "value": 1.3e-7, "min": 1.3e-7, "max": 0.000001, "kind": "si" }, { "key": "F", "label": "Inverter taper", "unit": "", "value": 3, "min": 1, "max": 6, "kind": "int" }, { "key": "Ws", "label": "W hysteresis switch unit (M11; M12 two copies)", "unit": "m", "value": 5e-7, "min": 1.5e-7, "max": 0.000005, "kind": "si" }, { "key": "RH", "label": "Hysteresis resistors", "unit": "Ω", "value": 300000, "min": 20000, "max": 2000000, "kind": "si" }, { "key": "CL", "label": "Load capacitance", "unit": "F", "value": 2e-14, "min": 1e-15, "max": 1e-12, "kind": "si" }, { "key": "VCM", "label": "Input common mode", "unit": "V", "value": 0.6, "min": 0.5, "max": 1, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Decided states", "note": "The comparator with its input well past its thresholds, each way: the output levels and the current it draws in each state.", "measures": [], "metricKeys": [ "voh", "vol", "i_supply" ], "acceptance": [ "voh", "vol", "i_supply" ], "acceptanceRules": [ { "key": "voh", "unit": "V", "min": 1.05, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "vol", "unit": "V", "min": null, "max": 0.05, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "i_supply", "unit": "A", "min": null, "max": 0.00004, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Comparator with hysteresis - decided states\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb vdd ib dc 10u\n.subckt cmph inp inn out vdd vss ib\n* bias: Ib into the diode MB; the tail MT, N copies\nXMB ib ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXMT tail ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=2\n* the pair on its mirror: d1 falls as inp rises past inn\nXM1 d1 inp tail vss sg13_lv_nmos w=10u l=500n ng=2 m=1\nXM2 d2 inn tail vss sg13_lv_nmos w=10u l=500n ng=2 m=1\nXM3 d2 d2 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\nXM4 d1 d2 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\n* three inverters, each F times the last: out is high when d1 is low\nXM5 a1 d1 vss vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXM6 a1 d1 vdd vdd sg13_lv_pmos w=700n l=130n ng=1 m=1\nXM7 a2 a1 vss vss sg13_lv_nmos w=500n l=130n ng=1 m=3\nXM8 a2 a1 vdd vdd sg13_lv_pmos w=700n l=130n ng=1 m=3\nXM9 out a2 vss vss sg13_lv_nmos w=500n l=130n ng=1 m=9\nXM10 out a2 vdd vdd sg13_lv_pmos w=700n l=130n ng=1 m=9\n* the output holds its state: high, it sinks current from d1; low, it feeds it in\nXRH1 d1 h1 vss rhigh w=0.5u l=92.548u\nXM11 h1 out vss vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXRH2 h2 d1 vss rhigh w=0.5u l=92.548u\nXM12 h2 out vdd vdd sg13_lv_pmos w=500n l=130n ng=1 m=2\n.ends\nXdut inp inn out vdd 0 ib cmph\nCl out 0 20f\nVcm cm 0 dc 600m\nVid id 0 dc 100m\n* the differential input split evenly either side of the common mode\nEinp inp cm id 0 0.5\nEinn inn cm id 0 -0.5\n* two points: V_id 100mV below its nominal threshold, and 100mV above\n.dc Vid -100m 100m 200m\n.end" }, { "id": "sweep", "label": "Thresholds", "note": "V_id swept slowly across its thresholds, up and back down: where the output flips each way, the hysteresis between them, and the offset at their midpoint.", "measures": [], "metricKeys": [ "vtrip_hi", "vtrip_lo", "v_hyst", "vos", "v_band" ], "acceptance": [ "v_hyst", "vos", "v_band" ], "acceptanceRules": [ { "key": "v_hyst", "unit": "V", "min": 0.01, "max": 0.04, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "vos", "unit": "V", "min": -0.01, "max": 0.01, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "v_band", "unit": "V", "min": null, "max": 0.001, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Comparator with hysteresis - thresholds, V_id swept slowly up and back down\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb vdd ib dc 10u\n.subckt cmph inp inn out vdd vss ib\n* bias: Ib into the diode MB; the tail MT, N copies\nXMB ib ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXMT tail ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=2\n* the pair on its mirror: d1 falls as inp rises past inn\nXM1 d1 inp tail vss sg13_lv_nmos w=10u l=500n ng=2 m=1\nXM2 d2 inn tail vss sg13_lv_nmos w=10u l=500n ng=2 m=1\nXM3 d2 d2 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\nXM4 d1 d2 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\n* three inverters, each F times the last: out is high when d1 is low\nXM5 a1 d1 vss vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXM6 a1 d1 vdd vdd sg13_lv_pmos w=700n l=130n ng=1 m=1\nXM7 a2 a1 vss vss sg13_lv_nmos w=500n l=130n ng=1 m=3\nXM8 a2 a1 vdd vdd sg13_lv_pmos w=700n l=130n ng=1 m=3\nXM9 out a2 vss vss sg13_lv_nmos w=500n l=130n ng=1 m=9\nXM10 out a2 vdd vdd sg13_lv_pmos w=700n l=130n ng=1 m=9\n* the output holds its state: high, it sinks current from d1; low, it feeds it in\nXRH1 d1 h1 vss rhigh w=0.5u l=92.548u\nXM11 h1 out vss vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXRH2 h2 d1 vss rhigh w=0.5u l=92.548u\nXM12 h2 out vdd vdd sg13_lv_pmos w=500n l=130n ng=1 m=2\n.ends\nXdut inp inn out vdd 0 ib cmph\nCl out 0 20f\nVcm cm 0 dc 600m\nVid id 0 pwl(0 -60m 40u 60m 80u -60m)\n* the differential input split evenly either side of the common mode\nEinp inp cm id 0 0.5\nEinn inn cm id 0 -0.5\n.tran 20n 80u\n.end" }, { "id": "delay", "label": "Decision time", "note": "The thresholds found first; then, for each overdrive from 1 mV to 50 mV, a step past each of them from 100 mV the other side, timed to the output at half the supply. 7 runs.", "measures": [], "metricKeys": [ "t_dec", "t_dec_small" ], "acceptance": [ "t_dec", "t_dec_small" ], "acceptanceRules": [ { "key": "t_dec", "unit": "s", "min": null, "max": 1e-8, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "t_dec_small", "unit": "s", "min": null, "max": 2.5e-8, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "seconds": 14, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Comparator with hysteresis - decision time at 10 mV overdrive\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb vdd ib dc 10u\n.subckt cmph inp inn out vdd vss ib\n* bias: Ib into the diode MB; the tail MT, N copies\nXMB ib ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXMT tail ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=2\n* the pair on its mirror: d1 falls as inp rises past inn\nXM1 d1 inp tail vss sg13_lv_nmos w=10u l=500n ng=2 m=1\nXM2 d2 inn tail vss sg13_lv_nmos w=10u l=500n ng=2 m=1\nXM3 d2 d2 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\nXM4 d1 d2 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\n* three inverters, each F times the last: out is high when d1 is low\nXM5 a1 d1 vss vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXM6 a1 d1 vdd vdd sg13_lv_pmos w=700n l=130n ng=1 m=1\nXM7 a2 a1 vss vss sg13_lv_nmos w=500n l=130n ng=1 m=3\nXM8 a2 a1 vdd vdd sg13_lv_pmos w=700n l=130n ng=1 m=3\nXM9 out a2 vss vss sg13_lv_nmos w=500n l=130n ng=1 m=9\nXM10 out a2 vdd vdd sg13_lv_pmos w=700n l=130n ng=1 m=9\n* the output holds its state: high, it sinks current from d1; low, it feeds it in\nXRH1 d1 h1 vss rhigh w=0.5u l=92.548u\nXM11 h1 out vss vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXRH2 h2 d1 vss rhigh w=0.5u l=92.548u\nXM12 h2 out vdd vdd sg13_lv_pmos w=500n l=130n ng=1 m=2\n.ends\nXdut inp inn out vdd 0 ib cmph\nCl out 0 20f\n* 100 mV below the lower threshold, a step to 10 mV past the upper one, then to 10 mV past the lower\nVcm cm 0 dc 600m\nVid id 0 pwl(0 -100m 100n -100m 101n 10m 1.1u 10m 1.101u -10m 2.1u -10m)\n* the differential input split evenly either side of the common mode\nEinp inp cm id 0 0.5\nEinn inn cm id 0 -0.5\n.tran 250p 2.1u\n.end" } ], "measurements": { "v_hyst": { "label": "Hysteresis", "unit": "V", "spec": { "min": 0.01, "max": 0.04 } }, "vos": { "label": "Offset", "unit": "V", "spec": { "min": -0.01, "max": 0.01 } }, "t_dec": { "label": "Decision time", "unit": "s", "spec": { "min": null, "max": 1e-8 } }, "t_dec_small": { "label": "Decision time, smallest overdrive", "unit": "s", "spec": { "min": null, "max": 2.5e-8 } }, "v_band": { "label": "Transition width, 10-90 %", "unit": "V", "spec": { "min": null, "max": 0.001 } }, "voh": { "label": "Output high level", "unit": "V", "spec": { "min": 1.05, "max": null } }, "vol": { "label": "Output low level", "unit": "V", "spec": { "min": null, "max": 0.05 } }, "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.00004 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "c373d41ad2487d15a3e2b35ed6b325b4ddcc7a0ea6616d4be1fd59e6cfa7dcdd" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/comparator-hysteresis.js", "sha256": "6bf71cd9e723c411ae1674190422a6803fddfad876e849813a9c751865b4d2ce" }, "simulationFingerprints": { "op": "f55514f69bff008d8becce5b6ecb40fe2fc6336f589b4bcc0eeda89fd5ace454", "sweep": "c617aaf91155e2077d02c2aa86295ba81851d38e37e42b40faa2085e732ea03c", "delay": "b00185c3dad76aff6f8c2286bad882339ccbe386aed50af23c2bb4a00d1c9d20" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "a9e0592a2b5accf2b03d58cb5b80034aa82719b5497655980835b363628eb130", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "comparator-hysteresis", "parameters": { "Ib": 0.00001, "N": 2, "Wt": 0.000008, "Lt": 0.000001, "W1": 0.00001, "L1": 5e-7, "W3": 0.000004, "L3": 0.000001, "Wn": 5e-7, "Wp": 7e-7, "Li": 1.3e-7, "F": 3, "Ws": 5e-7, "RH": 300000, "CL": 2e-14, "VCM": 0.6 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/comparator-hysteresis/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "cmph", "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMT tail ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=500n ng=2 m=1", "source": "XM1 d1 inp tail vss sg13_lv_nmos w=10u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=500n ng=2 m=1", "source": "XM2 d2 inn tail vss sg13_lv_nmos w=10u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XM3 d2 d2 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XM4 d1 d2 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM5 a1 d1 vss vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=700n l=130n ng=1 m=1", "source": "XM6 a1 d1 vdd vdd sg13_lv_pmos w=700n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=3", "source": "XM7 a2 a1 vss vss sg13_lv_nmos w=500n l=130n ng=1 m=3", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "a1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=700n l=130n ng=1 m=3", "source": "XM8 a2 a1 vdd vdd sg13_lv_pmos w=700n l=130n ng=1 m=3", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "a1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=9", "source": "XM9 out a2 vss vss sg13_lv_nmos w=500n l=130n ng=1 m=9", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "a2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=700n l=130n ng=1 m=9", "source": "XM10 out a2 vdd vdd sg13_lv_pmos w=700n l=130n ng=1 m=9", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "a2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRH1", "displayName": "RH1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=92.548u", "source": "XRH1 d1 h1 vss rhigh w=0.5u l=92.548u", "pins": [ { "id": "p", "net": "d1" }, { "id": "n", "net": "h1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM11 h1 out vss vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "h1" }, { "id": "g", "net": "out" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRH2", "displayName": "RH2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=92.548u", "source": "XRH2 h2 d1 vss rhigh w=0.5u l=92.548u", "pins": [ { "id": "p", "net": "h2" }, { "id": "n", "net": "d1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=500n l=130n ng=1 m=2", "source": "XM12 h2 out vdd vdd sg13_lv_pmos w=500n l=130n ng=1 m=2", "pins": [ { "id": "d", "net": "h2" }, { "id": "g", "net": "out" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XRH1", "pin": "substrate" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XRH2", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XRH1", "pin": "p" }, { "device": "XRH2", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "a1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "a2", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XM11", "pin": "g" }, { "device": "XM12", "pin": "g" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "h1", "ground": false, "terminals": [ { "device": "XRH1", "pin": "n" }, { "device": "XM11", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "h2", "ground": false, "terminals": [ { "device": "XRH2", "pin": "p" }, { "device": "XM12", "pin": "d" } ], "ports": [], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 10u", "source": "Ib vdd ib dc 10u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "cmph", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib cmph", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/cmph" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "20f", "source": "Cl out 0 20f", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vcm", "displayName": "Vcm", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vcm cm 0 dc 600m", "pins": [ { "id": "p", "net": "cm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vid", "displayName": "Vid", "spiceType": "V", "model": null, "parametersOrValue": "dc 100m", "source": "Vid id 0 dc 100m", "pins": [ { "id": "p", "net": "id" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Einp", "displayName": "Einp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Einp inp cm id 0 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "cm" }, { "id": "cp", "net": "id" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Einn", "displayName": "Einn", "spiceType": "E", "model": null, "parametersOrValue": "-0.5", "source": "Einn inn cm id 0 -0.5", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "cm" }, { "id": "cp", "net": "id" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vcm", "pin": "n" }, { "device": "Vid", "pin": "n" }, { "device": "Einp", "pin": "cn" }, { "device": "Einn", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Einp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Einn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cm", "ground": false, "terminals": [ { "device": "Vcm", "pin": "p" }, { "device": "Einp", "pin": "n" }, { "device": "Einn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "id", "ground": false, "terminals": [ { "device": "Vid", "pin": "p" }, { "device": "Einp", "pin": "cp" }, { "device": "Einn", "pin": "cp" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/cmph", "name": "cmph", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMT tail ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=500n ng=2 m=1", "source": "XM1 d1 inp tail vss sg13_lv_nmos w=10u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=500n ng=2 m=1", "source": "XM2 d2 inn tail vss sg13_lv_nmos w=10u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XM3 d2 d2 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XM4 d1 d2 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM5 a1 d1 vss vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=700n l=130n ng=1 m=1", "source": "XM6 a1 d1 vdd vdd sg13_lv_pmos w=700n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=3", "source": "XM7 a2 a1 vss vss sg13_lv_nmos w=500n l=130n ng=1 m=3", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "a1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=700n l=130n ng=1 m=3", "source": "XM8 a2 a1 vdd vdd sg13_lv_pmos w=700n l=130n ng=1 m=3", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "a1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=9", "source": "XM9 out a2 vss vss sg13_lv_nmos w=500n l=130n ng=1 m=9", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "a2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=700n l=130n ng=1 m=9", "source": "XM10 out a2 vdd vdd sg13_lv_pmos w=700n l=130n ng=1 m=9", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "a2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRH1", "displayName": "RH1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=92.548u", "source": "XRH1 d1 h1 vss rhigh w=0.5u l=92.548u", "pins": [ { "id": "p", "net": "d1" }, { "id": "n", "net": "h1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM11 h1 out vss vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "h1" }, { "id": "g", "net": "out" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRH2", "displayName": "RH2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=92.548u", "source": "XRH2 h2 d1 vss rhigh w=0.5u l=92.548u", "pins": [ { "id": "p", "net": "h2" }, { "id": "n", "net": "d1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=500n l=130n ng=1 m=2", "source": "XM12 h2 out vdd vdd sg13_lv_pmos w=500n l=130n ng=1 m=2", "pins": [ { "id": "d", "net": "h2" }, { "id": "g", "net": "out" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XRH1", "pin": "substrate" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XRH2", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XRH1", "pin": "p" }, { "device": "XRH2", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "a1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "a2", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XM11", "pin": "g" }, { "device": "XM12", "pin": "g" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "h1", "ground": false, "terminals": [ { "device": "XRH1", "pin": "n" }, { "device": "XM11", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "h2", "ground": false, "terminals": [ { "device": "XRH2", "pin": "p" }, { "device": "XM12", "pin": "d" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/cmph" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. 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PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 10u", "source": "Ib vdd ib dc 10u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "cmph", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib cmph", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/cmph" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "20f", "source": "Cl out 0 20f", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vcm", "displayName": "Vcm", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vcm cm 0 dc 600m", "pins": [ { "id": "p", "net": "cm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vid", "displayName": "Vid", "spiceType": "V", "model": null, "parametersOrValue": "pwl(0 -60m 40u 60m 80u -60m)", "source": "Vid id 0 pwl(0 -60m 40u 60m 80u -60m)", "pins": [ { "id": "p", "net": "id" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Einp", "displayName": "Einp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Einp inp cm id 0 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "cm" }, { "id": "cp", "net": "id" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Einn", "displayName": "Einn", "spiceType": "E", "model": null, "parametersOrValue": "-0.5", "source": "Einn inn cm id 0 -0.5", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "cm" }, { "id": "cp", "net": "id" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vcm", "pin": "n" }, { "device": "Vid", "pin": "n" }, { "device": "Einp", "pin": "cn" }, { "device": "Einn", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Einp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Einn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cm", "ground": false, "terminals": [ { "device": "Vcm", "pin": "p" }, { "device": "Einp", "pin": "n" }, { "device": "Einn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "id", "ground": false, "terminals": [ { "device": "Vid", "pin": "p" }, { "device": "Einp", "pin": "cp" }, { "device": "Einn", "pin": "cp" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/cmph", "name": "cmph", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMT tail ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", 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w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XM4 d1 d2 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM5 a1 d1 vss vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=700n l=130n ng=1 m=1", "source": "XM6 a1 d1 vdd vdd sg13_lv_pmos w=700n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=3", "source": "XM7 a2 a1 vss vss sg13_lv_nmos w=500n l=130n ng=1 m=3", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "a1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=700n l=130n ng=1 m=3", "source": "XM8 a2 a1 vdd vdd sg13_lv_pmos w=700n l=130n ng=1 m=3", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "a1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=9", "source": "XM9 out a2 vss vss sg13_lv_nmos w=500n l=130n ng=1 m=9", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "a2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=700n l=130n ng=1 m=9", "source": "XM10 out a2 vdd vdd sg13_lv_pmos w=700n l=130n ng=1 m=9", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "a2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRH1", "displayName": "RH1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=92.548u", "source": "XRH1 d1 h1 vss rhigh w=0.5u l=92.548u", "pins": [ { "id": "p", "net": "d1" }, { "id": "n", "net": "h1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XM11 h1 out vss vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "h1" }, { "id": "g", "net": "out" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRH2", "displayName": "RH2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=92.548u", "source": "XRH2 h2 d1 vss rhigh w=0.5u l=92.548u", "pins": [ { "id": "p", "net": "h2" }, { "id": "n", "net": "d1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=500n l=130n ng=1 m=2", "source": "XM12 h2 out vdd vdd sg13_lv_pmos w=500n l=130n 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"vdd", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "a1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "a2", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM9", 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