{
  "schema": "aisic.circuit/1",
  "entryType": "library-block",
  "domain": "analog",
  "id": "cs-amp",
  "name": "Common-source amplifier",
  "group": "Amplifier stages",
  "subgroup": "Common-source stages",
  "title": "Common-source amplifier",
  "summary": "A transistor and resistor amplify small voltage changes and invert them. The transistor turns voltage into current; the resistor turns current back into voltage. Set the DC bias before measuring gain, then explore how the load changes bandwidth and output swing.",
  "reference": {
    "kind": "book",
    "authors": "B. Razavi",
    "title": "Design of Analog CMOS Integrated Circuits",
    "edition": "2nd ed.",
    "publisher": "McGraw-Hill",
    "year": 2017,
    "where": "Single-Stage Amplifiers - the common-source stage with resistive load",
    "takes": "The topology and the small-signal result Av = -gm*(RD || ro), which is what the r_o-limited behaviour below is measured against."
  },
  "resources": {
    "record": "/circuits/cs-amp.json",
    "page": "/index.html#cs-amp",
    "achieved": "/achieved/cs-amp.json",
    "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.",
    "modelCards": [
      {
        "name": "sg13g2_lv_tt.spice",
        "url": "/sg13g2_lv_tt.spice",
        "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a"
      },
      {
        "name": "sg13g2_passive_tt.spice",
        "url": "/sg13g2_passive_tt.spice",
        "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc"
      }
    ],
    "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.",
    "schema": "/schemas/circuit.schema.json"
  },
  "specificationPolicy": {
    "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.",
    "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.",
    "scopes": {
      "nominal": {
        "corner": "tt",
        "temp": 27,
        "vdd": 1,
        "temperatureUnit": "degC",
        "supplyMeaning": "scale of the bench's nominal supply"
      }
    },
    "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim."
  },
  "corners": {
    "cards": "a deck's sg13g2_<family>_tt.spice (family lv, hv, passive, hbt) becomes sg13g2_<family>_<corner>.spice",
    "process": [
      "tt",
      "ss",
      "ff",
      "sf",
      "fs"
    ],
    "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise",
    "temperatures": [
      -40,
      27,
      125
    ],
    "supplyScale": [
      0.9,
      1,
      1.1
    ],
    "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it",
    "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw",
    "sets": {
      "essential": [
        {
          "corner": "tt",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "ss",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "ff",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "sf",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "fs",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "tt",
          "temp": -40,
          "vdd": 1
        },
        {
          "corner": "tt",
          "temp": 125,
          "vdd": 1
        },
        {
          "corner": "tt",
          "temp": 27,
          "vdd": 0.9
        },
        {
          "corner": "tt",
          "temp": 27,
          "vdd": 1.1
        },
        {
          "corner": "ss",
          "temp": 125,
          "vdd": 0.9
        },
        {
          "corner": "ff",
          "temp": -40,
          "vdd": 1.1
        }
      ],
      "full": "all 45 combinations"
    },
    "montecarlo": {
      "cards": {
        "mc": "process and mismatch",
        "mcmm": "mismatch only",
        "mcproc": "process only"
      },
      "seed": "draw k adds .options seed=k, so draws are reproducible"
    }
  },
  "technology": {
    "id": "sg13g2",
    "name": "IHP SG13G2",
    "node": "130 nm",
    "corner": "tt",
    "vdd": 1.2,
    "lmin": 1.3e-7,
    "wmin": 1.5e-7,
    "models": "sg13g2_lv_tt.spice",
    "devices": {
      "nmos": "sg13_lv_nmos",
      "pmos": "sg13_lv_pmos",
      "resistor": "rppd, rhigh",
      "capacitor": "cap_cmim"
    },
    "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.",
    "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF."
  },
  "implementation": {
    "kind": "physical-device-reference",
    "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.",
    "evidence": "schematic-simulation",
    "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.",
    "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.",
    "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification."
  },
  "cards": [
    "sg13g2_lv_tt.spice",
    "sg13g2_passive_tt.spice"
  ],
  "ports": [
    {
      "name": "in",
      "kind": "input",
      "dc": "V_GS bias"
    },
    {
      "name": "out",
      "kind": "output"
    },
    {
      "name": "vdd",
      "kind": "supply",
      "value": "VDD"
    },
    {
      "name": "0",
      "kind": "ground"
    }
  ],
  "devices": [
    {
      "name": "M1",
      "type": "nmos",
      "nodes": "out in 0 0",
      "sizedBy": [
        "W",
        "L"
      ],
      "role": "transconductor",
      "fingers": 2,
      "copies": 1
    },
    {
      "name": "Rd",
      "type": "resistor",
      "nodes": "vdd out",
      "sizedBy": [
        "RD"
      ],
      "role": "load"
    },
    {
      "name": "Cl",
      "type": "capacitor",
      "nodes": "out 0",
      "sizedBy": [
        "CL"
      ],
      "role": "load capacitance"
    }
  ],
  "intent": [
    {
      "rule": "bias",
      "of": [
        "M1"
      ],
      "constraint": "V_out ~= VDD/2",
      "why": "Maximum symmetric swing, and close to the peak of the gain curve. It is the first thing to re-solve for in a new process: this circuit wanted V_GS = 0.75 V in 180 nm, 0.728 V in sky130 and 0.32 V in SG13G2, because the threshold and the supply moved."
    },
    {
      "rule": "region",
      "of": [
        "M1"
      ],
      "constraint": "saturation",
      "why": "In triode the gain collapses; the bias-point analysis exists to let you see where that boundary is."
    }
  ],
  "specs": [
    {
      "key": "av",
      "label": "DC gain",
      "unit": "V/V",
      "direction": "max"
    },
    {
      "key": "f3db",
      "label": "Bandwidth",
      "unit": "Hz",
      "direction": "max"
    },
    {
      "key": "gbw",
      "label": "Gain-bandwidth product",
      "unit": "Hz",
      "direction": "max",
      "note": "Approximately gm/(2*pi*C_total) for a dominant output pole and fixed small-signal parameters. Changing R_D also changes bias and parasitics."
    }
  ],
  "explanation": {
    "idea": "This stage makes a small voltage change larger and reverses its direction. The transistor converts input voltage into current; the resistor converts that current back into voltage. Choose the DC bias first so the output has room to move in both directions.",
    "detail": "M1's small-signal transconductance converts a change in gate voltage to drain current. The output resistance is the load resistor in parallel with the transistor's output resistance. Their product sets the low-frequency gain; bias and parasitic capacitance also affect bandwidth.",
    "lesson": {
      "relation": 0,
      "symbols": "A_v is voltage gain in V/V; g_m1 is M1's transconductance in siemens; R_D is the load resistance and r_o1 the transistor's output resistance, both in ohms. ∥ means parallel combination.",
      "assumptions": "Small signals around a DC bias with M1 in saturation. This low-frequency approximation neglects capacitive effects.",
      "exercise": {
        "param": "CL",
        "value": 1e-13,
        "analysis": "ac",
        "expect": "A larger load capacitance should lower the bandwidth while leaving the low-frequency gain nearly unchanged."
      },
      "limits": "Provide the input's DC bias as well as its signal. A large input can drive the transistor out of saturation and distort the output."
    },
    "path": [
      {
        "part": "Input transistor",
        "devices": "M1",
        "does": "Common source: the V_GS bias plus the signal on its gate set its drain current, and g_m1 converts input voltage to current."
      },
      {
        "part": "Load resistor",
        "devices": "Rd",
        "does": "From vdd to out, it turns M1's current into V_out = V_DD − I_D R_D, so the output falls as the input rises."
      },
      {
        "part": "Load capacitance",
        "devices": "Cl",
        "does": "At the output, it slows voltage changes. Together with device and resistor parasitics, it sets the dominant output pole."
      }
    ],
    "bias": "V_GS bias, 0.32 V by default, sets M1's drain current; R_D (20 kΩ by default) turns it into V_out = V_DD − I_D R_D, which the bias-point analysis places near V_DD/2 so M1 stays saturated with room to swing.",
    "relations": [
      {
        "what": "Small-signal gain",
        "expr": "A_v ≈ −g_m1 (R_D ∥ r_o1)",
        "note": "only while M1 is saturated; the minus sign is the inversion, so the phase starts at 180°"
      },
      {
        "what": "Bandwidth",
        "expr": "f_3dB ≈ 1 / (2π (R_D ∥ r_o1) C_total)",
        "note": "dominant-output-pole approximation; C_total includes the load and output parasitics"
      },
      {
        "what": "Gain-bandwidth product",
        "expr": "GBW ≈ g_m1 / (2π C_total)",
        "note": "approximately independent of R_D only while transconductance and total output capacitance remain fixed; changing R_D also changes the real circuit's bias and parasitics"
      },
      {
        "what": "Saturation limit",
        "expr": "V_out = V_DD − I_D R_D > V_GS − V_TH",
        "note": "below this M1 enters triode and the gain collapses; the DC transfer shows where"
      }
    ],
    "tradeoffs": [
      "R_D: usually more gain and less bandwidth. Their product is only approximately constant at fixed transconductance and capacitance; recheck the bias, since a larger resistor also pulls V_out down.",
      "V_GS bias: more current raises g_m1 and the gain-bandwidth product but lowers V_out; too high and M1 enters triode, too low and it barely conducts.",
      "L: longer raises r_o1, lifting the gain's ceiling g_m1 r_o1, but passes less current at the same V_GS bias and adds capacitance.",
      "C_L: a larger load lowers the bandwidth and the gain-bandwidth product together and leaves the DC gain untouched."
    ]
  },
  "sizing": [
    {
      "key": "W",
      "label": "W",
      "unit": "m",
      "value": 0.00001,
      "min": 1.5e-7,
      "max": 0.0001,
      "kind": "si"
    },
    {
      "key": "L",
      "label": "L",
      "unit": "m",
      "value": 5e-7,
      "min": 1.3e-7,
      "max": 0.000004,
      "kind": "si"
    },
    {
      "key": "RD",
      "label": "R_D",
      "unit": "Ω",
      "value": 20000,
      "min": 1000,
      "max": 1000000,
      "kind": "si"
    },
    {
      "key": "CL",
      "label": "C_L",
      "unit": "F",
      "value": 5e-14,
      "min": 1e-15,
      "max": 1e-11,
      "kind": "si"
    },
    {
      "key": "VGS",
      "label": "V_GS bias",
      "unit": "V",
      "value": 0.32,
      "min": 0.2,
      "max": 1.2,
      "kind": "si"
    }
  ],
  "testbenches": [
    {
      "id": "vtc",
      "label": "Bias point",
      "note": "Choose V_GS from this curve before reading the gain.",
      "measures": [
        "vout_bias",
        "av_at_bias",
        "av_peak"
      ],
      "metricKeys": [
        "vout_dc",
        "gain_peak_db"
      ],
      "acceptance": [],
      "acceptanceRules": [],
      "cards": [
        "sg13g2_lv_tt.spice",
        "sg13g2_passive_tt.spice"
      ],
      "netlist": "* Common-source amplifier - DC transfer, to place the bias point\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\nVdd vdd 0 1.2\nXRd vdd out 0 rhigh w=0.5u l=6.078u\nXM1 out in 0 0 sg13_lv_nmos w=10u l=500n ng=2 m=1\nVin in 0 0\n.dc Vin 0 1.2 0.004\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc vout_bias FIND v(out) AT=320m\n.end"
    },
    {
      "id": "ac",
      "label": "Frequency response",
      "note": "",
      "measures": [
        "av",
        "f3db",
        "funity",
        "gbw"
      ],
      "metricKeys": [
        "gain_db",
        "f3db_hz",
        "ugf_hz"
      ],
      "acceptance": [],
      "acceptanceRules": [],
      "cards": [
        "sg13g2_lv_tt.spice",
        "sg13g2_passive_tt.spice"
      ],
      "netlist": "* Common-source amplifier - small-signal response about the bias point\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\nVdd vdd 0 1.2\nXRd vdd out 0 rhigh w=0.5u l=6.078u\nXM1 out in 0 0 sg13_lv_nmos w=10u l=500n ng=2 m=1\nCl out 0 50f\nVin in 0 dc 320m ac 1\n.ac dec 30 100 100g\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas ac av_db FIND vdb(out) AT=100\n.meas ac funity WHEN vdb(out)=0 FALL=1\n.end"
    }
  ],
  "recordVersion": 1,
  "authoring": {
    "version": 1,
    "source": "this-record",
    "fields": [
      "name",
      "title",
      "group",
      "subgroup",
      "summary",
      "reference",
      "ports",
      "devices (except fingers/copies)",
      "intent",
      "specs",
      "explanation",
      "sizing[].label",
      "testbenches[].label",
      "testbenches[].note"
    ],
    "generated": [
      "revision",
      "technology",
      "cards",
      "corners",
      "specificationPolicy",
      "sizing (except label)",
      "measurements",
      "testbenches (except label/note)",
      "diagrams",
      "provenance",
      "devices[].fingers",
      "devices[].copies"
    ],
    "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.",
    "sha256": "1d837f428554c90c36aa6302e4f7cb07ee2997eb65270f9783fb465edd6abb98"
  },
  "provenance": {
    "schema": "aisic.record-provenance/1",
    "parameterScope": "published-defaults",
    "generator": {
      "url": "/library/cs-amp.js",
      "sha256": "131cdbc87ecdf8e4d3b66587fdbd638040afbd239543c3bef81d649454544ec9"
    },
    "simulationFingerprints": {
      "vtc": "abe220cf43d6c0f83061a43f6ad521a59e61905d72c98bdd5db3c372a9f88554",
      "ac": "62f80beb3e98d69ebea134fac3f8a69ed16b33976986c4ab671cba64f2d3fdf1"
    },
    "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification."
  },
  "revision": "af13b1f913446f9d3150e291831f2fde42adfad61b8a213821bb5610b1a689cf",
  "diagrams": {
    "schema": "aisic.diagrams/1",
    "circuit": "cs-amp",
    "parameters": {
      "W": 0.00001,
      "L": 5e-7,
      "RD": 20000,
      "CL": 5e-14,
      "VGS": 0.32
    },
    "parameterScope": "published-defaults",
    "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.",
    "variants": {
      "choiceParameters": [],
      "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation."
    },
    "resourceBase": "/circuits/cs-amp/",
    "graphs": [
      {
        "id": "graph-1",
        "kind": "electrical-connectivity",
        "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.",
        "root": "dut",
        "globalDefinitions": [],
        "scopes": [
          {
            "id": "dut",
            "name": "top",
            "ports": [
              {
                "name": "vdd",
                "net": "vdd",
                "kind": "supply"
              },
              {
                "name": "out",
                "net": "out",
                "kind": "output"
              },
              {
                "name": "in",
                "net": "in",
                "kind": "input"
              },
              {
                "name": "gnd",
                "net": "0",
                "kind": "ground"
              }
            ],
            "definitions": [],
            "devices": [
              {
                "id": "XRd",
                "displayName": "Rd",
                "spiceType": "X",
                "model": "rhigh",
                "parametersOrValue": "w=0.5u l=6.078u",
                "source": "XRd vdd out 0 rhigh w=0.5u l=6.078u",
                "pins": [
                  {
                    "id": "p",
                    "net": "vdd"
                  },
                  {
                    "id": "n",
                    "net": "out"
                  },
                  {
                    "id": "substrate",
                    "net": "0"
                  }
                ],
                "pinMeaning": "IHP resistor model terminal order"
              },
              {
                "id": "XM1",
                "displayName": "M1",
                "spiceType": "X",
                "model": "sg13_lv_nmos",
                "parametersOrValue": "w=10u l=500n ng=2 m=1",
                "source": "XM1 out in 0 0 sg13_lv_nmos w=10u l=500n ng=2 m=1",
                "pins": [
                  {
                    "id": "d",
                    "net": "out"
                  },
                  {
                    "id": "g",
                    "net": "in"
                  },
                  {
                    "id": "s",
                    "net": "0"
                  },
                  {
                    "id": "b",
                    "net": "0"
                  }
                ],
                "pinMeaning": "MOS drain, gate, source, bulk"
              }
            ],
            "nets": [
              {
                "id": "vdd",
                "ground": false,
                "terminals": [
                  {
                    "device": "XRd",
                    "pin": "p"
                  }
                ],
                "ports": [
                  "vdd"
                ],
                "voltageReferences": []
              },
              {
                "id": "out",
                "ground": false,
                "terminals": [
                  {
                    "device": "XRd",
                    "pin": "n"
                  },
                  {
                    "device": "XM1",
                    "pin": "d"
                  }
                ],
                "ports": [
                  "out"
                ],
                "voltageReferences": []
              },
              {
                "id": "0",
                "ground": true,
                "terminals": [
                  {
                    "device": "XRd",
                    "pin": "substrate"
                  },
                  {
                    "device": "XM1",
                    "pin": "s"
                  },
                  {
                    "device": "XM1",
                    "pin": "b"
                  }
                ],
                "ports": [
                  "gnd"
                ],
                "voltageReferences": []
              },
              {
                "id": "in",
                "ground": false,
                "terminals": [
                  {
                    "device": "XM1",
                    "pin": "g"
                  }
                ],
                "ports": [
                  "in"
                ],
                "voltageReferences": []
              }
            ]
          }
        ]
      },
      {
        "id": "graph-2",
        "kind": "electrical-connectivity",
        "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.",
        "root": "top",
        "globalDefinitions": [],
        "scopes": [
          {
            "id": "top",
            "name": "top",
            "ports": [],
            "definitions": [],
            "devices": [
              {
                "id": "Vdd",
                "displayName": "Vdd",
                "spiceType": "V",
                "model": null,
                "parametersOrValue": "1.2",
                "source": "Vdd vdd 0 1.2",
                "pins": [
                  {
                    "id": "p",
                    "net": "vdd"
                  },
                  {
                    "id": "n",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              },
              {
                "id": "XRd",
                "displayName": "Rd",
                "spiceType": "X",
                "model": "rhigh",
                "parametersOrValue": "w=0.5u l=6.078u",
                "source": "XRd vdd out 0 rhigh w=0.5u l=6.078u",
                "pins": [
                  {
                    "id": "p",
                    "net": "vdd"
                  },
                  {
                    "id": "n",
                    "net": "out"
                  },
                  {
                    "id": "substrate",
                    "net": "0"
                  }
                ],
                "pinMeaning": "IHP resistor model terminal order"
              },
              {
                "id": "XM1",
                "displayName": "M1",
                "spiceType": "X",
                "model": "sg13_lv_nmos",
                "parametersOrValue": "w=10u l=500n ng=2 m=1",
                "source": "XM1 out in 0 0 sg13_lv_nmos w=10u l=500n ng=2 m=1",
                "pins": [
                  {
                    "id": "d",
                    "net": "out"
                  },
                  {
                    "id": "g",
                    "net": "in"
                  },
                  {
                    "id": "s",
                    "net": "0"
                  },
                  {
                    "id": "b",
                    "net": "0"
                  }
                ],
                "pinMeaning": "MOS drain, gate, source, bulk"
              },
              {
                "id": "Vin",
                "displayName": "Vin",
                "spiceType": "V",
                "model": null,
                "parametersOrValue": "0",
                "source": "Vin in 0 0",
                "pins": [
                  {
                    "id": "p",
                    "net": "in"
                  },
                  {
                    "id": "n",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              }
            ],
            "nets": [
              {
                "id": "vdd",
                "ground": false,
                "terminals": [
                  {
                    "device": "Vdd",
                    "pin": "p"
                  },
                  {
                    "device": "XRd",
                    "pin": "p"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "0",
                "ground": true,
                "terminals": [
                  {
                    "device": "Vdd",
                    "pin": "n"
                  },
                  {
                    "device": "XRd",
                    "pin": "substrate"
                  },
                  {
                    "device": "XM1",
                    "pin": "s"
                  },
                  {
                    "device": "XM1",
                    "pin": "b"
                  },
                  {
                    "device": "Vin",
                    "pin": "n"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "out",
                "ground": false,
                "terminals": [
                  {
                    "device": "XRd",
                    "pin": "n"
                  },
                  {
                    "device": "XM1",
                    "pin": "d"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "in",
                "ground": false,
                "terminals": [
                  {
                    "device": "XM1",
                    "pin": "g"
                  },
                  {
                    "device": "Vin",
                    "pin": "p"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              }
            ]
          }
        ],
        "uninstantiatedDefinitions": [],
        "dut": {
          "kind": "top-level-device-set",
          "scope": "top",
          "devices": [
            "XRd",
            "XM1"
          ]
        }
      },
      {
        "id": "graph-3",
        "kind": "functional-graph",
        "classification": "heuristic-device-grouping",
        "electricalScope": "dut",
        "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.",
        "nodes": [
          {
            "id": "block-1",
            "label": "Transconductor",
            "devices": [
              {
                "scope": "dut",
                "device": "XM1"
              }
            ],
            "inferredStages": [
              1
            ]
          },
          {
            "id": "block-2",
            "label": "Load",
            "devices": [
              {
                "scope": "dut",
                "device": "XRd"
              }
            ],
            "inferredStages": [
              1
            ]
          }
        ],
        "edges": [
          {
            "id": "net-1",
            "net": "out",
            "nodes": [
              "block-2",
              "block-1"
            ],
            "direction": "undirected-shared-net"
          }
        ],
        "ports": [
          {
            "name": "vdd",
            "net": "vdd",
            "kind": "supply"
          },
          {
            "name": "out",
            "net": "out",
            "kind": "output"
          },
          {
            "name": "in",
            "net": "in",
            "kind": "input"
          },
          {
            "name": "gnd",
            "net": "0",
            "kind": "ground"
          }
        ],
        "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes."
      },
      {
        "id": "graph-4",
        "kind": "electrical-connectivity",
        "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.",
        "root": "dut",
        "globalDefinitions": [],
        "scopes": [
          {
            "id": "dut",
            "name": "top",
            "ports": [
              {
                "name": "vdd",
                "net": "vdd",
                "kind": "supply"
              },
              {
                "name": "out",
                "net": "out",
                "kind": "output"
              },
              {
                "name": "in",
                "net": "in",
                "kind": "input"
              },
              {
                "name": "gnd",
                "net": "0",
                "kind": "ground"
              }
            ],
            "definitions": [],
            "devices": [
              {
                "id": "XRd",
                "displayName": "Rd",
                "spiceType": "X",
                "model": "rhigh",
                "parametersOrValue": "w=0.5u l=6.078u",
                "source": "XRd vdd out 0 rhigh w=0.5u l=6.078u",
                "pins": [
                  {
                    "id": "p",
                    "net": "vdd"
                  },
                  {
                    "id": "n",
                    "net": "out"
                  },
                  {
                    "id": "substrate",
                    "net": "0"
                  }
                ],
                "pinMeaning": "IHP resistor model terminal order"
              },
              {
                "id": "XM1",
                "displayName": "M1",
                "spiceType": "X",
                "model": "sg13_lv_nmos",
                "parametersOrValue": "w=10u l=500n ng=2 m=1",
                "source": "XM1 out in 0 0 sg13_lv_nmos w=10u l=500n ng=2 m=1",
                "pins": [
                  {
                    "id": "d",
                    "net": "out"
                  },
                  {
                    "id": "g",
                    "net": "in"
                  },
                  {
                    "id": "s",
                    "net": "0"
                  },
                  {
                    "id": "b",
                    "net": "0"
                  }
                ],
                "pinMeaning": "MOS drain, gate, source, bulk"
              },
              {
                "id": "Cl",
                "displayName": "Cl",
                "spiceType": "C",
                "model": null,
                "parametersOrValue": "50f",
                "source": "Cl out 0 50f",
                "pins": [
                  {
                    "id": "p",
                    "net": "out"
                  },
                  {
                    "id": "n",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              }
            ],
            "nets": [
              {
                "id": "vdd",
                "ground": false,
                "terminals": [
                  {
                    "device": "XRd",
                    "pin": "p"
                  }
                ],
                "ports": [
                  "vdd"
                ],
                "voltageReferences": []
              },
              {
                "id": "out",
                "ground": false,
                "terminals": [
                  {
                    "device": "XRd",
                    "pin": "n"
                  },
                  {
                    "device": "XM1",
                    "pin": "d"
                  },
                  {
                    "device": "Cl",
                    "pin": "p"
                  }
                ],
                "ports": [
                  "out"
                ],
                "voltageReferences": []
              },
              {
                "id": "0",
                "ground": true,
                "terminals": [
                  {
                    "device": "XRd",
                    "pin": "substrate"
                  },
                  {
                    "device": "XM1",
                    "pin": "s"
                  },
                  {
                    "device": "XM1",
                    "pin": "b"
                  },
                  {
                    "device": "Cl",
                    "pin": "n"
                  }
                ],
                "ports": [
                  "gnd"
                ],
                "voltageReferences": []
              },
              {
                "id": "in",
                "ground": false,
                "terminals": [
                  {
                    "device": "XM1",
                    "pin": "g"
                  }
                ],
                "ports": [
                  "in"
                ],
                "voltageReferences": []
              }
            ]
          }
        ]
      },
      {
        "id": "graph-5",
        "kind": "electrical-connectivity",
        "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.",
        "root": "top",
        "globalDefinitions": [],
        "scopes": [
          {
            "id": "top",
            "name": "top",
            "ports": [],
            "definitions": [],
            "devices": [
              {
                "id": "Vdd",
                "displayName": "Vdd",
                "spiceType": "V",
                "model": null,
                "parametersOrValue": "1.2",
                "source": "Vdd vdd 0 1.2",
                "pins": [
                  {
                    "id": "p",
                    "net": "vdd"
                  },
                  {
                    "id": "n",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              },
              {
                "id": "XRd",
                "displayName": "Rd",
                "spiceType": "X",
                "model": "rhigh",
                "parametersOrValue": "w=0.5u l=6.078u",
                "source": "XRd vdd out 0 rhigh w=0.5u l=6.078u",
                "pins": [
                  {
                    "id": "p",
                    "net": "vdd"
                  },
                  {
                    "id": "n",
                    "net": "out"
                  },
                  {
                    "id": "substrate",
                    "net": "0"
                  }
                ],
                "pinMeaning": "IHP resistor model terminal order"
              },
              {
                "id": "XM1",
                "displayName": "M1",
                "spiceType": "X",
                "model": "sg13_lv_nmos",
                "parametersOrValue": "w=10u l=500n ng=2 m=1",
                "source": "XM1 out in 0 0 sg13_lv_nmos w=10u l=500n ng=2 m=1",
                "pins": [
                  {
                    "id": "d",
                    "net": "out"
                  },
                  {
                    "id": "g",
                    "net": "in"
                  },
                  {
                    "id": "s",
                    "net": "0"
                  },
                  {
                    "id": "b",
                    "net": "0"
                  }
                ],
                "pinMeaning": "MOS drain, gate, source, bulk"
              },
              {
                "id": "Cl",
                "displayName": "Cl",
                "spiceType": "C",
                "model": null,
                "parametersOrValue": "50f",
                "source": "Cl out 0 50f",
                "pins": [
                  {
                    "id": "p",
                    "net": "out"
                  },
                  {
                    "id": "n",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              },
              {
                "id": "Vin",
                "displayName": "Vin",
                "spiceType": "V",
                "model": null,
                "parametersOrValue": "dc 320m ac 1",
                "source": "Vin in 0 dc 320m ac 1",
                "pins": [
                  {
                    "id": "p",
                    "net": "in"
                  },
                  {
                    "id": "n",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              }
            ],
            "nets": [
              {
                "id": "vdd",
                "ground": false,
                "terminals": [
                  {
                    "device": "Vdd",
                    "pin": "p"
                  },
                  {
                    "device": "XRd",
                    "pin": "p"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "0",
                "ground": true,
                "terminals": [
                  {
                    "device": "Vdd",
                    "pin": "n"
                  },
                  {
                    "device": "XRd",
                    "pin": "substrate"
                  },
                  {
                    "device": "XM1",
                    "pin": "s"
                  },
                  {
                    "device": "XM1",
                    "pin": "b"
                  },
                  {
                    "device": "Cl",
                    "pin": "n"
                  },
                  {
                    "device": "Vin",
                    "pin": "n"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "out",
                "ground": false,
                "terminals": [
                  {
                    "device": "XRd",
                    "pin": "n"
                  },
                  {
                    "device": "XM1",
                    "pin": "d"
                  },
                  {
                    "device": "Cl",
                    "pin": "p"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "in",
                "ground": false,
                "terminals": [
                  {
                    "device": "XM1",
                    "pin": "g"
                  },
                  {
                    "device": "Vin",
                    "pin": "p"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              }
            ]
          }
        ],
        "uninstantiatedDefinitions": [],
        "dut": {
          "kind": "top-level-device-set",
          "scope": "top",
          "devices": [
            "XRd",
            "XM1",
            "Cl"
          ]
        }
      },
      {
        "id": "graph-6",
        "kind": "functional-graph",
        "classification": "heuristic-device-grouping",
        "electricalScope": "dut",
        "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.",
        "nodes": [
          {
            "id": "block-1",
            "label": "Transconductor",
            "devices": [
              {
                "scope": "dut",
                "device": "XM1"
              }
            ],
            "inferredStages": [
              1
            ]
          },
          {
            "id": "block-2",
            "label": "Load",
            "devices": [
              {
                "scope": "dut",
                "device": "XRd"
              }
            ],
            "inferredStages": [
              1
            ]
          },
          {
            "id": "block-3",
            "label": "Load capacitance",
            "devices": [
              {
                "scope": "dut",
                "device": "Cl"
              }
            ],
            "inferredStages": [
              1
            ]
          }
        ],
        "edges": [
          {
            "id": "net-1",
            "net": "out",
            "nodes": [
              "block-2",
              "block-1",
              "block-3"
            ],
            "direction": "undirected-shared-net"
          }
        ],
        "ports": [
          {
            "name": "vdd",
            "net": "vdd",
            "kind": "supply"
          },
          {
            "name": "out",
            "net": "out",
            "kind": "output"
          },
          {
            "name": "in",
            "net": "in",
            "kind": "input"
          },
          {
            "name": "gnd",
            "net": "0",
            "kind": "ground"
          }
        ],
        "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes."
      }
    ],
    "views": [
      {
        "bench": "vtc",
        "source": {
          "recordField": "testbenches",
          "id": "vtc",
          "field": "netlist"
        },
        "schematic": {
          "graph": "graph-1",
          "svg": {
            "url": "/circuits/cs-amp/vtc-schematic.svg",
            "asset": "vtc-schematic.svg"
          },
          "drawingCheck": {
            "method": "checkSchematic",
            "problems": []
          },
          "sheets": [
            {
              "name": "Common-source amplifier",
              "instances": []
            }
          ]
        },
        "benchDiagram": {
          "graph": "graph-2",
          "svg": {
            "url": "/circuits/cs-amp/vtc-bench.svg",
            "asset": "vtc-bench.svg"
          }
        },
        "blockDiagram": {
          "graph": "graph-3",
          "electricalGraph": "graph-1",
          "svg": {
            "url": "/circuits/cs-amp/vtc-block.svg",
            "asset": "vtc-block.svg"
          }
        }
      },
      {
        "bench": "ac",
        "source": {
          "recordField": "testbenches",
          "id": "ac",
          "field": "netlist"
        },
        "schematic": {
          "graph": "graph-4",
          "svg": {
            "url": "/circuits/cs-amp/ac-schematic.svg",
            "asset": "ac-schematic.svg"
          },
          "drawingCheck": {
            "method": "checkSchematic",
            "problems": []
          },
          "sheets": [
            {
              "name": "Common-source amplifier",
              "instances": []
            }
          ]
        },
        "benchDiagram": {
          "graph": "graph-5",
          "svg": {
            "url": "/circuits/cs-amp/ac-bench.svg",
            "asset": "ac-bench.svg"
          }
        },
        "blockDiagram": {
          "graph": "graph-6",
          "electricalGraph": "graph-4",
          "svg": {
            "url": "/circuits/cs-amp/ac-block.svg",
            "asset": "ac-block.svg"
          }
        }
      }
    ]
  }
}