{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "cs-cascode", "name": "Cascode common-source stage", "group": "Amplifier stages", "subgroup": "Common-source stages", "title": "Cascode common-source stage", "summary": "A voltage amplifier with stacked transistors that hold internal voltages steadier. This raises output resistance and gain, but reduces the available output swing. The testbench supplies a feedback path to set the DC operating point inside the cascodes' voltage window.", "reference": { "kind": "book", "authors": "B. Razavi", "title": "Design of Analog CMOS Integrated Circuits", "edition": "2nd ed.", "publisher": "McGraw-Hill", "year": 2016, "where": "Sec. 3.6 'Cascode Stage' (p. 82); the cascode bias from Ch. 5 'Current Mirrors and Biasing', Sec. 5.2 'Cascode Current Mirrors' (p. 139)", "takes": "The topology - a common-source device under an NMOS cascode, loaded by a cascoded PMOS current source - and the result that each cascode multiplies the resistance below it by g_m r_o. The ladders, each a diode over a resistor so the device under a cascode keeps only the V_DS it needs, and the sizing are this library's, for SG13G2 at 1.2 V." }, "resources": { "record": "/circuits/cs-cascode.json", "page": "/index.html#cs-cascode", "achieved": "/achieved/cs-cascode.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "in", "kind": "input" }, { "name": "out", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the reference current, drawn out of this pin" } ], "devices": [ { "name": "MB", "type": "pmos", "nodes": "pg pg vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "PMOS ladder, diode; two PMOS units", "fingers": 4, "copies": 2 }, { "name": "Rp", "type": "resistor", "nodes": "pg ib", "sizedBy": [ "Rp" ], "role": "PMOS ladder, the load cascode's drop" }, { "name": "M5", "type": "pmos", "nodes": "nc pg vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "NMOS ladder feed, one PMOS unit", "fingers": 4, "copies": 1 }, { "name": "MNb", "type": "nmos", "nodes": "nc nc nr vss", "sizedBy": [ "Wc", "Lc" ], "role": "NMOS ladder, diode; one NMOS cascode unit", "fingers": 2, "copies": 1 }, { "name": "Rn", "type": "resistor", "nodes": "nr vss", "sizedBy": [ "Rn" ], "role": "NMOS ladder, the input device's drop" }, { "name": "M1", "type": "nmos", "nodes": "x in vss vss", "sizedBy": [ "W1", "L1" ], "role": "input device, common source", "fingers": 6, "copies": 1 }, { "name": "M2", "type": "nmos", "nodes": "out nc x vss", "sizedBy": [ "Wc", "Lc", "N" ], "role": "NMOS cascode; 2N NMOS cascode units", "fingers": 2, "copies": 4 }, { "name": "M3", "type": "pmos", "nodes": "out ib y vdd", "sizedBy": [ "Wp", "Lp", "N" ], "role": "load cascode; 2N PMOS units", "fingers": 4, "copies": 4 }, { "name": "M4", "type": "pmos", "nodes": "y pg vdd vdd", "sizedBy": [ "Wp", "Lp", "N" ], "role": "load current source; 2N PMOS units", "fingers": 4, "copies": 4 } ], "intent": [ { "rule": "unit-copies", "of": [ "MB", "M3", "M4", "M5" ], "constraint": "MB = 2 PMOS units, M3 = M4 = 2N, M5 = 1", "why": "Repeated unit geometry preserves the intended nominal current ratio without a width-dependent threshold shift. Random mismatch remains. Matching M3's current density to MB's gives the nominal V_SG assumed by the ladder." }, { "rule": "unit-copies", "of": [ "MNb", "M2" ], "constraint": "M2 = 2N NMOS cascode units, MNb = 1", "why": "The ladder's diode MNb carries Ib/2 at M2's current density, so the two share a V_GS and M2's source - M1's drain - sits the drop across Rn above ground." }, { "rule": "headroom", "of": [ "Rp", "M4" ], "constraint": "Ib·Rp > V_DSAT,4", "why": "The load cascode's gate sits Ib·Rp below the diode's, so Ib·Rp is what M4 is left across it: less and the load stops being a current source, more and it only narrows the window." }, { "rule": "headroom", "of": [ "Rn", "M1" ], "constraint": "Ib/2·Rn > V_DSAT,1", "why": "Likewise M1's V_DS: Rn sets how far above ground the NMOS cascode holds M1's drain." }, { "rule": "window", "of": [ "M2", "M3" ], "constraint": "Ib/2·Rn + V_DSAT,2 < V_out < V_DD - Ib·Rp - V_DSAT,3", "why": "Both cascodes must stay saturated for the gain to hold: this is the output range. Its top is the PMOS ladder's and moves with V_DD, so the bias level is set below V_DD (VOB), in the window's middle." } ], "specs": [ { "key": "gain_db", "label": "Gain at the bias point", "unit": "dB", "direction": "max", "constraint": ">= 54 dB", "min": 54, "max": null, "why": "Two cascodes promise the square of a device's intrinsic gain; the NMOS side, the weaker, gives about 59 dB at these lengths, and 125 °C takes 4 dB of it: 54 dB holds at every corner." }, { "key": "out_span", "label": "Output range", "unit": "V", "direction": "max", "constraint": ">= 0.15 V", "min": 0.15, "max": null, "why": "The gain is bought with headroom: four devices share 1.2 V, and the window in which both cascodes hold the gain within 1 dB must stay wide enough to use - about 0.28 V at tt, never under 0.15 V at a corner." }, { "key": "ugf_hz", "label": "Unity-gain frequency", "unit": "Hz", "direction": "max", "constraint": ">= 25000000 Hz", "min": 25000000, "max": null, "why": "g_m1/2πC_L into 1 pF at 20 µA: the bandwidth the stage current buys, 30 MHz or more at every corner." }, { "key": "pm_deg", "label": "Phase margin", "unit": "deg", "direction": "max", "constraint": ">= 60 deg", "min": 60, "max": null, "why": "The pole at the cascode's source must stay well above the unity-gain frequency for the stage to be usable in a loop: a longer or wider M2 buys gain with it." }, { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.000045 A", "min": null, "max": 0.000045, "why": "N·Ib in the stage, Ib in the PMOS ladder and Ib/2 in the NMOS one: 3.5 Ib, set by copies, whatever the corner." } ], "explanation": { "idea": "This amplifier stacks extra transistors above its input device and below its current-source load. They hold internal voltages steadier, raising output resistance and voltage gain. The extra devices need voltage headroom, so the output has less room to swing.", "detail": "The input transistor converts voltage to current. Cascodes raise the effective resistance of both output branches, so their parallel combination gives a larger voltage gain. A feedback loop is needed to set the high-gain stage's DC operating point; the testbench supplies that loop.", "lesson": { "relation": 2, "symbols": "A_v is voltage gain; g_m1 is input-device transconductance in siemens. R_out,n and R_out,p are the effective NMOS and PMOS branch resistances in ohms; ∥ means parallel combination.", "assumptions": "Low-frequency small-signal estimate with all devices in saturation. Each cascode-resistance estimate assumes appreciable device gain.", "exercise": { "param": "CL", "value": 2e-12, "analysis": "ac", "expect": "A heavier capacitive load should lower the unity-gain frequency. Compare phase margin as well as gain, because the internal poles remain." }, "limits": "Provide the reference current and a DC feedback path. The allowed output window is narrower than the supply rails and changes with operating conditions." }, "path": [ { "part": "Input device", "devices": "M1", "does": "Common source: in sets its drain current, and g_m1 is the stage's transconductance. It is long, 2 µm, so that r_o1 - the resistance the NMOS cascode multiplies - is high." }, { "part": "NMOS cascode", "devices": "M2", "does": "Common gate, from nc: it passes M1's current to out while holding x, M1's drain, still, which multiplies r_o1 by g_m2 r_o2." }, { "part": "Load", "devices": "M4, M3", "does": "M4 sources N copies of the reference into y; M3, its cascode, with its gate on ib, holds y still and raises the load's output resistance the same way." }, { "part": "PMOS ladder", "devices": "MB, Rp", "does": "Ib, drawn out of the ib pin, flows through the diode MB and then Rp: pg sets M4's gate, and ib, Ib·Rp below it, sets M3's - so M4 is left about Ib·Rp across it." }, { "part": "NMOS ladder", "devices": "M5, MNb, Rn", "does": "M5 feeds Ib/2 into the diode MNb over Rn. MNb runs at M2's current density, so the two share a V_GS, and M2 holds M1's drain at the drop across Rn." } ], "bias": "The testbench draws Ib, 10 µA, out of the ib pin through MB and Rp. M4 and M3 use four PMOS units against MB's two, targeting 20 µA in the output branch; M5 targets 5 µA in the NMOS ladder. The measured total is about 34.5 µA at nominal and varies slightly across the checked corners. The testbench servo sets the input near 0.30 V at TT while holding the output 0.55 V below the supply. This bias keeps the stacked devices in saturation at the checked default conditions; it does not validate every editable setting.", "relations": [ { "what": "Output resistance, NMOS side", "expr": "R_out,n ≈ (g_m2 + g_mb2) r_o2 · r_o1", "note": "M1's r_o multiplied by the cascode's intrinsic gain: the weaker side, and so the one that sets the gain" }, { "what": "Output resistance, PMOS side", "expr": "R_out,p ≈ (g_m3 + g_mb3) r_o3 · r_o4", "note": "the load, cascoded the same way: several times R_out,n, the PMOS devices' intrinsic gain being much the higher" }, { "what": "Gain", "expr": "A_v ≈ −g_m1 (R_out,n ∥ R_out,p)", "note": "about 920 V/V, 59 dB, at tt; 125 °C lowers every g_m r_o and takes 4 dB of it" }, { "what": "Output window", "expr": "Ib/2·Rn + V_DSAT,2 < V_out < V_DD − Ib·Rp − V_DSAT,3", "note": "the output range in which both cascodes stay saturated; the 1 dB range the DC transfer reads lies inside it, about 0.51 to 0.80 V at tt" }, { "what": "Unity-gain frequency", "expr": "f_u ≈ g_m1/(2π C_L)", "note": "42 MHz into 1 pF; the bandwidth is f_u over the gain, about 48 kHz" }, { "what": "Pole at the cascode's source", "expr": "f_p2 ≈ g_m2/(2π C_x)", "note": "at x, where M2's gate-source capacitance sits: a longer or wider M2 raises the gain but pulls this pole in towards f_u, and the phase margin with it" } ], "tradeoffs": [ "NMOS lengths (L1, Lc): longer raises R_out,n and the gain, until the PMOS side takes over; a longer cascode also brings the pole at x down towards f_u - a 3 µm cascode bought 1.2 dB for 12° of phase margin.", "Ladder resistors (Rp, Rn): larger drops give M4 and M1 more V_DS and more margin at the corners, but raise the window's floor and lower its ceiling.", "Stage current (N): more raises g_m1 and f_u but lowers every r_o in proportion, so the gain barely moves while the supply current grows.", "Output bias (VOB): the window hangs from V_DD, so the bias is set below V_DD; placed outside the window, one cascode leaves saturation and the gain collapses by tens of dB." ] }, "sizing": [ { "key": "Ib", "label": "Reference current", "unit": "A", "value": 0.00001, "min": 0.000001, "max": 0.00005, "kind": "si" }, { "key": "N", "label": "Stage current, in Ib", "unit": "", "value": 2, "min": 1, "max": 8, "kind": "int" }, { "key": "W1", "label": "W input device (M1)", "unit": "m", "value": 0.000024, "min": 5e-7, "max": 0.00005, "kind": "si" }, { "key": "L1", "label": "L input device", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wc", "label": "W NMOS cascode unit (M2, MNb)", "unit": "m", "value": 0.000006, "min": 3e-7, "max": 0.00002, "kind": "si" }, { "key": "Lc", "label": "L NMOS cascode unit", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wp", "label": "W PMOS unit (MB, M3, M4, M5)", "unit": "m", "value": 0.000012, "min": 5e-7, "max": 0.00002, "kind": "si" }, { "key": "Lp", "label": "L PMOS unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Rp", "label": "PMOS ladder resistor", "unit": "Ω", "value": 28000, "min": 2000, "max": 200000, "kind": "si" }, { "key": "Rn", "label": "NMOS ladder resistor", "unit": "Ω", "value": 48000, "min": 2000, "max": 200000, "kind": "si" }, { "key": "CL", "label": "Load capacitance", "unit": "F", "value": 1e-12, "min": 1e-13, "max": 2e-11, "kind": "si" }, { "key": "VOB", "label": "Output bias, below V_DD", "unit": "V", "value": 0.55, "min": 0.3, "max": 0.9, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The stage at its bias point, the servo holding its output where it is meant to sit: the current it draws and the input that takes.", "measures": [], "metricKeys": [ "i_supply", "vin_dc", "vout_dc" ], "acceptance": [ "i_supply" ], "acceptanceRules": [ { "key": "i_supply", "unit": "A", "min": null, "max": 0.000045, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Cascode common-source stage - operating point\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 dc 10u\n.subckt cscas in out vdd vss ib\n* PMOS ladder: Ib through the diode MB and Rp; pg sets the load current, ib (pg - Ib*Rp) its cascode\nXMB pg pg vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=2\nXRp pg ib vss rhigh w=0.5u l=8.548u\n* NMOS ladder: M5 feeds Ib/2 into the diode MNb over Rn; nc = V_GS + Ib/2*Rn biases the cascode\nXM5 nc pg vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMNb nc nc nr vss sg13_lv_nmos w=6u l=2u ng=2 m=1\nXRn nr vss vss rhigh w=0.5u l=14.725u\n* the stage: M1 common source, M2 its cascode; the load M4 under its cascode M3\nXM1 x in vss vss sg13_lv_nmos w=24u l=2u ng=6 m=1\nXM2 out nc x vss sg13_lv_nmos w=6u l=2u ng=2 m=4\nXM3 out ib y vdd sg13_lv_pmos w=12u l=1u ng=4 m=4\nXM4 y pg vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4\n.ends\nXdut in out vdd 0 ib cscas\nCl out 0 1p\n* the bias: a servo moves the input, within the rails, until v(out) sits at {VDD-0.55},\n* through a 1 TH coil - open at every frequency analysed; the signal comes in through 1 TF\nVset set 0 dc {VDD-0.55}\nBsv sv 0 v=0.6+0.6*tanh(1000*(v(out)-v(set)))\nLsv sv in 1t\nCsig in sig 1t\nVsig sig 0 dc 0\n.op\n.end" }, { "id": "dc", "label": "DC transfer", "note": "The transfer traced from one rail to the other by a servo of gain one: the output against the input, the gain against the output, and the output range - how far the output moves before that gain falls 1 dB from its peak.", "measures": [], "metricKeys": [ "gain_peak_db", "out_lo", "out_hi", "out_span", "in_span" ], "acceptance": [ "out_span" ], "acceptanceRules": [ { "key": "out_span", "unit": "V", "min": 0.15, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Cascode common-source stage - DC transfer, traced by a servo of gain one\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 dc 10u\n.subckt cscas in out vdd vss ib\n* PMOS ladder: Ib through the diode MB and Rp; pg sets the load current, ib (pg - Ib*Rp) its cascode\nXMB pg pg vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=2\nXRp pg ib vss rhigh w=0.5u l=8.548u\n* NMOS ladder: M5 feeds Ib/2 into the diode MNb over Rn; nc = V_GS + Ib/2*Rn biases the cascode\nXM5 nc pg vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMNb nc nc nr vss sg13_lv_nmos w=6u l=2u ng=2 m=1\nXRn nr vss vss rhigh w=0.5u l=14.725u\n* the stage: M1 common source, M2 its cascode; the load M4 under its cascode M3\nXM1 x in vss vss sg13_lv_nmos w=24u l=2u ng=6 m=1\nXM2 out nc x vss sg13_lv_nmos w=6u l=2u ng=2 m=4\nXM3 out ib y vdd sg13_lv_pmos w=12u l=1u ng=4 m=4\nXM4 y pg vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4\n.ends\nXdut in out vdd 0 ib cscas\nCl out 0 1p\n* v(in) = v(c0) + (v(out) - v(set)) for an inverting stage, v(c0) - (v(out) - v(set)) otherwise:\n* each set point meets the transfer once, and the sweep walks along it from rail to rail\nVc c0 0 dc 400m\nVset set 0 dc 0\nEsv in c0 out set 1\n.dc Vset -300m 1.5 1m\n.end" }, { "id": "ac", "label": "Gain and bandwidth", "note": "Gain and phase at the bias point, into the circuit's load.", "measures": [], "metricKeys": [ "gain_db", "f3db_hz", "ugf_hz", "pm_deg", "peak_db" ], "acceptance": [ "gain_db", "ugf_hz", "pm_deg" ], "acceptanceRules": [ { "key": "gain_db", "unit": "dB", "min": 54, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "ugf_hz", "unit": "Hz", "min": 25000000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "pm_deg", "unit": "deg", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Cascode common-source stage - small-signal gain at the bias point\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 dc 10u\n.subckt cscas in out vdd vss ib\n* PMOS ladder: Ib through the diode MB and Rp; pg sets the load current, ib (pg - Ib*Rp) its cascode\nXMB pg pg vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=2\nXRp pg ib vss rhigh w=0.5u l=8.548u\n* NMOS ladder: M5 feeds Ib/2 into the diode MNb over Rn; nc = V_GS + Ib/2*Rn biases the cascode\nXM5 nc pg vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMNb nc nc nr vss sg13_lv_nmos w=6u l=2u ng=2 m=1\nXRn nr vss vss rhigh w=0.5u l=14.725u\n* the stage: M1 common source, M2 its cascode; the load M4 under its cascode M3\nXM1 x in vss vss sg13_lv_nmos w=24u l=2u ng=6 m=1\nXM2 out nc x vss sg13_lv_nmos w=6u l=2u ng=2 m=4\nXM3 out ib y vdd sg13_lv_pmos w=12u l=1u ng=4 m=4\nXM4 y pg vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4\n.ends\nXdut in out vdd 0 ib cscas\nCl out 0 1p\n* the bias: a servo moves the input, within the rails, until v(out) sits at {VDD-0.55},\n* through a 1 TH coil - open at every frequency analysed; the signal comes in through 1 TF\nVset set 0 dc {VDD-0.55}\nBsv sv 0 v=0.6+0.6*tanh(1000*(v(out)-v(set)))\nLsv sv in 1t\nCsig in sig 1t\nVsig sig 0 dc 0 ac 1\n.ac dec 20 1 10g\n.end" }, { "id": "rout", "label": "Output resistance", "note": "A 1 A AC current into the output with the input held at its bias: the voltage it makes is the output impedance.", "measures": [], "metricKeys": [ "rout" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Cascode common-source stage - output impedance at the bias point\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 dc 10u\n.subckt cscas in out vdd vss ib\n* PMOS ladder: Ib through the diode MB and Rp; pg sets the load current, ib (pg - Ib*Rp) its cascode\nXMB pg pg vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=2\nXRp pg ib vss rhigh w=0.5u l=8.548u\n* NMOS ladder: M5 feeds Ib/2 into the diode MNb over Rn; nc = V_GS + Ib/2*Rn biases the cascode\nXM5 nc pg vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMNb nc nc nr vss sg13_lv_nmos w=6u l=2u ng=2 m=1\nXRn nr vss vss rhigh w=0.5u l=14.725u\n* the stage: M1 common source, M2 its cascode; the load M4 under its cascode M3\nXM1 x in vss vss sg13_lv_nmos w=24u l=2u ng=6 m=1\nXM2 out nc x vss sg13_lv_nmos w=6u l=2u ng=2 m=4\nXM3 out ib y vdd sg13_lv_pmos w=12u l=1u ng=4 m=4\nXM4 y pg vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4\n.ends\nXdut in out vdd 0 ib cscas\nCl out 0 1p\n* the bias: a servo moves the input, within the rails, until v(out) sits at {VDD-0.55},\n* through a 1 TH coil - open at every frequency analysed; the signal comes in through 1 TF\nVset set 0 dc {VDD-0.55}\nBsv sv 0 v=0.6+0.6*tanh(1000*(v(out)-v(set)))\nLsv sv in 1t\nCsig in sig 1t\nVsig sig 0 dc 0\n* 1 A of AC current into the output: v(out) is the output impedance\nIout 0 out dc 0 ac 1\n.ac dec 20 1 10g\n.end" } ], "measurements": { "gain_db": { "label": "Gain at the bias point", "unit": "dB", "spec": { "min": 54, "max": null } }, "out_span": { "label": "Output range", "unit": "V", "spec": { "min": 0.15, "max": null } }, "ugf_hz": { "label": "Unity-gain frequency", "unit": "Hz", "spec": { "min": 25000000, "max": null } }, "pm_deg": { "label": "Phase margin", "unit": "deg", "spec": { "min": 60, "max": null } }, "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.000045 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "ba946515635280b20b7ab418ad7ac80461da2788ed2563f96395fdf6cb6ffe08" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/cs-cascode.js", "sha256": "3c581d59e8b170fa866a7e54e3ec41f08edd7e4a20d5a5a39dcdcf97e1b5a964" }, "simulationFingerprints": { "op": "779f9ee051bd8d4034db043fd849690e9a7746edee7fddb6b9005f31e97dd25f", "dc": "cd910ad0075b9622e906342bf0653607320cfcd379dc9abb64b7e0734b691fe9", "ac": "fe766a77711de781332c55125510f14f371c796f0e40f23f9dd666be41f26d30", "rout": "b8f1cce338987043d0e718a97f9aee4ea93bef792fbc71daf4bdb02d326ad952" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "8436f72dd0ed6bfcf426ed29365ea7028081df0d080e24d3818d1cabead851eb", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "cs-cascode", "parameters": { "Ib": 0.00001, "N": 2, "W1": 0.000024, "L1": 0.000002, "Wc": 0.000006, "Lc": 0.000002, "Wp": 0.000012, "Lp": 0.000001, "Rp": 28000, "Rn": 48000, "CL": 1e-12, "VOB": 0.55 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/cs-cascode/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "cscas", "ports": [ { "name": "in", "net": "in", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=2", "source": "XMB pg pg vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "pg" }, { "id": "g", "net": "pg" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRp", "displayName": "Rp", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=8.548u", "source": "XRp pg ib vss rhigh w=0.5u l=8.548u", "pins": [ { "id": "p", "net": "pg" }, { "id": "n", "net": "ib" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XM5 nc pg vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "nc" }, { "id": "g", "net": "pg" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMNb", "displayName": "MNb", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=6u l=2u ng=2 m=1", "source": "XMNb nc nc nr vss sg13_lv_nmos w=6u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nc" }, { "id": "g", "net": "nc" }, { "id": "s", "net": "nr" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRn", "displayName": "Rn", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=14.725u", "source": "XRn nr vss vss rhigh w=0.5u l=14.725u", "pins": [ { "id": "p", "net": "nr" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=24u l=2u ng=6 m=1", "source": "XM1 x in vss vss sg13_lv_nmos w=24u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "in" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=6u l=2u ng=2 m=4", "source": "XM2 out nc x vss sg13_lv_nmos w=6u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "nc" }, { "id": "s", "net": "x" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=4", "source": "XM3 out ib y vdd sg13_lv_pmos w=12u l=1u ng=4 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "y" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=4", "source": "XM4 y pg vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4", "pins": [ { "id": "d", "net": "y" }, { "id": "g", "net": "pg" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "pg", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XRp", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "XRp", "pin": "n" }, { "device": "XM3", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRp", "pin": "substrate" }, { "device": "XMNb", "pin": "b" }, { "device": "XRn", "pin": "n" }, { "device": "XRn", "pin": "substrate" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "nc", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XMNb", "pin": "d" }, { "device": "XMNb", "pin": "g" }, { "device": "XM2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "nr", "ground": false, "terminals": [ { "device": "XMNb", "pin": "s" }, { "device": "XRn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "in", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "in" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM3", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "y", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM4", "pin": "d" } ], "ports": [], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 10u", "source": "Ib ib 0 dc 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "cscas", "parametersOrValue": "", "source": "Xdut in out vdd 0 ib cscas", "pins": [ { "id": "in", "net": "in" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/cscas" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "1p", "source": "Cl out 0 1p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vset", "displayName": "Vset", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD-0.55}", "source": "Vset set 0 dc {VDD-0.55}", "pins": [ { "id": "p", "net": "set" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bsv", "displayName": "Bsv", "spiceType": "B", "model": null, "parametersOrValue": "v=0.6+0.6*tanh(1000*(v(out)-v(set)))", "source": "Bsv sv 0 v=0.6+0.6*tanh(1000*(v(out)-v(set)))", "pins": [ { "id": "p", "net": "sv" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "out", "set" ], "currentDevices": [] } }, { "id": "Lsv", "displayName": "Lsv", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lsv sv in 1t", "pins": [ { "id": "p", "net": "sv" }, { "id": "n", "net": "in" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Csig", "displayName": "Csig", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Csig in sig 1t", "pins": [ { "id": "p", "net": "in" }, { "id": "n", "net": "sig" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vsig", "displayName": "Vsig", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vsig sig 0 dc 0", "pins": [ { "id": "p", "net": "sig" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", 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"voltageReferences": [] }, { "id": "sig", "ground": false, "terminals": [ { "device": "Csig", "pin": "n" }, { "device": "Vsig", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/cscas", "name": "cscas", "ports": [ { "name": "in", "net": "in" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=2", "source": "XMB pg pg vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "pg" }, { "id": "g", "net": "pg" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRp", "displayName": "Rp", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=8.548u", "source": "XRp pg ib vss rhigh w=0.5u l=8.548u", "pins": [ { "id": "p", "net": "pg" }, { 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