{
  "schema": "aisic.circuit/1",
  "entryType": "library-block",
  "domain": "analog",
  "id": "current-mirror",
  "name": "NMOS current mirror",
  "group": "Mirrors, bias and references",
  "subgroup": "Current mirrors",
  "title": "NMOS current mirror",
  "summary": "Copies a reference current into an output branch. Two transistors share a gate voltage; repeated unit devices set the current ratio. The output needs enough voltage to work, and its current still changes with drain voltage and device mismatch.",
  "reference": {
    "kind": "book",
    "authors": "B. Razavi",
    "title": "Design of Analog CMOS Integrated Circuits",
    "edition": "2nd ed.",
    "publisher": "McGraw-Hill",
    "year": 2017,
    "where": "Current Mirrors - the simple MOS mirror, its copy accuracy and its output resistance",
    "takes": "The topology, and the result that the copy error is channel-length modulation rather than mismatch when the two devices are identical."
  },
  "resources": {
    "record": "/circuits/current-mirror.json",
    "page": "/index.html#current-mirror",
    "achieved": "/achieved/current-mirror.json",
    "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.",
    "modelCards": [
      {
        "name": "sg13g2_lv_tt.spice",
        "url": "/sg13g2_lv_tt.spice",
        "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a"
      }
    ],
    "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.",
    "schema": "/schemas/circuit.schema.json"
  },
  "specificationPolicy": {
    "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.",
    "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.",
    "scopes": {
      "nominal": {
        "corner": "tt",
        "temp": 27,
        "vdd": 1,
        "temperatureUnit": "degC",
        "supplyMeaning": "scale of the bench's nominal supply"
      }
    },
    "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim."
  },
  "corners": {
    "cards": "a deck's sg13g2_<family>_tt.spice (family lv, hv, passive, hbt) becomes sg13g2_<family>_<corner>.spice",
    "process": [
      "tt",
      "ss",
      "ff",
      "sf",
      "fs"
    ],
    "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise",
    "temperatures": [
      -40,
      27,
      125
    ],
    "supplyScale": [
      0.9,
      1,
      1.1
    ],
    "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it",
    "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw",
    "sets": {
      "essential": [
        {
          "corner": "tt",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "ss",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "ff",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "sf",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "fs",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "tt",
          "temp": -40,
          "vdd": 1
        },
        {
          "corner": "tt",
          "temp": 125,
          "vdd": 1
        },
        {
          "corner": "tt",
          "temp": 27,
          "vdd": 0.9
        },
        {
          "corner": "tt",
          "temp": 27,
          "vdd": 1.1
        },
        {
          "corner": "ss",
          "temp": 125,
          "vdd": 0.9
        },
        {
          "corner": "ff",
          "temp": -40,
          "vdd": 1.1
        }
      ],
      "full": "all 45 combinations"
    },
    "montecarlo": {
      "cards": {
        "mc": "process and mismatch",
        "mcmm": "mismatch only",
        "mcproc": "process only"
      },
      "seed": "draw k adds .options seed=k, so draws are reproducible"
    }
  },
  "technology": {
    "id": "sg13g2",
    "name": "IHP SG13G2",
    "node": "130 nm",
    "corner": "tt",
    "vdd": 1.2,
    "lmin": 1.3e-7,
    "wmin": 1.5e-7,
    "models": "sg13g2_lv_tt.spice",
    "devices": {
      "nmos": "sg13_lv_nmos",
      "pmos": "sg13_lv_pmos",
      "resistor": "rppd, rhigh",
      "capacitor": "cap_cmim"
    },
    "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.",
    "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF."
  },
  "implementation": {
    "kind": "physical-device-reference",
    "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.",
    "evidence": "schematic-simulation",
    "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.",
    "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.",
    "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification."
  },
  "cards": [
    "sg13g2_lv_tt.spice"
  ],
  "ports": [
    {
      "name": "ref",
      "kind": "input",
      "note": "diode-connected, carries I_ref"
    },
    {
      "name": "out",
      "kind": "output"
    },
    {
      "name": "vdd",
      "kind": "supply"
    },
    {
      "name": "0",
      "kind": "ground"
    }
  ],
  "devices": [
    {
      "name": "M1",
      "type": "nmos",
      "nodes": "ref ref 0 0",
      "sizedBy": [
        "W",
        "L"
      ],
      "role": "reference, diode-connected",
      "fingers": 1,
      "copies": 1
    },
    {
      "name": "M2",
      "type": "nmos",
      "nodes": "out ref 0 0",
      "sizedBy": [
        "W",
        "L",
        "ratio"
      ],
      "role": "output, m = ratio parallel copies of M1",
      "fingers": 1,
      "copies": 1
    }
  ],
  "intent": [
    {
      "rule": "same-length",
      "of": [
        "M1",
        "M2"
      ],
      "why": "The copy ratio is W2/W1 only while both share a length. With different lengths it is not even (W/L)2/(W/L)1: threshold and output conductance both depend on L, and a 4/4 um device copying this 2/2 um one delivers 1.25x instead of 1x."
    },
    {
      "rule": "unit-devices",
      "of": [
        "M2"
      ],
      "expr": "I_out/I_ref = m, with M2 as m parallel copies of M1",
      "why": "The ratio is built from parallel unit devices, not from one wider device. That is what a layout does for matching, and in SG13G2 it is also what makes the ratio right at all: a narrow device has a higher threshold than a wide one, so where four copies of the 2/2 um device deliver 4.11x, one 8 um device delivers 5.00x. Unit copies share nominal geometry-dependent behavior; random threshold mismatch remains."
    },
    {
      "rule": "region",
      "of": [
        "M1",
        "M2"
      ],
      "constraint": "saturation",
      "why": "Below the compliance voltage M2 enters triode and stops being a current source. That knee is the number this bench measures."
    }
  ],
  "specs": [
    {
      "key": "iout",
      "label": "Output current",
      "unit": "A",
      "direction": "target"
    },
    {
      "key": "err",
      "label": "Copy error",
      "unit": "%",
      "direction": "min"
    },
    {
      "key": "vmin",
      "label": "Compliance voltage",
      "unit": "V",
      "direction": "min"
    },
    {
      "key": "rout",
      "label": "Output resistance",
      "unit": "Ω",
      "direction": "max"
    }
  ],
  "explanation": {
    "idea": "Copies a reference current into an output branch. Two transistors share a gate voltage; repeated unit devices set the current ratio. The output needs enough voltage to work, and its current still changes with drain voltage and device mismatch.",
    "detail": "Copies a reference current, a common building block of bias networks. M1 is diode-connected, so I_ref settles it at the V_GS that carries I_ref; M2 shares that gate voltage and, built as m copies of M1, approximately carries m·I_ref while saturated. In the nominal matched model, unequal drain voltages cause systematic copy error: M1's drain sits at V_GS1, M2's at V_out, and the output current slopes with the difference.",
    "lesson": {
      "relation": 0,
      "symbols": "I_out is output current; I_ref is reference current; m is the unit-copy count; λ models drain-voltage sensitivity; V_out is output voltage; V_GS1 is M1's gate-source voltage.",
      "assumptions": "A first-order, long-channel model with matched unit devices in saturation. The expression omits random mismatch and other real-device effects.",
      "exercise": {
        "param": "ratio",
        "value": 2,
        "analysis": "dc",
        "expect": "The output current should approximately double. Each output unit sees the same gate voltage, while the total output resistance decreases."
      },
      "limits": "This is a current sink, not a complete bias generator. Supply the reference current externally and keep the output above its compliance voltage."
    },
    "path": [
      {
        "part": "Reference diode",
        "devices": "M1",
        "does": "I_ref flows into its drain, tied to its gate, so it settles at the V_GS that carries exactly I_ref."
      },
      {
        "part": "Output copy",
        "devices": "M2",
        "does": "Same gate voltage and m parallel copies of M1, so it approximately sinks m·I_ref from out while saturated; below the compliance voltage it enters triode."
      }
    ],
    "bias": "I_ref (10 µA by default) sets V_GS1 through the diode; M2 copies it as m·I_ref, with m the mirror ratio, and repeated unit geometry supports matching, but drain-voltage differences and random mismatch leave copy error.",
    "relations": [
      {
        "what": "Copy ratio",
        "expr": "I_out/I_ref ≈ m (1 + λ V_out) / (1 + λ V_GS1)",
        "note": "a first-order nominal model; equal drain voltages remove this systematic term, not random device mismatch"
      },
      {
        "what": "Output resistance",
        "expr": "R_out = r_o2 ≈ 1 / (λ I_out)",
        "note": "the slope of the flat part of the curve; λ falls roughly as 1/L"
      },
      {
        "what": "Compliance voltage",
        "expr": "V_out,min ≈ V_GS1 − V_TH = V_ov",
        "note": "below it M2 leaves saturation and stops being a current source"
      },
      {
        "what": "Diode voltage",
        "expr": "V_GS1 ≈ V_TH + √(2 I_ref / (µ_n C_ox W/L))",
        "note": "square law; at the default 2 µm/2 µm and 10 µA the devices sit at the edge of strong inversion, V_ov ≈ 0.24 V"
      }
    ],
    "tradeoffs": [
      "L: longer lowers λ, so copy error falls and R_out rises, at the cost of area and a larger V_ov, which raises the compliance voltage.",
      "W: wider lowers V_ov and with it the compliance voltage, at more area and capacitance.",
      "I_ref: more current raises V_ov and the compliance voltage, and lowers R_out, which falls as 1/I_out.",
      "Mirror ratio (unit devices): m unit copies approximately deliver m·I_ref without changing nominal unit geometry; R_out falls as 1/m."
    ]
  },
  "sizing": [
    {
      "key": "Iref",
      "label": "I_ref",
      "unit": "A",
      "value": 0.00001,
      "min": 1e-7,
      "max": 0.001,
      "kind": "si"
    },
    {
      "key": "W",
      "label": "W",
      "unit": "m",
      "value": 0.000002,
      "min": 1.5e-7,
      "max": 0.0001,
      "kind": "si"
    },
    {
      "key": "L",
      "label": "L",
      "unit": "m",
      "value": 0.000002,
      "min": 1.3e-7,
      "max": 0.00001,
      "kind": "si"
    },
    {
      "key": "ratio",
      "label": "Mirror ratio (unit devices)",
      "unit": "",
      "value": 1,
      "min": 1,
      "max": 8,
      "kind": "int"
    }
  ],
  "testbenches": [
    {
      "id": "dc",
      "label": "Output characteristic",
      "note": "",
      "measures": [
        "iout",
        "err",
        "vmin",
        "rout"
      ],
      "metricKeys": [
        "iout",
        "err",
        "vmin",
        "rout"
      ],
      "acceptance": [],
      "acceptanceRules": [],
      "cards": [
        "sg13g2_lv_tt.spice"
      ],
      "netlist": "* NMOS current mirror - output current against output voltage\n.include sg13g2_lv_tt.spice\nVdd vdd 0 1.2\nIref vdd ref 10u\nXM1 ref ref 0 0 sg13_lv_nmos w=2u l=2u ng=1 m=1\nXM2 out ref 0 0 sg13_lv_nmos w=2u l=2u ng=1 m=1\nVout out 0 0\n.dc Vout 0 1.2 0.005\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc iout FIND i(Vout) AT=600m\n.end"
    }
  ],
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    "generated": [
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    ],
    "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.",
    "sha256": "a2df69b4cdad5f2f429e3d0ad12c4c8e058ac95a75bf3a1cb5a8d18c31db4f49"
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    "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification."
  },
  "revision": "ad199e7372ac65e41eaf2b2c73a2047505bb2a68a76daf96d92f17c03db9c36b",
  "diagrams": {
    "schema": "aisic.diagrams/1",
    "circuit": "current-mirror",
    "parameters": {
      "Iref": 0.00001,
      "W": 0.000002,
      "L": 0.000002,
      "ratio": 1
    },
    "parameterScope": "published-defaults",
    "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.",
    "variants": {
      "choiceParameters": [],
      "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation."
    },
    "resourceBase": "/circuits/current-mirror/",
    "graphs": [
      {
        "id": "graph-1",
        "kind": "electrical-connectivity",
        "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.",
        "root": "dut",
        "globalDefinitions": [],
        "scopes": [
          {
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                "kind": "ground"
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              {
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                "net": "out",
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            "definitions": [],
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                "model": "sg13_lv_nmos",
                "parametersOrValue": "w=2u l=2u ng=1 m=1",
                "source": "XM1 ref ref 0 0 sg13_lv_nmos w=2u l=2u ng=1 m=1",
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              },
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        "id": "graph-2",
        "kind": "electrical-connectivity",
        "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.",
        "root": "top",
        "globalDefinitions": [],
        "scopes": [
          {
            "id": "top",
            "name": "top",
            "ports": [],
            "definitions": [],
            "devices": [
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                "id": "Vdd",
                "displayName": "Vdd",
                "spiceType": "V",
                "model": null,
                "parametersOrValue": "1.2",
                "source": "Vdd vdd 0 1.2",
                "pins": [
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                    "net": "vdd"
                  },
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                    "net": "0"
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                ],
                "pinMeaning": "SPICE primitive terminal order"
              },
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                "id": "Iref",
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                "model": null,
                "parametersOrValue": "10u",
                "source": "Iref vdd ref 10u",
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                "source": "XM2 out ref 0 0 sg13_lv_nmos w=2u l=2u ng=1 m=1",
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                "id": "ref",
                "ground": false,
                "terminals": [
                  {
                    "device": "Iref",
                    "pin": "n"
                  },
                  {
                    "device": "XM1",
                    "pin": "d"
                  },
                  {
                    "device": "XM1",
                    "pin": "g"
                  },
                  {
                    "device": "XM2",
                    "pin": "g"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "out",
                "ground": false,
                "terminals": [
                  {
                    "device": "XM2",
                    "pin": "d"
                  },
                  {
                    "device": "Vout",
                    "pin": "p"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              }
            ]
          }
        ],
        "uninstantiatedDefinitions": [],
        "dut": {
          "kind": "top-level-device-set",
          "scope": "top",
          "devices": [
            "XM1",
            "XM2"
          ]
        }
      },
      {
        "id": "graph-3",
        "kind": "functional-graph",
        "classification": "heuristic-device-grouping",
        "electricalScope": "dut",
        "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.",
        "nodes": [
          {
            "id": "block-1",
            "label": "Reference",
            "devices": [
              {
                "scope": "dut",
                "device": "XM1"
              }
            ],
            "inferredStages": [
              1
            ]
          },
          {
            "id": "block-2",
            "label": "Output",
            "devices": [
              {
                "scope": "dut",
                "device": "XM2"
              }
            ],
            "inferredStages": [
              1
            ]
          }
        ],
        "edges": [
          {
            "id": "net-1",
            "net": "ref",
            "nodes": [
              "block-1",
              "block-2"
            ],
            "direction": "undirected-shared-net"
          }
        ],
        "ports": [
          {
            "name": "ref",
            "net": "ref",
            "kind": "input"
          },
          {
            "name": "gnd",
            "net": "0",
            "kind": "ground"
          },
          {
            "name": "out",
            "net": "out",
            "kind": "output"
          }
        ],
        "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes."
      }
    ],
    "views": [
      {
        "bench": "dc",
        "source": {
          "recordField": "testbenches",
          "id": "dc",
          "field": "netlist"
        },
        "schematic": {
          "graph": "graph-1",
          "svg": {
            "url": "/circuits/current-mirror/dc-schematic.svg",
            "asset": "dc-schematic.svg"
          },
          "drawingCheck": {
            "method": "checkSchematic",
            "problems": []
          },
          "sheets": [
            {
              "name": "NMOS current mirror",
              "instances": []
            }
          ]
        },
        "benchDiagram": {
          "graph": "graph-2",
          "svg": {
            "url": "/circuits/current-mirror/dc-bench.svg",
            "asset": "dc-bench.svg"
          }
        },
        "blockDiagram": {
          "graph": "graph-3",
          "electricalGraph": "graph-1",
          "svg": {
            "url": "/circuits/current-mirror/dc-block.svg",
            "asset": "dc-block.svg"
          }
        }
      }
    ]
  }
}