{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "diff-pair-degenerated", "name": "Differential pair with source degeneration", "group": "Amplifier stages", "subgroup": "Differential pairs", "title": "Differential pair with source degeneration", "summary": "A differential amplifier with a resistor between its input transistors' sources. The resistor opposes current changes, reducing gain but extending the linear input range. Separate tail sources keep this resistor out of the balanced common-mode current path; matching and voltage headroom still matter.", "reference": { "kind": "book", "authors": "B. Razavi", "title": "Design of Analog CMOS Integrated Circuits", "edition": "2nd ed.", "publisher": "McGraw-Hill", "year": 2016, "where": "Sec. 4.2 'Basic Differential Pair' (p. 103), Secs. 4.2.1-4.2.2 qualitative and quantitative analysis (pp. 104, 106)", "takes": "The resistively loaded NMOS pair and its large-signal analysis: the pair steers its tail current fully within a few overdrives. To that it adds the standard remedy, degeneration by a resistor between the sources, which trades gain for the range over which the pair is linear. The split tail and the sizing are this library's, for SG13G2 at 1.2 V." }, "resources": { "record": "/circuits/diff-pair-degenerated.json", "page": "/index.html#diff-pair-degenerated", "achieved": "/achieved/diff-pair-degenerated.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "inp", "kind": "input", "polarity": "+" }, { "name": "inn", "kind": "input", "polarity": "-" }, { "name": "outp", "kind": "output" }, { "name": "outn", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the reference current, fed into this pin" } ], "devices": [ { "name": "MB", "type": "nmos", "nodes": "ib ib vss vss", "sizedBy": [ "Wt", "Lt" ], "role": "bias reference, diode-connected", "fingers": 2, "copies": 1 }, { "name": "MT1", "type": "nmos", "nodes": "s1 ib vss vss", "sizedBy": [ "Wt", "Lt", "N" ], "role": "tail source, N copies of MB", "fingers": 2, "copies": 2 }, { "name": "MT2", "type": "nmos", "nodes": "s2 ib vss vss", "sizedBy": [ "Wt", "Lt", "N" ], "role": "tail source, N copies of MB", "fingers": 2, "copies": 2 }, { "name": "M1", "type": "nmos", "nodes": "outn inp s1 vss", "sizedBy": [ "W", "L" ], "role": "input pair", "fingers": 2, "copies": 1 }, { "name": "M2", "type": "nmos", "nodes": "outp inn s2 vss", "sizedBy": [ "W", "L" ], "role": "input pair", "fingers": 2, "copies": 1 }, { "name": "RS", "type": "resistor", "nodes": "s1 s2", "sizedBy": [ "RS" ], "role": "degeneration" }, { "name": "RD1", "type": "resistor", "nodes": "vdd outn", "sizedBy": [ "RD" ], "role": "load" }, { "name": "RD2", "type": "resistor", "nodes": "vdd outp", "sizedBy": [ "RD" ], "role": "load" } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "The input pair: any difference between them is input offset, which the degeneration does not remove." }, { "rule": "match", "of": [ "RD1", "RD2" ], "why": "A load mismatch is offset too, and unbalances the two outputs' swing." }, { "rule": "unit-copies", "of": [ "MB", "MT1", "MT2" ], "constraint": "MT1 = MT2 = N copies of MB", "why": "The two tails must carry the same current: any difference flows through RS at balance and appears as offset." }, { "rule": "degeneration", "of": [ "RS", "M1", "M2" ], "constraint": "A_d = g_m R_D/(1 + g_m R_S/2)", "why": "With g_m R_S/2 well above one the gain approaches 2R_D/R_S, a ratio of resistors, and the linear range stretches to about N·Ib·R_S: both are set by RS." }, { "rule": "split-tail", "of": [ "MT1", "MT2", "RS" ], "constraint": "RS between the sources, not in series with one tail", "why": "No common-mode current crosses RS, so it costs no headroom: each tail keeps the V_DS it would have without it." }, { "rule": "headroom", "of": [ "RD1", "RD2", "M1", "M2" ], "constraint": "V_DD - N·Ib·R_D - |v_od|/2 > V_CM + |v_id|/2 - V_TH", "why": "The loads' drop, and the output's swing below it, must leave the pair saturated at the input common mode." } ], "specs": [ { "key": "gain_db", "label": "Gain at the bias point", "unit": "dB", "direction": "target", "constraint": ">= 4 dB, <= 7.5 dB", "min": 4, "max": 7.5, "why": "The gain the degeneration leaves, g_m R_D/(1 + g_m R_S/2): about 1.9 V/V, and less at 125 °C, where g_m falls. A window, not a floor - more gain would mean less degeneration, and with it less of the range the circuit is for." }, { "key": "in_span", "label": "Input range", "unit": "V", "direction": "max", "constraint": ">= 0.35 V", "min": 0.35, "max": null, "why": "The point of the circuit: the differential input over which the gain holds within 1 dB - about 0.5 V, where the same pair without RS holds it over 0.14 V." }, { "key": "out_span", "label": "Output range", "unit": "V", "direction": "max", "constraint": ">= 0.6 V", "min": 0.6, "max": null, "why": "The differential output swing inside that range: the loads' drop and the pair's headroom at the input common mode decide it." }, { "key": "f3db_hz", "label": "Bandwidth, -3 dB", "unit": "Hz", "direction": "max", "constraint": ">= 12000000 Hz", "min": 12000000, "max": null, "why": "R_D against 0.5 pF on each output: the load resistor sets both the gain and the pole." }, { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.00006 A", "min": null, "max": 0.00006, "why": "(2N + 1)·Ib: both tails and the reference." } ], "explanation": { "idea": "This differential amplifier adds a resistor between the input transistors' sources. The resistor opposes changes in their current, making the response more linear over a wider input range. The trade-off is lower gain, with a stronger dependence on resistor ratios than on transistor gain.", "detail": "Separate tail sources keep the degeneration resistor out of the balanced common-mode current path. Differential current develops a voltage across RS that subtracts from the gate drive. When g_m R_S/2 is large, differential gain approaches 2R_D/R_S; finite transistor gain and headroom limit that approximation.", "lesson": { "relation": 0, "symbols": "A_d is differential voltage gain; v_outp, v_outn, v_inp and v_inn are the output and input voltages. g_m is one input device's transconductance in siemens; R_D is each load resistance and R_S the source-to-source resistance, in ohms.", "assumptions": "Small-signal matched-pair estimate with high-resistance tail sources and sufficient headroom. Neglects body effect and finite device output resistance.", "exercise": { "param": "RS", "value": 24000, "analysis": "dc", "expect": "More degeneration should reduce gain and extend the approximately linear input region. Check where voltage headroom eventually limits the improvement." }, "limits": "The bench supplies the reference current. Resistor and tail-source mismatch still create offset; degeneration does not remove voltage-headroom limits." }, "path": [ { "part": "Tail sources", "devices": "MB, MT1, MT2", "does": "Ib, fed into the ib pin, sets the diode MB; MT1 and MT2, N copies each, sink N·Ib from each side's source." }, { "part": "Input pair", "devices": "M1, M2", "does": "inp drives M1 and inn drives M2; their difference steers current through RS from one source to the other." }, { "part": "Degeneration", "devices": "RS", "does": "Between s1 and s2 it carries the steered current, so its drop takes up most of the input and each device's V_GS moves little - which is what keeps the pair linear." }, { "part": "Loads", "devices": "RD1, RD2", "does": "From vdd to outn, M1's drain, and to outp, M2's: outp rises as inp rises." } ], "bias": "Ib, 10 µA, flows into the diode MB, and MT1 and MT2 each sink 20 µA from their side: 49 µA from the supply in all. With both inputs at 0.6 V the sources sit near 0.27 V, leaving each tail about 0.14 V above its V_DSAT, and both outputs sit 20 µA × 19.5 kΩ below V_DD, near 0.82 V. All three resistors are p+ poly: a material that moves little with temperature, and one they share, so the gain - a ratio of them, nearly - holds across the corners.", "relations": [ { "what": "Differential gain", "expr": "A_d = (v_outp − v_outn)/(v_inp − v_inn) ≈ g_m R_D/(1 + g_m R_S/2)", "note": "g_m of one device: about 1.9 V/V at tt, where the same pair without RS gives 5" }, { "what": "Linear range", "expr": "|v_id| ≲ N·Ib·R_S", "note": "the current RS can carry is at most one tail's; the gain holds within 1 dB over about ±0.26 V, against ±70 mV without RS" }, { "what": "Output common mode", "expr": "V_out,CM = V_DD − N·Ib·R_D", "note": "it moves one for one with V_DD: the loads hang from it" }, { "what": "Headroom", "expr": "V_DD − N·Ib·R_D − |v_od|/2 > V_CM + |v_id|/2 − V_TH", "note": "the output that falls must leave its device saturated: at a low supply this, more than RS, ends the range" } ], "tradeoffs": [ "Degeneration (RS): more widens the linear range and makes the gain a ratio of resistors, less sensitive to g_m's drift with temperature; the gain falls with it.", "Loads (RD): more gain, but the outputs sit lower and the falling one reaches its device's triode edge sooner; above 20 kΩ the resistors would be high-resistance poly, whose ratio to RS drifts by a third over temperature.", "Tail current (N): more g_m and a wider range, N·Ib·R_S, at more power and more drop across the loads.", "Split tail: two sources keep RS out of the common-mode path, so it costs no headroom - at the price of a second device, whose mismatch with the first flows through RS as offset." ] }, "sizing": [ { "key": "Ib", "label": "Reference current", "unit": "A", "value": 0.00001, "min": 0.000001, "max": 0.00005, "kind": "si" }, { "key": "N", "label": "Current per side, in Ib", "unit": "", "value": 2, "min": 1, "max": 10, "kind": "int" }, { "key": "W", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.00001, "min": 5e-7, "max": 0.00005, "kind": "si" }, { "key": "L", "label": "L input pair", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wt", "label": "W tail unit (MB, MT1, MT2)", "unit": "m", "value": 0.000008, "min": 5e-7, "max": 0.00002, "kind": "si" }, { "key": "Lt", "label": "L tail unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "RS", "label": "Degeneration resistor", "unit": "Ω", "value": 12000, "min": 200, "max": 100000, "kind": "si" }, { "key": "RD", "label": "Load resistors", "unit": "Ω", "value": 19500, "min": 1000, "max": 100000, "kind": "si" }, { "key": "CL", "label": "Load capacitance, each output", "unit": "F", "value": 5e-13, "min": 5e-14, "max": 1e-11, "kind": "si" }, { "key": "VCM", "label": "Input common mode", "unit": "V", "value": 0.6, "min": 0.5, "max": 1, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The pair with both inputs at their common mode: the current it draws and where its outputs sit.", "measures": [], "metricKeys": [ "i_supply", "vocm", "vod" ], "acceptance": [ "i_supply" ], "acceptanceRules": [ { "key": "i_supply", "unit": "A", "min": null, "max": 0.00006, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Differential pair with source degeneration - operating point\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb vdd ib dc 10u\n.subckt dpdeg inp inn outp outn vdd vss ib\n* the tail: Ib into the diode MB, copied N times into each side's source\nXMB ib ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXMT1 s1 ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=2\nXMT2 s2 ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=2\n* the pair: outn falls as inp rises, outp rises\nXM1 outn inp s1 vss sg13_lv_nmos w=10u l=500n ng=2 m=1\nXM2 outp inn s2 vss sg13_lv_nmos w=10u l=500n ng=2 m=1\n* degeneration between the two sources\nXRS s1 s2 vss rppd w=0.5u l=23.355u\n* the loads\nXRD1 vdd outn vss rppd w=0.5u l=38.124u\nXRD2 vdd outp vss rppd w=0.5u l=38.124u\n.ends\nXdut inp inn outp outn vdd 0 ib dpdeg\nClp outp 0 500f\nCln outn 0 500f\nVcm cm 0 dc 600m\nVid id 0 dc 0\n* the differential input split evenly either side of the common mode\nEinp inp cm id 0 0.5\nEinn inn cm id 0 -0.5\n.op\n.end" }, { "id": "dc", "label": "DC transfer", "note": "The differential input swept either side of balance at a fixed common mode: both outputs, the gain along the way, and how far the output swings before that gain falls 1 dB.", "measures": [], "metricKeys": [ "gain_peak_db", "out_span", "in_span" ], "acceptance": [ "out_span", "in_span" ], "acceptanceRules": [ { "key": "out_span", "unit": "V", "min": 0.6, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "in_span", "unit": "V", "min": 0.35, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Differential pair with source degeneration - DC transfer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb vdd ib dc 10u\n.subckt dpdeg inp inn outp outn vdd vss ib\n* the tail: Ib into the diode MB, copied N times into each side's source\nXMB ib ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXMT1 s1 ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=2\nXMT2 s2 ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=2\n* the pair: outn falls as inp rises, outp rises\nXM1 outn inp s1 vss sg13_lv_nmos w=10u l=500n ng=2 m=1\nXM2 outp inn s2 vss sg13_lv_nmos w=10u l=500n ng=2 m=1\n* degeneration between the two sources\nXRS s1 s2 vss rppd w=0.5u l=23.355u\n* the loads\nXRD1 vdd outn vss rppd w=0.5u l=38.124u\nXRD2 vdd outp vss rppd w=0.5u l=38.124u\n.ends\nXdut inp inn outp outn vdd 0 ib dpdeg\nClp outp 0 500f\nCln outn 0 500f\nVcm cm 0 dc 600m\nVid id 0 dc 0\nEinp inp cm id 0 0.5\nEinn inn cm id 0 -0.5\n.dc Vid -600m 600m 2m\n.end" }, { "id": "ac", "label": "Gain and bandwidth", "note": "Gain and phase at the bias point, into the circuit's load.", "measures": [], "metricKeys": [ "gain_db", "f3db_hz", "ugf_hz", "pm_deg", "peak_db" ], "acceptance": [ "gain_db", "f3db_hz" ], "acceptanceRules": [ { "key": "gain_db", "unit": "dB", "min": 4, "max": 7.5, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "f3db_hz", "unit": "Hz", "min": 12000000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Differential pair with source degeneration - small-signal gain at the bias point\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb vdd ib dc 10u\n.subckt dpdeg inp inn outp outn vdd vss ib\n* the tail: Ib into the diode MB, copied N times into each side's source\nXMB ib ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXMT1 s1 ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=2\nXMT2 s2 ib vss vss sg13_lv_nmos w=8u l=1u ng=2 m=2\n* the pair: outn falls as inp rises, outp rises\nXM1 outn inp s1 vss sg13_lv_nmos w=10u l=500n ng=2 m=1\nXM2 outp inn s2 vss sg13_lv_nmos w=10u l=500n ng=2 m=1\n* degeneration between the two sources\nXRS s1 s2 vss rppd w=0.5u l=23.355u\n* the loads\nXRD1 vdd outn vss rppd w=0.5u l=38.124u\nXRD2 vdd outp vss rppd w=0.5u l=38.124u\n.ends\nXdut inp inn outp outn vdd 0 ib dpdeg\nClp outp 0 500f\nCln outn 0 500f\nVcm cm 0 dc 600m\nVid id 0 dc 0 ac 1\n* the differential input split evenly either side of the common mode\nEinp inp cm id 0 0.5\nEinn inn cm id 0 -0.5\n.ac dec 20 1 10g\n.end" } ], "measurements": { "gain_db": { "label": "Gain at the bias point", "unit": "dB", "spec": { "min": 4, "max": 7.5 } }, "in_span": { "label": "Input range", "unit": "V", "spec": { "min": 0.35, "max": null } }, "out_span": { "label": "Output range", "unit": "V", "spec": { "min": 0.6, "max": null } }, "f3db_hz": { "label": "Bandwidth, -3 dB", "unit": "Hz", "spec": { "min": 12000000, "max": null } }, "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.00006 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "c5511f15876dcf4d0dc13ad8380c58bc74ef0ed5308afe2ead1d2b299b790877" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/diff-pair-degenerated.js", "sha256": "d9ed189dab28f07d1d9799a11b02b4e9cc25dc34216e58bb7403e873b48ceac8" }, "simulationFingerprints": { "op": "89db024225408be90856471b298ac2a0a9c1317c7764c765d2926eef9dd68101", "dc": "a78691e446d1b7ac64ebe5bdd7d8f5a126d14e9bae49041ff19dd759cc291f42", "ac": "a18597ce08154eaa017ac8b39907420c0e36d20a4a8079f01cfaf68876243fb7" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "351f636f07afcae6a68a2cd5422c40e9e5cfdb630059363e84982d8520f7b6b5", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "diff-pair-degenerated", "parameters": { "Ib": 0.00001, "N": 2, "W": 0.00001, "L": 5e-7, "Wt": 0.000008, "Lt": 0.000001, "RS": 12000, "RD": 19500, "CL": 5e-13, "VCM": 0.6 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/diff-pair-degenerated/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. 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