{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "diff-pair", "name": "Differential pair", "group": "Amplifier stages", "subgroup": "Differential pairs", "title": "Differential pair", "summary": "Two transistors share a current and respond to the difference between their input voltages. Resistors turn the current imbalance into output voltages. The sweep shows the nearly linear region around balance and how a larger input steers current into one side.", "reference": { "kind": "book", "authors": "B. Razavi", "title": "Design of Analog CMOS Integrated Circuits", "edition": "2nd ed.", "publisher": "McGraw-Hill", "year": 2017, "where": "Differential Amplifiers - the basic MOS differential pair and its large-signal behaviour", "takes": "The topology and the result that the pair fully steers its tail current at a differential input of about sqrt(2)*V_ov." }, "resources": { "record": "/circuits/diff-pair.json", "page": "/index.html#diff-pair", "achieved": "/achieved/diff-pair.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "inp", "kind": "input", "polarity": "+" }, { "name": "inn", "kind": "input", "polarity": "-" }, { "name": "d1", "kind": "output" }, { "name": "d2", "kind": "output" }, { "name": "bn", "kind": "bias" }, { "name": "vdd", "kind": "supply" }, { "name": "0", "kind": "ground", "note": "NMOS substrate and tail/bias-current return" } ], "devices": [ { "name": "M1", "type": "nmos", "nodes": "d1 inp tail 0", "sizedBy": [ "W", "L" ], "role": "input pair", "fingers": 2, "copies": 1 }, { "name": "M2", "type": "nmos", "nodes": "d2 inn tail 0", "sizedBy": [ "W", "L" ], "role": "input pair", "fingers": 2, "copies": 1 }, { "name": "Rd1", "type": "resistor", "nodes": "vdd d1", "sizedBy": [ "RD" ], "role": "load" }, { "name": "Rd2", "type": "resistor", "nodes": "vdd d2", "sizedBy": [ "RD" ], "role": "load" }, { "name": "Mt", "type": "nmos", "nodes": "tail bn 0 0", "sizedBy": [ "Wt", "Lt" ], "role": "tail current source", "fingers": 4, "copies": 1 }, { "name": "Mb", "type": "nmos", "nodes": "bn bn 0 0", "sizedBy": [ "Wt", "Lt" ], "role": "bias mirror, diode-connected", "fingers": 4, "copies": 1 } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "Their mismatch creates input-referred offset unless the system provides an explicit correction such as calibration or offset cancellation." }, { "rule": "match", "of": [ "Rd1", "Rd2" ], "why": "Load mismatch is offset too, and it also unbalances the differential output swing." }, { "rule": "budget", "of": [ "Rd1", "Rd2", "Mt" ], "constraint": "I_tail/2 * R_D < VDD - V_ov - V_CM + V_th", "why": "The drain drop has to leave the input devices in saturation at the chosen common mode. Raising R_D for gain is what pushes them out of it." }, { "rule": "trade", "of": [ "Mt" ], "constraint": "in strong inversion: g_m ~ sqrt(I_tail), steering range ~ sqrt(I_tail)", "why": "More current raises transconductance. The square-root steering-range estimate assumes strong inversion; in ideal weak inversion the normalized steering curve is mainly set by thermal voltage, not tail current." }, { "rule": "headroom", "of": [ "Mt", "Mb" ], "constraint": "V_tail = V_CM - V_GS1 > V_ov(Mt)", "why": "The tail copies the reference only while it stays saturated. Lower the common mode and the tail node follows it down until Mt enters triode and the tail current, and with it g_m, collapses." } ], "specs": [ { "key": "gm", "label": "Transconductance at balance", "unit": "S", "direction": "max" }, { "key": "av", "label": "Differential gain", "unit": "V/V", "direction": "max" }, { "key": "vfull", "label": "Full-steering input", "unit": "V", "direction": "target" } ], "explanation": { "idea": "This stage amplifies the difference between two input voltages. Its transistors share a current: raising one input sends more current through that side and less through the other. Resistors turn this imbalance into output voltages; large input differences steer almost all the current to one side.", "detail": "A differential pair is a common input stage for amplifiers and comparators. Matched devices reject a shared input change while the bias devices retain enough headroom. Strong-inversion square-law estimates and weak-inversion exponential steering describe different operating regimes; neither is an exact compact-model equation.", "lesson": { "relation": 1, "symbols": "A_d is differential voltage gain in V/V; v_d1 and v_d2 are drain voltages, and v_inp and v_inn are input voltages, all in volts. g_m is one input transistor's transconductance in siemens, R_D the load resistance, and r_o its output resistance in ohms. ∥ means parallel combination.", "assumptions": "Small differential signals around balance, matched sides and transistors in saturation; the tail source is approximately constant.", "exercise": { "param": "Itail", "value": 0.00004, "analysis": "dc", "expect": "More tail current should increase transconductance but lower the drain voltages. Compare the slopes and check that neither side runs out of voltage headroom." }, "limits": "Both inputs must remain inside the common-mode range. Matching and tail-source headroom matter; a balanced schematic does not eliminate physical offset." }, "path": [ { "part": "Tail mirror", "devices": "Mb, Mt", "does": "Mb, diode-connected, takes the testbench's I_tail; Mt copies it into the tail node the pair shares." }, { "part": "Input pair", "devices": "M1, M2", "does": "A differential input steers current between the two sides. A shared input change mainly moves the tail node; ideal matched sides keep an equal split while all devices retain headroom." }, { "part": "Loads", "devices": "Rd1, Rd2", "does": "Turn the two drain currents into voltages below V_DD; v(d2) − v(d1) is the differential output." } ], "bias": "Mt copies the testbench's I_tail (20 µA by default), each side carries half at balance, and each drain sits at V_DD − I_tail R_D/2; V_CM, 0.7 V by default, must keep the tail node high enough for Mt to stay saturated. The ground port returns the bias diode and tail current and ties the NMOS bodies.", "relations": [ { "what": "Transconductance", "expr": "g_m = √(µ_n C_ox (W/L) I_tail)", "note": "each device at balance, strong inversion; nearer weak inversion, as here, it tends to I_tail/(2 n V_T)" }, { "what": "Differential gain", "expr": "A_d = (v_d2 − v_d1) / (v_inp − v_inn) ≈ g_m (R_D ∥ r_o)", "note": "g_m R_D when r_o ≫ R_D; each output alone carries half of it" }, { "what": "Full steering", "expr": "|V_id| ≈ √2 · V_ov", "note": "strong inversion; biased nearer weak inversion, the currents approach their limits exponentially instead" }, { "what": "Tail headroom", "expr": "V_CM − V_GS1 > V_ov(Mt)", "note": "below it Mt enters triode and I_tail, and g_m with it, collapses" }, { "what": "Drain headroom", "expr": "V_DD − I_tail R_D/2 > V_CM − V_TH", "note": "keeps M1 and M2 saturated at balance; raising R_D for gain is what breaks it" } ], "tradeoffs": [ "I_tail: more current raises g_m and drops more across R_D. In strong inversion it also widens the steering range; in ideal weak inversion the normalized steering range is mainly set by thermal voltage, not current.", "R_D: gain rises with it, but the drains fall by I_tail R_D/2 and push M1 and M2 towards triode.", "L_tail: a longer tail device has more output resistance, holding I_tail steady while the pair steers and the tail node moves.", "V_CM: too low and Mt leaves saturation and I_tail collapses; too high and M1 and M2 run out of drain headroom into triode." ] }, "sizing": [ { "key": "W", "label": "W", "unit": "m", "value": 0.00001, "min": 1.5e-7, "max": 0.0001, "kind": "si" }, { "key": "L", "label": "L", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.00001, "kind": "si" }, { "key": "Itail", "label": "I_tail", "unit": "A", "value": 0.00002, "min": 0.000001, "max": 0.0005, "kind": "si" }, { "key": "Wt", "label": "W_tail", "unit": "m", "value": 0.00002, "min": 1.5e-7, "max": 0.0001, "kind": "si" }, { "key": "Lt", "label": "L_tail", "unit": "m", "value": 0.000004, "min": 1.3e-7, "max": 0.00001, "kind": "si" }, { "key": "RD", "label": "R_D", "unit": "Ω", "value": 30000, "min": 1000, "max": 500000, "kind": "si" }, { "key": "VCM", "label": "V_CM", "unit": "V", "value": 0.7, "min": 0.3, "max": 1.1, "kind": "si" }, { "key": "span", "label": "Sweep ±", "unit": "V", "value": 0.4, "min": 0.05, "max": 0.6, "kind": "si" } ], "testbenches": [ { "id": "dc", "label": "Differential sweep", "note": "", "measures": [ "gm", "av", "vfull" ], "metricKeys": [ "gain_db", "vfull" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* NMOS differential pair with resistive loads\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\nVdd vdd 0 1.2\n* the tail: a mirror copying the reference current the bench supplies\nIb vdd bn 20u\nXMb bn bn 0 0 sg13_lv_nmos w=20u l=4u ng=4 m=1\nXMt tail bn 0 0 sg13_lv_nmos w=20u l=4u ng=4 m=1\n* zero-volt sources used as drain-current ammeters\nXRd1 vdd n1 0 rhigh w=0.5u l=9.166u\nVm1 n1 d1 0\nXRd2 vdd n2 0 rhigh w=0.5u l=9.166u\nVm2 n2 d2 0\nXM1 d1 inp tail 0 sg13_lv_nmos w=10u l=500n ng=2 m=1\nXM2 d2 inn tail 0 sg13_lv_nmos w=10u l=500n ng=2 m=1\n* the input: V_id split evenly either side of a fixed common mode. Sweeping\n* one input alone would carry the common mode up with it, and M1, its gate\n* rising as its drain falls, would be in triode before the pair had steered.\nVcm cm 0 700m\nVid id 0 0\nEinp inp cm id 0 0.5\nEinn inn cm id 0 -0.5\n.dc Vid -400m 400m 0.004\n.end" } ], "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "e6dfc67d2ef4001887579909f6d569bee84c4a5f38ebc3959d60042fb3fcd43a" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/diff-pair.js", "sha256": "7c5b6604778dfa8ed4f5fd1f593b1eed914b15fe0b87efd0135fcb04e2063024" }, "simulationFingerprints": { "dc": "6b4f8e8e714b8eba72edf1321b995104cab5eb5a6a63d582bf121004a0632095" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "096053ac5edae6a17c876383468c696a887bab9ab6b8dd106442beeded6314f7", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "diff-pair", "parameters": { "W": 0.00001, "L": 5e-7, "Itail": 0.00002, "Wt": 0.00002, "Lt": 0.000004, "RD": 30000, "VCM": 0.7, "span": 0.4 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/diff-pair/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [], "scopes": [ { "id": "dut", "name": "top", "ports": [ { "name": "bn", "net": "bn", "kind": "bias" }, { "name": "gnd", "net": "0", "kind": "ground" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "n1", "net": "n1", "kind": "signal" }, { "name": "n2", "net": "n2", "kind": "signal" }, { "name": "d1", "net": "d1", "kind": "output" }, { "name": "inp", "net": "inp", "kind": "input" }, { "name": "d2", "net": "d2", "kind": "output" }, { "name": "inn", "net": "inn", "kind": "input" } ], "definitions": [], "devices": [ { "id": "XMb", "displayName": "Mb", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=4u ng=4 m=1", "source": "XMb bn bn 0 0 sg13_lv_nmos w=20u l=4u ng=4 m=1", "pins": [ { "id": "d", "net": "bn" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMt", "displayName": "Mt", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=4u ng=4 m=1", "source": "XMt tail bn 0 0 sg13_lv_nmos w=20u l=4u ng=4 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRd1", "displayName": "Rd1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=9.166u", "source": "XRd1 vdd n1 0 rhigh w=0.5u l=9.166u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "n1" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRd2", "displayName": "Rd2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=9.166u", "source": "XRd2 vdd n2 0 rhigh w=0.5u l=9.166u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "n2" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=500n ng=2 m=1", "source": "XM1 d1 inp tail 0 sg13_lv_nmos w=10u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=500n ng=2 m=1", "source": "XM2 d2 inn tail 0 sg13_lv_nmos w=10u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "bn", "ground": false, "terminals": [ { "device": "XMb", "pin": "d" }, { "device": "XMb", "pin": "g" }, { "device": "XMt", "pin": "g" } ], "ports": [ "bn" ], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "XMb", "pin": "s" }, { "device": "XMb", "pin": "b" }, { "device": "XMt", "pin": "s" }, { "device": "XMt", "pin": "b" }, { "device": "XRd1", "pin": "substrate" }, { "device": "XRd2", "pin": "substrate" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" } ], "ports": [ "gnd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMt", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XRd1", "pin": "p" }, { "device": "XRd2", "pin": "p" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "n1", "ground": false, "terminals": [ { "device": "XRd1", "pin": "n" } ], "ports": [ "n1" ], "voltageReferences": [] }, { "id": "n2", "ground": false, "terminals": [ { "device": "XRd2", "pin": "n" } ], "ports": [ "n2" ], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" } ], "ports": [ "d1" ], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" } ], "ports": [ "d2" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. 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