{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "fd-2stage-2cmfb", "name": "Fully differential two-stage amplifier, complementary input, two common-mode loops", "group": "Fully differential", "subgroup": "Op amps and OTA cores", "title": "Two-stage amplifier, two common-mode loops", "summary": "This differential amplifier combines NMOS and PMOS input devices so both contribute to amplification. A second stage provides additional gain and output swing. Two common-mode feedback loops set the average voltage of each stage; both must work together without causing ringing.", "reference": { "kind": "paper", "authors": "Y.-P. Hsu, Z. Liu, M. M. Hella", "title": "A -68 dB THD, 0.6 mm2 Active Area Biosignal Acquisition System With a 40-320 Hz Duty-Cycle Controlled Filter", "year": 2020, "where": "IEEE Transactions on Circuits and Systems I: Regular Papers, 67(1):48-59", "doi": "10.1109/TCSI.2019.2943904", "takes": "The topology of the filter's core amplifier: complementary input devices sharing each first-stage node, common-source NMOS second stages with Miller compensation, a common-mode loop holding the first stage through the PMOS tail and a second holding the outputs through the PMOS loads, each sensing through a resistive averager. The first loop's reference as the gate voltage of a replica of the second stage, the error amplifiers' current outputs into diodes, the split of tail and loads into fixed and controlled parts, the sizing and the targets are this library's, for SG13G2 at 1.2 V." }, "resources": { "record": "/circuits/fd-2stage-2cmfb.json", "page": "/index.html#fd-2stage-2cmfb", "achieved": "/achieved/fd-2stage-2cmfb.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "inp", "kind": "input" }, { "name": "inn", "kind": "input" }, { "name": "outp", "kind": "output" }, { "name": "outn", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" }, { "name": "vocm", "kind": "bias", "note": "the output common mode asked for" }, { "name": "ib", "kind": "bias", "note": "the reference current, drawn out of this pin" }, { "name": "cmo2", "kind": "bias", "note": "the output common-mode amplifier's output, the diode Q10: the testbench joins it to cmg2, and breaks that loop there" }, { "name": "cmg2", "kind": "bias", "note": "the gates of the loads M9, M10 the output loop sets" }, { "name": "cmo1", "kind": "bias", "note": "the first-stage common-mode amplifier's output, the diode Q5: joined to cmg1 by the testbench" }, { "name": "cmg1", "kind": "bias", "note": "the gate of MTQ, the part of the PMOS tail the first-stage loop sets" } ], "devices": [ { "name": "MB", "type": "pmos", "nodes": "ib ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "bias reference, diode-connected: the gate of every fixed PMOS source", "fingers": 2, "copies": 1 }, { "name": "MB1", "type": "pmos", "nodes": "vgn ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "one unit feeding MB2", "fingers": 2, "copies": 1 }, { "name": "MB2", "type": "nmos", "nodes": "vgn vgn vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "NMOS reference, diode-connected: vgn", "fingers": 1, "copies": 1 }, { "name": "MB3", "type": "pmos", "nodes": "vr1 ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "two units feeding the replica MR", "fingers": 2, "copies": 2 }, { "name": "MR", "type": "nmos", "nodes": "vr1 vr1 vss vss", "sizedBy": [ "W5", "L5" ], "role": "replica of the second stage, diode-connected: vr1, the first-stage loop's reference", "fingers": 1, "copies": 1 }, { "name": "MTN", "type": "nmos", "nodes": "tn vgn vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "NMOS tail, 3 units", "fingers": 1, "copies": 3 }, { "name": "M1", "type": "nmos", "nodes": "a1 inp tn vss", "sizedBy": [ "W1", "L1" ], "role": "NMOS input, driven by inp", "fingers": 4, "copies": 1 }, { "name": "M2", "type": "nmos", "nodes": "a2 inn tn vss", "sizedBy": [ "W1", "L1" ], "role": "NMOS input, driven by inn", "fingers": 4, "copies": 1 }, { "name": "MTP", "type": "pmos", "nodes": "tp ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "PMOS tail, fixed part, 2 units", "fingers": 2, "copies": 2 }, { "name": "MTQ", "type": "pmos", "nodes": "tp cmg1 vdd vdd", "sizedBy": [ "Wq", "Lq" ], "role": "PMOS tail, the part the first-stage loop sets: 2 copies of Q5", "fingers": 1, "copies": 2 }, { "name": "M3", "type": "pmos", "nodes": "a1 inp tp tp", "sizedBy": [ "W3", "L3" ], "role": "PMOS input, driven by inp, n-well on its source", "fingers": 6, "copies": 1 }, { "name": "M4", "type": "pmos", "nodes": "a2 inn tp tp", "sizedBy": [ "W3", "L3" ], "role": "PMOS input, driven by inn, n-well on its source", "fingers": 6, "copies": 1 }, { "name": "M5", "type": "nmos", "nodes": "outp a1 vss vss", "sizedBy": [ "W5", "L5", "N5" ], "role": "second stage, common source: N5 copies of MR", "fingers": 1, "copies": 10 }, { "name": "M6", "type": "nmos", "nodes": "outn a2 vss vss", "sizedBy": [ "W5", "L5", "N5" ], "role": "second stage, common source: N5 copies of MR", "fingers": 1, "copies": 10 }, { "name": "M7", "type": "pmos", "nodes": "outp ib vdd vdd", "sizedBy": [ "Wp", "Lp", "N5", "K" ], "role": "second-stage load, fixed part: 2·N5 - K units", "fingers": 2, "copies": 12 }, { "name": "M8", "type": "pmos", "nodes": "outn ib vdd vdd", "sizedBy": [ "Wp", "Lp", "N5", "K" ], "role": "second-stage load, fixed part: 2·N5 - K units", "fingers": 2, "copies": 12 }, { "name": "M9", "type": "pmos", "nodes": "outp cmg2 vdd vdd", "sizedBy": [ "Wr", "Lr", "K" ], "role": "second-stage load, the part the output loop sets: K copies of Q10", "fingers": 1, "copies": 8 }, { "name": "M10", "type": "pmos", "nodes": "outn cmg2 vdd vdd", "sizedBy": [ "Wr", "Lr", "K" ], "role": "second-stage load, the part the output loop sets: K copies of Q10", "fingers": 1, "copies": 8 }, { "name": "CC1", "type": "capacitor", "nodes": "a1 z1", "sizedBy": [ "Cc" ], "role": "Miller compensation" }, { "name": "RZ1", "type": "resistor", "nodes": "z1 outp", "sizedBy": [ "Rz" ], "role": "nulling resistor" }, { "name": "CC2", "type": "capacitor", "nodes": "a2 z2", "sizedBy": [ "Cc" ], "role": "Miller compensation" }, { "name": "RZ2", "type": "resistor", "nodes": "z2 outn", "sizedBy": [ "Rz" ], "role": "nulling resistor" }, { "name": "R1", "type": "resistor", "nodes": "a1 cm1", "sizedBy": [ "R1" ], "role": "first-stage detector" }, { "name": "R2", "type": "resistor", "nodes": "a2 cm1", "sizedBy": [ "R1" ], "role": "first-stage detector" }, { "name": "C1", "type": "capacitor", "nodes": "a1 cm1", "sizedBy": [ "C1" ], "role": "first-stage detector, its fast path" }, { "name": "C2", "type": "capacitor", "nodes": "a2 cm1", "sizedBy": [ "C1" ], "role": "first-stage detector, its fast path" }, { "name": "R3", "type": "resistor", "nodes": "outp cm2", "sizedBy": [ "R3" ], "role": "output detector" }, { "name": "R4", "type": "resistor", "nodes": "outn cm2", "sizedBy": [ "R3" ], "role": "output detector" }, { "name": "C3", "type": "capacitor", "nodes": "outp cm2", "sizedBy": [ "C3" ], "role": "output detector, its fast path" }, { "name": "C4", "type": "capacitor", "nodes": "outn cm2", "sizedBy": [ "C3" ], "role": "output detector, its fast path" }, { "name": "MC1", "type": "nmos", "nodes": "tc1 vgn vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "first-stage loop amplifier's tail, 2 units", "fingers": 1, "copies": 2 }, { "name": "Q1", "type": "nmos", "nodes": "e1 cm1 tc1 vss", "sizedBy": [ "Wc", "Lc" ], "role": "first-stage loop pair, sensing side", "fingers": 2, "copies": 1 }, { "name": "Q2", "type": "nmos", "nodes": "cmo1 vr1 tc1 vss", "sizedBy": [ "Wc", "Lc" ], "role": "first-stage loop pair, reference side", "fingers": 2, "copies": 1 }, { "name": "Q3", "type": "pmos", "nodes": "e1 e1 vdd vdd", "sizedBy": [ "Wq", "Lq" ], "role": "first-stage loop mirror, diode, 2 units", "fingers": 1, "copies": 2 }, { "name": "Q4", "type": "pmos", "nodes": "cmo1 e1 vdd vdd", "sizedBy": [ "Wq", "Lq" ], "role": "first-stage loop mirror, 1 unit", "fingers": 1, "copies": 1 }, { "name": "Q5", "type": "pmos", "nodes": "cmo1 cmo1 vdd vdd", "sizedBy": [ "Wq", "Lq" ], "role": "the first-stage loop amplifier's output, a diode: the unit MTQ copies", "fingers": 1, "copies": 1 }, { "name": "MC2", "type": "nmos", "nodes": "tc2 vgn vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "output loop amplifier's tail, 4 units", "fingers": 1, "copies": 4 }, { "name": "Q6", "type": "nmos", "nodes": "e2 cm2 tc2 vss", "sizedBy": [ "Wc", "Lc" ], "role": "output loop pair, sensing side", "fingers": 2, "copies": 1 }, { "name": "Q7", "type": "nmos", "nodes": "cmo2 vocm tc2 vss", "sizedBy": [ "Wc", "Lc" ], "role": "output loop pair, reference side", "fingers": 2, "copies": 1 }, { "name": "Q8", "type": "pmos", "nodes": "e2 e2 vdd vdd", "sizedBy": [ "Wr", "Lr" ], "role": "output loop mirror, diode, 2 units", "fingers": 1, "copies": 2 }, { "name": "Q9", "type": "pmos", "nodes": "cmo2 e2 vdd vdd", "sizedBy": [ "Wr", "Lr" ], "role": "output loop mirror, 1 unit", "fingers": 1, "copies": 1 }, { "name": "Q10", "type": "pmos", "nodes": "cmo2 cmo2 vdd vdd", "sizedBy": [ "Wr", "Lr" ], "role": "the output loop amplifier's output, a diode: the unit M9, M10 copy", "fingers": 1, "copies": 1 } ], "intent": [ { "rule": "match", "of": [ "M1", "M2", "M3", "M4" ], "why": "Each input's NMOS and PMOS device against the other input's: any difference is input offset." }, { "rule": "unit-copies", "of": [ "MB", "MB1", "MB3", "MTP", "M7", "M8" ], "constraint": "every fixed PMOS current a whole number of Wp/Lp units, one Ib each", "why": "Repeating the same unit geometry preserves the intended nominal ratio and avoids geometry-dependent systematic shifts. Random mismatch and unequal drain voltages still cause current-copy errors." }, { "rule": "unit-copies", "of": [ "MB2", "MTN", "MC1", "MC2" ], "constraint": "every NMOS current a whole number of Wn/Ln units", "why": "The same on the NMOS side." }, { "rule": "replica", "of": [ "MR", "M5", "M6" ], "constraint": "M5 = N5 copies of MR; loop 1 holds a1 at vr1 = V_GS(MR)", "why": "The second stage's current is then N5 times MR's by a count of devices, at every corner; a first-stage reference held as a voltage would make it follow every threshold." }, { "rule": "balance", "of": [ "MTN", "MTP", "MTQ", "Q5", "Q4", "Q3" ], "constraint": "3 units in MTN = 2 in MTP + 2 copies of Q5; Q4 is half of Q3, so Q5 carries Ib/2 at balance", "why": "The two tails must carry the same current with the first-stage loop's amplifier balanced, so that loop settles with a1, a2 on vr1 and its inputs equal." }, { "rule": "balance", "of": [ "M5", "M7", "M9", "Q10", "Q9", "Q8" ], "constraint": "K < 2·N5; (2·N5 − K) units in M7 + K copies of Q10 = N5 copies of MR at 2 Ib; Q9 is half of Q8, so Q10 carries Ib at balance", "why": "The loads must equal the second stage's current with the output loop's amplifier balanced; then the outputs settle on vocm with its inputs equal." }, { "rule": "window", "of": [ "M1", "M3", "MR" ], "constraint": "V_ICM - V_GS1 + V_DSAT1 < V_GS(MR) < V_ICM + V_SG3 - V_DSAT3", "why": "a1 sits between the NMOS pair's source and the PMOS pair's; that window shrinks when hot, so the pairs run in moderate inversion, the inputs at 0.42 V and MR near its zero-temperature-coefficient point." }, { "rule": "well", "of": [ "M3", "M4" ], "constraint": "n-well on the source", "why": "Without body effect the PMOS pair's V_SG stays small, leaving room for its tail." }, { "rule": "zero", "of": [ "RZ1", "M5" ], "constraint": "Rz > 1/g_m5", "why": "The Miller capacitor feeds a1 forward to the output: a right-half-plane zero at g_m5/C_c. A series resistor above 1/g_m5 moves it into the left half-plane." }, { "rule": "loop-speed", "of": [ "Q10", "M9", "M10", "Q5", "MTQ" ], "constraint": "each loop's diode pole well above its crossover", "why": "Each loop sets its devices by a current into a diode, so the diode node with the copies' gates is the loop's second pole: the output loop's units are small and short for that reason." }, { "rule": "match", "of": [ "R1", "R2", "C1", "C2", "R3", "R4", "C3", "C4" ], "why": "Each detector averages only if its halves are equal." } ], "specs": [ { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.00014 A", "min": null, "max": 0.00014, "why": "3 Ib through the input stage, 4·N5 Ib in the second stages, 2 and 4 Ib in the common-mode amplifiers and 4 Ib of bias." }, { "key": "voc_err", "label": "Output common mode less its reference", "unit": "V", "direction": "target", "constraint": ">= -0.03 V, <= 0.03 V", "min": -0.03, "max": 0.03, "why": "The output loop steers K Ib into a node the second stage holds low: about 30 dB of loop gain. It lands within 7 mV at every corner; the copy errors of the small, fast mirror devices it needs spread it by about 8 mV (σ) over Monte Carlo." }, { "key": "dc_gain_db", "label": "DC differential gain", "unit": "dB", "direction": "max", "constraint": ">= 50 dB", "min": 50, "max": null, "why": "Two stages, the first loaded by its detector: about 57 dB at 27 °C, 53 dB at 125 °C." }, { "key": "ugf_hz", "label": "Unity-gain frequency", "unit": "Hz", "direction": "max", "constraint": ">= 5000000 Hz", "min": 5000000, "max": null, "why": "(g_m1 + g_m3)/C_c: 10 MHz typical, 7 MHz at the slowest corner." }, { "key": "pm_deg", "label": "Phase margin", "unit": "deg", "direction": "max", "constraint": ">= 60 deg", "min": 60, "max": null, "why": "The nulling resistor puts its zero near the output pole: 70° or more at every corner." }, { "key": "cm_pm_deg", "label": "Output common-mode loop: phase margin", "unit": "deg", "direction": "max", "constraint": ">= 60 deg", "min": 60, "max": null, "why": "The output loop turns into the second stage's output, which the Miller capacitor holds at about 1/g_m5 above the dominant pole: its gain falls through one before a second pole arrives." }, { "key": "cm1_pm_deg", "label": "First-stage common-mode loop: phase margin", "unit": "deg", "direction": "max", "constraint": ">= 60 deg", "min": 60, "max": null, "why": "The first-stage loop crosses near 1.4 MHz on the Miller capacitors, a decade below the diode Q5's pole." }, { "key": "cm_settle", "label": "Common-mode settling, 1 %", "unit": "s", "direction": "min", "constraint": "<= 8e-7 s", "min": null, "max": 8e-7 }, { "key": "sr", "label": "Slew rate", "unit": "V/s", "direction": "max", "constraint": ">= 3000000 V/s", "min": 3000000, "max": null, "why": "The input stage's 6 Ib into C_c: about 2.5 V/µs a side." }, { "key": "t_settle", "label": "Settling time, 1 %", "unit": "s", "direction": "min", "constraint": "<= 2e-7 s", "min": null, "max": 2e-7 }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz, differential", "unit": "dB", "direction": "max", "constraint": ">= 90 dB", "min": 90, "max": null, "why": "Set by mismatch alone: 102 dB at the worst of 20 Monte Carlo draws." }, { "key": "psrr_cm_db", "label": "Supply rejection at 1 kHz, common mode", "unit": "dB", "direction": "max", "constraint": ">= 35 dB", "min": 35, "max": null, "why": "Every PMOS source hangs from MB, fed by an ideal current; what reaches the output common mode is what the output loop's 30 dB leaves: 41 dB at the worst Monte Carlo draw." }, { "key": "cmrr_db", "label": "Common-mode rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 70 dB", "min": 70, "max": null, "why": "Set by mismatch alone: 82 dB at the worst of 20 Monte Carlo draws." } ], "explanation": { "idea": "This differential amplifier combines NMOS and PMOS input devices so both contribute to amplification. A second stage provides additional gain and output swing. Two common-mode feedback loops set the average voltage of each stage; both must work together without causing ringing.", "detail": "A two-stage fully differential amplifier whose inputs each drive an NMOS and a PMOS device into one first-stage node, so the two transconductances add for one current. Common-source NMOS stages with Miller compensation follow. The two tails of the complementary stage leave its output level undefined, so a first common-mode loop sets the PMOS tail until a1 and a2 sit at a replica's gate voltage, and a second sets part of the output loads until the outputs sit where vocm asks.", "lesson": { "relation": 1, "symbols": "ω_u is angular unity-gain frequency in rad/s; g_m1 and g_m3 are the NMOS and PMOS input-device transconductances in S; C_c is compensation capacitance per side in F. Divide ω_u by 2π for Hz.", "assumptions": "Small signals around the default bias point, with the intended dominant pole and the other internal poles above crossover. Device and load parasitics make the relation approximate.", "exercise": { "param": "Cc", "value": 4e-12, "analysis": "open_loop", "expect": "Increasing the compensation capacitance should lower the unity-gain frequency. Compare the phase margin as well; a slower crossover does not by itself prove every internal loop is stable." }, "limits": "Set input and output common-mode levels separately and provide the reference bias current. Differential-loop stability does not establish common-mode-loop stability; check both after resizing or changing the load. Setting Rz to zero removes that resistor and directly joins its terminals; it does not leave a minimum-sized poly resistor." }, "path": [ { "part": "Complementary input", "devices": "M1, M2, M3, M4, MTN, MTP, MTQ", "does": "inp drives M1 and M3, whose drains meet at a1; inn drives M2 and M4 at a2. MTN is the NMOS tail; the PMOS tail is MTP, fixed, and MTQ, set by the first-stage loop." }, { "part": "Second stage", "devices": "M5, M6, M7, M8, M9, M10", "does": "M5 and M6, N5 copies of the replica MR, amplify a1 and a2 onto outp and outn against fixed PMOS loads M7, M8 and the loads M9, M10 the output loop sets." }, { "part": "Miller compensation", "devices": "CC1, RZ1, CC2, RZ2", "does": "Each capacitor, with its nulling resistor, feeds back from an output to its first-stage node and splits the poles." }, { "part": "First-stage loop", "devices": "R1, R2, C1, C2, MC1, Q1, Q2, Q3, Q4, Q5", "does": "R1, R2 with C1, C2 average a1 and a2 onto cm1; Q1, Q2 compare it with vr1 on the 2:1 mirror Q3, Q4 and put the difference into the diode Q5, which MTQ copies: as a1 and a2 rise, the PMOS tail gives less." }, { "part": "Output loop", "devices": "R3, R4, C3, C4, MC2, Q6, Q7, Q8, Q9, Q10", "does": "R3, R4 with C3, C4 average the outputs onto cm2; Q6, Q7 compare it with vocm on the 2:1 mirror Q8, Q9 into the diode Q10, which M9, M10 copy: as the outputs rise, their loads give less." } ], "bias": "The bench draws Ib out of the PMOS diode MB, whose gate the fixed PMOS sources share; MB1 feeds the NMOS diode MB2 for the tails, and MB3 feeds 2 Ib into MR, the replica of the second stage, whose gate voltage vr1 is the first loop's reference. Holding a1 and a2 at vr1 makes M5 and M6 run at N5 times MR's current by a count of devices. The output loop then sets M9, M10 until the loads match that current with the outputs at vocm, 0.6 V by default. The inputs sit at 0.42 V: a1 must stay above the NMOS pair's source and below the PMOS pair's, with room for both.", "relations": [ { "what": "Differential gain", "expr": "A_d ≈ (g_m1 + g_m3)·(r_o1 ∥ r_o3 ∥ R1)·g_m5·(r_o5 ∥ r_o7 ∥ R3)", "note": "The detector resistors load both stages, since each detector node is a differential ground." }, { "what": "Unity-gain frequency", "expr": "ω_u ≈ (g_m1 + g_m3)/C_c", "note": "C_c is CC1, 2 pF by default." }, { "what": "Second-stage current", "expr": "I_M5 = N5·I_MR", "note": "Because the first loop holds a1 at V_GS of MR, M5 is a mirror of it." }, { "what": "Level window", "expr": "V_icm − V_GS1 + V_DSAT1 < V_r1 < V_icm + V_SG3 − V_DSAT3", "note": "Where a1 may sit; it narrows when hot, so the pairs run in moderate inversion and MR near its zero-temperature-coefficient point." }, { "what": "Output loop gain", "expr": "T_2 ≈ 1.5·(g_m/I_D)·K·I_b·R_out", "note": "The share K·Ib of the load the loop controls, into the second stage's output resistance: about 30 dB, and the Miller capacitor holds that node near 1/g_m5 above the dominant pole." } ], "tradeoffs": [ "Output loop share K: more gives the loop gain and accuracy, and more copies on Q10's node, which slows the loop's second pole.", "Input pair widths: wider lowers noise and V_GS, but narrows the window a1 must sit in when hot.", "Nulling resistor: sets where the zero lands against the output pole; too small costs margin at 125 °C, too large lowers the gain margin.", "Detector resistors: larger load the stages less, keeping gain, but slow each loop's sensing unless the capacitors across them bypass it." ] }, "sizing": [ { "key": "Ib", "label": "Reference current", "unit": "A", "value": 0.000002, "min": 5e-7, "max": 0.000006, "kind": "si" }, { "key": "W1", "label": "W NMOS input pair (M1, M2)", "unit": "m", "value": 0.000012, "min": 0.000001, "max": 0.0001, "kind": "si" }, { "key": "L1", "label": "L NMOS input pair", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "W3", "label": "W PMOS input pair (M3, M4)", "unit": "m", "value": 0.000024, "min": 0.000001, "max": 0.00015, "kind": "si" }, { "key": "L3", "label": "L PMOS input pair", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wn", "label": "W NMOS unit", "unit": "m", "value": 0.000004, "min": 0.000001, "max": 0.00004, "kind": "si" }, { "key": "Ln", "label": "L NMOS unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wp", "label": "W PMOS unit", "unit": "m", "value": 0.000008, "min": 0.000001, "max": 0.00004, "kind": "si" }, { "key": "Lp", "label": "L PMOS unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wq", "label": "W first-stage loop PMOS unit (MTQ, Q3-Q5)", "unit": "m", "value": 0.000004, "min": 5e-7, "max": 0.00002, "kind": "si" }, { "key": "Lq", "label": "L first-stage loop PMOS unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wr", "label": "W output loop PMOS unit (M9, M10, Q8-Q10)", "unit": "m", "value": 0.000002, "min": 5e-7, "max": 0.00002, "kind": "si" }, { "key": "Lr", "label": "L output loop PMOS unit", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "W5", "label": "W second-stage unit (MR, M5, M6)", "unit": "m", "value": 9e-7, "min": 3e-7, "max": 0.00001, "kind": "si" }, { "key": "L5", "label": "L second-stage unit", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "N5", "label": "Second-stage current, in replica currents", "unit": "", "value": 10, "min": 5, "max": 20, "kind": "int" }, { "key": "K", "label": "Output loop share of the load, in its diode currents", "unit": "", "value": 8, "min": 2, "max": 10, "kind": "int" }, { "key": "Wc", "label": "W common-mode pairs (Q1, Q2, Q6, Q7)", "unit": "m", "value": 0.000008, "min": 0.000001, "max": 0.00004, "kind": "si" }, { "key": "Lc", "label": "L common-mode pairs", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Cc", "label": "Miller capacitor, per side", "unit": "F", "value": 2e-12, "min": 2e-13, "max": 1e-11, "kind": "si" }, { "key": "Rz", "label": "Nulling resistor, per side", "unit": "Ω", "value": 6000, "min": 0, "max": 19900, "kind": "si" }, { "key": "R1", "label": "First-stage detector resistor", "unit": "Ω", "value": 1000000, "min": 100000, "max": 3000000, "kind": "si" }, { "key": "C1", "label": "First-stage detector capacitor", "unit": "F", "value": 1e-13, "min": 2e-14, "max": 2e-12, "kind": "si" }, { "key": "R3", "label": "Output detector resistor", "unit": "Ω", "value": 500000, "min": 50000, "max": 3000000, "kind": "si" }, { "key": "C3", "label": "Output detector capacitor", "unit": "F", "value": 2e-13, "min": 2e-14, "max": 2e-12, "kind": "si" }, { "key": "CL", "label": "Load capacitance, per side", "unit": "F", "value": 2e-12, "min": 1e-13, "max": 2e-11, "kind": "si" }, { "key": "VICM", "label": "Input common mode", "unit": "V", "value": 0.42, "min": 0.35, "max": 0.5, "kind": "si" }, { "key": "VOCM", "label": "Output common mode asked for", "unit": "V", "value": 0.6, "min": 0.4, "max": 0.8, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The amplifier as a unity-gain differential buffer, its inputs at their common mode: the current it draws, where its output common mode lands against the reference on vocm, and the differential offset.", "measures": [], "metricKeys": [ "i_supply", "voc", "voc_err", "vos" ], "acceptance": [ "i_supply", "voc_err" ], "acceptanceRules": [ { "key": "i_supply", "unit": "A", "min": null, "max": 0.00014, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "voc_err", "unit": "V", "min": -0.03, "max": 0.03, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Fully differential two-stage amplifier with two common-mode loops - operating point as a unity-gain differential buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVocm vocm 0 dc 600m\nIb ib 0 2u\n.subckt fd2cmfb inp inn outp outn vdd vss vocm ib cmo2 cmg2 cmo1 cmg1\n* bias: the reference drawn out of a PMOS diode; the NMOS reference; the replica of the second stage\nXMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMB1 vgn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMB2 vgn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMB3 vr1 ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\nXMR vr1 vr1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=1\n* complementary input stage: each input drives an NMOS and a PMOS into one node\nXMTN tn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=3\nXM1 a1 inp tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1\nXM2 a2 inn tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1\nXMTP tp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\nXMTQ tp cmg1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2\nXM3 a1 inp tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1\nXM4 a2 inn tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1\n* second stage: common source, N5 copies of the replica MR, on fixed and controlled PMOS loads\nXM5 outp a1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10\nXM6 outn a2 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10\nXM7 outp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12\nXM8 outn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12\nXM9 outp cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8\nXM10 outn cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8\n* Miller compensation with nulling resistors\nXCC1 a1 z1 cap_cmim w=25.767u l=25.767u m=2\nXRZ1 z1 outp vss rppd w=0.5u l=11.54u\nXCC2 a2 z2 cap_cmim w=25.767u l=25.767u m=2\nXRZ2 z2 outn vss rppd w=0.5u l=11.54u\n* detectors: the first stage's common mode on cm1, the outputs' on cm2\nXR1 a1 cm1 vss rhigh w=0.5u l=308.725u\nXR2 a2 cm1 vss rhigh w=0.5u l=308.725u\nXC1 a1 cm1 cap_cmim w=8.112u l=8.112u\nXC2 a2 cm1 cap_cmim w=8.112u l=8.112u\nXR3 outp cm2 vss rhigh w=0.5u l=154.313u\nXR4 outn cm2 vss rhigh w=0.5u l=154.313u\nXC3 outp cm2 cap_cmim w=11.494u l=11.494u\nXC4 outn cm2 cap_cmim w=11.494u l=11.494u\n* first-stage common-mode amplifier: cm1 against the replica's V_GS, its output current into Q5\nXMC1 tc1 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2\nXQ1 e1 cm1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ2 cmo1 vr1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ3 e1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2\nXQ4 cmo1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\nXQ5 cmo1 cmo1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\n* output common-mode amplifier: cm2 against vocm, its output current into Q10\nXMC2 tc2 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4\nXQ6 e2 cm2 tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ7 cmo2 vocm tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ8 e2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=2\nXQ9 cmo2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXQ10 cmo2 cmo2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\n.ends\nXdut inp inn outp outn vdd 0 vocm ib cmo2 cmg2 cmo1 cmg1 fd2cmfb\nClp outp 0 2p\nCln outn 0 2p\n* the common-mode loop, joined at its break point\nVbrk_cm cmg2 cmo2 0\nVbrk_cm1 cmg1 cmo1 0\n* the unity-gain differential buffer: each input at V_ICM plus or minus half\n* the output difference - the loop closed for the difference only\nVicm icm 0 dc 420m\nEfp inp icm outn outp 0.5\nEfn inn icm outp outn 0.5\n.op\n.end" }, { "id": "open_loop", "label": "Open-loop gain", "note": "Differential gain and phase with the loop closed only at DC, through 1 TH inductors, so the operating point is the buffer's and every frequency sees the open loop.", "measures": [], "metricKeys": [ "dc_gain_db", "ugf_hz", "pm_deg", "gm_db" ], "acceptance": [ "dc_gain_db", "ugf_hz", "pm_deg" ], "acceptanceRules": [ { "key": "dc_gain_db", "unit": "dB", "min": 50, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "ugf_hz", "unit": "Hz", "min": 5000000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "pm_deg", "unit": "deg", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Fully differential two-stage amplifier with two common-mode loops - open-loop differential gain and phase\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVocm vocm 0 dc 600m\nIb ib 0 2u\n.subckt fd2cmfb inp inn outp outn vdd vss vocm ib cmo2 cmg2 cmo1 cmg1\n* bias: the reference drawn out of a PMOS diode; the NMOS reference; the replica of the second stage\nXMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMB1 vgn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMB2 vgn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMB3 vr1 ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\nXMR vr1 vr1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=1\n* complementary input stage: each input drives an NMOS and a PMOS into one node\nXMTN tn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=3\nXM1 a1 inp tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1\nXM2 a2 inn tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1\nXMTP tp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\nXMTQ tp cmg1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2\nXM3 a1 inp tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1\nXM4 a2 inn tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1\n* second stage: common source, N5 copies of the replica MR, on fixed and controlled PMOS loads\nXM5 outp a1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10\nXM6 outn a2 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10\nXM7 outp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12\nXM8 outn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12\nXM9 outp cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8\nXM10 outn cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8\n* Miller compensation with nulling resistors\nXCC1 a1 z1 cap_cmim w=25.767u l=25.767u m=2\nXRZ1 z1 outp vss rppd w=0.5u l=11.54u\nXCC2 a2 z2 cap_cmim w=25.767u l=25.767u m=2\nXRZ2 z2 outn vss rppd w=0.5u l=11.54u\n* detectors: the first stage's common mode on cm1, the outputs' on cm2\nXR1 a1 cm1 vss rhigh w=0.5u l=308.725u\nXR2 a2 cm1 vss rhigh w=0.5u l=308.725u\nXC1 a1 cm1 cap_cmim w=8.112u l=8.112u\nXC2 a2 cm1 cap_cmim w=8.112u l=8.112u\nXR3 outp cm2 vss rhigh w=0.5u l=154.313u\nXR4 outn cm2 vss rhigh w=0.5u l=154.313u\nXC3 outp cm2 cap_cmim w=11.494u l=11.494u\nXC4 outn cm2 cap_cmim w=11.494u l=11.494u\n* first-stage common-mode amplifier: cm1 against the replica's V_GS, its output current into Q5\nXMC1 tc1 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2\nXQ1 e1 cm1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ2 cmo1 vr1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ3 e1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2\nXQ4 cmo1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\nXQ5 cmo1 cmo1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\n* output common-mode amplifier: cm2 against vocm, its output current into Q10\nXMC2 tc2 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4\nXQ6 e2 cm2 tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ7 cmo2 vocm tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ8 e2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=2\nXQ9 cmo2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXQ10 cmo2 cmo2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\n.ends\nXdut inp inn outp outn vdd 0 vocm ib cmo2 cmg2 cmo1 cmg1 fd2cmfb\nClp outp 0 2p\nCln outn 0 2p\n* the common-mode loop, joined at its break point\nVbrk_cm cmg2 cmo2 0\nVbrk_cm1 cmg1 cmo1 0\n* the unity-gain differential buffer: each input at V_ICM plus or minus half\n* the output difference - the loop closed for the difference only\nVicm icm 0 dc 420m\nEfp fbp icm outn outp 0.5\nEfn fbn icm outp outn 0.5\n* the loop closed at DC and open at every frequency the sweep visits\nLfp inp fbp 1t\nLfn inn fbn 1t\n* the differential input, through 1 TF capacitors\nCdp inp dp 1t\nCdn inn dn 1t\nVdp dp 0 dc 0 ac 0.5\nVdn dn 0 dc 0 ac 0.5 180\n.ac dec 25 0.1 10g\n.end" }, { "id": "cm_loop", "label": "Common-mode loop gain", "note": "Each common-mode loop opened at the break point the circuit brings out, by Middlebrook's double injection - a voltage in series, then a current into the controlled side - with the differential loop closed as in the buffer: the loop's gain, its crossover, and its phase margin.", "measures": [], "metricKeys": [ "cm_gain_db", "cm_ugf_hz", "cm_pm_deg", "cm1_gain_db", "cm1_ugf_hz", "cm1_pm_deg" ], "acceptance": [ "cm_pm_deg", "cm1_pm_deg" ], "acceptanceRules": [ { "key": "cm_pm_deg", "unit": "deg", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "cm1_pm_deg", "unit": "deg", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Fully differential two-stage amplifier with two common-mode loops - Output common-mode loop gain, voltage injection\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVocm vocm 0 dc 600m\nIb ib 0 2u\n.subckt fd2cmfb inp inn outp outn vdd vss vocm ib cmo2 cmg2 cmo1 cmg1\n* bias: the reference drawn out of a PMOS diode; the NMOS reference; the replica of the second stage\nXMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMB1 vgn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMB2 vgn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMB3 vr1 ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\nXMR vr1 vr1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=1\n* complementary input stage: each input drives an NMOS and a PMOS into one node\nXMTN tn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=3\nXM1 a1 inp tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1\nXM2 a2 inn tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1\nXMTP tp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\nXMTQ tp cmg1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2\nXM3 a1 inp tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1\nXM4 a2 inn tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1\n* second stage: common source, N5 copies of the replica MR, on fixed and controlled PMOS loads\nXM5 outp a1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10\nXM6 outn a2 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10\nXM7 outp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12\nXM8 outn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12\nXM9 outp cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8\nXM10 outn cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8\n* Miller compensation with nulling resistors\nXCC1 a1 z1 cap_cmim w=25.767u l=25.767u m=2\nXRZ1 z1 outp vss rppd w=0.5u l=11.54u\nXCC2 a2 z2 cap_cmim w=25.767u l=25.767u m=2\nXRZ2 z2 outn vss rppd w=0.5u l=11.54u\n* detectors: the first stage's common mode on cm1, the outputs' on cm2\nXR1 a1 cm1 vss rhigh w=0.5u l=308.725u\nXR2 a2 cm1 vss rhigh w=0.5u l=308.725u\nXC1 a1 cm1 cap_cmim w=8.112u l=8.112u\nXC2 a2 cm1 cap_cmim w=8.112u l=8.112u\nXR3 outp cm2 vss rhigh w=0.5u l=154.313u\nXR4 outn cm2 vss rhigh w=0.5u l=154.313u\nXC3 outp cm2 cap_cmim w=11.494u l=11.494u\nXC4 outn cm2 cap_cmim w=11.494u l=11.494u\n* first-stage common-mode amplifier: cm1 against the replica's V_GS, its output current into Q5\nXMC1 tc1 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2\nXQ1 e1 cm1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ2 cmo1 vr1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ3 e1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2\nXQ4 cmo1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\nXQ5 cmo1 cmo1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\n* output common-mode amplifier: cm2 against vocm, its output current into Q10\nXMC2 tc2 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4\nXQ6 e2 cm2 tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ7 cmo2 vocm tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ8 e2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=2\nXQ9 cmo2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXQ10 cmo2 cmo2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\n.ends\nXdut inp inn outp outn vdd 0 vocm ib cmo2 cmg2 cmo1 cmg1 fd2cmfb\nClp outp 0 2p\nCln outn 0 2p\n* the common-mode loop, joined at its break point\nVbrk_cm1 cmg1 cmo1 0\n* the unity-gain differential buffer: each input at V_ICM plus or minus half\n* the output difference - the loop closed for the difference only\nVicm icm 0 dc 420m\nEfp inp icm outn outp 0.5\nEfn inn icm outp outn 0.5\n* voltage injection at the break point; the other run of the pair injects the other\nVbrk_cm cmg2 cmo2 dc 0 ac 1\nIbrk_cm 0 cmg2 dc 0 ac 0\n.ac dec 25 1 10g\n.end" }, { "id": "cm_step", "label": "Common-mode step", "note": "A 50mV step on the output common-mode reference, vocm, with the amplifier a unity-gain differential buffer: the output common mode follows it, and rings if its loop is short of margin.", "measures": [], "metricKeys": [ "cm_settle", "cm_overshoot_pct", "cm_step_err" ], "acceptance": [ "cm_settle" ], "acceptanceRules": [ { "key": "cm_settle", "unit": "s", "min": null, "max": 8e-7, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Fully differential two-stage amplifier with two common-mode loops - common-mode step\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVocm vocm 0 dc 600m pulse(600m 650m 200n 1n 1n 1u 4u)\nIb ib 0 2u\n.subckt fd2cmfb inp inn outp outn vdd vss vocm ib cmo2 cmg2 cmo1 cmg1\n* bias: the reference drawn out of a PMOS diode; the NMOS reference; the replica of the second stage\nXMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMB1 vgn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMB2 vgn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMB3 vr1 ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\nXMR vr1 vr1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=1\n* complementary input stage: each input drives an NMOS and a PMOS into one node\nXMTN tn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=3\nXM1 a1 inp tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1\nXM2 a2 inn tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1\nXMTP tp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\nXMTQ tp cmg1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2\nXM3 a1 inp tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1\nXM4 a2 inn tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1\n* second stage: common source, N5 copies of the replica MR, on fixed and controlled PMOS loads\nXM5 outp a1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10\nXM6 outn a2 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10\nXM7 outp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12\nXM8 outn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12\nXM9 outp cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8\nXM10 outn cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8\n* Miller compensation with nulling resistors\nXCC1 a1 z1 cap_cmim w=25.767u l=25.767u m=2\nXRZ1 z1 outp vss rppd w=0.5u l=11.54u\nXCC2 a2 z2 cap_cmim w=25.767u l=25.767u m=2\nXRZ2 z2 outn vss rppd w=0.5u l=11.54u\n* detectors: the first stage's common mode on cm1, the outputs' on cm2\nXR1 a1 cm1 vss rhigh w=0.5u l=308.725u\nXR2 a2 cm1 vss rhigh w=0.5u l=308.725u\nXC1 a1 cm1 cap_cmim w=8.112u l=8.112u\nXC2 a2 cm1 cap_cmim w=8.112u l=8.112u\nXR3 outp cm2 vss rhigh w=0.5u l=154.313u\nXR4 outn cm2 vss rhigh w=0.5u l=154.313u\nXC3 outp cm2 cap_cmim w=11.494u l=11.494u\nXC4 outn cm2 cap_cmim w=11.494u l=11.494u\n* first-stage common-mode amplifier: cm1 against the replica's V_GS, its output current into Q5\nXMC1 tc1 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2\nXQ1 e1 cm1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ2 cmo1 vr1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ3 e1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2\nXQ4 cmo1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\nXQ5 cmo1 cmo1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\n* output common-mode amplifier: cm2 against vocm, its output current into Q10\nXMC2 tc2 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4\nXQ6 e2 cm2 tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ7 cmo2 vocm tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ8 e2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=2\nXQ9 cmo2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXQ10 cmo2 cmo2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\n.ends\nXdut inp inn outp outn vdd 0 vocm ib cmo2 cmg2 cmo1 cmg1 fd2cmfb\nClp outp 0 2p\nCln outn 0 2p\n* the common-mode loop, joined at its break point\nVbrk_cm cmg2 cmo2 0\nVbrk_cm1 cmg1 cmo1 0\n* the unity-gain differential buffer: each input at V_ICM plus or minus half\n* the output difference - the loop closed for the difference only\nVicm icm 0 dc 420m\nEfp inp icm outn outp 0.5\nEfn inn icm outp outn 0.5\n.tran 500p 2u\n.end" }, { "id": "step", "label": "Step response", "note": "A 400mV differential step into the unity-gain differential buffer: how fast the differential output follows, whether it rings, and how far the output common mode is pushed on the way.", "measures": [], "metricKeys": [ "sr", "t_settle", "overshoot_pct", "cm_dev" ], "acceptance": [ "sr", "t_settle" ], "acceptanceRules": [ { "key": "sr", "unit": "V/s", "min": 3000000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "t_settle", "unit": "s", "min": null, "max": 2e-7, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Fully differential two-stage amplifier with two common-mode loops - differential step response of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVocm vocm 0 dc 600m\nIb ib 0 2u\n.subckt fd2cmfb inp inn outp outn vdd vss vocm ib cmo2 cmg2 cmo1 cmg1\n* bias: the reference drawn out of a PMOS diode; the NMOS reference; the replica of the second stage\nXMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMB1 vgn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMB2 vgn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMB3 vr1 ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\nXMR vr1 vr1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=1\n* complementary input stage: each input drives an NMOS and a PMOS into one node\nXMTN tn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=3\nXM1 a1 inp tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1\nXM2 a2 inn tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1\nXMTP tp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\nXMTQ tp cmg1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2\nXM3 a1 inp tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1\nXM4 a2 inn tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1\n* second stage: common source, N5 copies of the replica MR, on fixed and controlled PMOS loads\nXM5 outp a1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10\nXM6 outn a2 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10\nXM7 outp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12\nXM8 outn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12\nXM9 outp cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8\nXM10 outn cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8\n* Miller compensation with nulling resistors\nXCC1 a1 z1 cap_cmim w=25.767u l=25.767u m=2\nXRZ1 z1 outp vss rppd w=0.5u l=11.54u\nXCC2 a2 z2 cap_cmim w=25.767u l=25.767u m=2\nXRZ2 z2 outn vss rppd w=0.5u l=11.54u\n* detectors: the first stage's common mode on cm1, the outputs' on cm2\nXR1 a1 cm1 vss rhigh w=0.5u l=308.725u\nXR2 a2 cm1 vss rhigh w=0.5u l=308.725u\nXC1 a1 cm1 cap_cmim w=8.112u l=8.112u\nXC2 a2 cm1 cap_cmim w=8.112u l=8.112u\nXR3 outp cm2 vss rhigh w=0.5u l=154.313u\nXR4 outn cm2 vss rhigh w=0.5u l=154.313u\nXC3 outp cm2 cap_cmim w=11.494u l=11.494u\nXC4 outn cm2 cap_cmim w=11.494u l=11.494u\n* first-stage common-mode amplifier: cm1 against the replica's V_GS, its output current into Q5\nXMC1 tc1 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2\nXQ1 e1 cm1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ2 cmo1 vr1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ3 e1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2\nXQ4 cmo1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\nXQ5 cmo1 cmo1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\n* output common-mode amplifier: cm2 against vocm, its output current into Q10\nXMC2 tc2 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4\nXQ6 e2 cm2 tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ7 cmo2 vocm tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ8 e2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=2\nXQ9 cmo2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXQ10 cmo2 cmo2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\n.ends\nXdut inp inn outp outn vdd 0 vocm ib cmo2 cmg2 cmo1 cmg1 fd2cmfb\nClp outp 0 2p\nCln outn 0 2p\n* the common-mode loop, joined at its break point\nVbrk_cm cmg2 cmo2 0\nVbrk_cm1 cmg1 cmo1 0\n* the unity-gain differential buffer: each input at V_ICM plus or minus half\n* the output difference - the loop closed for the difference only\nVicm icm 0 dc 420m\nEfp fsp icm outn outp 0.5\nEfn fsn icm outp outn 0.5\nVsp inp fsp dc -100m pulse(-100m 100m 200n 1n 1n 1u 4u)\nVsn inn fsn dc 100m pulse(100m -100m 200n 1n 1n 1u 4u)\n.tran 500p 2u\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on V_DD, and how much of it reaches the unity-gain buffer's differential output and its output common mode.", "measures": [], "metricKeys": [ "psrr_db", "psrr_cm_db" ], "acceptance": [ "psrr_db", "psrr_cm_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 90, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "psrr_cm_db", "unit": "dB", "min": 35, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Fully differential two-stage amplifier with two common-mode loops - supply rejection of the unity-gain differential buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD} ac 1\nVocm vocm 0 dc 600m\nIb ib 0 2u\n.subckt fd2cmfb inp inn outp outn vdd vss vocm ib cmo2 cmg2 cmo1 cmg1\n* bias: the reference drawn out of a PMOS diode; the NMOS reference; the replica of the second stage\nXMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMB1 vgn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMB2 vgn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMB3 vr1 ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\nXMR vr1 vr1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=1\n* complementary input stage: each input drives an NMOS and a PMOS into one node\nXMTN tn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=3\nXM1 a1 inp tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1\nXM2 a2 inn tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1\nXMTP tp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\nXMTQ tp cmg1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2\nXM3 a1 inp tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1\nXM4 a2 inn tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1\n* second stage: common source, N5 copies of the replica MR, on fixed and controlled PMOS loads\nXM5 outp a1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10\nXM6 outn a2 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10\nXM7 outp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12\nXM8 outn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12\nXM9 outp cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8\nXM10 outn cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8\n* Miller compensation with nulling resistors\nXCC1 a1 z1 cap_cmim w=25.767u l=25.767u m=2\nXRZ1 z1 outp vss rppd w=0.5u l=11.54u\nXCC2 a2 z2 cap_cmim w=25.767u l=25.767u m=2\nXRZ2 z2 outn vss rppd w=0.5u l=11.54u\n* detectors: the first stage's common mode on cm1, the outputs' on cm2\nXR1 a1 cm1 vss rhigh w=0.5u l=308.725u\nXR2 a2 cm1 vss rhigh w=0.5u l=308.725u\nXC1 a1 cm1 cap_cmim w=8.112u l=8.112u\nXC2 a2 cm1 cap_cmim w=8.112u l=8.112u\nXR3 outp cm2 vss rhigh w=0.5u l=154.313u\nXR4 outn cm2 vss rhigh w=0.5u l=154.313u\nXC3 outp cm2 cap_cmim w=11.494u l=11.494u\nXC4 outn cm2 cap_cmim w=11.494u l=11.494u\n* first-stage common-mode amplifier: cm1 against the replica's V_GS, its output current into Q5\nXMC1 tc1 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2\nXQ1 e1 cm1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ2 cmo1 vr1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ3 e1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2\nXQ4 cmo1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\nXQ5 cmo1 cmo1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\n* output common-mode amplifier: cm2 against vocm, its output current into Q10\nXMC2 tc2 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4\nXQ6 e2 cm2 tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ7 cmo2 vocm tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ8 e2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=2\nXQ9 cmo2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXQ10 cmo2 cmo2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\n.ends\nXdut inp inn outp outn vdd 0 vocm ib cmo2 cmg2 cmo1 cmg1 fd2cmfb\nClp outp 0 2p\nCln outn 0 2p\n* the common-mode loop, joined at its break point\nVbrk_cm cmg2 cmo2 0\nVbrk_cm1 cmg1 cmo1 0\n* the unity-gain differential buffer: each input at V_ICM plus or minus half\n* the output difference - the loop closed for the difference only\nVicm icm 0 dc 420m\nEfp inp icm outn outp 0.5\nEfn inn icm outp outn 0.5\n.ac dec 25 1 100meg\n.end" }, { "id": "cmrr", "label": "Common-mode rejection", "note": "The same signal on both inputs, on the unity-gain buffer's input common mode: what reaches the differential output is the common-mode to differential gain over the differential one, and what reaches the output common mode is how firmly the common-mode loop holds it.", "measures": [], "metricKeys": [ "cmrr_db", "cm_rej_db" ], "acceptance": [ "cmrr_db" ], "acceptanceRules": [ { "key": "cmrr_db", "unit": "dB", "min": 70, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Fully differential two-stage amplifier with two common-mode loops - common-mode rejection\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVocm vocm 0 dc 600m\nIb ib 0 2u\n.subckt fd2cmfb inp inn outp outn vdd vss vocm ib cmo2 cmg2 cmo1 cmg1\n* bias: the reference drawn out of a PMOS diode; the NMOS reference; the replica of the second stage\nXMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMB1 vgn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMB2 vgn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMB3 vr1 ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\nXMR vr1 vr1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=1\n* complementary input stage: each input drives an NMOS and a PMOS into one node\nXMTN tn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=3\nXM1 a1 inp tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1\nXM2 a2 inn tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1\nXMTP tp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\nXMTQ tp cmg1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2\nXM3 a1 inp tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1\nXM4 a2 inn tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1\n* second stage: common source, N5 copies of the replica MR, on fixed and controlled PMOS loads\nXM5 outp a1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10\nXM6 outn a2 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10\nXM7 outp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12\nXM8 outn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12\nXM9 outp cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8\nXM10 outn cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8\n* Miller compensation with nulling resistors\nXCC1 a1 z1 cap_cmim w=25.767u l=25.767u m=2\nXRZ1 z1 outp vss rppd w=0.5u l=11.54u\nXCC2 a2 z2 cap_cmim w=25.767u l=25.767u m=2\nXRZ2 z2 outn vss rppd w=0.5u l=11.54u\n* detectors: the first stage's common mode on cm1, the outputs' on cm2\nXR1 a1 cm1 vss rhigh w=0.5u l=308.725u\nXR2 a2 cm1 vss rhigh w=0.5u l=308.725u\nXC1 a1 cm1 cap_cmim w=8.112u l=8.112u\nXC2 a2 cm1 cap_cmim w=8.112u l=8.112u\nXR3 outp cm2 vss rhigh w=0.5u l=154.313u\nXR4 outn cm2 vss rhigh w=0.5u l=154.313u\nXC3 outp cm2 cap_cmim w=11.494u l=11.494u\nXC4 outn cm2 cap_cmim w=11.494u l=11.494u\n* first-stage common-mode amplifier: cm1 against the replica's V_GS, its output current into Q5\nXMC1 tc1 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2\nXQ1 e1 cm1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ2 cmo1 vr1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ3 e1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2\nXQ4 cmo1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\nXQ5 cmo1 cmo1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\n* output common-mode amplifier: cm2 against vocm, its output current into Q10\nXMC2 tc2 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4\nXQ6 e2 cm2 tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ7 cmo2 vocm tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ8 e2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=2\nXQ9 cmo2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXQ10 cmo2 cmo2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\n.ends\nXdut inp inn outp outn vdd 0 vocm ib cmo2 cmg2 cmo1 cmg1 fd2cmfb\nClp outp 0 2p\nCln outn 0 2p\n* the common-mode loop, joined at its break point\nVbrk_cm cmg2 cmo2 0\nVbrk_cm1 cmg1 cmo1 0\n* the unity-gain differential buffer: each input at V_ICM plus or minus half\n* the output difference - the loop closed for the difference only\nVicm icm 0 dc 420m ac 1\nEfp inp icm outn outp 0.5\nEfn inn icm outp outn 0.5\n.ac dec 25 1 100meg\n.end" }, { "id": "noise", "label": "Noise", "note": "Differential noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.", "measures": [], "metricKeys": [ "vn_1k", "vn_int" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Fully differential two-stage amplifier with two common-mode loops - differential input-referred noise\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVocm vocm 0 dc 600m\nIb ib 0 2u\n.subckt fd2cmfb inp inn outp outn vdd vss vocm ib cmo2 cmg2 cmo1 cmg1\n* bias: the reference drawn out of a PMOS diode; the NMOS reference; the replica of the second stage\nXMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMB1 vgn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMB2 vgn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMB3 vr1 ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\nXMR vr1 vr1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=1\n* complementary input stage: each input drives an NMOS and a PMOS into one node\nXMTN tn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=3\nXM1 a1 inp tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1\nXM2 a2 inn tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1\nXMTP tp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2\nXMTQ tp cmg1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2\nXM3 a1 inp tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1\nXM4 a2 inn tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1\n* second stage: common source, N5 copies of the replica MR, on fixed and controlled PMOS loads\nXM5 outp a1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10\nXM6 outn a2 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10\nXM7 outp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12\nXM8 outn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12\nXM9 outp cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8\nXM10 outn cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8\n* Miller compensation with nulling resistors\nXCC1 a1 z1 cap_cmim w=25.767u l=25.767u m=2\nXRZ1 z1 outp vss rppd w=0.5u l=11.54u\nXCC2 a2 z2 cap_cmim w=25.767u l=25.767u m=2\nXRZ2 z2 outn vss rppd w=0.5u l=11.54u\n* detectors: the first stage's common mode on cm1, the outputs' on cm2\nXR1 a1 cm1 vss rhigh w=0.5u l=308.725u\nXR2 a2 cm1 vss rhigh w=0.5u l=308.725u\nXC1 a1 cm1 cap_cmim w=8.112u l=8.112u\nXC2 a2 cm1 cap_cmim w=8.112u l=8.112u\nXR3 outp cm2 vss rhigh w=0.5u l=154.313u\nXR4 outn cm2 vss rhigh w=0.5u l=154.313u\nXC3 outp cm2 cap_cmim w=11.494u l=11.494u\nXC4 outn cm2 cap_cmim w=11.494u l=11.494u\n* first-stage common-mode amplifier: cm1 against the replica's V_GS, its output current into Q5\nXMC1 tc1 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2\nXQ1 e1 cm1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ2 cmo1 vr1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ3 e1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2\nXQ4 cmo1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\nXQ5 cmo1 cmo1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1\n* output common-mode amplifier: cm2 against vocm, its output current into Q10\nXMC2 tc2 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4\nXQ6 e2 cm2 tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ7 cmo2 vocm tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1\nXQ8 e2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=2\nXQ9 cmo2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXQ10 cmo2 cmo2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\n.ends\nXdut inp inn outp outn vdd 0 vocm ib cmo2 cmg2 cmo1 cmg1 fd2cmfb\nClp outp 0 2p\nCln outn 0 2p\n* the common-mode loop, joined at its break point\nVbrk_cm cmg2 cmo2 0\nVbrk_cm1 cmg1 cmo1 0\n* the unity-gain differential buffer: each input at V_ICM plus or minus half\n* the output difference - the loop closed for the difference only\nVicm icm 0 dc 420m\nEfp inp icm outn outp 0.5\nEfn fsn icm outp outn 0.5\nVsn inn fsn dc 0 ac 1\n.control\nnoise v(outp,outn) Vsn dec 20 1 1meg\nsetplot noise1\n* 20 points a decade from 1 Hz: point 60 is 1 kHz\nlet vn_1k = inoise_spectrum[60]\nprint vn_1k\nsetplot noise2\nprint inoise_total\n.endc\n.op\n.end" } ], "measurements": { "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.00014 } }, "voc_err": { "label": "Output common mode less its reference", "unit": "V", "spec": { "min": -0.03, "max": 0.03 } }, "dc_gain_db": { "label": "DC differential gain", "unit": "dB", "spec": { "min": 50, "max": null } }, "ugf_hz": { "label": "Unity-gain frequency", "unit": "Hz", "spec": { "min": 5000000, "max": null } }, "pm_deg": { "label": "Phase margin", "unit": "deg", "spec": { "min": 60, "max": null } }, "cm_pm_deg": { "label": "Output common-mode loop: phase margin", "unit": "deg", "spec": { "min": 60, "max": null } }, "cm1_pm_deg": { "label": "First-stage common-mode loop: phase margin", "unit": "deg", "spec": { "min": 60, "max": null } }, "cm_settle": { "label": "Common-mode settling, 1 %", "unit": "s", "spec": { "min": null, "max": 8e-7 } }, "sr": { "label": "Slew rate", "unit": "V/s", "spec": { "min": 3000000, "max": null } }, "t_settle": { "label": "Settling time, 1 %", "unit": "s", "spec": { "min": null, "max": 2e-7 } }, "psrr_db": { "label": "Supply rejection at 1 kHz, differential", "unit": "dB", "spec": { "min": 90, "max": null } }, "psrr_cm_db": { "label": "Supply rejection at 1 kHz, common mode", "unit": "dB", "spec": { "min": 35, "max": null } }, "cmrr_db": { "label": "Common-mode rejection at 1 kHz", "unit": "dB", "spec": { "min": 70, "max": null } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "a59147a35b94814f54ae463884488d36a0f70ea459e1e3b0be2fd3c71e1c4fe4" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/fd-2stage-2cmfb.js", "sha256": "3969365862e2487118eb9760b2d17916247f14191e14997a0de513502b8e12f8" }, "simulationFingerprints": { "op": "1c76a29cb2de3ebe6d3e1e283d2875f09c154e21401d466aa44b9c72ce3bc6c3", "open_loop": "642da2f94ce83b9c5fde1ea10ba55d85c11bee0d0780970d5caefb405ea80c27", "cm_loop": "94ffeb9909fffeb305aeb6dad5784474cf381b77e4f0f2f0f1c5f9c3e4db25e0", "cm_step": "30547d94f2830455d5a38c9bc43b6fb81e87ec364c54040219959da0ac92e4f4", "step": "559c54ff6235055a32b264f44516f6c8d85a2cf888dc7df3d4f65a853ab836d2", "psrr": "95e75cf5ff8876d4c8929244ab40e17162d59e42f4d6bc966a13cc36be3bdbba", "cmrr": "f4160168aa2b002adb749133c6bfc9e9a1786e543e2c007b2a6848ff9fb764e6", "noise": "d279fbf996a014ab7411adb2774e3ac78717d5b4695503be80056a2dbb37c235" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "23b1e1b74e6a3f808407464223b5c89b773c1f7caabb6d9b011ff5f78e523892", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "fd-2stage-2cmfb", "parameters": { "Ib": 0.000002, "W1": 0.000012, "L1": 0.000001, "W3": 0.000024, "L3": 0.000001, "Wn": 0.000004, "Ln": 0.000001, "Wp": 0.000008, "Lp": 0.000001, "Wq": 0.000004, "Lq": 0.000001, "Wr": 0.000002, "Lr": 5e-7, "W5": 9e-7, "L5": 0.000002, "N5": 10, "K": 8, "Wc": 0.000008, "Lc": 0.000001, "Cc": 2e-12, "Rz": 6000, "R1": 1000000, "C1": 1e-13, "R3": 500000, "C3": 2e-13, "CL": 2e-12, "VICM": 0.42, "VOCM": 0.6 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/fd-2stage-2cmfb/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "fd2cmfb", "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "outp", "net": "outp", "kind": "output" }, { "name": "outn", "net": "outn", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "vocm", "net": "vocm", "kind": "bias" }, { "name": "ib", "net": "ib", "kind": "bias" }, { "name": "cmo2", "net": "cmo2", "kind": "bias" }, { "name": "cmg2", "net": "cmg2", "kind": "bias" }, { "name": "cmo1", "net": "cmo1", "kind": "bias" }, { "name": "cmg1", "net": "cmg1", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB1 vgn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMB2 vgn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMB3 vr1 ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "vr1" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR", "displayName": "MR", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=1", "source": "XMR vr1 vr1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vr1" }, { "id": "g", "net": "vr1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTN", "displayName": "MTN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=3", "source": "XMTN tn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=3", "pins": [ { "id": "d", "net": "tn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XM1 a1 inp tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XM2 a2 inn tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTP", "displayName": "MTP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTP tp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "tp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTQ", "displayName": "MTQ", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMTQ tp cmg1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "tp" }, { "id": "g", "net": "cmg1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=1u ng=6 m=1", "source": "XM3 a1 inp tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tp" }, { "id": "b", "net": "tp" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=1u ng=6 m=1", "source": "XM4 a2 inn tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tp" }, { "id": "b", "net": "tp" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=10", "source": "XM5 outp a1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "a1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=10", "source": "XM6 outn a2 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "a2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=12", "source": "XM7 outp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=12", "source": "XM8 outn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=8", "source": "XM9 outp cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "cmg2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=8", "source": "XM10 outn cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "cmg2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC1 a1 z1 cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC2 a2 z2 cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XR1 a1 cm1 vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "cm1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XR2 a2 cm1 vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "cm1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XC1", "displayName": "C1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=8.112u l=8.112u", "source": "XC1 a1 cm1 cap_cmim w=8.112u l=8.112u", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "cm1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC2", "displayName": "C2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=8.112u l=8.112u", "source": "XC2 a2 cm1 cap_cmim w=8.112u l=8.112u", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "cm1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XR3", "displayName": "R3", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=154.313u", "source": "XR3 outp cm2 vss rhigh w=0.5u l=154.313u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cm2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR4", "displayName": "R4", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=154.313u", "source": "XR4 outn cm2 vss rhigh w=0.5u l=154.313u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cm2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XC3", "displayName": "C3", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XC3 outp cm2 cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cm2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC4", "displayName": "C4", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XC4 outn cm2 cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cm2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMC1 tc1 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "tc1" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ1", "displayName": "Q1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ1 e1 cm1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "e1" }, { "id": "g", "net": "cm1" }, { "id": "s", "net": "tc1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ2", "displayName": "Q2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ2 cmo1 vr1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "vr1" }, { "id": "s", "net": "tc1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ3", "displayName": "Q3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XQ3 e1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "e1" }, { "id": "g", "net": "e1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ4", "displayName": "Q4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XQ4 cmo1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "e1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ5", "displayName": "Q5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XQ5 cmo1 cmo1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "cmo1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=4", "source": "XMC2 tc2 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4", "pins": [ { "id": "d", "net": "tc2" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ6", "displayName": "Q6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ6 e2 cm2 tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "e2" }, { "id": "g", "net": "cm2" }, { "id": "s", "net": "tc2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ7", "displayName": "Q7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ7 cmo2 vocm tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "tc2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ8", "displayName": "Q8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=2", "source": "XQ8 e2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=2", "pins": [ { "id": "d", "net": "e2" }, { "id": "g", "net": "e2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ9", "displayName": "Q9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XQ9 cmo2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "e2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ10", "displayName": "Q10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XQ10 cmo2 cmo2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "cmo2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB3", "pin": "g" }, { "device": "XMTP", "pin": "g" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XMTP", "pin": "s" }, { "device": "XMTP", "pin": "b" }, { "device": "XMTQ", "pin": "s" }, { "device": "XMTQ", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XQ3", "pin": "s" }, { "device": "XQ3", "pin": "b" }, { "device": "XQ4", "pin": "s" }, { "device": "XQ4", "pin": "b" }, { "device": "XQ5", "pin": "s" }, { "device": "XQ5", "pin": "b" }, { "device": "XQ8", "pin": "s" }, { "device": "XQ8", "pin": "b" }, { "device": "XQ9", "pin": "s" }, { "device": "XQ9", "pin": "b" }, { "device": "XQ10", "pin": "s" }, { "device": "XQ10", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vgn", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMB2", "pin": "d" }, { "device": "XMB2", "pin": "g" }, { "device": "XMTN", "pin": "g" }, { "device": "XMC1", "pin": "g" }, { "device": "XMC2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMR", "pin": "s" }, { "device": "XMR", "pin": "b" }, { "device": "XMTN", "pin": "s" }, { "device": "XMTN", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XRZ1", "pin": "substrate" }, { "device": "XRZ2", "pin": "substrate" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR2", "pin": "substrate" }, { "device": "XR3", "pin": "substrate" }, { "device": "XR4", "pin": "substrate" }, { "device": "XMC1", "pin": "s" }, { "device": "XMC1", "pin": "b" }, { "device": "XQ1", "pin": "b" }, { "device": "XQ2", "pin": "b" }, { "device": "XMC2", "pin": "s" }, { "device": "XMC2", "pin": "b" }, { "device": "XQ6", "pin": "b" }, { "device": "XQ7", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vr1", "ground": false, "terminals": [ { "device": "XMB3", "pin": "d" }, { "device": "XMR", "pin": "d" }, { "device": "XMR", "pin": "g" }, { "device": "XQ2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tn", "ground": false, "terminals": [ { "device": "XMTN", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "a1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XCC1", "pin": "p" }, { "device": "XR1", "pin": "p" }, { "device": "XC1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM3", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "a2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "g" }, { "device": "XCC2", "pin": "p" }, { "device": "XR2", "pin": "p" }, { "device": "XC2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "tp", "ground": false, "terminals": [ { "device": "XMTP", "pin": "d" }, { "device": "XMTQ", "pin": "d" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg1", "ground": false, "terminals": [ { "device": "XMTQ", "pin": "g" } ], "ports": [ "cmg1" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "d" }, { "device": "XRZ1", "pin": "n" }, { "device": "XR3", "pin": "p" }, { "device": "XC3", "pin": "p" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XRZ2", "pin": "n" }, { "device": "XR4", "pin": "p" }, { "device": "XC4", "pin": "p" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "cmg2", "ground": false, "terminals": [ { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [ "cmg2" ], "voltageReferences": [] }, { "id": "z1", "ground": false, "terminals": [ { "device": "XCC1", "pin": "n" }, { "device": "XRZ1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z2", "ground": false, "terminals": [ { "device": "XCC2", "pin": "n" }, { "device": "XRZ2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cm1", "ground": false, "terminals": [ { "device": "XR1", "pin": "n" }, { "device": "XR2", "pin": "n" }, { "device": "XC1", "pin": "n" }, { "device": "XC2", "pin": "n" }, { "device": "XQ1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cm2", "ground": false, "terminals": [ { "device": "XR3", "pin": "n" }, { "device": "XR4", "pin": "n" }, { "device": "XC3", "pin": "n" }, { "device": "XC4", "pin": "n" }, { "device": "XQ6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tc1", "ground": false, "terminals": [ { "device": "XMC1", "pin": "d" }, { "device": "XQ1", "pin": "s" }, { "device": "XQ2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "e1", "ground": false, "terminals": [ { "device": "XQ1", "pin": "d" }, { "device": "XQ3", "pin": "d" }, { "device": "XQ3", "pin": "g" }, { "device": "XQ4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo1", "ground": false, "terminals": [ { "device": "XQ2", "pin": "d" }, { "device": "XQ4", "pin": "d" }, { "device": "XQ5", "pin": "d" }, { "device": "XQ5", "pin": "g" } ], "ports": [ "cmo1" ], "voltageReferences": [] }, { "id": "tc2", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XQ6", "pin": "s" }, { "device": "XQ7", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "e2", "ground": false, "terminals": [ { "device": "XQ6", "pin": "d" }, { "device": "XQ8", "pin": "d" }, { "device": "XQ8", "pin": "g" }, { "device": "XQ9", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo2", "ground": false, "terminals": [ { "device": "XQ7", "pin": "d" }, { "device": "XQ9", "pin": "d" }, { "device": "XQ10", "pin": "d" }, { "device": "XQ10", "pin": "g" } ], "ports": [ "cmo2" ], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XQ7", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vocm vocm 0 dc 600m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2u", "source": "Ib ib 0 2u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "fd2cmfb", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 vocm ib cmo2 cmg2 cmo1 cmg1 fd2cmfb", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "vocm", "net": "vocm" }, { "id": "ib", "net": "ib" }, { "id": "cmo2", "net": "cmo2" }, { "id": "cmg2", "net": "cmg2" }, { "id": "cmo1", "net": "cmo1" }, { "id": "cmg1", "net": "cmg1" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/fd2cmfb" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm", "displayName": "Vbrk_cm", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm cmg2 cmo2 0", "pins": [ { "id": "p", "net": "cmg2" }, { "id": "n", "net": "cmo2" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm1", "displayName": "Vbrk_cm1", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm1 cmg1 cmo1 0", "pins": [ { "id": "p", "net": "cmg1" }, { "id": "n", "net": "cmo1" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 420m", "source": "Vicm icm 0 dc 420m", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efp", "displayName": "Efp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efp inp icm outn outp 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outn" }, { "id": "cn", "net": "outp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efn", "displayName": "Efn", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efn inn icm outp outn 0.5", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" }, { "device": "Xdut", "pin": "vocm" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Efp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Efn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Efp", "pin": "cn" }, { "device": "Efn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Efp", "pin": "cp" }, { "device": "Efn", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo2", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo2" }, { "device": "Vbrk_cm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg2", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg2" }, { "device": "Vbrk_cm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo1", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo1" }, { "device": "Vbrk_cm1", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg1", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg1" }, { "device": "Vbrk_cm1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Efp", "pin": "n" }, { "device": "Efn", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/fd2cmfb", "name": "fd2cmfb", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "vocm", "net": "vocm" }, { "name": "ib", "net": "ib" }, { "name": "cmo2", "net": "cmo2" }, { "name": "cmg2", "net": "cmg2" }, { "name": "cmo1", "net": "cmo1" }, { "name": "cmg1", "net": "cmg1" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB1 vgn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMB2 vgn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMB3 vr1 ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "vr1" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR", "displayName": "MR", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=1", "source": "XMR vr1 vr1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vr1" }, { "id": "g", "net": "vr1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTN", "displayName": "MTN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=3", "source": "XMTN tn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=3", "pins": [ { "id": "d", "net": "tn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XM1 a1 inp tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XM2 a2 inn tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTP", "displayName": "MTP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTP tp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "tp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTQ", "displayName": "MTQ", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMTQ tp cmg1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "tp" }, { "id": "g", "net": "cmg1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=1u ng=6 m=1", "source": "XM3 a1 inp tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tp" }, { "id": "b", "net": "tp" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=1u ng=6 m=1", "source": "XM4 a2 inn tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tp" }, { "id": "b", "net": "tp" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=10", "source": "XM5 outp a1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "a1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=10", "source": "XM6 outn a2 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "a2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=12", "source": "XM7 outp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=12", "source": "XM8 outn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=8", "source": "XM9 outp cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "cmg2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=8", "source": "XM10 outn cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "cmg2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC1 a1 z1 cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC2 a2 z2 cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XR1 a1 cm1 vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "cm1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XR2 a2 cm1 vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "cm1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XC1", "displayName": "C1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=8.112u l=8.112u", "source": "XC1 a1 cm1 cap_cmim w=8.112u l=8.112u", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "cm1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC2", "displayName": "C2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=8.112u l=8.112u", "source": "XC2 a2 cm1 cap_cmim w=8.112u l=8.112u", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "cm1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XR3", "displayName": "R3", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=154.313u", "source": "XR3 outp cm2 vss rhigh w=0.5u l=154.313u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cm2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR4", "displayName": "R4", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=154.313u", "source": "XR4 outn cm2 vss rhigh w=0.5u l=154.313u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cm2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XC3", "displayName": "C3", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XC3 outp cm2 cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cm2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC4", "displayName": "C4", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XC4 outn cm2 cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cm2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMC1 tc1 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "tc1" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ1", "displayName": "Q1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ1 e1 cm1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "e1" }, { "id": "g", "net": "cm1" }, { "id": "s", "net": "tc1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ2", "displayName": "Q2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ2 cmo1 vr1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "vr1" }, { "id": "s", "net": "tc1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ3", "displayName": "Q3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XQ3 e1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "e1" }, { "id": "g", "net": "e1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ4", "displayName": "Q4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XQ4 cmo1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "e1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ5", "displayName": "Q5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XQ5 cmo1 cmo1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "cmo1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=4", "source": "XMC2 tc2 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4", "pins": [ { "id": "d", "net": "tc2" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ6", "displayName": "Q6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ6 e2 cm2 tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "e2" }, { "id": "g", "net": "cm2" }, { "id": "s", "net": "tc2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ7", "displayName": "Q7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ7 cmo2 vocm tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "tc2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ8", "displayName": "Q8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=2", "source": "XQ8 e2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=2", "pins": [ { "id": "d", "net": "e2" }, { "id": "g", "net": "e2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ9", "displayName": "Q9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XQ9 cmo2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "e2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ10", "displayName": "Q10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XQ10 cmo2 cmo2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "cmo2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB3", "pin": "g" }, { "device": "XMTP", "pin": "g" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XMTP", "pin": "s" }, { "device": "XMTP", "pin": "b" }, { "device": "XMTQ", "pin": "s" }, { "device": "XMTQ", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XQ3", "pin": "s" }, { "device": "XQ3", "pin": "b" }, { "device": "XQ4", "pin": "s" }, { "device": "XQ4", "pin": "b" }, { "device": "XQ5", "pin": "s" }, { "device": "XQ5", "pin": "b" }, { "device": "XQ8", "pin": "s" }, { "device": "XQ8", "pin": "b" }, { "device": "XQ9", "pin": "s" }, { "device": "XQ9", "pin": "b" }, { "device": "XQ10", "pin": "s" }, { "device": "XQ10", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vgn", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMB2", "pin": "d" }, { "device": "XMB2", "pin": "g" }, { "device": "XMTN", "pin": "g" }, { "device": "XMC1", "pin": "g" }, { "device": "XMC2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMR", "pin": "s" }, { "device": "XMR", "pin": "b" }, { "device": "XMTN", "pin": "s" }, { "device": "XMTN", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XRZ1", "pin": "substrate" }, { "device": "XRZ2", "pin": "substrate" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR2", "pin": "substrate" }, { "device": "XR3", "pin": "substrate" }, { "device": "XR4", "pin": "substrate" }, { "device": "XMC1", "pin": "s" }, { "device": "XMC1", "pin": "b" }, { "device": "XQ1", "pin": "b" }, { "device": "XQ2", "pin": "b" }, { "device": "XMC2", "pin": "s" }, { "device": "XMC2", "pin": "b" }, { "device": "XQ6", "pin": "b" }, { "device": "XQ7", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vr1", "ground": false, "terminals": [ { "device": "XMB3", "pin": "d" }, { "device": "XMR", "pin": "d" }, { "device": "XMR", "pin": "g" }, { "device": "XQ2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tn", "ground": false, "terminals": [ { "device": "XMTN", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "a1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XCC1", "pin": "p" }, { "device": "XR1", "pin": "p" }, { "device": "XC1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM3", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "a2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "g" }, { "device": "XCC2", "pin": "p" }, { "device": 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primitive terminal order" }, { "id": "Cdp", "displayName": "Cdp", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cdp inp dp 1t", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "dp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cdn", "displayName": "Cdn", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cdn inn dn 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "dn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vdp", "displayName": "Vdp", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 0.5", "source": "Vdp dp 0 dc 0 ac 0.5", "pins": [ { "id": "p", "net": "dp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vdn", "displayName": "Vdn", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 0.5 180", "source": "Vdn dn 0 dc 0 ac 0.5 180", "pins": [ { "id": "p", "net": "dn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" }, { "device": "Vdp", "pin": "n" }, { "device": "Vdn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" }, { "device": "Xdut", "pin": "vocm" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Lfp", "pin": "p" }, { "device": "Cdp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Lfn", "pin": "p" }, { "device": "Cdn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Efp", "pin": "cn" }, { "device": "Efn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Efp", "pin": "cp" }, { "device": "Efn", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo2", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo2" }, { "device": "Vbrk_cm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg2", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg2" }, { "device": "Vbrk_cm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo1", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo1" }, { "device": "Vbrk_cm1", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg1", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg1" }, { "device": "Vbrk_cm1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Efp", "pin": "n" }, { "device": "Efn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "fbp", "ground": false, "terminals": [ { "device": "Efp", "pin": "p" }, { "device": "Lfp", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "fbn", "ground": false, "terminals": [ { "device": "Efn", "pin": "p" }, { "device": "Lfn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "dp", "ground": false, "terminals": [ { "device": "Cdp", "pin": "n" }, { "device": "Vdp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "dn", "ground": false, "terminals": [ { "device": "Cdn", "pin": "n" }, { "device": "Vdn", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/fd2cmfb", "name": "fd2cmfb", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "vocm", "net": "vocm" }, { "name": "ib", "net": "ib" }, { "name": "cmo2", "net": "cmo2" }, { "name": "cmg2", "net": "cmg2" }, { "name": "cmo1", "net": "cmo1" }, { "name": "cmg1", "net": "cmg1" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB1 vgn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMB2 vgn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMB3 vr1 ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "vr1" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR", "displayName": "MR", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=1", "source": "XMR vr1 vr1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vr1" }, { "id": "g", "net": "vr1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTN", "displayName": "MTN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=3", "source": "XMTN tn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=3", "pins": [ { "id": "d", "net": "tn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XM1 a1 inp tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XM2 a2 inn tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTP", "displayName": "MTP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTP tp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "tp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTQ", "displayName": "MTQ", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMTQ tp cmg1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "tp" }, { "id": "g", "net": "cmg1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=1u ng=6 m=1", "source": "XM3 a1 inp tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tp" }, { "id": "b", "net": "tp" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=1u ng=6 m=1", "source": "XM4 a2 inn tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tp" }, { "id": "b", "net": "tp" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=10", "source": "XM5 outp a1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "a1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=10", "source": "XM6 outn a2 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "a2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=12", "source": "XM7 outp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=12", "source": "XM8 outn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=8", "source": "XM9 outp cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "cmg2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=8", "source": "XM10 outn cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "cmg2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC1 a1 z1 cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC2 a2 z2 cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XR1 a1 cm1 vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "cm1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XR2 a2 cm1 vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "cm1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XC1", "displayName": "C1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=8.112u l=8.112u", "source": "XC1 a1 cm1 cap_cmim w=8.112u l=8.112u", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "cm1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC2", "displayName": "C2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=8.112u l=8.112u", "source": "XC2 a2 cm1 cap_cmim w=8.112u l=8.112u", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "cm1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XR3", "displayName": "R3", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=154.313u", "source": "XR3 outp cm2 vss rhigh w=0.5u l=154.313u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cm2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR4", "displayName": "R4", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=154.313u", "source": "XR4 outn cm2 vss rhigh w=0.5u l=154.313u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cm2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XC3", "displayName": "C3", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XC3 outp cm2 cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cm2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC4", "displayName": "C4", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XC4 outn cm2 cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cm2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMC1 tc1 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "tc1" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ1", "displayName": "Q1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ1 e1 cm1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "e1" }, { "id": "g", "net": "cm1" }, { "id": "s", "net": "tc1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ2", "displayName": "Q2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ2 cmo1 vr1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "vr1" }, { "id": "s", "net": "tc1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ3", "displayName": "Q3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XQ3 e1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "e1" }, { "id": "g", "net": "e1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ4", "displayName": "Q4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XQ4 cmo1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "e1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ5", "displayName": "Q5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XQ5 cmo1 cmo1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "cmo1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=4", "source": "XMC2 tc2 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4", "pins": [ { "id": "d", "net": "tc2" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ6", "displayName": "Q6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ6 e2 cm2 tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "e2" }, { "id": "g", "net": "cm2" }, { "id": "s", "net": "tc2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ7", 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"device": "XQ2", "pin": "b" }, { "device": "XMC2", "pin": "s" }, { "device": "XMC2", "pin": "b" }, { "device": "XQ6", "pin": "b" }, { "device": "XQ7", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vr1", "ground": false, "terminals": [ { "device": "XMB3", "pin": "d" }, { "device": "XMR", "pin": "d" }, { "device": "XMR", "pin": "g" }, { "device": "XQ2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tn", "ground": false, "terminals": [ { "device": "XMTN", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "a1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XCC1", "pin": "p" }, { "device": "XR1", "pin": "p" }, { "device": "XC1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { 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"device": "XQ2", "pin": "d" }, { "device": "XQ4", "pin": "d" }, { "device": "XQ5", "pin": "d" }, { "device": "XQ5", "pin": "g" } ], "ports": [ "cmo1" ], "voltageReferences": [] }, { "id": "tc2", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XQ6", "pin": "s" }, { "device": "XQ7", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "e2", "ground": false, "terminals": [ { "device": "XQ6", "pin": "d" }, { "device": "XQ8", "pin": "d" }, { "device": "XQ8", "pin": "g" }, { "device": "XQ9", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo2", "ground": false, "terminals": [ { "device": "XQ7", "pin": "d" }, { "device": "XQ9", "pin": "d" }, { "device": "XQ10", "pin": "d" }, { "device": "XQ10", "pin": "g" } ], "ports": [ "cmo2" ], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XQ7", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/fd2cmfb" } }, { "id": "graph-5", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vocm vocm 0 dc 600m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2u", "source": "Ib ib 0 2u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "fd2cmfb", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 vocm ib cmo2 cmg2 cmo1 cmg1 fd2cmfb", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "vocm", "net": "vocm" }, { "id": "ib", "net": "ib" }, { "id": "cmo2", "net": "cmo2" }, { "id": "cmg2", "net": "cmg2" }, { "id": "cmo1", "net": "cmo1" }, { "id": "cmg1", "net": "cmg1" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/fd2cmfb" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm1", "displayName": "Vbrk_cm1", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm1 cmg1 cmo1 0", "pins": [ { "id": "p", "net": "cmg1" }, { "id": "n", "net": "cmo1" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 420m", "source": "Vicm icm 0 dc 420m", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efp", "displayName": "Efp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efp inp icm outn outp 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outn" }, { "id": "cn", "net": "outp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efn", "displayName": "Efn", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efn inn icm outp outn 0.5", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm", "displayName": "Vbrk_cm", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Vbrk_cm cmg2 cmo2 dc 0 ac 1", "pins": [ { "id": "p", "net": "cmg2" }, { "id": "n", "net": "cmo2" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ibrk_cm", "displayName": "Ibrk_cm", "spiceType": "I", "model": null, "parametersOrValue": "dc 0 ac 0", "source": "Ibrk_cm 0 cmg2 dc 0 ac 0", "pins": [ { "id": "p", "net": "0" }, { "id": "n", "net": "cmg2" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" }, { "device": "Ibrk_cm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" }, { "device": "Xdut", "pin": "vocm" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Efp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Efn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Efp", "pin": "cn" }, { "device": "Efn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Efp", "pin": "cp" }, { "device": "Efn", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo2", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo2" }, { "device": "Vbrk_cm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg2", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg2" }, { "device": "Vbrk_cm", "pin": "p" }, { "device": "Ibrk_cm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo1", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo1" }, { "device": "Vbrk_cm1", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg1", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg1" }, { "device": "Vbrk_cm1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Efp", "pin": "n" }, { "device": "Efn", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/fd2cmfb", "name": "fd2cmfb", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "vocm", "net": "vocm" }, { "name": "ib", "net": "ib" }, { "name": "cmo2", "net": "cmo2" }, { "name": "cmg2", "net": "cmg2" }, { "name": "cmo1", "net": "cmo1" }, { "name": "cmg1", "net": "cmg1" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB1 vgn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMB2 vgn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMB3 vr1 ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "vr1" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR", "displayName": "MR", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=1", "source": "XMR vr1 vr1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vr1" }, { "id": "g", "net": "vr1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTN", "displayName": "MTN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=3", "source": "XMTN tn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=3", "pins": [ { "id": "d", "net": "tn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XM1 a1 inp tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XM2 a2 inn tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTP", "displayName": "MTP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTP tp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "tp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTQ", "displayName": "MTQ", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMTQ tp cmg1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "tp" }, { "id": "g", "net": "cmg1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=1u ng=6 m=1", "source": "XM3 a1 inp tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tp" }, { "id": "b", "net": "tp" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=1u ng=6 m=1", "source": "XM4 a2 inn tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tp" }, { "id": "b", "net": "tp" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=10", "source": "XM5 outp a1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "a1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=10", "source": "XM6 outn a2 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "a2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=12", "source": "XM7 outp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=12", "source": "XM8 outn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=8", "source": "XM9 outp cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "cmg2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=8", "source": "XM10 outn cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "cmg2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC1 a1 z1 cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC2 a2 z2 cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XR1 a1 cm1 vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "cm1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal 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"w=0.5u l=154.313u", "source": "XR3 outp cm2 vss rhigh w=0.5u l=154.313u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cm2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR4", "displayName": "R4", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=154.313u", "source": "XR4 outn cm2 vss rhigh w=0.5u l=154.313u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cm2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XC3", "displayName": "C3", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XC3 outp cm2 cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cm2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC4", "displayName": "C4", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XC4 outn cm2 cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cm2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMC1 tc1 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "tc1" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ1", "displayName": "Q1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ1 e1 cm1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "e1" }, { "id": "g", "net": "cm1" }, { "id": "s", "net": "tc1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ2", "displayName": "Q2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ2 cmo1 vr1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "vr1" }, { "id": "s", "net": "tc1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ3", "displayName": "Q3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XQ3 e1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "e1" }, { "id": "g", "net": "e1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ4", "displayName": "Q4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XQ4 cmo1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "e1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ5", "displayName": "Q5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XQ5 cmo1 cmo1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "cmo1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=4", "source": "XMC2 tc2 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4", "pins": [ { "id": "d", "net": "tc2" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ6", "displayName": "Q6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ6 e2 cm2 tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "e2" }, { "id": "g", "net": "cm2" }, { "id": "s", "net": "tc2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ7", "displayName": "Q7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ7 cmo2 vocm tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "tc2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ8", "displayName": "Q8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=2", "source": "XQ8 e2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=2", "pins": [ { "id": "d", "net": "e2" }, { "id": "g", "net": "e2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ9", "displayName": "Q9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XQ9 cmo2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "e2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ10", "displayName": "Q10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XQ10 cmo2 cmo2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "cmo2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB3", "pin": "g" }, { "device": "XMTP", "pin": "g" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { 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"ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMB2", "pin": "d" }, { "device": "XMB2", "pin": "g" }, { "device": "XMTN", "pin": "g" }, { "device": "XMC1", "pin": "g" }, { "device": "XMC2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMR", "pin": "s" }, { "device": "XMR", "pin": "b" }, { "device": "XMTN", "pin": "s" }, { "device": "XMTN", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XRZ1", "pin": "substrate" }, { "device": "XRZ2", "pin": "substrate" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR2", "pin": "substrate" }, { "device": "XR3", "pin": "substrate" }, { "device": "XR4", "pin": "substrate" }, { "device": "XMC1", "pin": "s" }, { "device": "XMC1", "pin": "b" }, { "device": "XQ1", "pin": "b" }, { "device": "XQ2", "pin": "b" }, { "device": "XMC2", "pin": "s" }, { "device": "XMC2", "pin": "b" }, { "device": "XQ6", "pin": "b" }, { "device": "XQ7", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vr1", "ground": false, "terminals": [ { "device": "XMB3", "pin": "d" }, { "device": "XMR", "pin": "d" }, { "device": "XMR", "pin": "g" }, { "device": "XQ2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tn", "ground": false, "terminals": [ { "device": "XMTN", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "a1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XCC1", "pin": "p" }, { "device": "XR1", "pin": "p" }, { "device": "XC1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM3", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "a2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "g" }, { "device": "XCC2", "pin": "p" }, { "device": "XR2", "pin": "p" }, { "device": "XC2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "tp", "ground": false, "terminals": [ { "device": "XMTP", "pin": "d" }, { "device": "XMTQ", "pin": "d" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg1", "ground": false, "terminals": [ { "device": "XMTQ", "pin": "g" } ], "ports": [ "cmg1" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "d" }, { "device": "XRZ1", "pin": "n" }, { "device": "XR3", "pin": "p" }, { "device": "XC3", "pin": "p" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XRZ2", "pin": "n" }, { "device": "XR4", "pin": "p" }, { "device": "XC4", "pin": "p" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "cmg2", "ground": false, "terminals": [ { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [ "cmg2" ], "voltageReferences": [] }, { "id": "z1", "ground": false, "terminals": [ { "device": "XCC1", "pin": "n" }, { "device": "XRZ1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z2", "ground": false, "terminals": [ { "device": "XCC2", "pin": "n" }, { "device": "XRZ2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cm1", "ground": false, "terminals": [ { "device": "XR1", "pin": "n" }, { "device": "XR2", "pin": "n" }, { "device": "XC1", "pin": "n" }, { "device": "XC2", "pin": "n" }, { "device": "XQ1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cm2", "ground": false, "terminals": [ { "device": "XR3", "pin": "n" }, { "device": "XR4", "pin": "n" }, { "device": "XC3", "pin": "n" }, { "device": "XC4", "pin": "n" }, { "device": "XQ6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tc1", "ground": false, "terminals": [ { "device": "XMC1", "pin": "d" }, { "device": "XQ1", "pin": "s" }, { "device": "XQ2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "e1", "ground": false, "terminals": [ { "device": "XQ1", "pin": "d" }, { "device": "XQ3", "pin": "d" }, { "device": "XQ3", "pin": "g" }, { "device": "XQ4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo1", "ground": false, "terminals": [ { "device": "XQ2", "pin": "d" }, { "device": "XQ4", "pin": "d" }, { "device": "XQ5", "pin": "d" }, { "device": "XQ5", "pin": "g" } ], "ports": [ "cmo1" ], "voltageReferences": [] }, { "id": "tc2", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XQ6", "pin": "s" }, { "device": "XQ7", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "e2", "ground": false, "terminals": [ { "device": "XQ6", "pin": "d" }, { "device": "XQ8", "pin": "d" }, { "device": "XQ8", "pin": "g" }, { "device": "XQ9", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo2", "ground": false, "terminals": [ { "device": "XQ7", "pin": "d" }, { "device": "XQ9", "pin": "d" }, { "device": "XQ10", "pin": "d" }, { "device": "XQ10", "pin": "g" } ], "ports": [ "cmo2" ], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XQ7", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/fd2cmfb" } }, { "id": "graph-6", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m pulse(600m 650m 200n 1n 1n 1u 4u)", "source": "Vocm vocm 0 dc 600m pulse(600m 650m 200n 1n 1n 1u 4u)", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2u", "source": "Ib ib 0 2u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "fd2cmfb", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 vocm ib cmo2 cmg2 cmo1 cmg1 fd2cmfb", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "vocm", "net": "vocm" }, { "id": "ib", "net": "ib" }, { "id": "cmo2", "net": "cmo2" }, { "id": "cmg2", "net": "cmg2" }, { "id": "cmo1", "net": "cmo1" }, { "id": "cmg1", "net": "cmg1" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/fd2cmfb" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm", "displayName": "Vbrk_cm", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm cmg2 cmo2 0", "pins": [ { "id": "p", "net": "cmg2" }, { "id": "n", "net": "cmo2" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm1", "displayName": "Vbrk_cm1", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm1 cmg1 cmo1 0", "pins": [ { "id": "p", "net": "cmg1" }, { "id": "n", "net": "cmo1" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 420m", "source": "Vicm icm 0 dc 420m", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efp", "displayName": "Efp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efp inp icm outn outp 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outn" }, { "id": "cn", "net": "outp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efn", "displayName": "Efn", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efn inn icm outp outn 0.5", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" }, { "device": "Xdut", "pin": "vocm" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Efp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Efn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Efp", "pin": "cn" }, { "device": "Efn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Efp", "pin": "cp" }, { "device": "Efn", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo2", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo2" }, { "device": "Vbrk_cm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg2", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg2" }, { "device": "Vbrk_cm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo1", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo1" }, { "device": "Vbrk_cm1", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg1", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg1" }, { "device": "Vbrk_cm1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Efp", "pin": "n" }, { "device": "Efn", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/fd2cmfb", "name": "fd2cmfb", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "vocm", "net": "vocm" }, { "name": "ib", "net": "ib" }, { "name": "cmo2", "net": "cmo2" }, { "name": "cmg2", "net": "cmg2" }, { "name": "cmo1", "net": "cmo1" }, { "name": "cmg1", "net": "cmg1" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB1 vgn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMB2 vgn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMB3 vr1 ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "vr1" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR", "displayName": "MR", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=1", "source": "XMR vr1 vr1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vr1" }, { "id": "g", "net": "vr1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTN", "displayName": "MTN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=3", "source": "XMTN tn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=3", "pins": [ { "id": "d", "net": "tn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XM1 a1 inp tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XM2 a2 inn tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTP", "displayName": "MTP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTP tp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "tp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTQ", "displayName": "MTQ", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMTQ tp cmg1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "tp" }, { "id": "g", "net": "cmg1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=1u ng=6 m=1", "source": "XM3 a1 inp tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tp" }, { "id": "b", "net": "tp" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=1u ng=6 m=1", "source": "XM4 a2 inn tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tp" }, { "id": "b", "net": "tp" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=10", "source": "XM5 outp a1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "a1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=10", "source": "XM6 outn a2 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "a2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=12", "source": "XM7 outp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=12", "source": "XM8 outn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=8", "source": "XM9 outp cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "cmg2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=8", "source": "XM10 outn cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "cmg2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC1 a1 z1 cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC2 a2 z2 cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XR1 a1 cm1 vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "cm1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XR2 a2 cm1 vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "cm1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XC1", "displayName": "C1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=8.112u l=8.112u", "source": "XC1 a1 cm1 cap_cmim w=8.112u l=8.112u", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "cm1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC2", "displayName": "C2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=8.112u l=8.112u", "source": "XC2 a2 cm1 cap_cmim w=8.112u l=8.112u", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "cm1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XR3", "displayName": "R3", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=154.313u", "source": "XR3 outp cm2 vss rhigh w=0.5u l=154.313u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cm2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR4", "displayName": "R4", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=154.313u", "source": "XR4 outn cm2 vss rhigh w=0.5u l=154.313u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cm2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XC3", "displayName": "C3", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XC3 outp cm2 cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cm2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC4", "displayName": "C4", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XC4 outn cm2 cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cm2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMC1 tc1 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "tc1" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ1", "displayName": "Q1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ1 e1 cm1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "e1" }, { "id": "g", "net": "cm1" }, { "id": "s", "net": "tc1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ2", "displayName": "Q2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ2 cmo1 vr1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "vr1" }, { "id": "s", "net": "tc1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ3", "displayName": "Q3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XQ3 e1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "e1" }, { "id": "g", "net": "e1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ4", "displayName": "Q4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XQ4 cmo1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "e1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ5", "displayName": "Q5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XQ5 cmo1 cmo1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "cmo1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=4", "source": "XMC2 tc2 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4", "pins": [ { "id": "d", "net": "tc2" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ6", "displayName": "Q6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ6 e2 cm2 tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "e2" }, { "id": "g", "net": "cm2" }, { "id": "s", "net": "tc2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ7", "displayName": "Q7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ7 cmo2 vocm tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "tc2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ8", "displayName": "Q8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=2", "source": "XQ8 e2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=2", "pins": [ { "id": "d", "net": "e2" }, { "id": "g", "net": "e2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ9", "displayName": "Q9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XQ9 cmo2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "e2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ10", "displayName": "Q10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XQ10 cmo2 cmo2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "cmo2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB3", "pin": "g" }, { "device": "XMTP", "pin": "g" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XMTP", "pin": "s" }, { "device": "XMTP", "pin": "b" }, { "device": "XMTQ", "pin": "s" }, { "device": "XMTQ", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XQ3", "pin": "s" }, { "device": "XQ3", "pin": "b" }, { "device": "XQ4", "pin": "s" }, { "device": "XQ4", "pin": "b" }, { "device": "XQ5", "pin": "s" }, { "device": "XQ5", "pin": "b" }, { "device": "XQ8", "pin": "s" }, { "device": "XQ8", "pin": "b" }, { "device": "XQ9", "pin": "s" }, { "device": "XQ9", "pin": "b" }, { "device": "XQ10", "pin": "s" }, { "device": "XQ10", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vgn", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMB2", "pin": "d" }, { "device": "XMB2", "pin": "g" }, { "device": "XMTN", "pin": "g" }, { "device": "XMC1", "pin": "g" }, { "device": "XMC2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMR", "pin": "s" }, { "device": "XMR", "pin": "b" }, { "device": "XMTN", "pin": "s" }, { "device": "XMTN", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XRZ1", "pin": "substrate" }, { "device": "XRZ2", "pin": "substrate" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR2", "pin": "substrate" }, { "device": "XR3", "pin": "substrate" }, { "device": "XR4", "pin": "substrate" }, { "device": "XMC1", "pin": "s" }, { "device": "XMC1", "pin": "b" }, { "device": "XQ1", "pin": "b" }, { "device": "XQ2", "pin": "b" }, { "device": "XMC2", "pin": "s" }, { "device": "XMC2", "pin": "b" }, { "device": "XQ6", "pin": "b" }, { "device": "XQ7", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vr1", "ground": false, "terminals": [ { "device": "XMB3", "pin": "d" }, { "device": "XMR", "pin": "d" }, { "device": "XMR", "pin": "g" }, { "device": "XQ2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tn", "ground": false, "terminals": [ { "device": "XMTN", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "a1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XCC1", "pin": "p" }, { "device": "XR1", "pin": "p" }, { "device": "XC1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM3", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "a2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", 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"XC3", "pin": "p" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XRZ2", "pin": "n" }, { "device": "XR4", "pin": "p" }, { "device": "XC4", "pin": "p" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "cmg2", "ground": false, "terminals": [ { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [ "cmg2" ], "voltageReferences": [] }, { "id": "z1", "ground": false, "terminals": [ { "device": "XCC1", "pin": "n" }, { "device": "XRZ1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z2", "ground": false, "terminals": [ { "device": "XCC2", "pin": "n" }, { "device": "XRZ2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cm1", "ground": false, "terminals": [ { "device": "XR1", "pin": "n" }, { "device": "XR2", "pin": "n" }, { "device": "XC1", "pin": "n" }, { "device": "XC2", "pin": "n" }, { "device": "XQ1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cm2", "ground": false, "terminals": [ { "device": "XR3", "pin": "n" }, { "device": "XR4", "pin": "n" }, { "device": "XC3", "pin": "n" }, { "device": "XC4", "pin": "n" }, { "device": "XQ6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tc1", "ground": false, "terminals": [ { "device": "XMC1", "pin": "d" }, { "device": "XQ1", "pin": "s" }, { "device": "XQ2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "e1", "ground": false, "terminals": [ { "device": "XQ1", "pin": "d" }, { "device": "XQ3", "pin": "d" }, { "device": "XQ3", "pin": "g" }, { "device": "XQ4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo1", "ground": false, "terminals": [ { "device": "XQ2", "pin": "d" }, { "device": "XQ4", "pin": "d" }, { "device": "XQ5", "pin": "d" }, { "device": "XQ5", "pin": "g" } ], "ports": [ "cmo1" ], "voltageReferences": [] }, { "id": "tc2", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XQ6", "pin": "s" }, { "device": "XQ7", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "e2", "ground": false, "terminals": [ { "device": "XQ6", "pin": "d" }, { "device": "XQ8", "pin": "d" }, { "device": "XQ8", "pin": "g" }, { "device": "XQ9", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo2", "ground": false, "terminals": [ { "device": "XQ7", "pin": "d" }, { "device": "XQ9", "pin": "d" }, { "device": "XQ10", "pin": "d" }, { "device": "XQ10", "pin": "g" } ], "ports": [ "cmo2" ], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XQ7", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/fd2cmfb" } }, { "id": "graph-7", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vocm vocm 0 dc 600m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2u", "source": "Ib ib 0 2u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "fd2cmfb", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 vocm ib cmo2 cmg2 cmo1 cmg1 fd2cmfb", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "vocm", "net": "vocm" }, { "id": "ib", "net": "ib" }, { "id": "cmo2", "net": "cmo2" }, { "id": "cmg2", "net": "cmg2" }, { "id": "cmo1", "net": "cmo1" }, { "id": "cmg1", "net": "cmg1" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/fd2cmfb" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm", "displayName": "Vbrk_cm", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm cmg2 cmo2 0", "pins": [ { "id": "p", "net": "cmg2" }, { "id": "n", "net": "cmo2" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm1", "displayName": "Vbrk_cm1", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm1 cmg1 cmo1 0", "pins": [ { "id": "p", "net": "cmg1" }, { "id": "n", "net": "cmo1" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 420m", "source": "Vicm icm 0 dc 420m", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efp", "displayName": "Efp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efp fsp icm outn outp 0.5", "pins": [ { "id": "p", "net": "fsp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outn" }, { "id": "cn", "net": "outp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efn", "displayName": "Efn", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efn fsn icm outp outn 0.5", "pins": [ { "id": "p", "net": "fsn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vsp", "displayName": "Vsp", "spiceType": "V", "model": null, "parametersOrValue": "dc -100m pulse(-100m 100m 200n 1n 1n 1u 4u)", "source": "Vsp inp fsp dc -100m pulse(-100m 100m 200n 1n 1n 1u 4u)", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "fsp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vsn", "displayName": "Vsn", "spiceType": "V", "model": null, "parametersOrValue": "dc 100m pulse(100m -100m 200n 1n 1n 1u 4u)", "source": "Vsn inn fsn dc 100m pulse(100m -100m 200n 1n 1n 1u 4u)", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "fsn" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" }, { "device": "Xdut", "pin": "vocm" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vsp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vsn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Efp", "pin": "cn" }, { "device": "Efn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Efp", "pin": "cp" }, { "device": "Efn", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo2", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo2" }, { "device": "Vbrk_cm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg2", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg2" }, { "device": "Vbrk_cm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo1", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo1" }, { "device": "Vbrk_cm1", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg1", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg1" }, { "device": "Vbrk_cm1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Efp", "pin": "n" }, { "device": "Efn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "fsp", "ground": false, "terminals": [ { "device": "Efp", "pin": "p" }, { "device": "Vsp", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "fsn", "ground": false, "terminals": [ { "device": "Efn", "pin": "p" }, { "device": "Vsn", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/fd2cmfb", "name": "fd2cmfb", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "vocm", "net": "vocm" }, { "name": "ib", "net": "ib" }, { "name": "cmo2", "net": "cmo2" }, { "name": "cmg2", "net": "cmg2" }, { "name": "cmo1", "net": "cmo1" }, { "name": "cmg1", "net": "cmg1" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB1 vgn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMB2 vgn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMB3 vr1 ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "vr1" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR", "displayName": "MR", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=1", "source": "XMR vr1 vr1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vr1" }, { "id": "g", "net": "vr1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTN", "displayName": "MTN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=3", "source": "XMTN tn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=3", "pins": [ { "id": "d", "net": "tn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XM1 a1 inp tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XM2 a2 inn tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTP", "displayName": "MTP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTP tp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "tp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTQ", "displayName": "MTQ", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMTQ tp cmg1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "tp" }, { "id": "g", "net": "cmg1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=1u ng=6 m=1", "source": "XM3 a1 inp tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tp" }, { "id": "b", "net": "tp" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=1u ng=6 m=1", "source": "XM4 a2 inn tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tp" }, { "id": "b", "net": "tp" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=10", "source": "XM5 outp a1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "a1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=10", "source": "XM6 outn a2 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "a2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=12", "source": "XM7 outp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=12", "source": "XM8 outn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=8", "source": "XM9 outp cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "cmg2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=8", "source": "XM10 outn cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "cmg2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC1 a1 z1 cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC2 a2 z2 cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XR1 a1 cm1 vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "cm1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XR2 a2 cm1 vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "cm1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XC1", "displayName": "C1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=8.112u l=8.112u", "source": "XC1 a1 cm1 cap_cmim w=8.112u l=8.112u", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "cm1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC2", "displayName": "C2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=8.112u l=8.112u", "source": "XC2 a2 cm1 cap_cmim w=8.112u l=8.112u", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "cm1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XR3", "displayName": "R3", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=154.313u", "source": "XR3 outp cm2 vss rhigh w=0.5u l=154.313u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cm2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR4", "displayName": "R4", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=154.313u", "source": "XR4 outn cm2 vss rhigh w=0.5u l=154.313u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cm2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XC3", "displayName": "C3", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XC3 outp cm2 cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cm2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC4", "displayName": "C4", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XC4 outn cm2 cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cm2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMC1 tc1 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "tc1" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ1", "displayName": "Q1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ1 e1 cm1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "e1" }, { "id": "g", "net": "cm1" }, { "id": "s", "net": "tc1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ2", "displayName": "Q2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ2 cmo1 vr1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "vr1" }, { "id": "s", "net": "tc1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ3", "displayName": "Q3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XQ3 e1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "e1" }, { "id": "g", "net": "e1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ4", "displayName": "Q4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XQ4 cmo1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "e1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ5", "displayName": "Q5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XQ5 cmo1 cmo1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "cmo1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=4", "source": "XMC2 tc2 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4", "pins": [ { "id": "d", "net": "tc2" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ6", "displayName": "Q6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ6 e2 cm2 tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "e2" }, { "id": "g", "net": "cm2" }, { "id": "s", "net": "tc2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ7", "displayName": "Q7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ7 cmo2 vocm tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "tc2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ8", "displayName": "Q8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=2", "source": "XQ8 e2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=2", "pins": [ { "id": "d", "net": "e2" }, { "id": "g", "net": "e2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ9", "displayName": "Q9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XQ9 cmo2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "e2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ10", "displayName": "Q10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XQ10 cmo2 cmo2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "cmo2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB3", "pin": "g" }, { "device": "XMTP", "pin": "g" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XMTP", "pin": "s" }, { "device": "XMTP", "pin": "b" }, { "device": "XMTQ", "pin": "s" }, { "device": "XMTQ", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XQ3", "pin": "s" }, { "device": "XQ3", "pin": "b" }, { "device": "XQ4", "pin": "s" }, { "device": "XQ4", "pin": "b" }, { "device": "XQ5", "pin": "s" }, { "device": "XQ5", "pin": "b" }, { "device": "XQ8", "pin": "s" }, { "device": "XQ8", "pin": "b" }, { "device": "XQ9", "pin": "s" }, { "device": "XQ9", "pin": "b" }, { "device": "XQ10", "pin": "s" }, { "device": "XQ10", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vgn", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMB2", "pin": "d" }, { "device": "XMB2", "pin": "g" }, { "device": "XMTN", "pin": "g" }, { "device": "XMC1", "pin": "g" }, { "device": "XMC2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMR", "pin": "s" }, { "device": "XMR", "pin": "b" }, { "device": "XMTN", "pin": "s" }, { "device": "XMTN", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XRZ1", "pin": "substrate" }, { "device": "XRZ2", "pin": "substrate" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR2", "pin": "substrate" }, { "device": "XR3", "pin": "substrate" }, { "device": "XR4", "pin": "substrate" }, { "device": "XMC1", "pin": "s" }, { "device": "XMC1", "pin": "b" }, { "device": "XQ1", "pin": "b" }, { "device": "XQ2", "pin": "b" }, { "device": "XMC2", "pin": "s" }, { "device": "XMC2", "pin": "b" }, { "device": "XQ6", "pin": "b" }, { "device": "XQ7", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vr1", "ground": false, "terminals": [ { "device": "XMB3", "pin": "d" }, { "device": "XMR", "pin": "d" }, { "device": "XMR", "pin": "g" }, { "device": "XQ2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tn", "ground": false, "terminals": [ { "device": "XMTN", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "a1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XCC1", "pin": "p" }, { "device": "XR1", "pin": "p" }, { "device": "XC1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM3", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "a2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "g" }, { "device": "XCC2", "pin": "p" }, { "device": "XR2", "pin": "p" }, { "device": "XC2", "pin": "p" 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"d" }, { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XRZ2", "pin": "n" }, { "device": "XR4", "pin": "p" }, { "device": "XC4", "pin": "p" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "cmg2", "ground": false, "terminals": [ { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [ "cmg2" ], "voltageReferences": [] }, { "id": "z1", "ground": false, "terminals": [ { "device": "XCC1", "pin": "n" }, { "device": "XRZ1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z2", "ground": false, "terminals": [ { "device": "XCC2", "pin": "n" }, { "device": "XRZ2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cm1", "ground": false, "terminals": [ { "device": "XR1", "pin": "n" }, { "device": "XR2", "pin": "n" }, { "device": "XC1", "pin": "n" }, { "device": "XC2", "pin": "n" }, { "device": "XQ1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cm2", "ground": false, "terminals": [ { "device": "XR3", "pin": "n" }, { "device": "XR4", "pin": "n" }, { "device": "XC3", "pin": "n" }, { "device": "XC4", "pin": "n" }, { "device": "XQ6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tc1", "ground": false, "terminals": [ { "device": "XMC1", "pin": "d" }, { "device": "XQ1", "pin": "s" }, { "device": "XQ2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "e1", "ground": false, "terminals": [ { "device": "XQ1", "pin": "d" }, { "device": "XQ3", "pin": "d" }, { "device": "XQ3", "pin": "g" }, { "device": "XQ4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo1", "ground": false, "terminals": [ { "device": "XQ2", "pin": "d" }, { "device": "XQ4", "pin": "d" }, { "device": "XQ5", "pin": "d" }, { "device": "XQ5", "pin": "g" } ], "ports": [ "cmo1" ], "voltageReferences": [] }, { "id": "tc2", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XQ6", "pin": "s" }, { "device": "XQ7", "pin": "s" } ], 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PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD} ac 1", "source": "Vdd vdd 0 dc {VDD} ac 1", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vocm vocm 0 dc 600m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2u", "source": "Ib ib 0 2u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "fd2cmfb", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 vocm ib cmo2 cmg2 cmo1 cmg1 fd2cmfb", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "vocm", "net": "vocm" }, { "id": "ib", "net": "ib" }, { "id": "cmo2", "net": "cmo2" }, { "id": "cmg2", "net": "cmg2" }, { "id": "cmo1", "net": "cmo1" }, { "id": "cmg1", "net": "cmg1" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/fd2cmfb" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm", "displayName": "Vbrk_cm", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm cmg2 cmo2 0", "pins": [ { "id": "p", "net": "cmg2" }, { "id": "n", "net": "cmo2" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm1", "displayName": "Vbrk_cm1", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm1 cmg1 cmo1 0", "pins": [ { "id": "p", "net": "cmg1" }, { "id": "n", "net": "cmo1" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 420m", "source": "Vicm icm 0 dc 420m", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efp", "displayName": "Efp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efp inp icm outn outp 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outn" }, { "id": "cn", "net": "outp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efn", "displayName": "Efn", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efn inn icm outp outn 0.5", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" }, { "device": "Xdut", "pin": "vocm" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Efp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Efn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Efp", "pin": "cn" }, { "device": "Efn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Efp", "pin": "cp" }, { "device": "Efn", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo2", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo2" }, { "device": "Vbrk_cm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg2", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg2" }, { "device": "Vbrk_cm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo1", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo1" }, { "device": "Vbrk_cm1", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg1", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg1" }, { "device": "Vbrk_cm1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Efp", "pin": "n" }, { "device": "Efn", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/fd2cmfb", "name": "fd2cmfb", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "vocm", "net": "vocm" }, { "name": "ib", "net": "ib" }, { "name": "cmo2", "net": "cmo2" }, { "name": "cmg2", "net": "cmg2" }, { "name": "cmo1", "net": "cmo1" }, { "name": "cmg1", "net": "cmg1" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB1 vgn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMB2 vgn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMB3 vr1 ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "vr1" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR", "displayName": "MR", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=1", "source": "XMR vr1 vr1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vr1" }, { "id": "g", "net": "vr1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTN", "displayName": "MTN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=3", "source": "XMTN tn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=3", "pins": [ { "id": "d", "net": "tn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XM1 a1 inp tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XM2 a2 inn tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTP", "displayName": "MTP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTP tp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "tp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTQ", "displayName": "MTQ", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMTQ tp cmg1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "tp" }, { "id": "g", "net": "cmg1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=1u ng=6 m=1", "source": "XM3 a1 inp tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tp" }, { "id": "b", "net": "tp" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=1u ng=6 m=1", "source": "XM4 a2 inn tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tp" }, { "id": "b", "net": "tp" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=10", "source": "XM5 outp a1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "a1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=10", "source": "XM6 outn a2 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "a2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=12", "source": "XM7 outp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=12", "source": "XM8 outn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=8", "source": "XM9 outp cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "cmg2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=8", "source": "XM10 outn cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "cmg2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC1 a1 z1 cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC2 a2 z2 cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XR1 a1 cm1 vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "cm1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XR2 a2 cm1 vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "cm1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XC1", "displayName": "C1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=8.112u l=8.112u", "source": "XC1 a1 cm1 cap_cmim w=8.112u l=8.112u", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "cm1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC2", "displayName": "C2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=8.112u l=8.112u", "source": "XC2 a2 cm1 cap_cmim w=8.112u l=8.112u", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "cm1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XR3", "displayName": "R3", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=154.313u", "source": "XR3 outp cm2 vss rhigh w=0.5u l=154.313u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cm2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR4", "displayName": "R4", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=154.313u", "source": "XR4 outn cm2 vss rhigh w=0.5u l=154.313u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cm2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XC3", "displayName": "C3", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XC3 outp cm2 cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cm2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC4", "displayName": "C4", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XC4 outn cm2 cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cm2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMC1 tc1 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "tc1" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ1", "displayName": "Q1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ1 e1 cm1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "e1" }, { "id": "g", "net": "cm1" }, { "id": "s", "net": "tc1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ2", "displayName": "Q2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ2 cmo1 vr1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "vr1" }, { "id": "s", "net": "tc1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ3", "displayName": "Q3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XQ3 e1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "e1" }, { "id": "g", "net": "e1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ4", "displayName": "Q4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XQ4 cmo1 e1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "e1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ5", "displayName": "Q5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XQ5 cmo1 cmo1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "cmo1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=4", "source": "XMC2 tc2 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4", "pins": [ { "id": "d", "net": "tc2" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ6", "displayName": "Q6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ6 e2 cm2 tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "e2" }, { "id": "g", "net": "cm2" }, { "id": "s", "net": "tc2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ7", "displayName": "Q7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ7 cmo2 vocm tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "tc2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ8", "displayName": "Q8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=2", "source": "XQ8 e2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=2", "pins": [ { "id": "d", "net": "e2" }, { "id": "g", "net": "e2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ9", "displayName": "Q9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XQ9 cmo2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "e2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ10", "displayName": "Q10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XQ10 cmo2 cmo2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "cmo2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB3", "pin": "g" }, { "device": "XMTP", "pin": "g" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XMTP", "pin": "s" }, { "device": "XMTP", "pin": "b" }, { "device": "XMTQ", "pin": "s" }, { "device": "XMTQ", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XQ3", "pin": "s" }, { "device": "XQ3", "pin": "b" }, { "device": "XQ4", "pin": "s" }, { "device": "XQ4", "pin": "b" }, { "device": "XQ5", "pin": "s" }, { "device": "XQ5", "pin": "b" }, { "device": "XQ8", "pin": "s" }, { "device": "XQ8", "pin": "b" }, { "device": "XQ9", "pin": "s" }, { "device": "XQ9", "pin": "b" }, { "device": "XQ10", "pin": "s" }, { "device": "XQ10", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vgn", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMB2", "pin": "d" }, { "device": "XMB2", "pin": "g" }, { "device": "XMTN", "pin": "g" }, { "device": "XMC1", "pin": "g" }, { "device": "XMC2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMR", "pin": "s" }, { "device": "XMR", "pin": "b" }, { "device": "XMTN", "pin": "s" }, { "device": "XMTN", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XRZ1", "pin": "substrate" }, { "device": "XRZ2", "pin": "substrate" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR2", "pin": "substrate" }, { "device": "XR3", "pin": "substrate" }, { "device": "XR4", "pin": "substrate" }, { "device": "XMC1", "pin": "s" }, { "device": "XMC1", "pin": "b" }, { "device": "XQ1", "pin": "b" }, { "device": "XQ2", "pin": "b" }, { "device": "XMC2", "pin": "s" }, { "device": "XMC2", "pin": "b" }, { "device": "XQ6", "pin": "b" }, { "device": "XQ7", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vr1", "ground": false, "terminals": [ { "device": "XMB3", "pin": "d" }, { "device": "XMR", "pin": "d" }, { "device": "XMR", "pin": "g" }, { "device": "XQ2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tn", "ground": false, "terminals": [ { "device": "XMTN", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "a1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XCC1", "pin": "p" }, { "device": "XR1", "pin": "p" }, { "device": "XC1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM3", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "a2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "g" }, { "device": "XCC2", "pin": "p" }, { "device": "XR2", "pin": "p" }, { "device": "XC2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "tp", "ground": false, "terminals": [ { "device": "XMTP", "pin": "d" }, { "device": "XMTQ", "pin": "d" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg1", "ground": false, "terminals": [ { "device": "XMTQ", "pin": "g" } ], "ports": [ "cmg1" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "d" }, { "device": "XRZ1", "pin": "n" }, { "device": "XR3", "pin": "p" }, { "device": "XC3", "pin": "p" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XRZ2", "pin": "n" }, { "device": "XR4", "pin": "p" }, { "device": "XC4", "pin": "p" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "cmg2", "ground": false, "terminals": [ { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [ "cmg2" ], "voltageReferences": [] }, { "id": "z1", "ground": false, "terminals": [ { "device": "XCC1", "pin": "n" }, { "device": "XRZ1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z2", "ground": false, "terminals": [ { "device": "XCC2", "pin": "n" }, { "device": "XRZ2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cm1", "ground": false, "terminals": [ { "device": "XR1", "pin": "n" }, { "device": "XR2", "pin": "n" }, { "device": "XC1", "pin": "n" }, { "device": "XC2", "pin": "n" }, { "device": "XQ1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cm2", "ground": false, "terminals": [ { "device": "XR3", "pin": "n" }, { "device": "XR4", "pin": "n" }, { "device": "XC3", "pin": "n" }, { "device": "XC4", "pin": "n" }, { "device": "XQ6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tc1", "ground": false, "terminals": [ { "device": "XMC1", "pin": "d" }, { "device": "XQ1", "pin": "s" }, { "device": "XQ2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "e1", "ground": false, "terminals": [ { "device": "XQ1", "pin": "d" }, { "device": "XQ3", "pin": "d" }, { "device": "XQ3", "pin": "g" }, { "device": "XQ4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo1", "ground": false, "terminals": [ { "device": "XQ2", "pin": "d" }, { "device": "XQ4", "pin": "d" }, { "device": "XQ5", "pin": "d" }, { "device": "XQ5", "pin": "g" } ], "ports": [ "cmo1" ], "voltageReferences": [] }, { "id": "tc2", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XQ6", "pin": "s" }, { "device": "XQ7", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "e2", "ground": false, "terminals": [ { "device": "XQ6", "pin": "d" }, { "device": "XQ8", "pin": "d" }, { "device": "XQ8", "pin": "g" }, { "device": "XQ9", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo2", "ground": false, "terminals": [ { "device": "XQ7", "pin": "d" }, { "device": "XQ9", "pin": "d" }, { "device": "XQ10", "pin": "d" }, { "device": "XQ10", "pin": "g" } ], "ports": [ "cmo2" ], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XQ7", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/fd2cmfb" } }, { "id": "graph-9", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vocm vocm 0 dc 600m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2u", "source": "Ib ib 0 2u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "fd2cmfb", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 vocm ib cmo2 cmg2 cmo1 cmg1 fd2cmfb", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "vocm", "net": "vocm" }, { "id": "ib", "net": "ib" }, { "id": "cmo2", "net": "cmo2" }, { "id": "cmg2", "net": "cmg2" }, { "id": "cmo1", "net": "cmo1" }, { "id": "cmg1", "net": "cmg1" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/fd2cmfb" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm", "displayName": "Vbrk_cm", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm cmg2 cmo2 0", "pins": [ { "id": "p", "net": "cmg2" }, { "id": "n", "net": "cmo2" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm1", "displayName": "Vbrk_cm1", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm1 cmg1 cmo1 0", "pins": [ { "id": "p", "net": "cmg1" }, { "id": "n", "net": "cmo1" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 420m ac 1", "source": "Vicm icm 0 dc 420m ac 1", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efp", "displayName": "Efp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efp inp icm outn outp 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outn" }, { "id": "cn", "net": "outp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efn", "displayName": "Efn", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efn inn icm outp outn 0.5", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" }, { "device": "Xdut", "pin": "vocm" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Efp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Efn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Efp", "pin": "cn" }, { "device": "Efn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Efp", "pin": "cp" }, { "device": "Efn", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo2", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo2" }, { "device": "Vbrk_cm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg2", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg2" }, { "device": "Vbrk_cm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo1", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo1" }, { "device": "Vbrk_cm1", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg1", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg1" }, { "device": "Vbrk_cm1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Efp", "pin": "n" }, { "device": "Efn", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/fd2cmfb", "name": "fd2cmfb", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "vocm", "net": "vocm" }, { "name": "ib", "net": "ib" }, { "name": "cmo2", "net": "cmo2" }, { "name": "cmg2", "net": "cmg2" }, { "name": "cmo1", "net": "cmo1" }, { "name": "cmg1", "net": "cmg1" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB1 vgn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMB2 vgn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMB3 vr1 ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "vr1" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR", "displayName": "MR", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=1", "source": "XMR vr1 vr1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vr1" }, { "id": "g", "net": "vr1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTN", "displayName": "MTN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=3", "source": "XMTN tn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=3", "pins": [ { "id": "d", "net": "tn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XM1 a1 inp tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XM2 a2 inn tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTP", "displayName": "MTP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTP tp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "tp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTQ", "displayName": "MTQ", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMTQ tp cmg1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "tp" }, { "id": "g", "net": "cmg1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=1u ng=6 m=1", "source": "XM3 a1 inp tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tp" }, { "id": "b", "net": "tp" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=1u ng=6 m=1", "source": "XM4 a2 inn tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tp" }, { "id": "b", "net": "tp" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=10", "source": "XM5 outp a1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "a1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=10", "source": "XM6 outn a2 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "a2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=12", "source": "XM7 outp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=12", "source": "XM8 outn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=8", "source": "XM9 outp cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "cmg2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=8", "source": "XM10 outn cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "cmg2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC1 a1 z1 cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC2 a2 z2 cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XR1 a1 cm1 vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "cm1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XR2 a2 cm1 vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "cm1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XC1", "displayName": "C1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=8.112u l=8.112u", "source": "XC1 a1 cm1 cap_cmim w=8.112u l=8.112u", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "cm1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC2", "displayName": "C2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=8.112u l=8.112u", "source": "XC2 a2 cm1 cap_cmim w=8.112u l=8.112u", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "cm1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XR3", "displayName": "R3", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=154.313u", "source": "XR3 outp cm2 vss rhigh w=0.5u l=154.313u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cm2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR4", "displayName": "R4", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=154.313u", "source": "XR4 outn cm2 vss rhigh w=0.5u l=154.313u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cm2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XC3", "displayName": "C3", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XC3 outp cm2 cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cm2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC4", "displayName": "C4", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XC4 outn cm2 cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cm2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMC1 tc1 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "tc1" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ1", "displayName": "Q1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ1 e1 cm1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "e1" }, { "id": "g", "net": "cm1" }, { "id": "s", "net": "tc1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ2", "displayName": "Q2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ2 cmo1 vr1 tc1 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cmo1" }, { "id": "g", "net": "vr1" }, { "id": "s", "net": "tc1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ3", "displayName": "Q3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u 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"XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=4", "source": "XMC2 tc2 vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4", "pins": [ { "id": "d", "net": "tc2" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ6", "displayName": "Q6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ6 e2 cm2 tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "e2" }, { "id": "g", "net": "cm2" }, { "id": "s", "net": "tc2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ7", "displayName": "Q7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XQ7 cmo2 vocm tc2 vss sg13_lv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "tc2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ8", "displayName": "Q8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=2", "source": "XQ8 e2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=2", "pins": [ { "id": "d", "net": "e2" }, { "id": "g", "net": "e2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ9", "displayName": "Q9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XQ9 cmo2 e2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "e2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XQ10", "displayName": "Q10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XQ10 cmo2 cmo2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "cmo2" }, { "id": "g", "net": "cmo2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB3", "pin": "g" }, { "device": "XMTP", "pin": "g" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XMTP", "pin": "s" }, { "device": "XMTP", "pin": "b" }, { "device": "XMTQ", "pin": "s" }, { "device": "XMTQ", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XQ3", "pin": "s" }, { "device": "XQ3", "pin": "b" }, { "device": "XQ4", "pin": "s" }, { "device": "XQ4", "pin": "b" }, { "device": "XQ5", "pin": "s" }, { "device": "XQ5", "pin": "b" }, { "device": "XQ8", "pin": "s" }, { "device": "XQ8", "pin": "b" }, { "device": "XQ9", "pin": "s" }, { "device": "XQ9", "pin": "b" }, { "device": "XQ10", "pin": "s" }, { "device": "XQ10", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vgn", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMB2", "pin": "d" }, { "device": "XMB2", "pin": "g" }, { "device": "XMTN", "pin": "g" }, { "device": "XMC1", "pin": "g" }, { "device": "XMC2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMR", "pin": "s" }, { "device": "XMR", "pin": "b" }, { "device": "XMTN", "pin": "s" }, { "device": "XMTN", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XRZ1", "pin": "substrate" }, { "device": "XRZ2", "pin": "substrate" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR2", "pin": "substrate" }, { "device": "XR3", "pin": "substrate" }, { "device": "XR4", "pin": "substrate" }, { "device": "XMC1", "pin": "s" }, { "device": "XMC1", "pin": "b" }, { "device": "XQ1", "pin": "b" }, { "device": "XQ2", "pin": "b" }, { "device": "XMC2", "pin": "s" }, { "device": "XMC2", "pin": "b" }, { "device": "XQ6", "pin": "b" }, { "device": "XQ7", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vr1", "ground": false, "terminals": [ { "device": "XMB3", "pin": "d" }, { "device": "XMR", "pin": "d" }, { "device": "XMR", "pin": "g" }, { "device": "XQ2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tn", "ground": false, "terminals": [ { "device": "XMTN", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "a1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XCC1", "pin": "p" }, { "device": "XR1", "pin": "p" }, { "device": "XC1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM3", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "a2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "g" }, { "device": "XCC2", "pin": "p" }, { "device": "XR2", "pin": "p" }, { "device": "XC2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "tp", "ground": false, "terminals": [ { "device": "XMTP", "pin": "d" }, { "device": "XMTQ", "pin": "d" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg1", "ground": false, "terminals": [ { "device": "XMTQ", "pin": "g" } ], "ports": [ "cmg1" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "d" }, { "device": "XRZ1", "pin": "n" }, { "device": "XR3", "pin": "p" }, { "device": "XC3", "pin": "p" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XRZ2", "pin": "n" }, { "device": "XR4", "pin": "p" }, { "device": "XC4", "pin": "p" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "cmg2", "ground": false, "terminals": [ { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [ "cmg2" ], "voltageReferences": [] }, { "id": "z1", "ground": false, "terminals": [ { "device": "XCC1", "pin": "n" }, { "device": "XRZ1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z2", "ground": false, "terminals": [ { "device": "XCC2", "pin": "n" }, { "device": "XRZ2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cm1", "ground": false, "terminals": [ { "device": "XR1", "pin": "n" }, { "device": "XR2", "pin": "n" }, { "device": "XC1", "pin": "n" }, { "device": "XC2", "pin": "n" }, { "device": "XQ1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cm2", "ground": false, "terminals": [ { "device": "XR3", "pin": "n" }, { "device": "XR4", "pin": "n" }, { "device": "XC3", "pin": "n" }, { "device": "XC4", "pin": "n" }, { "device": "XQ6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tc1", "ground": false, "terminals": [ { "device": "XMC1", "pin": "d" }, { "device": "XQ1", "pin": "s" }, { "device": "XQ2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "e1", "ground": false, "terminals": [ { "device": "XQ1", "pin": "d" }, { "device": "XQ3", "pin": "d" }, { "device": "XQ3", "pin": "g" }, { "device": "XQ4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo1", "ground": false, "terminals": [ { "device": "XQ2", "pin": "d" }, { "device": "XQ4", "pin": "d" }, { "device": "XQ5", "pin": "d" }, { "device": "XQ5", "pin": "g" } ], "ports": [ "cmo1" ], "voltageReferences": [] }, { "id": "tc2", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XQ6", "pin": "s" }, { "device": "XQ7", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "e2", "ground": false, "terminals": [ { "device": "XQ6", "pin": "d" }, { "device": "XQ8", "pin": "d" }, { "device": "XQ8", "pin": "g" }, { "device": "XQ9", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo2", "ground": false, "terminals": [ { "device": "XQ7", "pin": "d" }, { "device": "XQ9", "pin": "d" }, { "device": "XQ10", "pin": "d" }, { "device": "XQ10", "pin": "g" } ], "ports": [ "cmo2" ], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XQ7", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/fd2cmfb" } }, { "id": "graph-10", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vocm vocm 0 dc 600m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2u", "source": "Ib ib 0 2u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "fd2cmfb", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 vocm ib cmo2 cmg2 cmo1 cmg1 fd2cmfb", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "vocm", "net": "vocm" }, { "id": "ib", "net": "ib" }, { "id": "cmo2", "net": "cmo2" }, { "id": "cmg2", "net": "cmg2" }, { "id": "cmo1", "net": "cmo1" }, { "id": "cmg1", "net": "cmg1" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/fd2cmfb" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm", "displayName": "Vbrk_cm", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm cmg2 cmo2 0", "pins": [ { "id": "p", "net": "cmg2" }, { "id": "n", "net": "cmo2" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm1", "displayName": "Vbrk_cm1", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm1 cmg1 cmo1 0", "pins": [ { "id": "p", "net": "cmg1" }, { "id": "n", "net": "cmo1" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 420m", "source": "Vicm icm 0 dc 420m", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efp", "displayName": "Efp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efp inp icm outn outp 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outn" }, { "id": "cn", "net": "outp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efn", "displayName": "Efn", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efn fsn icm outp outn 0.5", "pins": [ { "id": "p", "net": "fsn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vsn", "displayName": "Vsn", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Vsn inn fsn dc 0 ac 1", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "fsn" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" }, { "device": "Xdut", "pin": "vocm" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Efp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vsn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Efp", "pin": "cn" }, { "device": "Efn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Efp", "pin": "cp" }, { "device": "Efn", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo2", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo2" }, { "device": "Vbrk_cm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg2", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg2" }, { "device": "Vbrk_cm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo1", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo1" }, { "device": "Vbrk_cm1", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg1", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg1" }, { "device": "Vbrk_cm1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Efp", "pin": "n" }, { "device": "Efn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "fsn", "ground": false, "terminals": [ { "device": "Efn", "pin": "p" }, { "device": "Vsn", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/fd2cmfb", "name": "fd2cmfb", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "vocm", "net": "vocm" }, { "name": "ib", "net": "ib" }, { "name": "cmo2", "net": "cmo2" }, { "name": "cmg2", "net": "cmg2" }, { "name": "cmo1", "net": "cmo1" }, { "name": "cmg1", "net": "cmg1" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB1 vgn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMB2 vgn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMB3 vr1 ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "vr1" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR", "displayName": "MR", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=1", "source": "XMR vr1 vr1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vr1" }, { "id": "g", "net": "vr1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTN", "displayName": "MTN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=3", "source": "XMTN tn vgn vss vss sg13_lv_nmos w=4u l=1u ng=1 m=3", "pins": [ { "id": "d", "net": "tn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XM1 a1 inp tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XM2 a2 inn tn vss sg13_lv_nmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTP", "displayName": "MTP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTP tp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "tp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTQ", "displayName": "MTQ", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMTQ tp cmg1 vdd vdd sg13_lv_pmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "tp" }, { "id": "g", "net": "cmg1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=1u ng=6 m=1", "source": "XM3 a1 inp tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1", "pins": [ { "id": "d", "net": "a1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tp" }, { "id": "b", "net": "tp" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=1u ng=6 m=1", "source": "XM4 a2 inn tp tp sg13_lv_pmos w=24u l=1u ng=6 m=1", "pins": [ { "id": "d", "net": "a2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tp" }, { "id": "b", "net": "tp" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=10", "source": "XM5 outp a1 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "a1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=900n l=2u ng=1 m=10", "source": "XM6 outn a2 vss vss sg13_lv_nmos w=900n l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "a2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=12", "source": "XM7 outp ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=12", "source": "XM8 outn ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=12", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=8", "source": "XM9 outp cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "cmg2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=8", "source": "XM10 outn cmg2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=8", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "cmg2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC1 a1 z1 cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCC2 a2 z2 cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XR1 a1 cm1 vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "cm1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XR2 a2 cm1 vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "cm1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XC1", "displayName": "C1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=8.112u l=8.112u", "source": "XC1 a1 cm1 cap_cmim w=8.112u l=8.112u", "pins": [ { "id": "p", "net": "a1" }, { "id": "n", "net": "cm1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XC2", "displayName": "C2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=8.112u l=8.112u", "source": "XC2 a2 cm1 cap_cmim w=8.112u l=8.112u", "pins": [ { "id": "p", "net": "a2" }, { "id": "n", "net": "cm1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XR3", "displayName": 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