{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "fd-telescopic", "name": "Fully differential telescopic-cascode OTA", "group": "Fully differential", "subgroup": "Op amps and OTA cores", "title": "Telescopic-cascode OTA", "summary": "This differential amplifier obtains gain from stacked transistors in one stage per side. Most of the signal current is reused through the stack, saving power. A separate loop holds the outputs’ average voltage, but the stack leaves limited room for input and output swings.", "reference": { "kind": "paper", "authors": "Q. Fan, F. Sebastiano, J. H. Huijsing, K. A. A. Makinwa", "title": "A 1.8 uW 60 nV/sqrt(Hz) Capacitively-Coupled Chopper Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor Nodes", "year": 2011, "where": "IEEE Journal of Solid-State Circuits, 46(7):1534-1543", "doi": "10.1109/JSSC.2011.2143610", "takes": "The topology: the telescopic-cascode OTA of the paper's ripple-reduction loop integrator, with a PMOS input pair, and its common-mode feedback by a differential-difference pair whose reference-side current, through a diode, sets the NMOS sinks. The bias with its resistor-set cascode gates, the choice of common modes that fits five devices in 1.2 V at the corners, the sizing and the targets are this library's, for SG13G2." }, "resources": { "record": "/circuits/fd-telescopic.json", "page": "/index.html#fd-telescopic", "achieved": "/achieved/fd-telescopic.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "inp", "kind": "input" }, { "name": "inn", "kind": "input" }, { "name": "outp", "kind": "output" }, { "name": "outn", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" }, { "name": "vocm", "kind": "bias", "note": "the output common mode asked for, on the gates of M10, M12" }, { "name": "ib", "kind": "bias", "note": "the reference current, drawn out of this pin" }, { "name": "cmo", "kind": "bias", "note": "the differential-difference amplifier's output, the diode M14: the testbench joins it to cmg, and breaks the loop there" }, { "name": "cmg", "kind": "bias", "note": "the gates of the sinks M7, M8" } ], "devices": [ { "name": "MB", "type": "pmos", "nodes": "ib ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "bias reference, diode-connected: the gate of every PMOS source", "fingers": 14, "copies": 1 }, { "name": "MB1", "type": "pmos", "nodes": "vcp ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "one unit pushing Ib through RP1, RP2: the PMOS cascode gate", "fingers": 14, "copies": 1 }, { "name": "RP1", "type": "resistor", "nodes": "vcp rp", "sizedBy": [ "Rp" ], "role": "half of vcp's resistor to ground" }, { "name": "RP2", "type": "resistor", "nodes": "rp vss", "sizedBy": [ "Rp" ], "role": "half of vcp's resistor to ground" }, { "name": "MB2", "type": "pmos", "nodes": "vcn ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "one unit pushing Ib through RN1, RN2 into MB3", "fingers": 14, "copies": 1 }, { "name": "RN1", "type": "resistor", "nodes": "vcn rn", "sizedBy": [ "Rn" ], "role": "half the drop from vcn to vgn" }, { "name": "RN2", "type": "resistor", "nodes": "rn vgn", "sizedBy": [ "Rn" ], "role": "half the drop from vcn to vgn" }, { "name": "MB3", "type": "nmos", "nodes": "vgn vgn vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "NMOS cascode reference, diode-connected, one unit", "fingers": 4, "copies": 1 }, { "name": "MT", "type": "pmos", "nodes": "tail ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "input tail, 4 units", "fingers": 14, "copies": 4 }, { "name": "M1", "type": "pmos", "nodes": "d1 inp tail tail", "sizedBy": [ "W1", "L1" ], "role": "input pair, n-well on its source", "fingers": 8, "copies": 1 }, { "name": "M2", "type": "pmos", "nodes": "d2 inn tail tail", "sizedBy": [ "W1", "L1" ], "role": "input pair, n-well on its source", "fingers": 8, "copies": 1 }, { "name": "M3", "type": "pmos", "nodes": "outn vcp d1 d1", "sizedBy": [ "W3", "L3" ], "role": "PMOS cascode, n-well on its source", "fingers": 16, "copies": 1 }, { "name": "M4", "type": "pmos", "nodes": "outp vcp d2 d2", "sizedBy": [ "W3", "L3" ], "role": "PMOS cascode, n-well on its source", "fingers": 16, "copies": 1 }, { "name": "M5", "type": "nmos", "nodes": "outn vcn k1 vss", "sizedBy": [ "Wn", "Ln" ], "role": "NMOS cascode, 2 units", "fingers": 4, "copies": 2 }, { "name": "M6", "type": "nmos", "nodes": "outp vcn k2 vss", "sizedBy": [ "Wn", "Ln" ], "role": "NMOS cascode, 2 units", "fingers": 4, "copies": 2 }, { "name": "M7", "type": "nmos", "nodes": "k1 cmg vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "sink, 2 copies of M14", "fingers": 4, "copies": 2 }, { "name": "M8", "type": "nmos", "nodes": "k2 cmg vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "sink, 2 copies of M14", "fingers": 4, "copies": 2 }, { "name": "MTC", "type": "pmos", "nodes": "td ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "common-mode amplifier tail, 2 units", "fingers": 14, "copies": 2 }, { "name": "M9", "type": "pmos", "nodes": "sn outp td td", "sizedBy": [ "Wc", "Lc" ], "role": "common-mode sensing, gate on outp", "fingers": 4, "copies": 1 }, { "name": "M10", "type": "pmos", "nodes": "cmo vocm td td", "sizedBy": [ "Wc", "Lc" ], "role": "common-mode reference, gate on vocm", "fingers": 4, "copies": 1 }, { "name": "M11", "type": "pmos", "nodes": "sn outn td td", "sizedBy": [ "Wc", "Lc" ], "role": "common-mode sensing, gate on outn", "fingers": 4, "copies": 1 }, { "name": "M12", "type": "pmos", "nodes": "cmo vocm td td", "sizedBy": [ "Wc", "Lc" ], "role": "common-mode reference, gate on vocm", "fingers": 4, "copies": 1 }, { "name": "M13", "type": "nmos", "nodes": "sn sn vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "the sensing side's diode, a match for M14", "fingers": 4, "copies": 1 }, { "name": "M14", "type": "nmos", "nodes": "cmo cmo vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "the reference side's diode: the unit M7, M8 copy", "fingers": 4, "copies": 1 } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "The input pair: any difference between them is input offset." }, { "rule": "match", "of": [ "M9", "M10", "M11", "M12" ], "why": "The four sensing devices: a mismatch between the sensing and reference sides is a common-mode offset at the output." }, { "rule": "unit-copies", "of": [ "MB", "MB1", "MB2", "MT", "MTC" ], "constraint": "every PMOS current a whole number of Wp/Lp units, one Ib each", "why": "Repeating the same unit geometry preserves the intended nominal ratio and avoids geometry-dependent systematic shifts. Random mismatch and unequal drain voltages still cause current-copy errors." }, { "rule": "unit-copies", "of": [ "MB3", "M5", "M6", "M7", "M8", "M13", "M14" ], "constraint": "every NMOS current a whole number of Wn/Ln units", "why": "The sinks are two copies of M14, the cascodes two of MB3." }, { "rule": "balance", "of": [ "M7", "M14", "MT", "MTC" ], "constraint": "(W/L)_M7/(W/L)_M14 = I_MT/I_MTC = 2", "why": "Each sink must return half the main tail's current while M14 carries half the common-mode amplifier's; with any other ratio the amplifier balances only with the outputs off vocm." }, { "rule": "headroom", "of": [ "MT", "M1", "M3", "M5", "M7" ], "constraint": "V_OCM >= V_DS5 + V_DS7; V_SG1 + V_ICM - V_OCM >= V_SD1 + V_SD3; V_DD - V_ICM - V_SG1 >= V_SD,MT", "why": "Five devices share the supply: the common modes decide who gets what, and 0.48 V in, 0.45 V out is where all five stay saturated from 1.08 V at 125 °C to 1.32 V at -40 °C." }, { "rule": "well", "of": [ "M1", "M2", "M3", "M4", "M9", "M10", "M11", "M12" ], "constraint": "n-well on the source", "why": "Without body effect their V_SG stays small, and the PMOS cascode's V_SG matches the pair's, which is what makes vcp set the pair's V_SD." }, { "rule": "cascode-drop", "of": [ "RN1", "RN2", "MB3", "M5", "M6" ], "constraint": "V_DS of M7, M8 = Ib·2Rn less M5's body effect", "why": "The NMOS cascodes sit at MB3's current density, so the sinks keep the drop across RN1, RN2 at every corner; rppd barely moves with temperature." }, { "rule": "cascode-gate", "of": [ "RP1", "RP2", "M3", "M4" ], "constraint": "vcp = Ib·2Rp, so V_SD1 = V_ICM - vcp + V_SG1 - V_SG3", "why": "The PMOS cascode gate sits a fixed voltage above ground; the pair keeps about V_ICM - vcp across it and the cascode the rest of its budget." }, { "rule": "load-compensated", "of": [ "M14", "M7", "M8" ], "constraint": "C_L sets both loops' dominant pole; M14's pole well above the common-mode crossover", "why": "Both loops cross over on the load capacitance; the common-mode loop's second pole is M14 with the sinks' gates, so the NMOS unit is kept small enough to leave it about four times above." } ], "specs": [ { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.0001 A", "min": null, "max": 0.0001, "why": "4 Ib through the two branches, 2 Ib in the common-mode amplifier and 3 Ib of bias." }, { "key": "voc_err", "label": "Output common mode less its reference", "unit": "V", "direction": "target", "constraint": ">= -0.01 V, <= 0.01 V", "min": -0.01, "max": 0.01, "why": "The sinks copy the diode M14 from a lower V_DS, and mismatch offsets the four sensing devices: within 5 mV at every corner and 7 mV over 20 Monte Carlo draws." }, { "key": "dc_gain_db", "label": "DC differential gain", "unit": "dB", "direction": "max", "constraint": ">= 50 dB", "min": 50, "max": null, "why": "One stage, both sides cascoded: g_m1 times the two cascoded resistances in parallel; 55 dB at 27 °C, 52 dB at 125 °C, set by the NMOS side." }, { "key": "ugf_hz", "label": "Unity-gain frequency", "unit": "Hz", "direction": "max", "constraint": ">= 12000000 Hz", "min": 12000000, "max": null, "why": "g_m1/C_L: 20 MHz typical, 16 MHz at the slowest corner." }, { "key": "pm_deg", "label": "Phase margin", "unit": "deg", "direction": "max", "constraint": ">= 65 deg", "min": 65, "max": null, "why": "The load is the dominant pole; the cascode sources are the next ones, far above: 76° or more at every corner." }, { "key": "cm_pm_deg", "label": "Common-mode loop: phase margin", "unit": "deg", "direction": "max", "constraint": ">= 60 deg", "min": 60, "max": null, "why": "The common-mode loop's dominant pole is also the load; its second is the diode M14 with the sinks' gates, which the NMOS unit's size keeps about four times above the crossover." }, { "key": "cm_settle", "label": "Common-mode settling, 1 %", "unit": "s", "direction": "min", "constraint": "<= 1e-7 s", "min": null, "max": 1e-7 }, { "key": "sr", "label": "Slew rate", "unit": "V/s", "direction": "max", "constraint": ">= 4000000 V/s", "min": 4000000, "max": null, "why": "The tail's 4 Ib into the two loads, differentially: about 6 V/µs." }, { "key": "t_settle", "label": "Settling time, 1 %", "unit": "s", "direction": "min", "constraint": "<= 6e-8 s", "min": null, "max": 6e-8 }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz, differential", "unit": "dB", "direction": "max", "constraint": ">= 80 dB", "min": 80, "max": null, "why": "Set by mismatch alone: 89 dB at the worst of 20 Monte Carlo draws." }, { "key": "psrr_cm_db", "label": "Supply rejection at 1 kHz, common mode", "unit": "dB", "direction": "max", "constraint": ">= 25 dB", "min": 25, "max": null, "why": "The tail's output resistance carries supply ripple into both branches alike; at 1.08 V, hot and slow, the tail is closest to leaving saturation and lets most through, 28 dB." }, { "key": "cmrr_db", "label": "Common-mode rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 60 dB", "min": 60, "max": null, "why": "Set by mismatch alone: 65 dB at the worst of 20 Monte Carlo draws." } ], "explanation": { "idea": "This differential amplifier obtains gain from stacked transistors in one stage per side. Most of the signal current is reused through the stack, saving power. A separate loop holds the outputs’ average voltage, but the stack leaves limited room for input and output swings.", "detail": "A single-stage fully differential OTA in which each side is one branch of five stacked devices: the shared PMOS tail, an input device, a PMOS cascode, an NMOS cascode and a sink. All the gain is made at one high-impedance node per side, where both cascoded resistances meet, for very little current, and the load capacitance compensates it. A differential-difference amplifier holds the output common mode: its devices sense the outputs at their gates, so it puts no resistor on them.", "lesson": { "relation": 1, "symbols": "f_u (also called GBW here) is unity-gain frequency in Hz; g_m1 is one input transistor's small-signal transconductance in S; C_L is load capacitance in F. Where angular frequency is used, ω_u = 2π f_u.", "assumptions": "Small signals, saturated devices and an output-dominated response. The simple relation neglects device capacitance and higher-frequency internal poles.", "exercise": { "param": "CL", "value": 4e-12, "analysis": "open_loop", "expect": "Doubling the load capacitance should reduce unity-gain frequency, roughly by half if the load dominates. Compare phase margin and DC gain rather than expecting every metric to halve." }, "limits": "Provide the bias current and keep input common mode and output swing inside their separate measured ranges. This is not a rail-to-rail input/output guarantee." }, "path": [ { "part": "Input pair", "devices": "MT, M1, M2", "does": "MT's 4 Ib splits between the PMOS pair, whose n-wells sit on their sources; a rise on inp takes current from M1's branch." }, { "part": "Cascodes and outputs", "devices": "M3, M4, M5, M6, M7, M8", "does": "The PMOS cascodes M3, M4 carry the pair's currents down to outn and outp, where the cascoded sinks M5 over M7 and M6 over M8 meet them: each output sees both cascoded resistances." }, { "part": "Common-mode sensing", "devices": "MTC, M9, M10, M11, M12", "does": "M9 and M11, gates on the outputs, and M10 and M12, gates on vocm, share MTC's 2 Ib; a purely differential output leaves the sensing side's total unchanged, a common-mode rise above vocm moves current to the reference side." }, { "part": "Common-mode loop", "devices": "M13, M14, M7, M8", "does": "The diode M14 turns the reference side's current into cmo, which the sinks M7, M8 copy twice each; M13 is the sensing side's matching diode. As the outputs rise, the sinks pull harder and bring them down." } ], "bias": "The bench draws Ib out of the PMOS diode MB; MT and MTC are copies. MB1 pushes Ib through RP1, RP2 to ground, which sets the PMOS cascode gate vcp, and MB2 pushes Ib through RN1, RN2 into the NMOS diode MB3, which puts vcn a fixed drop above an NMOS gate voltage. Five devices share 1.2 V: the outputs get the NMOS cascode and sink, the pair and the PMOS cascode share the pair's V_SG plus the 30 mV by which the inputs, at 0.48 V, sit above the outputs, at 0.45 V, and the tail keeps the rest.", "relations": [ { "what": "Differential gain", "expr": "A_d ≈ g_m1·[(g_m3·r_o3·r_o1) ∥ (g_m5·r_o5·r_o7)]", "note": "Both cascoded resistances meet at each output; with one stage this is the whole gain, and the NMOS side sets it." }, { "what": "Unity-gain frequency", "expr": "ω_u ≈ g_m1/C_L", "note": "Single stage: the load capacitance is the compensation, so a heavier load adds margin." }, { "what": "Common-mode sensing", "expr": "ΔI_M14 ≈ g_m10·(V_oc − V_ocm)", "note": "Equal devices on one tail; a differential output changes nothing to first order." }, { "what": "Output common mode", "expr": "V_oc = V_ocm when (W/L)_M7/(W/L)_M14 = I_MT/I_MTC", "note": "Each sink must return half the main tail's current while M14 carries half the common-mode tail's." }, { "what": "Headroom", "expr": "V_ocm ≥ V_DS5 + V_DS7; V_SG1 + V_icm − V_ocm ≥ V_SD1 + V_SD3", "note": "The two budgets the common modes divide; the tail takes what the input common mode and V_SG1 leave of V_DD." } ], "tradeoffs": [ "Common modes: a higher input common mode gives the pair and its cascode room and takes it from the tail; a higher output common mode gives the NMOS side room and takes it from both.", "NMOS unit size: longer raises the gain and holds the sinks' copy of M14 closer, but loads M14's node, the common-mode loop's second pole.", "Input pair width: narrower raises V_SG1, the budget the pair and its cascode share, at some cost in g_m1 and noise.", "Common-mode sensing devices: wider lowers their V_SG, which keeps MTC saturated at 1.08 V, and adds capacitance to the outputs." ] }, "sizing": [ { "key": "Ib", "label": "Reference current", "unit": "A", "value": 0.00001, "min": 0.000002, "max": 0.00002, "kind": "si" }, { "key": "W1", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.00004, "min": 0.000001, "max": 0.00016, "kind": "si" }, { "key": "L1", "label": "L input pair", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000002, "kind": "si" }, { "key": "W3", "label": "W PMOS cascodes (M3, M4)", "unit": "m", "value": 0.00008, "min": 0.000001, "max": 0.00016, "kind": "si" }, { "key": "L3", "label": "L PMOS cascodes", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000002, "kind": "si" }, { "key": "Wn", "label": "W NMOS unit", "unit": "m", "value": 0.000012, "min": 0.000001, "max": 0.00004, "kind": "si" }, { "key": "Ln", "label": "L NMOS unit", "unit": "m", "value": 0.0000015, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wp", "label": "W PMOS unit", "unit": "m", "value": 0.000064, "min": 0.000001, "max": 0.0001, "kind": "si" }, { "key": "Lp", "label": "L PMOS unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wc", "label": "W common-mode sensing unit (M9-M12)", "unit": "m", "value": 0.00002, "min": 0.000001, "max": 0.00004, "kind": "si" }, { "key": "Lc", "label": "L common-mode sensing unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Rp", "label": "PMOS cascode gate resistor, each of two (RP1, RP2)", "unit": "Ω", "value": 14000, "min": 2000, "max": 19900, "kind": "si" }, { "key": "Rn", "label": "NMOS cascode drop, each of two (RN1, RN2)", "unit": "Ω", "value": 12000, "min": 2000, "max": 19900, "kind": "si" }, { "key": "CL", "label": "Load capacitance, per side", "unit": "F", "value": 2e-12, "min": 1e-13, "max": 2e-11, "kind": "si" }, { "key": "VICM", "label": "Input common mode", "unit": "V", "value": 0.48, "min": 0.4, "max": 0.52, "kind": "si" }, { "key": "VOCM", "label": "Output common mode asked for", "unit": "V", "value": 0.45, "min": 0.42, "max": 0.5, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The amplifier as a unity-gain differential buffer, its inputs at their common mode: the current it draws, where its output common mode lands against the reference on vocm, and the differential offset.", "measures": [], "metricKeys": [ "i_supply", "voc", "voc_err", "vos" ], "acceptance": [ "i_supply", "voc_err" ], "acceptanceRules": [ { "key": "i_supply", "unit": "A", "min": null, "max": 0.0001, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "voc_err", "unit": "V", "min": -0.01, "max": 0.01, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Fully differential telescopic-cascode OTA - operating point as a unity-gain differential buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVocm vocm 0 dc 450m\nIb ib 0 10u\n.subckt fdtele inp inn outp outn vdd vss vocm ib cmo cmg\n* bias: the reference drawn out of a PMOS diode; the cascode gates from two copies\nXMB ib ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXMB1 vcp ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXRP1 vcp rp vss rppd w=0.5u l=27.294u\nXRP2 rp vss vss rppd w=0.5u l=27.294u\nXMB2 vcn ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXRN1 vcn rn vss rppd w=0.5u l=23.355u\nXRN2 rn vgn vss rppd w=0.5u l=23.355u\nXMB3 vgn vgn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\n* the telescopic branch, one per side: tail, pair, PMOS cascode, NMOS cascode, sink\nXMT tail ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=4\nXM1 d1 inp tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1\nXM2 d2 inn tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1\nXM3 outn vcp d1 d1 sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM4 outp vcp d2 d2 sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM5 outn vcn k1 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM6 outp vcn k2 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM7 k1 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM8 k2 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\n* the differential-difference common-mode amplifier: four PMOS on one tail\nXMTC td ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=2\nXM9 sn outp td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM10 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM11 sn outn td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM12 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM13 sn sn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\nXM14 cmo cmo vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\n.ends\nXdut inp inn outp outn vdd 0 vocm ib cmo cmg fdtele\nClp outp 0 2p\nCln outn 0 2p\n* the common-mode loop, joined at its break point\nVbrk_cm cmg cmo 0\n* the unity-gain differential buffer: each input at V_ICM plus or minus half\n* the output difference - the loop closed for the difference only\nVicm icm 0 dc 480m\nEfp inp icm outn outp 0.5\nEfn inn icm outp outn 0.5\n.op\n.end" }, { "id": "open_loop", "label": "Open-loop gain", "note": "Differential gain and phase with the loop closed only at DC, through 1 TH inductors, so the operating point is the buffer's and every frequency sees the open loop.", "measures": [], "metricKeys": [ "dc_gain_db", "ugf_hz", "pm_deg", "gm_db" ], "acceptance": [ "dc_gain_db", "ugf_hz", "pm_deg" ], "acceptanceRules": [ { "key": "dc_gain_db", "unit": "dB", "min": 50, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "ugf_hz", "unit": "Hz", "min": 12000000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "pm_deg", "unit": "deg", "min": 65, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Fully differential telescopic-cascode OTA - open-loop differential gain and phase\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVocm vocm 0 dc 450m\nIb ib 0 10u\n.subckt fdtele inp inn outp outn vdd vss vocm ib cmo cmg\n* bias: the reference drawn out of a PMOS diode; the cascode gates from two copies\nXMB ib ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXMB1 vcp ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXRP1 vcp rp vss rppd w=0.5u l=27.294u\nXRP2 rp vss vss rppd w=0.5u l=27.294u\nXMB2 vcn ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXRN1 vcn rn vss rppd w=0.5u l=23.355u\nXRN2 rn vgn vss rppd w=0.5u l=23.355u\nXMB3 vgn vgn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\n* the telescopic branch, one per side: tail, pair, PMOS cascode, NMOS cascode, sink\nXMT tail ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=4\nXM1 d1 inp tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1\nXM2 d2 inn tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1\nXM3 outn vcp d1 d1 sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM4 outp vcp d2 d2 sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM5 outn vcn k1 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM6 outp vcn k2 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM7 k1 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM8 k2 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\n* the differential-difference common-mode amplifier: four PMOS on one tail\nXMTC td ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=2\nXM9 sn outp td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM10 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM11 sn outn td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM12 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM13 sn sn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\nXM14 cmo cmo vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\n.ends\nXdut inp inn outp outn vdd 0 vocm ib cmo cmg fdtele\nClp outp 0 2p\nCln outn 0 2p\n* the common-mode loop, joined at its break point\nVbrk_cm cmg cmo 0\n* the unity-gain differential buffer: each input at V_ICM plus or minus half\n* the output difference - the loop closed for the difference only\nVicm icm 0 dc 480m\nEfp fbp icm outn outp 0.5\nEfn fbn icm outp outn 0.5\n* the loop closed at DC and open at every frequency the sweep visits\nLfp inp fbp 1t\nLfn inn fbn 1t\n* the differential input, through 1 TF capacitors\nCdp inp dp 1t\nCdn inn dn 1t\nVdp dp 0 dc 0 ac 0.5\nVdn dn 0 dc 0 ac 0.5 180\n.ac dec 25 0.1 10g\n.end" }, { "id": "cm_loop", "label": "Common-mode loop gain", "note": "Each common-mode loop opened at the break point the circuit brings out, by Middlebrook's double injection - a voltage in series, then a current into the controlled side - with the differential loop closed as in the buffer: the loop's gain, its crossover, and its phase margin.", "measures": [], "metricKeys": [ "cm_gain_db", "cm_ugf_hz", "cm_pm_deg" ], "acceptance": [ "cm_pm_deg" ], "acceptanceRules": [ { "key": "cm_pm_deg", "unit": "deg", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Fully differential telescopic-cascode OTA - Common-mode loop gain, voltage injection\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVocm vocm 0 dc 450m\nIb ib 0 10u\n.subckt fdtele inp inn outp outn vdd vss vocm ib cmo cmg\n* bias: the reference drawn out of a PMOS diode; the cascode gates from two copies\nXMB ib ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXMB1 vcp ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXRP1 vcp rp vss rppd w=0.5u l=27.294u\nXRP2 rp vss vss rppd w=0.5u l=27.294u\nXMB2 vcn ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXRN1 vcn rn vss rppd w=0.5u l=23.355u\nXRN2 rn vgn vss rppd w=0.5u l=23.355u\nXMB3 vgn vgn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\n* the telescopic branch, one per side: tail, pair, PMOS cascode, NMOS cascode, sink\nXMT tail ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=4\nXM1 d1 inp tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1\nXM2 d2 inn tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1\nXM3 outn vcp d1 d1 sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM4 outp vcp d2 d2 sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM5 outn vcn k1 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM6 outp vcn k2 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM7 k1 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM8 k2 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\n* the differential-difference common-mode amplifier: four PMOS on one tail\nXMTC td ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=2\nXM9 sn outp td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM10 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM11 sn outn td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM12 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM13 sn sn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\nXM14 cmo cmo vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\n.ends\nXdut inp inn outp outn vdd 0 vocm ib cmo cmg fdtele\nClp outp 0 2p\nCln outn 0 2p\n* the common-mode loop, joined at its break point\n* the unity-gain differential buffer: each input at V_ICM plus or minus half\n* the output difference - the loop closed for the difference only\nVicm icm 0 dc 480m\nEfp inp icm outn outp 0.5\nEfn inn icm outp outn 0.5\n* voltage injection at the break point; the other run of the pair injects the other\nVbrk_cm cmg cmo dc 0 ac 1\nIbrk_cm 0 cmg dc 0 ac 0\n.ac dec 25 1 10g\n.end" }, { "id": "cm_step", "label": "Common-mode step", "note": "A 50mV step on the output common-mode reference, vocm, with the amplifier a unity-gain differential buffer: the output common mode follows it, and rings if its loop is short of margin.", "measures": [], "metricKeys": [ "cm_settle", "cm_overshoot_pct", "cm_step_err" ], "acceptance": [ "cm_settle" ], "acceptanceRules": [ { "key": "cm_settle", "unit": "s", "min": null, "max": 1e-7, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Fully differential telescopic-cascode OTA - common-mode step\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVocm vocm 0 dc 450m pulse(450m 500m 100n 1n 1n 500n 2u)\nIb ib 0 10u\n.subckt fdtele inp inn outp outn vdd vss vocm ib cmo cmg\n* bias: the reference drawn out of a PMOS diode; the cascode gates from two copies\nXMB ib ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXMB1 vcp ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXRP1 vcp rp vss rppd w=0.5u l=27.294u\nXRP2 rp vss vss rppd w=0.5u l=27.294u\nXMB2 vcn ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXRN1 vcn rn vss rppd w=0.5u l=23.355u\nXRN2 rn vgn vss rppd w=0.5u l=23.355u\nXMB3 vgn vgn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\n* the telescopic branch, one per side: tail, pair, PMOS cascode, NMOS cascode, sink\nXMT tail ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=4\nXM1 d1 inp tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1\nXM2 d2 inn tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1\nXM3 outn vcp d1 d1 sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM4 outp vcp d2 d2 sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM5 outn vcn k1 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM6 outp vcn k2 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM7 k1 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM8 k2 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\n* the differential-difference common-mode amplifier: four PMOS on one tail\nXMTC td ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=2\nXM9 sn outp td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM10 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM11 sn outn td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM12 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM13 sn sn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\nXM14 cmo cmo vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\n.ends\nXdut inp inn outp outn vdd 0 vocm ib cmo cmg fdtele\nClp outp 0 2p\nCln outn 0 2p\n* the common-mode loop, joined at its break point\nVbrk_cm cmg cmo 0\n* the unity-gain differential buffer: each input at V_ICM plus or minus half\n* the output difference - the loop closed for the difference only\nVicm icm 0 dc 480m\nEfp inp icm outn outp 0.5\nEfn inn icm outp outn 0.5\n.tran 250p 1u\n.end" }, { "id": "step", "label": "Step response", "note": "A 100mV differential step into the unity-gain differential buffer: how fast the differential output follows, whether it rings, and how far the output common mode is pushed on the way.", "measures": [], "metricKeys": [ "sr", "t_settle", "overshoot_pct", "cm_dev" ], "acceptance": [ "sr", "t_settle" ], "acceptanceRules": [ { "key": "sr", "unit": "V/s", "min": 4000000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "t_settle", "unit": "s", "min": null, "max": 6e-8, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Fully differential telescopic-cascode OTA - differential step response of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVocm vocm 0 dc 450m\nIb ib 0 10u\n.subckt fdtele inp inn outp outn vdd vss vocm ib cmo cmg\n* bias: the reference drawn out of a PMOS diode; the cascode gates from two copies\nXMB ib ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXMB1 vcp ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXRP1 vcp rp vss rppd w=0.5u l=27.294u\nXRP2 rp vss vss rppd w=0.5u l=27.294u\nXMB2 vcn ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXRN1 vcn rn vss rppd w=0.5u l=23.355u\nXRN2 rn vgn vss rppd w=0.5u l=23.355u\nXMB3 vgn vgn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\n* the telescopic branch, one per side: tail, pair, PMOS cascode, NMOS cascode, sink\nXMT tail ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=4\nXM1 d1 inp tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1\nXM2 d2 inn tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1\nXM3 outn vcp d1 d1 sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM4 outp vcp d2 d2 sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM5 outn vcn k1 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM6 outp vcn k2 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM7 k1 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM8 k2 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\n* the differential-difference common-mode amplifier: four PMOS on one tail\nXMTC td ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=2\nXM9 sn outp td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM10 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM11 sn outn td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM12 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM13 sn sn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\nXM14 cmo cmo vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\n.ends\nXdut inp inn outp outn vdd 0 vocm ib cmo cmg fdtele\nClp outp 0 2p\nCln outn 0 2p\n* the common-mode loop, joined at its break point\nVbrk_cm cmg cmo 0\n* the unity-gain differential buffer: each input at V_ICM plus or minus half\n* the output difference - the loop closed for the difference only\nVicm icm 0 dc 480m\nEfp fsp icm outn outp 0.5\nEfn fsn icm outp outn 0.5\nVsp inp fsp dc -25m pulse(-25m 25m 100n 1n 1n 500n 2u)\nVsn inn fsn dc 25m pulse(25m -25m 100n 1n 1n 500n 2u)\n.tran 250p 1u\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on V_DD, and how much of it reaches the unity-gain buffer's differential output and its output common mode.", "measures": [], "metricKeys": [ "psrr_db", "psrr_cm_db" ], "acceptance": [ "psrr_db", "psrr_cm_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 80, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "psrr_cm_db", "unit": "dB", "min": 25, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Fully differential telescopic-cascode OTA - supply rejection of the unity-gain differential buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD} ac 1\nVocm vocm 0 dc 450m\nIb ib 0 10u\n.subckt fdtele inp inn outp outn vdd vss vocm ib cmo cmg\n* bias: the reference drawn out of a PMOS diode; the cascode gates from two copies\nXMB ib ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXMB1 vcp ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXRP1 vcp rp vss rppd w=0.5u l=27.294u\nXRP2 rp vss vss rppd w=0.5u l=27.294u\nXMB2 vcn ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXRN1 vcn rn vss rppd w=0.5u l=23.355u\nXRN2 rn vgn vss rppd w=0.5u l=23.355u\nXMB3 vgn vgn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\n* the telescopic branch, one per side: tail, pair, PMOS cascode, NMOS cascode, sink\nXMT tail ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=4\nXM1 d1 inp tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1\nXM2 d2 inn tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1\nXM3 outn vcp d1 d1 sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM4 outp vcp d2 d2 sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM5 outn vcn k1 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM6 outp vcn k2 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM7 k1 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM8 k2 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\n* the differential-difference common-mode amplifier: four PMOS on one tail\nXMTC td ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=2\nXM9 sn outp td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM10 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM11 sn outn td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM12 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM13 sn sn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\nXM14 cmo cmo vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\n.ends\nXdut inp inn outp outn vdd 0 vocm ib cmo cmg fdtele\nClp outp 0 2p\nCln outn 0 2p\n* the common-mode loop, joined at its break point\nVbrk_cm cmg cmo 0\n* the unity-gain differential buffer: each input at V_ICM plus or minus half\n* the output difference - the loop closed for the difference only\nVicm icm 0 dc 480m\nEfp inp icm outn outp 0.5\nEfn inn icm outp outn 0.5\n.ac dec 25 1 100meg\n.end" }, { "id": "cmrr", "label": "Common-mode rejection", "note": "The same signal on both inputs, on the unity-gain buffer's input common mode: what reaches the differential output is the common-mode to differential gain over the differential one, and what reaches the output common mode is how firmly the common-mode loop holds it.", "measures": [], "metricKeys": [ "cmrr_db", "cm_rej_db" ], "acceptance": [ "cmrr_db" ], "acceptanceRules": [ { "key": "cmrr_db", "unit": "dB", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Fully differential telescopic-cascode OTA - common-mode rejection\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVocm vocm 0 dc 450m\nIb ib 0 10u\n.subckt fdtele inp inn outp outn vdd vss vocm ib cmo cmg\n* bias: the reference drawn out of a PMOS diode; the cascode gates from two copies\nXMB ib ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXMB1 vcp ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXRP1 vcp rp vss rppd w=0.5u l=27.294u\nXRP2 rp vss vss rppd w=0.5u l=27.294u\nXMB2 vcn ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXRN1 vcn rn vss rppd w=0.5u l=23.355u\nXRN2 rn vgn vss rppd w=0.5u l=23.355u\nXMB3 vgn vgn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\n* the telescopic branch, one per side: tail, pair, PMOS cascode, NMOS cascode, sink\nXMT tail ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=4\nXM1 d1 inp tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1\nXM2 d2 inn tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1\nXM3 outn vcp d1 d1 sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM4 outp vcp d2 d2 sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM5 outn vcn k1 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM6 outp vcn k2 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM7 k1 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM8 k2 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\n* the differential-difference common-mode amplifier: four PMOS on one tail\nXMTC td ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=2\nXM9 sn outp td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM10 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM11 sn outn td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM12 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM13 sn sn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\nXM14 cmo cmo vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\n.ends\nXdut inp inn outp outn vdd 0 vocm ib cmo cmg fdtele\nClp outp 0 2p\nCln outn 0 2p\n* the common-mode loop, joined at its break point\nVbrk_cm cmg cmo 0\n* the unity-gain differential buffer: each input at V_ICM plus or minus half\n* the output difference - the loop closed for the difference only\nVicm icm 0 dc 480m ac 1\nEfp inp icm outn outp 0.5\nEfn inn icm outp outn 0.5\n.ac dec 25 1 100meg\n.end" }, { "id": "noise", "label": "Noise", "note": "Differential noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.", "measures": [], "metricKeys": [ "vn_1k", "vn_int" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Fully differential telescopic-cascode OTA - differential input-referred noise\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVocm vocm 0 dc 450m\nIb ib 0 10u\n.subckt fdtele inp inn outp outn vdd vss vocm ib cmo cmg\n* bias: the reference drawn out of a PMOS diode; the cascode gates from two copies\nXMB ib ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXMB1 vcp ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXRP1 vcp rp vss rppd w=0.5u l=27.294u\nXRP2 rp vss vss rppd w=0.5u l=27.294u\nXMB2 vcn ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1\nXRN1 vcn rn vss rppd w=0.5u l=23.355u\nXRN2 rn vgn vss rppd w=0.5u l=23.355u\nXMB3 vgn vgn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\n* the telescopic branch, one per side: tail, pair, PMOS cascode, NMOS cascode, sink\nXMT tail ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=4\nXM1 d1 inp tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1\nXM2 d2 inn tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1\nXM3 outn vcp d1 d1 sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM4 outp vcp d2 d2 sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM5 outn vcn k1 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM6 outp vcn k2 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM7 k1 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\nXM8 k2 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2\n* the differential-difference common-mode amplifier: four PMOS on one tail\nXMTC td ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=2\nXM9 sn outp td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM10 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM11 sn outn td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM12 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM13 sn sn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\nXM14 cmo cmo vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1\n.ends\nXdut inp inn outp outn vdd 0 vocm ib cmo cmg fdtele\nClp outp 0 2p\nCln outn 0 2p\n* the common-mode loop, joined at its break point\nVbrk_cm cmg cmo 0\n* the unity-gain differential buffer: each input at V_ICM plus or minus half\n* the output difference - the loop closed for the difference only\nVicm icm 0 dc 480m\nEfp inp icm outn outp 0.5\nEfn fsn icm outp outn 0.5\nVsn inn fsn dc 0 ac 1\n.control\nnoise v(outp,outn) Vsn dec 20 1 1meg\nsetplot noise1\n* 20 points a decade from 1 Hz: point 60 is 1 kHz\nlet vn_1k = inoise_spectrum[60]\nprint vn_1k\nsetplot noise2\nprint inoise_total\n.endc\n.op\n.end" } ], "measurements": { "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.0001 } }, "voc_err": { "label": "Output common mode less its reference", "unit": "V", "spec": { "min": -0.01, "max": 0.01 } }, "dc_gain_db": { "label": "DC differential gain", "unit": "dB", "spec": { "min": 50, "max": null } }, "ugf_hz": { "label": "Unity-gain frequency", "unit": "Hz", "spec": { "min": 12000000, "max": null } }, "pm_deg": { "label": "Phase margin", "unit": "deg", "spec": { "min": 65, "max": null } }, "cm_pm_deg": { "label": "Common-mode loop: phase margin", "unit": "deg", "spec": { "min": 60, "max": null } }, "cm_settle": { "label": "Common-mode settling, 1 %", "unit": "s", "spec": { "min": null, "max": 1e-7 } }, "sr": { "label": "Slew rate", "unit": "V/s", "spec": { "min": 4000000, "max": null } }, "t_settle": { "label": "Settling time, 1 %", "unit": "s", "spec": { "min": null, "max": 6e-8 } }, "psrr_db": { "label": "Supply rejection at 1 kHz, differential", "unit": "dB", "spec": { "min": 80, "max": null } }, "psrr_cm_db": { "label": "Supply rejection at 1 kHz, common mode", "unit": "dB", "spec": { "min": 25, "max": null } }, "cmrr_db": { "label": "Common-mode rejection at 1 kHz", "unit": "dB", "spec": { "min": 60, "max": null } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "611e2b4c67ed0c80e5805186d73c9d4b81eada49e50cf69e42b5741a4d727413" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/fd-telescopic.js", "sha256": "3d4a80022c6a042d30c8b08d2dac683250b200064562cde920a95a02c2e6032e" }, "simulationFingerprints": { "op": "f376f4139022755d4bb337a87fd14d5c6596a85a1968777249774c342d8fb4f2", "open_loop": "ea4e8de209c515f1992002ee348dfef97c57c6ca7ad18192022f3edfadd25127", "cm_loop": "012c21c1baa3f2f3c2b73b347a9454613af11e9fa6a79670cb37a6e3736ebaff", "cm_step": "c30995508fdb951d2fe94088b029cd08106ed96fbcb32e51a19723364b403640", "step": "82318568f9ea92b8134a9580564c773a390660b57826f69950e578a000442129", "psrr": "45a49b2a4219bd29721061eca52b520c5bc5eed1a5df3d44ea32593ed82722b1", "cmrr": "22b4209f2aaf8e2f63b1ecbf2f42f115d8cda04687c48cad179ef3f2fc03e2d5", "noise": "d46be0de4ad21a7fc20e03207d859800a82e6375799903bba88052131b4d4196" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "9672661a2fcb0822b72126e2e3739aab7857f8ee25fded6d780ecfba21c24f7e", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "fd-telescopic", "parameters": { "Ib": 0.00001, "W1": 0.00004, "L1": 0.000001, "W3": 0.00008, "L3": 0.000001, "Wn": 0.000012, "Ln": 0.0000015, "Wp": 0.000064, "Lp": 0.000001, "Wc": 0.00002, "Lc": 0.000001, "Rp": 14000, "Rn": 12000, "CL": 2e-12, "VICM": 0.48, "VOCM": 0.45 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/fd-telescopic/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "fdtele", "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "outp", "net": "outp", "kind": "output" }, { "name": "outn", "net": "outn", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "vocm", "net": "vocm", "kind": "bias" }, { "name": "ib", "net": "ib", "kind": "bias" }, { "name": "cmo", "net": "cmo", "kind": "bias" }, { "name": "cmg", "net": "cmg", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB1 vcp ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRP1", "displayName": "RP1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=27.294u", "source": "XRP1 vcp rp vss rppd w=0.5u l=27.294u", "pins": [ { "id": "p", "net": "vcp" }, { "id": "n", "net": "rp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRP2", "displayName": "RP2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=27.294u", "source": "XRP2 rp vss vss rppd w=0.5u l=27.294u", "pins": [ { "id": "p", "net": "rp" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB2 vcn ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRN1", "displayName": "RN1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRN1 vcn rn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "vcn" }, { "id": "n", "net": "rn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRN2", "displayName": "RN2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRN2 rn vgn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "rn" }, { "id": "n", "net": "vgn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XMB3 vgn vgn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=4", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=1u ng=8 m=1", "source": "XM1 d1 inp tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=1u ng=8 m=1", "source": "XM2 d2 inn tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM3 outn vcp d1 d1 sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "d1" }, { "id": "b", "net": "d1" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM4 outp vcp d2 d2 sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "d2" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM5 outn vcn k1 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM6 outp vcn k2 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM7 k1 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "cmg" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM8 k2 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "cmg" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTC", "displayName": "MTC", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=2", "source": "XMTC td ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=2", "pins": [ { "id": "d", "net": "td" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM9 sn outp td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "outp" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM10 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM11 sn outn td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "outn" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM12 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XM13 sn sn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "sn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XM14 cmo cmo vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "cmo" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB2", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMTC", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMTC", "pin": "s" }, { "device": "XMTC", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XRP1", "pin": "p" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rp", "ground": false, "terminals": [ { "device": "XRP1", "pin": "n" }, { "device": "XRP2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRP1", "pin": "substrate" }, { "device": "XRP2", "pin": "n" }, { "device": "XRP2", "pin": "substrate" }, { "device": "XRN1", "pin": "substrate" }, { "device": "XRN2", "pin": "substrate" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XRN1", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rn", "ground": false, "terminals": [ { "device": "XRN1", "pin": "n" }, { "device": "XRN2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vgn", "ground": false, "terminals": [ { "device": "XRN2", "pin": "n" }, { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM11", "pin": "g" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XM9", "pin": "g" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM5", "pin": "s" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM6", "pin": "s" }, { "device": "XM8", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [ "cmg" ], "voltageReferences": [] }, { "id": "td", "ground": false, "terminals": [ { "device": "XMTC", "pin": "d" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "sn", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XM13", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo", "ground": false, "terminals": [ { "device": "XM10", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XM14", "pin": "g" } ], "ports": [ "cmo" ], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XM10", "pin": "g" }, { "device": "XM12", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 450m", "source": "Vocm vocm 0 dc 450m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "fdtele", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 vocm ib cmo cmg fdtele", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "vocm", "net": "vocm" }, { "id": "ib", "net": "ib" }, { "id": "cmo", "net": "cmo" }, { "id": "cmg", "net": "cmg" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/fdtele" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm", "displayName": "Vbrk_cm", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm cmg cmo 0", "pins": [ { "id": "p", "net": "cmg" }, { "id": "n", "net": "cmo" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 480m", "source": "Vicm icm 0 dc 480m", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efp", "displayName": "Efp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efp inp icm outn outp 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outn" }, { "id": "cn", "net": "outp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efn", "displayName": "Efn", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efn inn icm outp outn 0.5", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" }, { "device": "Xdut", "pin": "vocm" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Efp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Efn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Efp", "pin": "cn" }, { "device": "Efn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Efp", "pin": "cp" }, { "device": "Efn", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo" }, { "device": "Vbrk_cm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg" }, { "device": "Vbrk_cm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Efp", "pin": "n" }, { "device": "Efn", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/fdtele", "name": "fdtele", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "vocm", "net": "vocm" }, { "name": "ib", "net": "ib" }, { "name": "cmo", "net": "cmo" }, { "name": "cmg", "net": "cmg" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB1 vcp ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRP1", "displayName": "RP1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=27.294u", "source": "XRP1 vcp rp vss rppd w=0.5u l=27.294u", "pins": [ { "id": "p", "net": "vcp" }, { "id": "n", "net": "rp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRP2", "displayName": "RP2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=27.294u", "source": "XRP2 rp vss vss rppd w=0.5u l=27.294u", "pins": [ { "id": "p", "net": "rp" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB2 vcn ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRN1", "displayName": "RN1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRN1 vcn rn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "vcn" }, { "id": "n", "net": "rn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRN2", "displayName": "RN2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRN2 rn vgn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "rn" }, { "id": "n", "net": "vgn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XMB3 vgn vgn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=4", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=1u ng=8 m=1", "source": "XM1 d1 inp tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=1u ng=8 m=1", "source": "XM2 d2 inn tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM3 outn vcp d1 d1 sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "d1" }, { "id": "b", "net": "d1" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM4 outp vcp d2 d2 sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "d2" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM5 outn vcn k1 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM6 outp vcn k2 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM7 k1 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "cmg" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM8 k2 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "cmg" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTC", "displayName": "MTC", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=2", "source": "XMTC td ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=2", "pins": [ { "id": "d", "net": "td" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM9 sn outp td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "outp" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM10 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM11 sn outn td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "outn" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM12 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XM13 sn sn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "sn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XM14 cmo cmo vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "cmo" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB2", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMTC", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMTC", "pin": "s" }, { "device": "XMTC", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XRP1", "pin": "p" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rp", "ground": false, "terminals": [ { "device": "XRP1", "pin": "n" }, { "device": "XRP2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRP1", "pin": "substrate" }, { "device": "XRP2", "pin": "n" }, { "device": "XRP2", "pin": "substrate" }, { "device": "XRN1", "pin": "substrate" }, { "device": "XRN2", "pin": "substrate" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XRN1", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rn", "ground": false, "terminals": [ { "device": "XRN1", "pin": "n" }, { "device": "XRN2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vgn", "ground": false, "terminals": [ { "device": "XRN2", "pin": "n" }, { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM11", "pin": "g" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XM9", "pin": "g" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM5", "pin": "s" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM6", "pin": "s" }, { "device": "XM8", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [ "cmg" ], "voltageReferences": [] }, { "id": "td", "ground": false, "terminals": [ { "device": "XMTC", "pin": "d" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "sn", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XM13", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo", "ground": false, "terminals": [ { "device": "XM10", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XM14", "pin": "g" } ], "ports": [ "cmo" ], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XM10", "pin": "g" }, { "device": "XM12", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/fdtele" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Bias reference", "devices": [ { "scope": "dut", "device": "XMB" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "One unit pushing Ib through RP1", "devices": [ { "scope": "dut", "device": "XMB1" } ], "inferredStages": [ "bias" ] }, { "id": "block-3", "label": "Half of vcp's resistor to ground", "devices": [ { "scope": "dut", "device": "XRP1" }, { "scope": "dut", "device": "XRP2" } ], "inferredStages": [ "bias" ] }, { "id": "block-4", "label": "One unit pushing Ib through RN1", "devices": [ { "scope": "dut", "device": "XMB2" } ], "inferredStages": [ "bias" ] }, { "id": "block-5", "label": "Half the drop from vcn to vgn", "devices": [ { "scope": "dut", "device": "XRN1" }, { "scope": "dut", "device": "XRN2" } ], "inferredStages": [ "bias" ] }, { "id": "block-6", "label": "NMOS cascode reference", "devices": [ { "scope": "dut", "device": "XMB3" } ], "inferredStages": [ "bias" ] }, { "id": "block-7", "label": "Input tail", "devices": [ { "scope": "dut", "device": "XMT" } ], "inferredStages": [ 1 ] }, { "id": "block-8", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 1 ] }, { "id": "block-9", "label": "PMOS cascode", "devices": [ { "scope": "dut", "device": "XM3" }, { "scope": "dut", "device": "XM4" } ], "inferredStages": [ 2 ] }, { "id": "block-10", "label": "NMOS cascode", "devices": [ { "scope": "dut", "device": "XM5" }, { "scope": "dut", "device": "XM6" } ], "inferredStages": [ 2 ] }, { "id": "block-11", "label": "Sink", "devices": [ { "scope": "dut", "device": "XM7" }, { "scope": "dut", "device": "XM8" } ], "inferredStages": [ "bias" ] }, { "id": "block-12", "label": "Common-mode amplifier tail", "devices": [ { "scope": "dut", "device": "XMTC" } ], "inferredStages": [ 3 ] }, { "id": "block-13", "label": "Common-mode sensing", "devices": [ { "scope": "dut", "device": "XM9" }, { "scope": "dut", "device": "XM11" } ], "inferredStages": [ 3 ] }, { "id": "block-14", "label": "Common-mode reference", "devices": [ { "scope": "dut", "device": "XM10" }, { "scope": "dut", "device": "XM12" } ], "inferredStages": [ 4 ] }, { "id": "block-15", "label": "The sensing side's diode", "devices": [ { "scope": "dut", "device": "XM13" } ], "inferredStages": [ 3 ] }, { "id": "block-16", "label": "The reference side's diode: the unit M7", "devices": [ { "scope": "dut", "device": "XM14" } ], "inferredStages": [ 4 ] } ], "edges": [ { "id": "net-1", "net": "ib", "nodes": [ "block-1", "block-2", "block-4", "block-7", "block-12" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "vcp", "nodes": [ "block-2", "block-3", "block-9" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "vcn", "nodes": [ "block-4", "block-5", "block-10" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "vgn", "nodes": [ "block-5", "block-6" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "tail", "nodes": [ "block-7", "block-8" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "d1", "nodes": [ "block-8", "block-9" ], "direction": "undirected-shared-net" }, { "id": "net-7", "net": "d2", "nodes": [ "block-8", "block-9" ], "direction": "undirected-shared-net" }, { "id": "net-8", "net": "outn", "nodes": [ "block-9", "block-10", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-9", "net": "outp", "nodes": [ "block-9", "block-10", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-10", "net": "k1", "nodes": [ "block-10", "block-11" ], "direction": "undirected-shared-net" }, { "id": "net-11", "net": "k2", "nodes": [ "block-10", "block-11" ], "direction": "undirected-shared-net" }, { "id": "net-12", "net": "td", "nodes": [ "block-12", "block-13", "block-14" ], "direction": "undirected-shared-net" }, { "id": "net-13", "net": "sn", "nodes": [ "block-13", "block-15" ], "direction": "undirected-shared-net" }, { "id": "net-14", "net": "cmo", "nodes": [ "block-14", "block-16" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "outp", "net": "outp", "kind": "output" }, { "name": "outn", "net": "outn", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "vocm", "net": "vocm", "kind": "bias" }, { "name": "ib", "net": "ib", "kind": "bias" }, { "name": "cmo", "net": "cmo", "kind": "bias" }, { "name": "cmg", "net": "cmg", "kind": "bias" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 450m", "source": "Vocm vocm 0 dc 450m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "fdtele", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 vocm ib cmo cmg fdtele", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "vocm", "net": "vocm" }, { "id": "ib", "net": "ib" }, { "id": "cmo", "net": "cmo" }, { "id": "cmg", "net": "cmg" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/fdtele" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm", "displayName": "Vbrk_cm", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm cmg cmo 0", "pins": [ { "id": "p", "net": "cmg" }, { "id": "n", "net": "cmo" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 480m", "source": "Vicm icm 0 dc 480m", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efp", "displayName": "Efp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efp fbp icm outn outp 0.5", "pins": [ { "id": "p", "net": "fbp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outn" }, { "id": "cn", "net": "outp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efn", "displayName": "Efn", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efn fbn icm outp outn 0.5", "pins": [ { "id": "p", "net": "fbn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfp", "displayName": "Lfp", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfp inp fbp 1t", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "fbp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfn", "displayName": "Lfn", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfn inn fbn 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "fbn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cdp", "displayName": "Cdp", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cdp inp dp 1t", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "dp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cdn", "displayName": "Cdn", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cdn inn dn 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "dn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vdp", "displayName": "Vdp", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 0.5", "source": "Vdp dp 0 dc 0 ac 0.5", "pins": [ { "id": "p", "net": "dp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vdn", "displayName": "Vdn", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 0.5 180", "source": "Vdn dn 0 dc 0 ac 0.5 180", "pins": [ { "id": "p", "net": "dn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" }, { "device": "Vdp", "pin": "n" }, { "device": "Vdn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" }, { "device": "Xdut", "pin": "vocm" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Lfp", "pin": "p" }, { "device": "Cdp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Lfn", "pin": "p" }, { "device": "Cdn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Efp", "pin": "cn" }, { "device": "Efn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Efp", "pin": "cp" }, { "device": "Efn", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo" }, { "device": "Vbrk_cm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg" }, { "device": "Vbrk_cm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Efp", "pin": "n" }, { "device": "Efn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "fbp", "ground": false, "terminals": [ { "device": "Efp", "pin": "p" }, { "device": "Lfp", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "fbn", "ground": false, "terminals": [ { "device": "Efn", "pin": "p" }, { "device": "Lfn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "dp", "ground": false, "terminals": [ { "device": "Cdp", "pin": "n" }, { "device": "Vdp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "dn", "ground": false, "terminals": [ { "device": "Cdn", "pin": "n" }, { "device": "Vdn", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/fdtele", "name": "fdtele", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "vocm", "net": "vocm" }, { "name": "ib", "net": "ib" }, { "name": "cmo", "net": "cmo" }, { "name": "cmg", "net": "cmg" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB1 vcp ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRP1", "displayName": "RP1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=27.294u", "source": "XRP1 vcp rp vss rppd w=0.5u l=27.294u", "pins": [ { "id": "p", "net": "vcp" }, { "id": "n", "net": "rp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRP2", "displayName": "RP2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=27.294u", "source": "XRP2 rp vss vss rppd w=0.5u l=27.294u", "pins": [ { "id": "p", "net": "rp" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB2 vcn ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRN1", "displayName": "RN1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRN1 vcn rn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "vcn" }, { "id": "n", "net": "rn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRN2", "displayName": "RN2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRN2 rn vgn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "rn" }, { "id": "n", "net": "vgn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XMB3 vgn vgn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=4", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=1u ng=8 m=1", "source": "XM1 d1 inp tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=1u ng=8 m=1", "source": "XM2 d2 inn tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM3 outn vcp d1 d1 sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "d1" }, { "id": "b", "net": "d1" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM4 outp vcp d2 d2 sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "d2" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM5 outn vcn k1 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM6 outp vcn k2 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM7 k1 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "cmg" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM8 k2 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "cmg" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTC", "displayName": "MTC", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=2", "source": "XMTC td ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=2", "pins": [ { "id": "d", "net": "td" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM9 sn outp td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "outp" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM10 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM11 sn outn td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "outn" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM12 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XM13 sn sn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "sn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XM14 cmo cmo vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "cmo" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB2", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMTC", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMTC", "pin": "s" }, { "device": "XMTC", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XRP1", "pin": "p" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rp", "ground": false, "terminals": [ { "device": "XRP1", "pin": "n" }, { "device": "XRP2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRP1", "pin": "substrate" }, { "device": "XRP2", "pin": "n" }, { "device": "XRP2", "pin": "substrate" }, { "device": "XRN1", "pin": "substrate" }, { "device": "XRN2", "pin": "substrate" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XRN1", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rn", "ground": false, "terminals": [ { "device": "XRN1", "pin": "n" }, { "device": "XRN2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vgn", "ground": false, "terminals": [ { "device": "XRN2", "pin": "n" }, { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM11", "pin": "g" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XM9", "pin": "g" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM5", "pin": "s" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM6", "pin": "s" }, { "device": "XM8", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [ "cmg" ], "voltageReferences": [] }, { "id": "td", "ground": false, "terminals": [ { "device": "XMTC", "pin": "d" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "sn", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XM13", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo", "ground": false, "terminals": [ { "device": "XM10", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XM14", "pin": "g" } ], "ports": [ "cmo" ], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XM10", "pin": "g" }, { "device": "XM12", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/fdtele" } }, { "id": "graph-5", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 450m", "source": "Vocm vocm 0 dc 450m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "fdtele", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 vocm ib cmo cmg fdtele", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "vocm", "net": "vocm" }, { "id": "ib", "net": "ib" }, { "id": "cmo", "net": "cmo" }, { "id": "cmg", "net": "cmg" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/fdtele" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 480m", "source": "Vicm icm 0 dc 480m", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efp", "displayName": "Efp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efp inp icm outn outp 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outn" }, { "id": "cn", "net": "outp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efn", "displayName": "Efn", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efn inn icm outp outn 0.5", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm", "displayName": "Vbrk_cm", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Vbrk_cm cmg cmo dc 0 ac 1", "pins": [ { "id": "p", "net": "cmg" }, { "id": "n", "net": "cmo" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ibrk_cm", "displayName": "Ibrk_cm", "spiceType": "I", "model": null, "parametersOrValue": "dc 0 ac 0", "source": "Ibrk_cm 0 cmg dc 0 ac 0", "pins": [ { "id": "p", "net": "0" }, { "id": "n", "net": "cmg" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" }, { "device": "Ibrk_cm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" }, { "device": "Xdut", "pin": "vocm" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Efp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Efn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Efp", "pin": "cn" }, { "device": "Efn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Efp", "pin": "cp" }, { "device": "Efn", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo" }, { "device": "Vbrk_cm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg" }, { "device": "Vbrk_cm", "pin": "p" }, { "device": "Ibrk_cm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Efp", "pin": "n" }, { "device": "Efn", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/fdtele", "name": "fdtele", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "vocm", "net": "vocm" }, { "name": "ib", "net": "ib" }, { "name": "cmo", "net": "cmo" }, { "name": "cmg", "net": "cmg" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB1 vcp ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRP1", "displayName": "RP1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=27.294u", "source": "XRP1 vcp rp vss rppd w=0.5u l=27.294u", "pins": [ { "id": "p", "net": "vcp" }, { "id": "n", "net": "rp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRP2", "displayName": "RP2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=27.294u", "source": "XRP2 rp vss vss rppd w=0.5u l=27.294u", "pins": [ { "id": "p", "net": "rp" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB2 vcn ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRN1", "displayName": "RN1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRN1 vcn rn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "vcn" }, { "id": "n", "net": "rn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRN2", "displayName": "RN2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRN2 rn vgn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "rn" }, { "id": "n", "net": "vgn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XMB3 vgn vgn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=4", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=1u ng=8 m=1", "source": "XM1 d1 inp tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=1u ng=8 m=1", "source": "XM2 d2 inn tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM3 outn vcp d1 d1 sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "d1" }, { "id": "b", "net": "d1" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM4 outp vcp d2 d2 sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "d2" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM5 outn vcn k1 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM6 outp vcn k2 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM7 k1 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "cmg" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM8 k2 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "cmg" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTC", "displayName": "MTC", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=2", "source": "XMTC td ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=2", "pins": [ { "id": "d", "net": "td" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM9 sn outp td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "outp" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM10 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM11 sn outn td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "outn" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM12 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XM13 sn sn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "sn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XM14 cmo cmo vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "cmo" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB2", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMTC", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMTC", "pin": "s" }, { "device": "XMTC", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XRP1", "pin": "p" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rp", "ground": false, "terminals": [ { "device": "XRP1", "pin": "n" }, { "device": "XRP2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRP1", "pin": "substrate" }, { "device": "XRP2", "pin": "n" }, { "device": "XRP2", "pin": "substrate" }, { "device": "XRN1", "pin": "substrate" }, { "device": "XRN2", "pin": "substrate" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XRN1", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rn", "ground": false, "terminals": [ { "device": "XRN1", "pin": "n" }, { "device": "XRN2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vgn", "ground": false, "terminals": [ { "device": "XRN2", "pin": "n" }, { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM11", "pin": "g" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XM9", "pin": "g" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM5", "pin": "s" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM6", "pin": "s" }, { "device": "XM8", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [ "cmg" ], "voltageReferences": [] }, { "id": "td", "ground": false, "terminals": [ { "device": "XMTC", "pin": "d" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "sn", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XM13", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo", "ground": false, "terminals": [ { "device": "XM10", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XM14", "pin": "g" } ], "ports": [ "cmo" ], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XM10", "pin": "g" }, { "device": "XM12", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/fdtele" } }, { "id": "graph-6", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 450m pulse(450m 500m 100n 1n 1n 500n 2u)", "source": "Vocm vocm 0 dc 450m pulse(450m 500m 100n 1n 1n 500n 2u)", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "fdtele", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 vocm ib cmo cmg fdtele", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "vocm", "net": "vocm" }, { "id": "ib", "net": "ib" }, { "id": "cmo", "net": "cmo" }, { "id": "cmg", "net": "cmg" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/fdtele" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm", "displayName": "Vbrk_cm", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm cmg cmo 0", "pins": [ { "id": "p", "net": "cmg" }, { "id": "n", "net": "cmo" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 480m", "source": "Vicm icm 0 dc 480m", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efp", "displayName": "Efp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efp inp icm outn outp 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outn" }, { "id": "cn", "net": "outp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efn", "displayName": "Efn", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efn inn icm outp outn 0.5", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" }, { "device": "Xdut", "pin": "vocm" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Efp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Efn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Efp", "pin": "cn" }, { "device": "Efn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Efp", "pin": "cp" }, { "device": "Efn", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo" }, { "device": "Vbrk_cm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg" }, { "device": "Vbrk_cm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Efp", "pin": "n" }, { "device": "Efn", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/fdtele", "name": "fdtele", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "vocm", "net": "vocm" }, { "name": "ib", "net": "ib" }, { "name": "cmo", "net": "cmo" }, { "name": "cmg", "net": "cmg" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB1 vcp ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRP1", "displayName": "RP1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=27.294u", "source": "XRP1 vcp rp vss rppd w=0.5u l=27.294u", "pins": [ { "id": "p", "net": "vcp" }, { "id": "n", "net": "rp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRP2", "displayName": "RP2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=27.294u", "source": "XRP2 rp vss vss rppd w=0.5u l=27.294u", "pins": [ { "id": "p", "net": "rp" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB2 vcn ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRN1", "displayName": "RN1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRN1 vcn rn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "vcn" }, { "id": "n", "net": "rn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRN2", "displayName": "RN2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRN2 rn vgn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "rn" }, { "id": "n", "net": "vgn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XMB3 vgn vgn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=4", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=1u ng=8 m=1", "source": "XM1 d1 inp tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=1u ng=8 m=1", "source": "XM2 d2 inn tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM3 outn vcp d1 d1 sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "d1" }, { "id": "b", "net": "d1" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM4 outp vcp d2 d2 sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "d2" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM5 outn vcn k1 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM6 outp vcn k2 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM7 k1 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "cmg" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM8 k2 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "cmg" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTC", "displayName": "MTC", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=2", "source": "XMTC td ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=2", "pins": [ { "id": "d", "net": "td" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM9 sn outp td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "outp" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM10 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM11 sn outn td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "outn" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM12 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XM13 sn sn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "sn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XM14 cmo cmo vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "cmo" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB2", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMTC", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMTC", "pin": "s" }, { "device": "XMTC", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XRP1", "pin": "p" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rp", "ground": false, "terminals": [ { "device": "XRP1", "pin": "n" }, { "device": "XRP2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRP1", "pin": "substrate" }, { "device": "XRP2", "pin": "n" }, { "device": "XRP2", "pin": "substrate" }, { "device": "XRN1", "pin": "substrate" }, { "device": "XRN2", "pin": "substrate" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XRN1", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rn", "ground": false, "terminals": [ { "device": "XRN1", "pin": "n" }, { "device": "XRN2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vgn", "ground": false, "terminals": [ { "device": "XRN2", "pin": "n" }, { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM11", "pin": "g" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XM9", "pin": "g" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM5", "pin": "s" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM6", "pin": "s" }, { "device": "XM8", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [ "cmg" ], "voltageReferences": [] }, { "id": "td", "ground": false, "terminals": [ { "device": "XMTC", "pin": "d" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "sn", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XM13", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo", "ground": false, "terminals": [ { "device": "XM10", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XM14", "pin": "g" } ], "ports": [ "cmo" ], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XM10", "pin": "g" }, { "device": "XM12", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/fdtele" } }, { "id": "graph-7", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 450m", "source": "Vocm vocm 0 dc 450m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "fdtele", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 vocm ib cmo cmg fdtele", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "vocm", "net": "vocm" }, { "id": "ib", "net": "ib" }, { "id": "cmo", "net": "cmo" }, { "id": "cmg", "net": "cmg" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/fdtele" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm", "displayName": "Vbrk_cm", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm cmg cmo 0", "pins": [ { "id": "p", "net": "cmg" }, { "id": "n", "net": "cmo" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 480m", "source": "Vicm icm 0 dc 480m", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efp", "displayName": "Efp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efp fsp icm outn outp 0.5", "pins": [ { "id": "p", "net": "fsp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outn" }, { "id": "cn", "net": "outp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efn", "displayName": "Efn", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efn fsn icm outp outn 0.5", "pins": [ { "id": "p", "net": "fsn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vsp", "displayName": "Vsp", "spiceType": "V", "model": null, "parametersOrValue": "dc -25m pulse(-25m 25m 100n 1n 1n 500n 2u)", "source": "Vsp inp fsp dc -25m pulse(-25m 25m 100n 1n 1n 500n 2u)", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "fsp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vsn", "displayName": "Vsn", "spiceType": "V", "model": null, "parametersOrValue": "dc 25m pulse(25m -25m 100n 1n 1n 500n 2u)", "source": "Vsn inn fsn dc 25m pulse(25m -25m 100n 1n 1n 500n 2u)", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "fsn" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" }, { "device": "Xdut", "pin": "vocm" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vsp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vsn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Efp", "pin": "cn" }, { "device": "Efn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Efp", "pin": "cp" }, { "device": "Efn", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo" }, { "device": "Vbrk_cm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg" }, { "device": "Vbrk_cm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Efp", "pin": "n" }, { "device": "Efn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "fsp", "ground": false, "terminals": [ { "device": "Efp", "pin": "p" }, { "device": "Vsp", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "fsn", "ground": false, "terminals": [ { "device": "Efn", "pin": "p" }, { "device": "Vsn", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/fdtele", "name": "fdtele", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "vocm", "net": "vocm" }, { "name": "ib", "net": "ib" }, { "name": "cmo", "net": "cmo" }, { "name": "cmg", "net": "cmg" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB1 vcp ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRP1", "displayName": "RP1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=27.294u", "source": "XRP1 vcp rp vss rppd w=0.5u l=27.294u", "pins": [ { "id": "p", "net": "vcp" }, { "id": "n", "net": "rp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRP2", "displayName": "RP2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=27.294u", "source": "XRP2 rp vss vss rppd w=0.5u l=27.294u", "pins": [ { "id": "p", "net": "rp" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB2 vcn ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRN1", "displayName": "RN1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRN1 vcn rn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "vcn" }, { "id": "n", "net": "rn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRN2", "displayName": "RN2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRN2 rn vgn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "rn" }, { "id": "n", "net": "vgn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XMB3 vgn vgn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=4", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=1u ng=8 m=1", "source": "XM1 d1 inp tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=1u ng=8 m=1", "source": "XM2 d2 inn tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM3 outn vcp d1 d1 sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "d1" }, { "id": "b", "net": "d1" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM4 outp vcp d2 d2 sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "d2" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM5 outn vcn k1 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM6 outp vcn k2 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM7 k1 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "cmg" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM8 k2 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "cmg" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTC", "displayName": "MTC", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=2", "source": "XMTC td ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=2", "pins": [ { "id": "d", "net": "td" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM9 sn outp td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "outp" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM10 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM11 sn outn td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "outn" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM12 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XM13 sn sn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "sn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XM14 cmo cmo vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "cmo" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB2", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMTC", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMTC", "pin": "s" }, { "device": "XMTC", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XRP1", "pin": "p" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rp", "ground": false, "terminals": [ { "device": "XRP1", "pin": "n" }, { "device": "XRP2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRP1", "pin": "substrate" }, { "device": "XRP2", "pin": "n" }, { "device": "XRP2", "pin": "substrate" }, { "device": "XRN1", "pin": "substrate" }, { "device": "XRN2", "pin": "substrate" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XRN1", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rn", "ground": false, "terminals": [ { "device": "XRN1", "pin": "n" }, { "device": "XRN2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vgn", "ground": false, "terminals": [ { "device": "XRN2", "pin": "n" }, { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM11", "pin": "g" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XM9", "pin": "g" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM5", "pin": "s" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM6", "pin": "s" }, { "device": "XM8", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [ "cmg" ], "voltageReferences": [] }, { "id": "td", "ground": false, "terminals": [ { "device": "XMTC", "pin": "d" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "sn", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XM13", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo", "ground": false, "terminals": [ { "device": "XM10", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XM14", "pin": "g" } ], "ports": [ "cmo" ], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XM10", "pin": "g" }, { "device": "XM12", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/fdtele" } }, { "id": "graph-8", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD} ac 1", "source": "Vdd vdd 0 dc {VDD} ac 1", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 450m", "source": "Vocm vocm 0 dc 450m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "fdtele", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 vocm ib cmo cmg fdtele", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "vocm", "net": "vocm" }, { "id": "ib", "net": "ib" }, { "id": "cmo", "net": "cmo" }, { "id": "cmg", "net": "cmg" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/fdtele" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm", "displayName": "Vbrk_cm", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm cmg cmo 0", "pins": [ { "id": "p", "net": "cmg" }, { "id": "n", "net": "cmo" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 480m", "source": "Vicm icm 0 dc 480m", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efp", "displayName": "Efp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efp inp icm outn outp 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outn" }, { "id": "cn", "net": "outp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efn", "displayName": "Efn", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efn inn icm outp outn 0.5", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" }, { "device": "Xdut", "pin": "vocm" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Efp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Efn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Efp", "pin": "cn" }, { "device": "Efn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Efp", "pin": "cp" }, { "device": "Efn", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo" }, { "device": "Vbrk_cm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg" }, { "device": "Vbrk_cm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Efp", "pin": "n" }, { "device": "Efn", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/fdtele", "name": "fdtele", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "vocm", "net": "vocm" }, { "name": "ib", "net": "ib" }, { "name": "cmo", "net": "cmo" }, { "name": "cmg", "net": "cmg" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB1 vcp ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRP1", "displayName": "RP1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=27.294u", "source": "XRP1 vcp rp vss rppd w=0.5u l=27.294u", "pins": [ { "id": "p", "net": "vcp" }, { "id": "n", "net": "rp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRP2", "displayName": "RP2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=27.294u", "source": "XRP2 rp vss vss rppd w=0.5u l=27.294u", "pins": [ { "id": "p", "net": "rp" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB2 vcn ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRN1", "displayName": "RN1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRN1 vcn rn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "vcn" }, { "id": "n", "net": "rn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRN2", "displayName": "RN2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRN2 rn vgn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "rn" }, { "id": "n", "net": "vgn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XMB3 vgn vgn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=4", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=1u ng=8 m=1", "source": "XM1 d1 inp tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=1u ng=8 m=1", "source": "XM2 d2 inn tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM3 outn vcp d1 d1 sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "d1" }, { "id": "b", "net": "d1" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM4 outp vcp d2 d2 sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "d2" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM5 outn vcn k1 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM6 outp vcn k2 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM7 k1 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "cmg" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM8 k2 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "cmg" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTC", "displayName": "MTC", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=2", "source": "XMTC td ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=2", "pins": [ { "id": "d", "net": "td" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM9 sn outp td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "outp" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM10 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM11 sn outn td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "outn" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM12 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XM13 sn sn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "sn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XM14 cmo cmo vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "cmo" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB2", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMTC", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMTC", "pin": "s" }, { "device": "XMTC", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XRP1", "pin": "p" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rp", "ground": false, "terminals": [ { "device": "XRP1", "pin": "n" }, { "device": "XRP2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRP1", "pin": "substrate" }, { "device": "XRP2", "pin": "n" }, { "device": "XRP2", "pin": "substrate" }, { "device": "XRN1", "pin": "substrate" }, { "device": "XRN2", "pin": "substrate" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XRN1", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rn", "ground": false, "terminals": [ { "device": "XRN1", "pin": "n" }, { "device": "XRN2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vgn", "ground": false, "terminals": [ { "device": "XRN2", "pin": "n" }, { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM11", "pin": "g" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XM9", "pin": "g" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM5", "pin": "s" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM6", "pin": "s" }, { "device": "XM8", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [ "cmg" ], "voltageReferences": [] }, { "id": "td", "ground": false, "terminals": [ { "device": "XMTC", "pin": "d" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "sn", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XM13", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo", "ground": false, "terminals": [ { "device": "XM10", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XM14", "pin": "g" } ], "ports": [ "cmo" ], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XM10", "pin": "g" }, { "device": "XM12", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/fdtele" } }, { "id": "graph-9", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 450m", "source": "Vocm vocm 0 dc 450m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "fdtele", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 vocm ib cmo cmg fdtele", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "vocm", "net": "vocm" }, { "id": "ib", "net": "ib" }, { "id": "cmo", "net": "cmo" }, { "id": "cmg", "net": "cmg" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/fdtele" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm", "displayName": "Vbrk_cm", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm cmg cmo 0", "pins": [ { "id": "p", "net": "cmg" }, { "id": "n", "net": "cmo" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 480m ac 1", "source": "Vicm icm 0 dc 480m ac 1", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efp", "displayName": "Efp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efp inp icm outn outp 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outn" }, { "id": "cn", "net": "outp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efn", "displayName": "Efn", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efn inn icm outp outn 0.5", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" }, { "device": "Xdut", "pin": "vocm" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Efp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Efn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Efp", "pin": "cn" }, { "device": "Efn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Efp", "pin": "cp" }, { "device": "Efn", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo" }, { "device": "Vbrk_cm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg" }, { "device": "Vbrk_cm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Efp", "pin": "n" }, { "device": "Efn", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/fdtele", "name": "fdtele", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "vocm", "net": "vocm" }, { "name": "ib", "net": "ib" }, { "name": "cmo", "net": "cmo" }, { "name": "cmg", "net": "cmg" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB1 vcp ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRP1", "displayName": "RP1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=27.294u", "source": "XRP1 vcp rp vss rppd w=0.5u l=27.294u", "pins": [ { "id": "p", "net": "vcp" }, { "id": "n", "net": "rp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRP2", "displayName": "RP2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=27.294u", "source": "XRP2 rp vss vss rppd w=0.5u l=27.294u", "pins": [ { "id": "p", "net": "rp" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB2 vcn ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRN1", "displayName": "RN1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRN1 vcn rn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "vcn" }, { "id": "n", "net": "rn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRN2", "displayName": "RN2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRN2 rn vgn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "rn" }, { "id": "n", "net": "vgn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XMB3 vgn vgn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=4", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=1u ng=8 m=1", "source": "XM1 d1 inp tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=1u ng=8 m=1", "source": "XM2 d2 inn tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM3 outn vcp d1 d1 sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "d1" }, { "id": "b", "net": "d1" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM4 outp vcp d2 d2 sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "d2" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM5 outn vcn k1 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM6 outp vcn k2 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM7 k1 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "cmg" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM8 k2 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "cmg" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTC", "displayName": "MTC", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=2", "source": "XMTC td ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=2", "pins": [ { "id": "d", "net": "td" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM9 sn outp td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "outp" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM10 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM11 sn outn td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "outn" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM12 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XM13 sn sn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "sn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XM14 cmo cmo vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "cmo" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB2", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMTC", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMTC", "pin": "s" }, { "device": "XMTC", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XRP1", "pin": "p" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rp", "ground": false, "terminals": [ { "device": "XRP1", "pin": "n" }, { "device": "XRP2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRP1", "pin": "substrate" }, { "device": "XRP2", "pin": "n" }, { "device": "XRP2", "pin": "substrate" }, { "device": "XRN1", "pin": "substrate" }, { "device": "XRN2", "pin": "substrate" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XRN1", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rn", "ground": false, "terminals": [ { "device": "XRN1", "pin": "n" }, { "device": "XRN2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vgn", "ground": false, "terminals": [ { "device": "XRN2", "pin": "n" }, { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM11", "pin": "g" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XM9", "pin": "g" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM5", "pin": "s" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM6", "pin": "s" }, { "device": "XM8", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [ "cmg" ], "voltageReferences": [] }, { "id": "td", "ground": false, "terminals": [ { "device": "XMTC", "pin": "d" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "sn", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XM13", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo", "ground": false, "terminals": [ { "device": "XM10", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XM14", "pin": "g" } ], "ports": [ "cmo" ], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XM10", "pin": "g" }, { "device": "XM12", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/fdtele" } }, { "id": "graph-10", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 450m", "source": "Vocm vocm 0 dc 450m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "fdtele", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 vocm ib cmo cmg fdtele", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "vocm", "net": "vocm" }, { "id": "ib", "net": "ib" }, { "id": "cmo", "net": "cmo" }, { "id": "cmg", "net": "cmg" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/fdtele" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Clp outp 0 2p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cln outn 0 2p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vbrk_cm", "displayName": "Vbrk_cm", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vbrk_cm cmg cmo 0", "pins": [ { "id": "p", "net": "cmg" }, { "id": "n", "net": "cmo" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 480m", "source": "Vicm icm 0 dc 480m", "pins": [ { "id": "p", "net": "icm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efp", "displayName": "Efp", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efp inp icm outn outp 0.5", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outn" }, { "id": "cn", "net": "outp" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efn", "displayName": "Efn", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Efn fsn icm outp outn 0.5", "pins": [ { "id": "p", "net": "fsn" }, { "id": "n", "net": "icm" }, { "id": "cp", "net": "outp" }, { "id": "cn", "net": "outn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vsn", "displayName": "Vsn", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Vsn inn fsn dc 0 ac 1", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "fsn" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" }, { "device": "Vicm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" }, { "device": "Xdut", "pin": "vocm" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Efp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vsn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" }, { "device": "Efp", "pin": "cn" }, { "device": "Efn", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" }, { "device": "Efp", "pin": "cp" }, { "device": "Efn", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmo" }, { "device": "Vbrk_cm", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg", "ground": false, "terminals": [ { "device": "Xdut", "pin": "cmg" }, { "device": "Vbrk_cm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "icm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Efp", "pin": "n" }, { "device": "Efn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "fsn", "ground": false, "terminals": [ { "device": "Efn", "pin": "p" }, { "device": "Vsn", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/fdtele", "name": "fdtele", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "vocm", "net": "vocm" }, { "name": "ib", "net": "ib" }, { "name": "cmo", "net": "cmo" }, { "name": "cmg", "net": "cmg" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB1 vcp ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRP1", "displayName": "RP1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=27.294u", "source": "XRP1 vcp rp vss rppd w=0.5u l=27.294u", "pins": [ { "id": "p", "net": "vcp" }, { "id": "n", "net": "rp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRP2", "displayName": "RP2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=27.294u", "source": "XRP2 rp vss vss rppd w=0.5u l=27.294u", "pins": [ { "id": "p", "net": "rp" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=1", "source": "XMB2 vcn ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRN1", "displayName": "RN1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRN1 vcn rn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "vcn" }, { "id": "n", "net": "rn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRN2", "displayName": "RN2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRN2 rn vgn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "rn" }, { "id": "n", "net": "vgn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XMB3 vgn vgn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "vgn" }, { "id": "g", "net": "vgn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=4", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=1u ng=8 m=1", "source": "XM1 d1 inp tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=1u ng=8 m=1", "source": "XM2 d2 inn tail tail sg13_lv_pmos w=40u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM3 outn vcp d1 d1 sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "d1" }, { "id": "b", "net": "d1" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM4 outp vcp d2 d2 sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "d2" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM5 outn vcn k1 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM6 outp vcn k2 vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM7 k1 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "cmg" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=2", "source": "XM8 k2 cmg vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=2", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "cmg" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTC", "displayName": "MTC", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=1u ng=14 m=2", "source": "XMTC td ib vdd vdd sg13_lv_pmos w=64u l=1u ng=14 m=2", "pins": [ { "id": "d", "net": "td" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM9 sn outp td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "outp" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM10 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM11 sn outn td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "outn" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM12 cmo vocm td td sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "td" }, { "id": "b", "net": "td" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XM13 sn sn vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "sn" }, { "id": "g", "net": "sn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=12u l=1.5u ng=4 m=1", "source": "XM14 cmo cmo vss vss sg13_lv_nmos w=12u l=1.5u ng=4 m=1", "pins": [ { "id": "d", "net": "cmo" }, { "id": "g", "net": "cmo" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB2", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMTC", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMTC", "pin": "s" }, { "device": "XMTC", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XRP1", "pin": "p" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rp", "ground": false, "terminals": [ { "device": "XRP1", "pin": "n" }, { "device": "XRP2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRP1", "pin": "substrate" }, { "device": "XRP2", "pin": "n" }, { "device": "XRP2", "pin": "substrate" }, { "device": "XRN1", "pin": "substrate" }, { "device": "XRN2", "pin": "substrate" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XRN1", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rn", "ground": false, "terminals": [ { "device": "XRN1", "pin": "n" }, { "device": "XRN2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vgn", "ground": false, "terminals": [ { "device": "XRN2", "pin": "n" }, { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM11", "pin": "g" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XM9", "pin": "g" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM5", "pin": "s" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM6", "pin": "s" }, { "device": "XM8", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cmg", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [ "cmg" ], "voltageReferences": [] }, { "id": "td", "ground": false, "terminals": [ { "device": "XMTC", "pin": "d" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "sn", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XM13", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cmo", "ground": false, "terminals": [ { "device": "XM10", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XM14", "pin": "g" } ], "ports": [ "cmo" ], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XM10", "pin": "g" }, { "device": "XM12", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/fdtele" } } ], "views": [ { "bench": "op", "source": { "recordField": "testbenches", "id": "op", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/fd-telescopic/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Fully differential telescopic-cascode OTA", "instances": [] } ] }, "benchDiagram": { "graph": "graph-2", "svg": { "url": "/circuits/fd-telescopic/op-bench.svg", "asset": "op-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/fd-telescopic/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "open_loop", "source": { "recordField": "testbenches", "id": "open_loop", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/fd-telescopic/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Fully differential telescopic-cascode OTA", "instances": [] } ] }, "benchDiagram": { "graph": "graph-4", "svg": { "url": "/circuits/fd-telescopic/open_loop-bench.svg", "asset": "open_loop-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/fd-telescopic/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "cm_loop", "source": { "recordField": "testbenches", "id": "cm_loop", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/fd-telescopic/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Fully differential telescopic-cascode OTA", "instances": [] } ] }, "benchDiagram": { "graph": "graph-5", "svg": { "url": "/circuits/fd-telescopic/cm_loop-bench.svg", "asset": "cm_loop-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/fd-telescopic/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "cm_step", "source": { "recordField": "testbenches", "id": "cm_step", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/fd-telescopic/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Fully differential telescopic-cascode OTA", "instances": [] } ] }, "benchDiagram": { "graph": "graph-6", "svg": { "url": "/circuits/fd-telescopic/cm_step-bench.svg", "asset": "cm_step-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/fd-telescopic/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "step", "source": { "recordField": "testbenches", "id": "step", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/fd-telescopic/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Fully differential telescopic-cascode OTA", "instances": [] } ] }, "benchDiagram": { "graph": "graph-7", "svg": { "url": "/circuits/fd-telescopic/step-bench.svg", "asset": "step-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/fd-telescopic/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "psrr", "source": { "recordField": "testbenches", "id": "psrr", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/fd-telescopic/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Fully differential telescopic-cascode OTA", "instances": [] } ] }, "benchDiagram": { "graph": "graph-8", "svg": { "url": "/circuits/fd-telescopic/psrr-bench.svg", "asset": "psrr-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/fd-telescopic/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "cmrr", "source": { "recordField": "testbenches", "id": "cmrr", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/fd-telescopic/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Fully differential telescopic-cascode OTA", "instances": [] } ] }, "benchDiagram": { "graph": "graph-9", "svg": { "url": "/circuits/fd-telescopic/cmrr-bench.svg", "asset": "cmrr-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/fd-telescopic/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "noise", "source": { "recordField": "testbenches", "id": "noise", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/fd-telescopic/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Fully differential telescopic-cascode OTA", "instances": [] } ] }, "benchDiagram": { "graph": "graph-10", "svg": { "url": "/circuits/fd-telescopic/noise-bench.svg", "asset": "noise-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/fd-telescopic/op-block.svg", "asset": "op-block.svg" } } } ] } }