{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "mixed-signal", "id": "flash-adc", "name": "Flash ADC (3 bit)", "group": "Data converters", "subgroup": "ADCs", "title": "Flash ADC (3 bit)", "summary": "This ADC compares an input with seven reference levels at once. A resistor ladder sets the levels, and logic turns the comparator decisions into a three-bit number. Parallel comparisons are fast, but each extra bit requires roughly twice as many comparators.", "reference": { "kind": "book", "authors": "T. Chan Carusone, D. A. Johns and K. W. Martin", "title": "Analog Integrated Circuit Design", "edition": "2nd ed.", "publisher": "Wiley", "year": 2012, "where": "Nyquist-rate A/D converters - flash converters: the resistor string, the comparators, thermometer to 1-of-N to binary encoding, and bubble errors", "takes": "The architecture, the one-hot (ROM) encoder, and why a bubble in the thermometer code costs more than one code.", "also": [ { "authors": "B. Razavi", "title": "Principles of Data Conversion System Design", "publisher": "IEEE Press", "year": 1995, "where": "Flash architectures - the reference ladder, comparator offset and the encoder" } ] }, "resources": { "record": "/circuits/flash-adc.json", "page": "/index.html#flash-adc", "achieved": "/achieved/flash-adc.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" }, { "name": "sg13g2_stdcell.spice", "url": "/sg13g2_stdcell.spice", "sha256": "cfd805c964d3238b3342b5b1432522c3cf614d167b848d540a1499d1253ef3d4" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice", "sg13g2_stdcell.spice" ], "ports": [ { "name": "vin", "kind": "input" }, { "name": "vrp", "kind": "bias", "note": "the top of the ladder: the top of the input range" }, { "name": "vrn", "kind": "bias", "note": "the bottom of the ladder" }, { "name": "bn", "kind": "bias", "note": "the comparators' bias: the bench gives a current into MB" }, { "name": "clk", "kind": "clock", "note": "high: the latches follow the comparators; low: they hold" }, { "name": "b2", "kind": "output" }, { "name": "b1", "kind": "output" }, { "name": "b0", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "0", "kind": "ground" } ], "devices": [ { "name": "RL1..RL8", "type": "resistor", "sizedBy": [ "RL", "mismatch", "seed" ], "role": "the ladder: eight equal units" }, { "name": "MB", "type": "nmos", "sizedBy": [ "Wt", "Lt" ], "role": "the comparators' bias diode", "fingers": 1, "copies": 1 }, { "name": "MT1..MT7", "type": "nmos", "sizedBy": [ "Wt", "Lt" ], "role": "each comparator's tail, a copy of MB" }, { "name": "MR1..MR7", "type": "nmos", "sizedBy": [ "Wi", "Li" ], "role": "each comparator's input on its tap" }, { "name": "MV1..MV7", "type": "nmos", "sizedBy": [ "Wi", "Li" ], "role": "each comparator's input on vin" }, { "name": "ML1..ML7", "type": "pmos", "sizedBy": [ "Wl", "Ll" ], "role": "each comparator's load, diode side" }, { "name": "MO1..MO7", "type": "pmos", "sizedBy": [ "Wl", "Ll" ], "role": "each comparator's load, output side" }, { "name": "I1..I7", "type": "logic", "sizedBy": [], "role": "square each comparator's output into t_k: NAND gates with their inputs tied, inverters whose threshold sits at the amplifier's balance level" }, { "name": "D1..D7", "type": "logic", "sizedBy": [], "role": "latches: hold the thermometer code while clk is low" }, { "name": "H1..H6", "type": "logic", "sizedBy": [], "role": "one-hot: h_k = q_k and not q_(k+1)" }, { "name": "E0", "type": "logic", "sizedBy": [], "role": "encoder: b0 = h1 + h3 + h5 + q7" }, { "name": "E1", "type": "logic", "sizedBy": [], "role": "encoder: b1 = h2 + h3 + h6 + q7" }, { "name": "E2", "type": "logic", "sizedBy": [], "role": "encoder: b2 = h4 + h5 + h6 + q7" } ], "intent": [ { "rule": "ladder", "of": [ "RL1..RL8" ], "constraint": "tap k = V_REF- + k (V_REF+ - V_REF-)/8", "why": "Eight equal units put the taps one LSB apart: 75 mV with the default references. At three bits the ladder hardly matters - with its units at σ = 5 % the largest DNL is 0.075 LSB (seed 1) - but an N-bit flash has 2^N units and an LSB 2^N times smaller than its range." }, { "rule": "comparator-offset", "of": [ "MR1..MR7", "MV1..MV7", "I1..I7" ], "constraint": "the squaring gate switches where the amplifier balances", "why": "An amplifier balanced on its tap puts its output at 0.68 V, and a NAND gate with its inputs tied switches at 0.68 V: the output hardly has to move, and every threshold sits within 1.2 mV of its tap (-0.4 to +1.2 mV) - an offset error of 0.017 LSB, DNL 0.006 LSB, what differs from one comparator to the next being only the common mode. An inverter switches at 0.61 V: the output must fall 70 mV to reach it, and its finite gain put every threshold 4.2 to 6.2 mV above its tap." }, { "rule": "input-range", "of": [ "MR1..MR7", "MV1..MV7", "MT1..MT7", "I1..I7" ], "constraint": "taps between about 0.33 and 0.88 V", "why": "The amplifier's output can fall no lower than its pair's common source, which follows the tap up, and hot or with fast NMOS the pair's V_GS shrinks: behind inverters, a ladder from 0.35 to 0.95 V left the top comparator switching 41 mV late at 125 °C, so that 7 read as 6, and on the ff corner 0.29 V late or, with the supply 10 % low, not at all. Behind the higher-threshold NAND gates, and with the ladder from 0.3 to 0.9 V, centred on half the supply, every threshold stays within 15 mV of its tap at all 45 corners. The limits: a 0.925 V tap switches 55 mV early at 125 °C on the fs corner with the supply 10 % low; at a 0.275 V tap the pair leaves its tail so little voltage that comparator 1 misses its clock at -40 °C on the ss corner." }, { "rule": "latches", "of": [ "D1..D7" ], "constraint": "the encoder reads latched, full logic levels", "why": "Within a fraction of a millivolt of its tap a comparator's output is neither 0 nor 1, and two gates reading it can disagree: without the latches, this converter swept in 0.1 mV steps read code 0 at 600.1 mV, between 3 and 4. The latches close on the falling clock edge and hold full levels while the encoder works." }, { "rule": "one-hot-encoder", "of": [ "H1..H6", "E0", "E1", "E2" ], "why": "h_k marks where the ones stop, and each output bit is the OR of the one-hot lines whose code has it set - a ROM of three rows. A bubble in the thermometer code can light several one-hot lines and make their OR encode a large error. Gray coding limits bit changes between adjacent valid codes; it does not by itself correct an arbitrary thermometer bubble. This encoder includes no bubble-correction network." }, { "rule": "doubling", "of": [ "MT1..MT7" ], "constraint": "2^N - 1 comparators", "why": "Seven comparators for three bits, drawing 63 of the 80 µA a conversion takes; every further bit doubles them and halves the LSB each one has to resolve. That is the price of converting in one clock." } ], "specs": [ { "key": "dnl", "label": "Largest DNL", "unit": "LSB", "direction": "min" }, { "key": "inl", "label": "Largest INL", "unit": "LSB", "direction": "min" }, { "key": "offset", "label": "Offset error", "unit": "LSB", "direction": "min" }, { "key": "tconv", "label": "Clock period / sample interval", "unit": "s", "direction": "min" }, { "key": "energy", "label": "Main-supply energy per conversion", "unit": "J", "direction": "min" } ], "explanation": { "idea": "This ADC compares an input with seven reference levels at once. A resistor ladder sets the levels, and logic turns the comparator decisions into a three-bit number. Parallel comparisons are fast, but each extra bit requires roughly twice as many comparators.", "detail": "Converts an input to three bits with one scheduled conversion per clock period by comparing it with every threshold at once. A string of eight equal resistors divides V_REF+ − V_REF− into taps one LSB apart, and seven comparators each report whether vin is above their tap; the result is a thermometer code whose count of ones is the output. Latches freeze that code on the falling clock edge, and a one-hot encoder turns it into three binary bits. The price is 2^N − 1 comparators for N bits. The displayed clock interval is calculated, not a measured output-valid delay.", "lesson": { "relation": 1, "symbols": "LSB is one ideal input-voltage step; V_rp and V_rn are the upper and lower reference voltages; N is the resolution, three bits here.", "assumptions": "Equal ladder resistors and negligible comparator offset give equally spaced thresholds. Each comparator must operate within its input common-mode range and settle before the latches close.", "exercise": { "param": "vrp", "value": 0.8, "analysis": "transfer", "expect": "The reference span shrinks, so the ideal voltage step becomes smaller and the upper code transitions move down. Compare the measured thresholds with the ideal ones." }, "limits": "The bench supplies ideal references, comparator bias and a clock. Reference loading, comparator offset and latch timing matter in a system. This encoder assumes an ordered thermometer code; do not infer bubble-error correction or a qualified maximum conversion rate. Current and energy figures measure Vdd only; the separately supplied reference ladder and external clock/input drivers are excluded. Gray coding alone does not correct arbitrary thermometer bubbles." }, "path": [ { "part": "Reference ladder", "devices": "RL1..RL8", "does": "Eight equal poly resistors from V_REF+ down to V_REF− put tap k at V_REF− + k·LSB: seven thresholds, 75 mV apart by default." }, { "part": "Comparators", "devices": "MT1..MT7, MR1..MR7, MV1..MV7, ML1..ML7, MO1..MO7", "does": "Seven five-transistor amplifiers, vin on the gate of MVk and tap k on MRk; each pulls its output o_k low when vin is above its tap, all at once." }, { "part": "Squaring", "devices": "I1..I7", "does": "A NAND gate with both inputs on o_k, switching at 0.68 V where the amplifier balances, turns each output into t_k, 1 when vin is above tap k: a thermometer code." }, { "part": "Latches", "devices": "D1..D7", "does": "Transparent while clk is high, they close on its falling edge and hold full logic levels q_k while the encoder works through the low half." }, { "part": "Encoder", "devices": "H1..H6, E0, E1, E2", "does": "h_k = q_k and not q_(k+1) marks where the ones stop; each output bit ORs the one-hot lines whose code has it set, with q7 standing for code 7." } ], "bias": "The bench drives the comparator bias, 10 µA by default, into MB, and MT1..MT7 each copy it, so the comparators draw up to seven times the bias; V_REF+ and V_REF−, 0.9 and 0.3 V by default, set the range and pass (V_REF+ − V_REF−)/(8·R_L) down the ladder. The clock sets the timing: the latches follow while clk is high and hold while it is low.", "relations": [ { "what": "Tap voltages", "expr": "V_k = V_rn + k·(V_rp − V_rn)/2^N", "note": "V_rp and V_rn are V_REF+ and V_REF−, on pins vrp and vrn; k = 1 to 7" }, { "what": "LSB", "expr": "LSB = (V_rp − V_rn)/2^N", "note": "75 mV with the defaults; ladder mismatch moves each tap by the unit errors below it" }, { "what": "Comparator count", "expr": "n = 2^N − 1", "note": "seven here; each extra bit doubles them and halves the LSB each must resolve" }, { "what": "Systematic threshold offset", "expr": "V_os ≈ (V_o,0 − V_M)/A_v; A_v = g_m·(r_on ∥ r_op)", "note": "the amplifier must move o_k from balance to the squaring gate's threshold V_M; the NAND gate's V_M sits at V_o,0, 0.68 V, so V_os stays under 1.2 mV" }, { "what": "Comparator speed", "expr": "dv_o/dt ≤ I_tail/C_o", "note": "the tail current slews each output node, which must settle before the latches close" } ], "tradeoffs": [ "Comparator bias: more current lets each comparator slew and settle faster, but seven tails copy it, so the supply current rises seven times as fast.", "Ladder unit: smaller units keep the taps stiff against the comparators' input kickback, but the references then supply more current, (V_REF+ − V_REF−)/(8·R_L).", "V_REF+ and V_REF−: a wider ladder enlarges the LSB, but the comparators convert right at every corner only for taps from about 0.33 to 0.88 V: higher, a hot fast corner moves the top threshold tens of millivolts; lower, the cold slow corner starves comparator 1.", "W (comparator input): a wider pair lowers random offset and raises g_m, but loads vin and every tap with more gate capacitance." ] }, "sizing": [ { "key": "vrp", "label": "V_REF+ (top of the ladder)", "unit": "V", "value": 0.9, "min": 0.6, "max": 1.1, "kind": "si" }, { "key": "vrn", "label": "V_REF- (bottom of the ladder)", "unit": "V", "value": 0.3, "min": 0.2, "max": 0.6, "kind": "si" }, { "key": "RL", "label": "Ladder unit", "unit": "Ω", "value": 5000, "min": 500, "max": 50000, "kind": "si" }, { "key": "mismatch", "label": "Ladder unit σ", "unit": "%", "value": 0, "min": 0, "max": 10, "kind": "si" }, { "key": "seed", "label": "Mismatch seed", "unit": "", "value": 1, "min": 1, "max": 999, "kind": "int" }, { "key": "ib", "label": "Comparator bias", "unit": "A", "value": 0.00001, "min": 0.000001, "max": 0.0001, "kind": "si" }, { "key": "Wi", "label": "W (comparator input)", "unit": "m", "value": 0.000004, "min": 1.5e-7, "max": 0.00005, "kind": "si" }, { "key": "Li", "label": "L (comparator input)", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.00001, "kind": "si" }, { "key": "Wl", "label": "W (comparator load)", "unit": "m", "value": 0.000002, "min": 1.5e-7, "max": 0.00005, "kind": "si" }, { "key": "Ll", "label": "L (comparator load)", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.00001, "kind": "si" }, { "key": "Wt", "label": "W (tail and bias)", "unit": "m", "value": 0.000002, "min": 1.5e-7, "max": 0.00005, "kind": "si" }, { "key": "Lt", "label": "L (tail and bias)", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.00001, "kind": "si" } ], "testbenches": [ { "id": "transfer", "label": "Transfer (input swept)", "note": "", "measures": [ "dnl", "inl", "offset" ], "metricKeys": [ "offset", "gain_err", "dnl", "inl" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice", "sg13g2_stdcell.spice" ], "netlist": "* 3-bit flash ADC - the input swept, the latches held transparent\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.include sg13g2_stdcell.spice\nVdd vdd 0 1.2\nVrp vrp 0 900m\nVrn vrn 0 300m\nIb vdd bn 10u\nVclk clk 0 1.2\nVin vin 0 0\n* the ladder, vrp down to vrn: tap k sits k/8 of the way up\nXRL8 vrp tap7 0 rppd w=0.5u l=9.57u\nXRL7 tap7 tap6 0 rppd w=0.5u l=9.57u\nXRL6 tap6 tap5 0 rppd w=0.5u l=9.57u\nXRL5 tap5 tap4 0 rppd w=0.5u l=9.57u\nXRL4 tap4 tap3 0 rppd w=0.5u l=9.57u\nXRL3 tap3 tap2 0 rppd w=0.5u l=9.57u\nXRL2 tap2 tap1 0 rppd w=0.5u l=9.57u\nXRL1 tap1 vrn 0 rppd w=0.5u l=9.57u\n* the comparators' tails all copy the bias current the bench gives on bn\nXMB bn bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1\n* comparator 1: t1 = 1 when vin is above tap1\nXMT1 s1 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1\nXMR1 x1 tap1 s1 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXMV1 o1 vin s1 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXML1 x1 x1 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXMO1 o1 x1 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXI1 t1 o1 o1 vdd 0 sg13g2_nand2_1\nXD1 q1 t1 clk vdd 0 sg13g2_dlhq_1\n* comparator 2: t2 = 1 when vin is above tap2\nXMT2 s2 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1\nXMR2 x2 tap2 s2 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXMV2 o2 vin s2 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXML2 x2 x2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXMO2 o2 x2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXI2 t2 o2 o2 vdd 0 sg13g2_nand2_1\nXD2 q2 t2 clk vdd 0 sg13g2_dlhq_1\n* comparator 3: t3 = 1 when vin is above tap3\nXMT3 s3 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1\nXMR3 x3 tap3 s3 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXMV3 o3 vin s3 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXML3 x3 x3 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXMO3 o3 x3 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXI3 t3 o3 o3 vdd 0 sg13g2_nand2_1\nXD3 q3 t3 clk vdd 0 sg13g2_dlhq_1\n* comparator 4: t4 = 1 when vin is above tap4\nXMT4 s4 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1\nXMR4 x4 tap4 s4 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXMV4 o4 vin s4 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXML4 x4 x4 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXMO4 o4 x4 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXI4 t4 o4 o4 vdd 0 sg13g2_nand2_1\nXD4 q4 t4 clk vdd 0 sg13g2_dlhq_1\n* comparator 5: t5 = 1 when vin is above tap5\nXMT5 s5 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1\nXMR5 x5 tap5 s5 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXMV5 o5 vin s5 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXML5 x5 x5 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXMO5 o5 x5 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXI5 t5 o5 o5 vdd 0 sg13g2_nand2_1\nXD5 q5 t5 clk vdd 0 sg13g2_dlhq_1\n* comparator 6: t6 = 1 when vin is above tap6\nXMT6 s6 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1\nXMR6 x6 tap6 s6 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXMV6 o6 vin s6 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXML6 x6 x6 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXMO6 o6 x6 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXI6 t6 o6 o6 vdd 0 sg13g2_nand2_1\nXD6 q6 t6 clk vdd 0 sg13g2_dlhq_1\n* comparator 7: t7 = 1 when vin is above tap7\nXMT7 s7 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1\nXMR7 x7 tap7 s7 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXMV7 o7 vin s7 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXML7 x7 x7 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXMO7 o7 x7 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXI7 t7 o7 o7 vdd 0 sg13g2_nand2_1\nXD7 q7 t7 clk vdd 0 sg13g2_dlhq_1\n* the encoder: one-hot h_k = q_k and not q_(k+1), then each output bit the OR\n* of the one-hot lines whose code has that bit set\nXH1 h1 q2 q1 vdd 0 sg13g2_nor2b_1\nXH2 h2 q3 q2 vdd 0 sg13g2_nor2b_1\nXH3 h3 q4 q3 vdd 0 sg13g2_nor2b_1\nXH4 h4 q5 q4 vdd 0 sg13g2_nor2b_1\nXH5 h5 q6 q5 vdd 0 sg13g2_nor2b_1\nXH6 h6 q7 q6 vdd 0 sg13g2_nor2b_1\nXE0 b0 h1 h3 h5 q7 vdd 0 sg13g2_or4_1\nXE1 b1 h2 h3 h6 q7 vdd 0 sg13g2_or4_1\nXE2 b2 h4 h5 h6 q7 vdd 0 sg13g2_or4_1\n.dc Vin 0 1.2 0.001\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc vt1 WHEN v(t1)=600m RISE=1\n.meas dc vt2 WHEN v(t2)=600m RISE=1\n.meas dc vt3 WHEN v(t3)=600m RISE=1\n.meas dc vt4 WHEN v(t4)=600m RISE=1\n.meas dc vt5 WHEN v(t5)=600m RISE=1\n.meas dc vt6 WHEN v(t6)=600m RISE=1\n.meas dc vt7 WHEN v(t7)=600m RISE=1\n.end" }, { "id": "convert", "label": "Conversion (clocked)", "note": "Eight conversions, every transistor simulated: about 8 s in the browser.", "measures": [ "tconv", "energy" ], "metricKeys": [ "tconv", "energy" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice", "sg13g2_stdcell.spice" ], "netlist": "* 3-bit flash ADC - eight conversions, one per clock\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.include sg13g2_stdcell.spice\nVdd vdd 0 1.2\nVrp vrp 0 900m\nVrn vrn 0 300m\nIb vdd bn 10u\nVclk clk 0 PULSE(1.2 0 10n 50p 50p 9.95n 20n)\nVin vin 0 PWL(0 337.5m 19.95n 337.5m 20n 412.5m 39.95n 412.5m 40n 487.5m 59.95n 487.5m 60n 562.5m 79.95n 562.5m 80n 637.5m 99.95n 637.5m 100n 712.5m 119.95n 712.5m 120n 787.5m 139.95n 787.5m 140n 862.5m 159.95n 862.5m)\n* the ladder, vrp down to vrn: tap k sits k/8 of the way up\nXRL8 vrp tap7 0 rppd w=0.5u l=9.57u\nXRL7 tap7 tap6 0 rppd w=0.5u l=9.57u\nXRL6 tap6 tap5 0 rppd w=0.5u l=9.57u\nXRL5 tap5 tap4 0 rppd w=0.5u l=9.57u\nXRL4 tap4 tap3 0 rppd w=0.5u l=9.57u\nXRL3 tap3 tap2 0 rppd w=0.5u l=9.57u\nXRL2 tap2 tap1 0 rppd w=0.5u l=9.57u\nXRL1 tap1 vrn 0 rppd w=0.5u l=9.57u\n* the comparators' tails all copy the bias current the bench gives on bn\nXMB bn bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1\n* comparator 1: t1 = 1 when vin is above tap1\nXMT1 s1 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1\nXMR1 x1 tap1 s1 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXMV1 o1 vin s1 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXML1 x1 x1 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXMO1 o1 x1 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXI1 t1 o1 o1 vdd 0 sg13g2_nand2_1\nXD1 q1 t1 clk vdd 0 sg13g2_dlhq_1\n* comparator 2: t2 = 1 when vin is above tap2\nXMT2 s2 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1\nXMR2 x2 tap2 s2 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXMV2 o2 vin s2 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXML2 x2 x2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXMO2 o2 x2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXI2 t2 o2 o2 vdd 0 sg13g2_nand2_1\nXD2 q2 t2 clk vdd 0 sg13g2_dlhq_1\n* comparator 3: t3 = 1 when vin is above tap3\nXMT3 s3 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1\nXMR3 x3 tap3 s3 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXMV3 o3 vin s3 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXML3 x3 x3 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXMO3 o3 x3 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXI3 t3 o3 o3 vdd 0 sg13g2_nand2_1\nXD3 q3 t3 clk vdd 0 sg13g2_dlhq_1\n* comparator 4: t4 = 1 when vin is above tap4\nXMT4 s4 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1\nXMR4 x4 tap4 s4 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXMV4 o4 vin s4 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXML4 x4 x4 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXMO4 o4 x4 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXI4 t4 o4 o4 vdd 0 sg13g2_nand2_1\nXD4 q4 t4 clk vdd 0 sg13g2_dlhq_1\n* comparator 5: t5 = 1 when vin is above tap5\nXMT5 s5 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1\nXMR5 x5 tap5 s5 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXMV5 o5 vin s5 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXML5 x5 x5 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXMO5 o5 x5 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXI5 t5 o5 o5 vdd 0 sg13g2_nand2_1\nXD5 q5 t5 clk vdd 0 sg13g2_dlhq_1\n* comparator 6: t6 = 1 when vin is above tap6\nXMT6 s6 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1\nXMR6 x6 tap6 s6 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXMV6 o6 vin s6 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXML6 x6 x6 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXMO6 o6 x6 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXI6 t6 o6 o6 vdd 0 sg13g2_nand2_1\nXD6 q6 t6 clk vdd 0 sg13g2_dlhq_1\n* comparator 7: t7 = 1 when vin is above tap7\nXMT7 s7 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1\nXMR7 x7 tap7 s7 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXMV7 o7 vin s7 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXML7 x7 x7 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXMO7 o7 x7 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXI7 t7 o7 o7 vdd 0 sg13g2_nand2_1\nXD7 q7 t7 clk vdd 0 sg13g2_dlhq_1\n* the encoder: one-hot h_k = q_k and not q_(k+1), then each output bit the OR\n* of the one-hot lines whose code has that bit set\nXH1 h1 q2 q1 vdd 0 sg13g2_nor2b_1\nXH2 h2 q3 q2 vdd 0 sg13g2_nor2b_1\nXH3 h3 q4 q3 vdd 0 sg13g2_nor2b_1\nXH4 h4 q5 q4 vdd 0 sg13g2_nor2b_1\nXH5 h5 q6 q5 vdd 0 sg13g2_nor2b_1\nXH6 h6 q7 q6 vdd 0 sg13g2_nor2b_1\nXE0 b0 h1 h3 h5 q7 vdd 0 sg13g2_or4_1\nXE1 b1 h2 h3 h6 q7 vdd 0 sg13g2_or4_1\nXE2 b2 h4 h5 h6 q7 vdd 0 sg13g2_or4_1\n.tran 400p 160n\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas tran idd AVG i(Vdd) FROM=0 TO=160n\n.end" } ], "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "68268dc7566eefc81d98a59b4ff1707eff7565f10885eb555859843985d09cb1" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/flash-adc.js", "sha256": "b5172125e7fd09f330d0d6328df71d7d485a65429902289b546e7fe7fabb3a60" }, "simulationFingerprints": { "transfer": "1d2528a98f695c511075e2deb1dd27034933bfbeacc6d17fcbd0258fa41b9ab9", "convert": "761a7eea515f1be0b5680d1634b5012af2ec1def832aa1162000675180ab984b" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "76d1c9140f172a33b326bc24075ecf156b6d8f4b1f9a3e5fa0bbf048b1dbc234", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "flash-adc", "parameters": { "vrp": 0.9, "vrn": 0.3, "RL": 5000, "mismatch": 0, "seed": 1, "ib": 0.00001, "Wi": 0.000004, "Li": 5e-7, "Wl": 0.000002, "Ll": 5e-7, "Wt": 0.000002, "Lt": 0.000001 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/flash-adc/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [], "scopes": [ { "id": "dut", "name": "top", "ports": [ { "name": "vrp", "net": "vrp", "kind": "bias" }, { "name": "vrn", "net": "vrn", "kind": "bias" }, { "name": "bn", "net": "bn", "kind": "bias" }, { "name": "gnd", "net": "0", "kind": "ground" }, { "name": "vin", "net": "vin", "kind": "input" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "clk", "net": "clk", "kind": "clock" }, { "name": "b0", "net": "b0", "kind": "output" }, { "name": "b1", "net": "b1", "kind": "output" }, { "name": "b2", "net": "b2", "kind": "output" } ], "definitions": [], "devices": [ { "id": "XRL8", "displayName": "RL8", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL8 vrp tap7 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "vrp" }, { "id": "n", "net": "tap7" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL7", "displayName": "RL7", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL7 tap7 tap6 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap7" }, { "id": "n", "net": "tap6" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL6", "displayName": "RL6", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL6 tap6 tap5 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap6" }, { "id": "n", "net": "tap5" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL5", "displayName": "RL5", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL5 tap5 tap4 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap5" }, { "id": "n", "net": "tap4" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL4", "displayName": "RL4", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL4 tap4 tap3 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap4" }, { "id": "n", "net": "tap3" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL3", "displayName": "RL3", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL3 tap3 tap2 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap3" }, { "id": "n", "net": "tap2" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL2", "displayName": "RL2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL2 tap2 tap1 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap2" }, { "id": "n", "net": "tap1" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL1", "displayName": "RL1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL1 tap1 vrn 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap1" }, { "id": "n", "net": "vrn" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMB bn bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "bn" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT1", "displayName": "MT1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT1 s1 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s1" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR1", "displayName": "MR1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR1 x1 tap1 s1 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "tap1" }, { "id": "s", "net": "s1" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMV1", "displayName": "MV1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMV1 o1 vin s1 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vin" }, { "id": "s", "net": "s1" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML1", "displayName": "ML1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XML1 x1 x1 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO1", "displayName": "MO1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMO1 o1 x1 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XI1", "displayName": "I1", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XI1 t1 o1 o1 vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "t1" }, { "id": "A", "net": "o1" }, { "id": "B", "net": "o1" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD1", "displayName": "D1", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD1 q1 t1 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q1" }, { "id": "D", "net": "t1" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMT2", "displayName": "MT2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT2 s2 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s2" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR2", "displayName": "MR2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR2 x2 tap2 s2 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "tap2" }, { "id": "s", "net": "s2" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMV2", "displayName": "MV2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMV2 o2 vin s2 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vin" }, { "id": "s", "net": "s2" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML2", "displayName": "ML2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XML2 x2 x2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "x2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO2", "displayName": "MO2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMO2 o2 x2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "x2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XI2", "displayName": "I2", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XI2 t2 o2 o2 vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "t2" }, { "id": "A", "net": "o2" }, { "id": "B", "net": "o2" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD2", "displayName": "D2", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD2 q2 t2 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q2" }, { "id": "D", "net": "t2" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMT3", "displayName": "MT3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT3 s3 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s3" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR3", "displayName": "MR3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR3 x3 tap3 s3 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x3" }, { "id": "g", "net": "tap3" }, { "id": "s", "net": "s3" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMV3", "displayName": "MV3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMV3 o3 vin s3 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o3" }, { "id": "g", "net": "vin" }, { "id": "s", "net": "s3" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML3", "displayName": "ML3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XML3 x3 x3 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x3" }, { "id": "g", "net": "x3" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO3", "displayName": "MO3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMO3 o3 x3 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o3" }, { "id": "g", "net": "x3" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XI3", "displayName": "I3", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XI3 t3 o3 o3 vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "t3" }, { "id": "A", "net": "o3" }, { "id": "B", "net": "o3" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD3", "displayName": "D3", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD3 q3 t3 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q3" }, { "id": "D", "net": "t3" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMT4", "displayName": "MT4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT4 s4 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s4" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR4", "displayName": "MR4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR4 x4 tap4 s4 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x4" }, { "id": "g", "net": "tap4" }, { "id": "s", "net": "s4" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMV4", "displayName": "MV4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMV4 o4 vin s4 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o4" }, { "id": "g", "net": "vin" }, { "id": "s", "net": "s4" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML4", "displayName": "ML4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XML4 x4 x4 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x4" }, { "id": "g", "net": "x4" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO4", "displayName": "MO4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMO4 o4 x4 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o4" }, { "id": "g", "net": "x4" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XI4", "displayName": "I4", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XI4 t4 o4 o4 vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "t4" }, { "id": "A", "net": "o4" }, { "id": "B", "net": "o4" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD4", "displayName": "D4", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD4 q4 t4 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q4" }, { "id": "D", "net": "t4" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMT5", "displayName": "MT5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT5 s5 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s5" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR5", "displayName": "MR5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR5 x5 tap5 s5 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x5" }, { "id": "g", "net": "tap5" }, { "id": "s", "net": "s5" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMV5", "displayName": "MV5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMV5 o5 vin s5 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o5" }, { "id": "g", "net": "vin" }, { "id": "s", "net": "s5" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML5", "displayName": "ML5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XML5 x5 x5 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x5" }, { "id": "g", "net": "x5" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO5", "displayName": "MO5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMO5 o5 x5 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o5" }, { "id": "g", "net": "x5" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XI5", "displayName": "I5", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XI5 t5 o5 o5 vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "t5" }, { "id": "A", "net": "o5" }, { "id": "B", "net": "o5" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD5", "displayName": "D5", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD5 q5 t5 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q5" }, { "id": "D", "net": "t5" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMT6", "displayName": "MT6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT6 s6 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s6" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR6", "displayName": "MR6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR6 x6 tap6 s6 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { 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"net": "t7" }, { "id": "A", "net": "o7" }, { "id": "B", "net": "o7" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD7", "displayName": "D7", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD7 q7 t7 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q7" }, { "id": "D", "net": "t7" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XH1", "displayName": "H1", "spiceType": "X", "model": "sg13g2_nor2b_1", "parametersOrValue": "", "source": "XH1 h1 q2 q1 vdd 0 sg13g2_nor2b_1", "pins": [ { "id": "Y", "net": "h1" }, { "id": "A", "net": "q2" }, { "id": "B_N", "net": "q1" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XH2", "displayName": "H2", "spiceType": "X", "model": "sg13g2_nor2b_1", "parametersOrValue": "", "source": "XH2 h2 q3 q2 vdd 0 sg13g2_nor2b_1", "pins": [ { "id": "Y", "net": "h2" }, { "id": "A", "net": "q3" }, { "id": "B_N", "net": "q2" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XH3", "displayName": "H3", "spiceType": "X", "model": "sg13g2_nor2b_1", "parametersOrValue": "", "source": "XH3 h3 q4 q3 vdd 0 sg13g2_nor2b_1", "pins": [ { "id": "Y", "net": "h3" }, { "id": "A", "net": "q4" }, { "id": "B_N", "net": "q3" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XH4", "displayName": "H4", "spiceType": "X", "model": "sg13g2_nor2b_1", "parametersOrValue": "", "source": "XH4 h4 q5 q4 vdd 0 sg13g2_nor2b_1", "pins": [ { "id": "Y", "net": "h4" }, { "id": "A", "net": "q5" }, { "id": "B_N", "net": "q4" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], 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"id": "A", "net": "h1" }, { "id": "B", "net": "h3" }, { "id": "C", "net": "h5" }, { "id": "D", "net": "q7" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XE1", "displayName": "E1", "spiceType": "X", "model": "sg13g2_or4_1", "parametersOrValue": "", "source": "XE1 b1 h2 h3 h6 q7 vdd 0 sg13g2_or4_1", "pins": [ { "id": "X", "net": "b1" }, { "id": "A", "net": "h2" }, { "id": "B", "net": "h3" }, { "id": "C", "net": "h6" }, { "id": "D", "net": "q7" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XE2", "displayName": "E2", "spiceType": "X", "model": "sg13g2_or4_1", "parametersOrValue": "", "source": "XE2 b2 h4 h5 h6 q7 vdd 0 sg13g2_or4_1", "pins": [ { "id": "X", "net": "b2" }, { "id": "A", "net": "h4" }, { "id": "B", "net": "h5" }, { "id": "C", "net": "h6" }, { "id": "D", "net": "q7" }, { "id": "VDD", "net": "vdd" }, { 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"b" }, { "device": "XI1", "pin": "VSS" }, { "device": "XD1", "pin": "VSS" }, { "device": "XMT2", "pin": "s" }, { "device": "XMT2", "pin": "b" }, { "device": "XMR2", "pin": "b" }, { "device": "XMV2", "pin": "b" }, { "device": "XI2", "pin": "VSS" }, { "device": "XD2", "pin": "VSS" }, { "device": "XMT3", "pin": "s" }, { "device": "XMT3", "pin": "b" }, { "device": "XMR3", "pin": "b" }, { "device": "XMV3", "pin": "b" }, { "device": "XI3", "pin": "VSS" }, { "device": "XD3", "pin": "VSS" }, { "device": "XMT4", "pin": "s" }, { "device": "XMT4", "pin": "b" }, { "device": "XMR4", "pin": "b" }, { "device": "XMV4", "pin": "b" }, { "device": "XI4", "pin": "VSS" }, { "device": "XD4", "pin": "VSS" }, { "device": "XMT5", "pin": "s" }, { "device": "XMT5", "pin": "b" }, { "device": "XMR5", "pin": "b" }, { "device": "XMV5", "pin": "b" }, { "device": "XI5", "pin": "VSS" }, { "device": "XD5", "pin": "VSS" }, { "device": "XMT6", "pin": "s" }, { "device": "XMT6", "pin": "b" }, { "device": "XMR6", "pin": "b" }, { "device": "XMV6", "pin": "b" }, { "device": "XI6", "pin": "VSS" }, { "device": "XD6", "pin": "VSS" }, { "device": "XMT7", "pin": "s" }, { "device": "XMT7", "pin": "b" }, { "device": "XMR7", "pin": "b" }, { "device": "XMV7", "pin": "b" }, { "device": "XI7", "pin": "VSS" }, { "device": "XD7", "pin": "VSS" }, { "device": "XH1", "pin": "VSS" }, { "device": "XH2", "pin": "VSS" }, { "device": "XH3", "pin": "VSS" }, { "device": "XH4", "pin": "VSS" }, { "device": "XH5", "pin": "VSS" }, { "device": "XH6", "pin": "VSS" }, { "device": "XE0", "pin": "VSS" }, { "device": "XE1", "pin": "VSS" }, { "device": "XE2", "pin": "VSS" } ], "ports": [ "gnd" ], "voltageReferences": [] }, { "id": "tap6", "ground": false, "terminals": [ { "device": "XRL7", "pin": "n" }, { "device": "XRL6", "pin": "p" }, { "device": "XMR6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tap5", "ground": false, "terminals": [ { "device": "XRL6", "pin": "n" }, { "device": "XRL5", "pin": "p" }, { "device": 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}, { "id": "vin", "ground": false, "terminals": [ { "device": "XMV1", "pin": "g" }, { "device": "XMV2", "pin": "g" }, { "device": "XMV3", "pin": "g" }, { "device": "XMV4", "pin": "g" }, { "device": "XMV5", "pin": "g" }, { "device": "XMV6", "pin": "g" }, { "device": "XMV7", "pin": "g" } ], "ports": [ "vin" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XML1", "pin": "s" }, { "device": "XML1", "pin": "b" }, { "device": "XMO1", "pin": "s" }, { "device": "XMO1", "pin": "b" }, { "device": "XI1", "pin": "VDD" }, { "device": "XD1", "pin": "VDD" }, { "device": "XML2", "pin": "s" }, { "device": "XML2", "pin": "b" }, { "device": "XMO2", "pin": "s" }, { "device": "XMO2", "pin": "b" }, { "device": "XI2", "pin": "VDD" }, { "device": "XD2", "pin": "VDD" }, { "device": "XML3", "pin": "s" }, { "device": "XML3", "pin": "b" }, { "device": "XMO3", "pin": "s" }, { "device": "XMO3", "pin": "b" }, { "device": "XI3", "pin": "VDD" }, { "device": "XD3", "pin": "VDD" }, { "device": "XML4", "pin": "s" }, { "device": "XML4", "pin": "b" }, { "device": "XMO4", "pin": "s" }, { "device": "XMO4", "pin": "b" }, { "device": "XI4", "pin": "VDD" }, { "device": "XD4", "pin": "VDD" }, { "device": "XML5", "pin": "s" }, { "device": "XML5", "pin": "b" }, { "device": "XMO5", "pin": "s" }, { "device": "XMO5", "pin": "b" }, { "device": "XI5", "pin": "VDD" }, { "device": "XD5", "pin": "VDD" }, { "device": "XML6", "pin": "s" }, { "device": "XML6", "pin": "b" }, { "device": "XMO6", "pin": "s" }, { "device": "XMO6", "pin": "b" }, { "device": "XI6", "pin": "VDD" }, { "device": "XD6", "pin": "VDD" }, { "device": "XML7", "pin": "s" }, { "device": "XML7", "pin": "b" }, { "device": "XMO7", "pin": "s" }, { "device": "XMO7", "pin": "b" }, { "device": "XI7", "pin": "VDD" }, { "device": "XD7", "pin": "VDD" }, { "device": "XH1", "pin": "VDD" }, { "device": "XH2", "pin": "VDD" }, { "device": "XH3", "pin": "VDD" }, { "device": "XH4", "pin": "VDD" }, { "device": "XH5", "pin": "VDD" }, { "device": "XH6", "pin": "VDD" }, { "device": "XE0", "pin": "VDD" }, { "device": "XE1", "pin": "VDD" }, { "device": "XE2", "pin": "VDD" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "t1", "ground": false, "terminals": [ { "device": "XI1", "pin": "Y" }, { "device": "XD1", "pin": "D" } ], "ports": [], "voltageReferences": [] }, { "id": "q1", "ground": false, "terminals": [ { "device": "XD1", "pin": "Q" }, { "device": "XH1", "pin": "B_N" } ], "ports": [], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "XD1", "pin": "GATE" }, { "device": "XD2", "pin": "GATE" }, { "device": "XD3", "pin": "GATE" }, { "device": "XD4", "pin": "GATE" }, { "device": "XD5", "pin": "GATE" }, { "device": "XD6", "pin": "GATE" }, { "device": "XD7", "pin": "GATE" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "s2", "ground": false, "terminals": [ { "device": "XMT2", "pin": "d" }, { "device": "XMR2", "pin": "s" }, { "device": "XMV2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x2", "ground": false, "terminals": [ { "device": "XMR2", "pin": "d" }, { "device": "XML2", "pin": "d" }, { "device": "XML2", "pin": "g" }, { "device": "XMO2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XMV2", "pin": "d" }, { "device": "XMO2", "pin": "d" }, { "device": "XI2", "pin": "A" }, { "device": "XI2", "pin": "B" } ], "ports": [], "voltageReferences": [] }, { "id": "t2", "ground": false, "terminals": [ { "device": "XI2", "pin": "Y" }, { "device": "XD2", "pin": "D" } ], "ports": [], "voltageReferences": [] }, { "id": "q2", "ground": false, "terminals": [ { "device": "XD2", "pin": "Q" }, { "device": "XH1", "pin": "A" }, { "device": "XH2", "pin": "B_N" } ], "ports": [], "voltageReferences": [] }, { "id": "s3", "ground": false, "terminals": [ { "device": "XMT3", "pin": "d" }, { "device": "XMR3", "pin": "s" }, { "device": "XMV3", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x3", "ground": false, "terminals": [ { "device": "XMR3", "pin": "d" }, { "device": "XML3", "pin": "d" }, { "device": "XML3", "pin": "g" }, { "device": "XMO3", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o3", "ground": false, "terminals": [ { "device": "XMV3", "pin": "d" }, { "device": "XMO3", "pin": "d" }, { "device": "XI3", "pin": "A" }, { "device": "XI3", "pin": "B" } ], "ports": [], "voltageReferences": [] }, { "id": "t3", "ground": false, "terminals": [ { "device": "XI3", "pin": "Y" }, { "device": "XD3", "pin": "D" } ], "ports": [], "voltageReferences": [] }, { "id": "q3", "ground": false, "terminals": [ { "device": "XD3", "pin": "Q" }, { "device": "XH2", "pin": "A" }, { "device": "XH3", "pin": "B_N" } ], "ports": [], "voltageReferences": [] }, { "id": "s4", "ground": false, "terminals": [ { "device": "XMT4", "pin": "d" }, { "device": "XMR4", "pin": "s" }, { "device": "XMV4", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x4", "ground": false, "terminals": [ { "device": "XMR4", "pin": "d" }, { "device": "XML4", "pin": "d" }, { "device": "XML4", "pin": "g" }, { "device": "XMO4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o4", "ground": false, "terminals": [ { "device": "XMV4", "pin": "d" }, { "device": "XMO4", "pin": "d" }, { "device": "XI4", "pin": "A" }, { "device": "XI4", "pin": "B" } ], "ports": [], "voltageReferences": [] }, { "id": "t4", "ground": false, "terminals": [ { "device": "XI4", "pin": "Y" }, { "device": "XD4", "pin": "D" } ], "ports": [], "voltageReferences": [] }, { "id": "q4", "ground": false, "terminals": [ { "device": "XD4", "pin": "Q" }, { "device": "XH3", "pin": "A" }, { "device": "XH4", "pin": "B_N" } ], "ports": [], "voltageReferences": [] }, { "id": "s5", "ground": false, "terminals": [ { "device": "XMT5", "pin": "d" }, { "device": "XMR5", "pin": "s" }, { "device": "XMV5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x5", "ground": false, "terminals": [ { "device": "XMR5", "pin": "d" }, { "device": "XML5", "pin": "d" }, { "device": "XML5", "pin": "g" }, { "device": "XMO5", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o5", "ground": false, "terminals": [ { "device": "XMV5", "pin": "d" }, { "device": "XMO5", "pin": "d" }, { "device": "XI5", "pin": "A" }, { "device": "XI5", "pin": "B" } ], "ports": [], "voltageReferences": [] }, { "id": "t5", "ground": false, "terminals": [ { "device": "XI5", "pin": "Y" }, { "device": "XD5", "pin": "D" } ], "ports": [], "voltageReferences": [] }, { "id": "q5", "ground": false, "terminals": [ { "device": "XD5", "pin": "Q" }, { "device": "XH4", "pin": "A" }, { "device": "XH5", "pin": "B_N" } ], "ports": [], "voltageReferences": [] }, { "id": "s6", "ground": false, "terminals": [ { "device": "XMT6", "pin": "d" }, { "device": "XMR6", "pin": "s" }, { "device": "XMV6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x6", "ground": false, "terminals": [ { "device": "XMR6", "pin": "d" }, { "device": "XML6", "pin": "d" }, { "device": "XML6", "pin": "g" }, { "device": "XMO6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o6", "ground": false, "terminals": [ { "device": "XMV6", "pin": "d" }, { "device": "XMO6", "pin": "d" }, { "device": "XI6", "pin": "A" }, { "device": "XI6", "pin": "B" } ], "ports": [], "voltageReferences": [] }, { "id": "t6", "ground": false, "terminals": [ { "device": "XI6", "pin": "Y" }, { "device": "XD6", "pin": "D" } ], "ports": [], "voltageReferences": [] }, { "id": "q6", "ground": false, "terminals": [ { "device": "XD6", "pin": "Q" }, { "device": "XH5", "pin": "A" }, { "device": "XH6", "pin": "B_N" } ], "ports": [], "voltageReferences": [] }, { "id": "s7", "ground": false, "terminals": [ { "device": "XMT7", "pin": "d" }, { "device": "XMR7", "pin": "s" }, { "device": "XMV7", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x7", "ground": false, "terminals": [ { "device": "XMR7", "pin": "d" }, { "device": "XML7", "pin": "d" }, { "device": "XML7", "pin": "g" }, { "device": "XMO7", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o7", "ground": false, "terminals": [ { "device": "XMV7", "pin": "d" }, { "device": "XMO7", "pin": "d" }, { "device": "XI7", "pin": "A" }, { "device": "XI7", "pin": "B" } ], "ports": [], "voltageReferences": [] }, { "id": "t7", "ground": false, "terminals": [ { "device": "XI7", "pin": "Y" }, { "device": "XD7", "pin": "D" } ], "ports": [], "voltageReferences": [] }, { "id": "q7", "ground": false, "terminals": [ { "device": "XD7", "pin": "Q" }, { "device": "XH6", "pin": "A" }, { "device": "XE0", "pin": "D" }, { "device": "XE1", "pin": "D" }, { "device": "XE2", "pin": "D" } ], "ports": [], "voltageReferences": [] }, { "id": "h1", "ground": false, "terminals": [ { "device": "XH1", "pin": "Y" }, { "device": "XE0", "pin": "A" } ], "ports": [], "voltageReferences": [] }, { "id": "h2", "ground": false, "terminals": [ { "device": "XH2", "pin": "Y" }, { "device": "XE1", "pin": "A" } ], "ports": [], "voltageReferences": [] }, { "id": "h3", "ground": false, "terminals": [ { "device": "XH3", "pin": "Y" }, { "device": "XE0", "pin": "B" }, { "device": "XE1", "pin": "B" } ], "ports": [], "voltageReferences": [] }, { "id": "h4", "ground": false, "terminals": [ { "device": "XH4", "pin": "Y" }, { "device": "XE2", "pin": "A" } ], "ports": [], "voltageReferences": [] }, { "id": "h5", "ground": false, "terminals": [ { "device": "XH5", "pin": "Y" }, { "device": "XE0", "pin": "C" }, { "device": "XE2", "pin": "B" } ], "ports": [], "voltageReferences": [] }, { "id": "h6", "ground": false, "terminals": [ { "device": "XH6", "pin": "Y" }, { "device": "XE1", "pin": "C" }, { "device": "XE2", "pin": "C" } ], "ports": [], "voltageReferences": [] }, { "id": "b0", "ground": false, "terminals": [ { "device": "XE0", "pin": "X" } ], "ports": [ "b0" ], "voltageReferences": [] }, { "id": "b1", "ground": false, "terminals": [ { "device": "XE1", "pin": "X" } ], "ports": [ "b1" ], "voltageReferences": [] }, { "id": "b2", "ground": false, "terminals": [ { "device": "XE2", "pin": "X" } ], "ports": [ "b2" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "1.2", "source": "Vdd vdd 0 1.2", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vrp", "displayName": "Vrp", "spiceType": "V", "model": null, "parametersOrValue": "900m", "source": "Vrp vrp 0 900m", "pins": [ { "id": "p", "net": "vrp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vrn", "displayName": "Vrn", "spiceType": "V", "model": null, "parametersOrValue": "300m", "source": "Vrn vrn 0 300m", "pins": [ { "id": "p", "net": "vrn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib vdd bn 10u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "bn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclk", "displayName": "Vclk", "spiceType": "V", "model": null, "parametersOrValue": "1.2", "source": "Vclk clk 0 1.2", "pins": [ { "id": "p", "net": "clk" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vin vin 0 0", "pins": [ { "id": "p", "net": "vin" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "XRL8", "displayName": "RL8", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL8 vrp tap7 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "vrp" }, { "id": "n", "net": "tap7" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL7", "displayName": "RL7", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL7 tap7 tap6 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap7" }, { "id": "n", "net": "tap6" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL6", "displayName": "RL6", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL6 tap6 tap5 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap6" }, { "id": "n", "net": "tap5" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL5", "displayName": "RL5", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL5 tap5 tap4 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap5" }, { "id": "n", "net": "tap4" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL4", "displayName": "RL4", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL4 tap4 tap3 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap4" }, { "id": "n", "net": "tap3" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL3", "displayName": "RL3", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL3 tap3 tap2 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap3" }, { "id": "n", "net": "tap2" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL2", "displayName": "RL2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL2 tap2 tap1 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap2" }, { "id": "n", "net": "tap1" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL1", "displayName": "RL1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL1 tap1 vrn 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap1" }, { "id": "n", "net": "vrn" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMB bn bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "bn" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT1", "displayName": "MT1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT1 s1 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s1" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR1", "displayName": "MR1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR1 x1 tap1 s1 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "tap1" }, { "id": "s", "net": "s1" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMV1", "displayName": "MV1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMV1 o1 vin s1 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vin" }, { "id": "s", "net": "s1" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML1", "displayName": "ML1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XML1 x1 x1 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO1", "displayName": "MO1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMO1 o1 x1 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XI1", "displayName": "I1", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XI1 t1 o1 o1 vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "t1" }, { "id": "A", "net": "o1" }, { "id": "B", "net": "o1" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD1", "displayName": "D1", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD1 q1 t1 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q1" }, { "id": "D", "net": "t1" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMT2", "displayName": "MT2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT2 s2 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s2" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR2", "displayName": "MR2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR2 x2 tap2 s2 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "tap2" }, { "id": "s", "net": "s2" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMV2", "displayName": "MV2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMV2 o2 vin s2 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vin" }, { "id": "s", "net": "s2" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML2", "displayName": "ML2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XML2 x2 x2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "x2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO2", "displayName": "MO2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMO2 o2 x2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "x2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XI2", "displayName": "I2", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XI2 t2 o2 o2 vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "t2" }, { "id": "A", "net": "o2" }, { "id": "B", "net": "o2" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD2", "displayName": "D2", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD2 q2 t2 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q2" }, { "id": "D", "net": "t2" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMT3", "displayName": "MT3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT3 s3 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s3" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR3", "displayName": "MR3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR3 x3 tap3 s3 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x3" }, { "id": "g", "net": "tap3" }, { "id": "s", "net": "s3" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMV3", "displayName": "MV3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMV3 o3 vin s3 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o3" }, { "id": "g", "net": "vin" }, { "id": "s", "net": "s3" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML3", "displayName": "ML3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XML3 x3 x3 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x3" }, { "id": "g", "net": "x3" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO3", "displayName": "MO3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMO3 o3 x3 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o3" }, { "id": "g", "net": "x3" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XI3", "displayName": "I3", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XI3 t3 o3 o3 vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "t3" }, { "id": "A", "net": "o3" }, { "id": "B", "net": "o3" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD3", "displayName": "D3", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD3 q3 t3 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q3" }, { "id": "D", "net": "t3" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMT4", "displayName": "MT4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT4 s4 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s4" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR4", "displayName": "MR4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR4 x4 tap4 s4 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x4" }, { "id": "g", "net": "tap4" }, { "id": "s", "net": "s4" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMV4", "displayName": "MV4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMV4 o4 vin s4 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o4" }, { "id": "g", "net": "vin" }, { "id": "s", "net": "s4" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML4", "displayName": "ML4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XML4 x4 x4 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x4" }, { "id": "g", "net": "x4" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO4", "displayName": "MO4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMO4 o4 x4 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o4" }, { "id": "g", "net": "x4" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XI4", "displayName": "I4", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XI4 t4 o4 o4 vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "t4" }, { "id": "A", "net": "o4" }, { "id": "B", "net": "o4" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD4", "displayName": "D4", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD4 q4 t4 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q4" }, { "id": "D", "net": "t4" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMT5", "displayName": "MT5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT5 s5 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s5" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR5", "displayName": "MR5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR5 x5 tap5 s5 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x5" }, { "id": "g", "net": "tap5" }, { "id": "s", "net": "s5" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMV5", "displayName": "MV5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMV5 o5 vin s5 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o5" }, { "id": "g", "net": "vin" }, { "id": "s", "net": "s5" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML5", "displayName": "ML5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XML5 x5 x5 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x5" }, { "id": "g", "net": "x5" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO5", "displayName": "MO5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMO5 o5 x5 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o5" }, { "id": "g", "net": "x5" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XI5", "displayName": "I5", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XI5 t5 o5 o5 vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "t5" }, { "id": "A", "net": "o5" }, { "id": "B", "net": "o5" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD5", "displayName": "D5", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD5 q5 t5 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q5" }, { "id": "D", "net": "t5" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMT6", "displayName": "MT6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT6 s6 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s6" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR6", "displayName": "MR6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR6 x6 tap6 s6 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x6" }, { "id": "g", "net": "tap6" }, { "id": "s", "net": "s6" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMV6", "displayName": "MV6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMV6 o6 vin s6 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o6" }, { "id": "g", "net": "vin" }, { "id": "s", "net": "s6" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML6", "displayName": "ML6", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XML6 x6 x6 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x6" }, { "id": "g", "net": "x6" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO6", "displayName": "MO6", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMO6 o6 x6 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o6" }, { "id": "g", "net": "x6" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XI6", "displayName": "I6", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XI6 t6 o6 o6 vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "t6" }, { "id": "A", "net": "o6" }, { "id": "B", "net": "o6" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD6", "displayName": "D6", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD6 q6 t6 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q6" }, { "id": "D", "net": "t6" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMT7", "displayName": "MT7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT7 s7 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s7" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR7", "displayName": "MR7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR7 x7 tap7 s7 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x7" }, { "id": "g", "net": "tap7" }, { "id": "s", "net": "s7" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMV7", "displayName": "MV7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMV7 o7 vin s7 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o7" }, { "id": "g", "net": "vin" }, { "id": "s", "net": "s7" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML7", "displayName": "ML7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XML7 x7 x7 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x7" }, { "id": "g", "net": "x7" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO7", "displayName": "MO7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMO7 o7 x7 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o7" }, { "id": "g", "net": "x7" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XI7", "displayName": "I7", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XI7 t7 o7 o7 vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "t7" }, { "id": "A", "net": "o7" }, { "id": "B", "net": "o7" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD7", "displayName": "D7", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD7 q7 t7 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q7" }, { "id": "D", "net": "t7" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XH1", "displayName": "H1", "spiceType": "X", "model": "sg13g2_nor2b_1", "parametersOrValue": "", "source": "XH1 h1 q2 q1 vdd 0 sg13g2_nor2b_1", "pins": [ { "id": "Y", "net": "h1" }, { "id": "A", "net": "q2" }, { "id": "B_N", "net": "q1" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XH2", "displayName": "H2", "spiceType": "X", "model": "sg13g2_nor2b_1", "parametersOrValue": "", "source": "XH2 h2 q3 q2 vdd 0 sg13g2_nor2b_1", "pins": [ { "id": "Y", "net": "h2" }, { "id": "A", "net": "q3" }, { "id": "B_N", "net": "q2" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XH3", "displayName": "H3", "spiceType": "X", "model": "sg13g2_nor2b_1", "parametersOrValue": "", "source": "XH3 h3 q4 q3 vdd 0 sg13g2_nor2b_1", "pins": [ { "id": "Y", "net": "h3" }, { "id": "A", "net": "q4" }, { "id": "B_N", "net": "q3" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XH4", "displayName": "H4", "spiceType": "X", "model": "sg13g2_nor2b_1", "parametersOrValue": "", "source": "XH4 h4 q5 q4 vdd 0 sg13g2_nor2b_1", "pins": [ { "id": "Y", "net": "h4" }, { "id": "A", "net": "q5" }, { "id": "B_N", "net": "q4" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XH5", "displayName": "H5", "spiceType": "X", "model": "sg13g2_nor2b_1", "parametersOrValue": "", "source": "XH5 h5 q6 q5 vdd 0 sg13g2_nor2b_1", "pins": [ { "id": "Y", "net": "h5" }, { "id": "A", "net": "q6" }, { "id": "B_N", "net": "q5" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XH6", "displayName": "H6", "spiceType": "X", "model": "sg13g2_nor2b_1", "parametersOrValue": "", "source": "XH6 h6 q7 q6 vdd 0 sg13g2_nor2b_1", "pins": [ { "id": "Y", "net": "h6" }, { "id": "A", "net": "q7" }, { "id": "B_N", "net": "q6" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XE0", "displayName": "E0", "spiceType": "X", "model": "sg13g2_or4_1", "parametersOrValue": "", "source": "XE0 b0 h1 h3 h5 q7 vdd 0 sg13g2_or4_1", "pins": [ { "id": "X", "net": "b0" }, { "id": "A", "net": "h1" }, { "id": "B", "net": "h3" }, { "id": "C", "net": "h5" }, { "id": "D", "net": "q7" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XE1", "displayName": "E1", "spiceType": "X", "model": "sg13g2_or4_1", "parametersOrValue": "", "source": "XE1 b1 h2 h3 h6 q7 vdd 0 sg13g2_or4_1", "pins": [ { "id": "X", "net": "b1" }, { "id": "A", "net": "h2" }, { "id": "B", "net": "h3" }, { "id": "C", "net": "h6" }, { "id": "D", "net": "q7" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XE2", "displayName": "E2", "spiceType": "X", "model": "sg13g2_or4_1", "parametersOrValue": "", "source": "XE2 b2 h4 h5 h6 q7 vdd 0 sg13g2_or4_1", "pins": [ { "id": "X", "net": "b2" }, { "id": "A", "net": "h4" }, { "id": "B", "net": "h5" }, { "id": "C", "net": "h6" }, { "id": "D", "net": "q7" }, { "id": "VDD", "net": "vdd" }, { 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"device": "XMR2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tap1", "ground": false, "terminals": [ { "device": "XRL2", "pin": "n" }, { "device": "XRL1", "pin": "p" }, { "device": "XMR1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "s1", "ground": false, "terminals": [ { "device": "XMT1", "pin": "d" }, { "device": "XMR1", "pin": "s" }, { "device": "XMV1", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XMR1", "pin": "d" }, { "device": "XML1", "pin": "d" }, { "device": "XML1", "pin": "g" }, { "device": "XMO1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XMV1", "pin": "d" }, { "device": "XMO1", "pin": "d" }, { "device": "XI1", "pin": "A" }, { "device": "XI1", "pin": "B" } ], "ports": [], "voltageReferences": [] }, { "id": "t1", "ground": false, "terminals": [ { "device": "XI1", "pin": "Y" }, { "device": "XD1", "pin": "D" } ], "ports": [], "voltageReferences": [] }, { "id": "q1", "ground": false, "terminals": [ { "device": "XD1", "pin": "Q" }, { "device": "XH1", "pin": "B_N" } ], "ports": [], "voltageReferences": [] }, { "id": "s2", "ground": false, "terminals": [ { "device": "XMT2", "pin": "d" }, { "device": "XMR2", "pin": "s" }, { "device": "XMV2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x2", "ground": false, "terminals": [ { "device": "XMR2", "pin": "d" }, { "device": "XML2", "pin": "d" }, { "device": "XML2", "pin": "g" }, { "device": "XMO2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XMV2", "pin": "d" }, { "device": "XMO2", "pin": "d" }, { "device": "XI2", "pin": "A" }, { "device": "XI2", "pin": "B" } ], "ports": [], "voltageReferences": [] }, { "id": "t2", "ground": false, "terminals": [ { "device": "XI2", "pin": "Y" }, { "device": "XD2", "pin": "D" } ], "ports": [], "voltageReferences": [] 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"ground": false, "terminals": [ { "device": "XD3", "pin": "Q" }, { "device": "XH2", "pin": "A" }, { "device": "XH3", "pin": "B_N" } ], "ports": [], "voltageReferences": [] }, { "id": "s4", "ground": false, "terminals": [ { "device": "XMT4", "pin": "d" }, { "device": "XMR4", "pin": "s" }, { "device": "XMV4", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x4", "ground": false, "terminals": [ { "device": "XMR4", "pin": "d" }, { "device": "XML4", "pin": "d" }, { "device": "XML4", "pin": "g" }, { "device": "XMO4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o4", "ground": false, "terminals": [ { "device": "XMV4", "pin": "d" }, { "device": "XMO4", "pin": "d" }, { "device": "XI4", "pin": "A" }, { "device": "XI4", "pin": "B" } ], "ports": [], "voltageReferences": [] }, { "id": "t4", "ground": false, "terminals": [ { "device": "XI4", "pin": "Y" }, { "device": "XD4", "pin": "D" } ], "ports": [], "voltageReferences": [] }, { "id": "q4", "ground": false, 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"parametersOrValue": "10u", "source": "Ib vdd bn 10u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "bn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclk", "displayName": "Vclk", "spiceType": "V", "model": null, "parametersOrValue": "PULSE(1.2 0 10n 50p 50p 9.95n 20n)", "source": "Vclk clk 0 PULSE(1.2 0 10n 50p 50p 9.95n 20n)", "pins": [ { "id": "p", "net": "clk" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "PWL(0 337.5m 19.95n 337.5m 20n 412.5m 39.95n 412.5m 40n 487.5m 59.95n 487.5m 60n 562.5m 79.95n 562.5m 80n 637.5m 99.95n 637.5m 100n 712.5m 119.95n 712.5m 120n 787.5m 139.95n 787.5m 140n 862.5m 159.95n 862.5m)", "source": "Vin vin 0 PWL(0 337.5m 19.95n 337.5m 20n 412.5m 39.95n 412.5m 40n 487.5m 59.95n 487.5m 60n 562.5m 79.95n 562.5m 80n 637.5m 99.95n 637.5m 100n 712.5m 119.95n 712.5m 120n 787.5m 139.95n 787.5m 140n 862.5m 159.95n 862.5m)", "pins": [ { "id": "p", "net": "vin" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "XRL8", "displayName": "RL8", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL8 vrp tap7 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "vrp" }, { "id": "n", "net": "tap7" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL7", "displayName": "RL7", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL7 tap7 tap6 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap7" }, { "id": "n", "net": "tap6" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL6", "displayName": "RL6", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL6 tap6 tap5 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap6" }, { "id": "n", "net": "tap5" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL5", "displayName": "RL5", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL5 tap5 tap4 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap5" }, { "id": "n", "net": "tap4" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL4", "displayName": "RL4", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL4 tap4 tap3 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap4" }, { "id": "n", "net": "tap3" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL3", "displayName": "RL3", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL3 tap3 tap2 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap3" }, { "id": "n", "net": "tap2" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL2", "displayName": "RL2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL2 tap2 tap1 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap2" }, { "id": "n", "net": "tap1" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRL1", "displayName": "RL1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=9.57u", "source": "XRL1 tap1 vrn 0 rppd w=0.5u l=9.57u", "pins": [ { "id": "p", "net": "tap1" }, { "id": "n", "net": "vrn" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMB bn bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "bn" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT1", "displayName": "MT1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT1 s1 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s1" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR1", "displayName": "MR1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR1 x1 tap1 s1 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "tap1" }, { "id": "s", "net": "s1" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMV1", "displayName": "MV1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMV1 o1 vin s1 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vin" }, { "id": "s", "net": "s1" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML1", "displayName": "ML1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XML1 x1 x1 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO1", "displayName": "MO1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMO1 o1 x1 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XI1", "displayName": "I1", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XI1 t1 o1 o1 vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "t1" }, { "id": "A", "net": "o1" }, { "id": "B", "net": "o1" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD1", "displayName": "D1", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD1 q1 t1 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q1" }, { "id": "D", "net": "t1" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMT2", "displayName": "MT2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT2 s2 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s2" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR2", "displayName": "MR2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR2 x2 tap2 s2 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "tap2" }, { "id": "s", "net": "s2" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMV2", "displayName": "MV2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMV2 o2 vin s2 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vin" }, { "id": "s", "net": "s2" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML2", "displayName": "ML2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XML2 x2 x2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "x2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO2", "displayName": "MO2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMO2 o2 x2 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "x2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XI2", "displayName": "I2", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XI2 t2 o2 o2 vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "t2" }, { "id": "A", "net": "o2" }, { "id": "B", "net": "o2" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD2", "displayName": "D2", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD2 q2 t2 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q2" }, { "id": "D", "net": "t2" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMT3", "displayName": "MT3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT3 s3 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s3" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR3", "displayName": "MR3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR3 x3 tap3 s3 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x3" }, { "id": "g", "net": "tap3" }, { "id": "s", "net": "s3" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMV3", "displayName": "MV3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMV3 o3 vin s3 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o3" }, { "id": "g", "net": "vin" }, { "id": "s", "net": "s3" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML3", "displayName": "ML3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XML3 x3 x3 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x3" }, { "id": "g", "net": "x3" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO3", "displayName": "MO3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMO3 o3 x3 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o3" }, { "id": "g", "net": "x3" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XI3", "displayName": "I3", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XI3 t3 o3 o3 vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "t3" }, { "id": "A", "net": "o3" }, { "id": "B", "net": "o3" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD3", "displayName": "D3", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD3 q3 t3 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q3" }, { "id": "D", "net": "t3" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMT4", "displayName": "MT4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT4 s4 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s4" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR4", "displayName": "MR4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR4 x4 tap4 s4 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x4" }, { "id": "g", "net": "tap4" }, { "id": "s", "net": "s4" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMV4", "displayName": "MV4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMV4 o4 vin s4 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o4" }, { "id": "g", "net": "vin" }, { "id": "s", "net": "s4" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML4", "displayName": "ML4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XML4 x4 x4 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x4" }, { "id": "g", "net": "x4" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO4", "displayName": "MO4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMO4 o4 x4 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o4" }, { "id": "g", "net": "x4" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XI4", "displayName": "I4", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XI4 t4 o4 o4 vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "t4" }, { "id": "A", "net": "o4" }, { "id": "B", "net": "o4" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD4", "displayName": "D4", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD4 q4 t4 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q4" }, { "id": "D", "net": "t4" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMT5", "displayName": "MT5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT5 s5 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s5" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR5", "displayName": "MR5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR5 x5 tap5 s5 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x5" }, { "id": "g", "net": "tap5" }, { "id": "s", "net": "s5" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMV5", "displayName": "MV5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMV5 o5 vin s5 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o5" }, { "id": "g", "net": "vin" }, { "id": "s", "net": "s5" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML5", "displayName": "ML5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XML5 x5 x5 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x5" }, { "id": "g", "net": "x5" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO5", "displayName": "MO5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMO5 o5 x5 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o5" }, { "id": "g", "net": "x5" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XI5", "displayName": "I5", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XI5 t5 o5 o5 vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "t5" }, { "id": "A", "net": "o5" }, { "id": "B", "net": "o5" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD5", "displayName": "D5", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD5 q5 t5 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q5" }, { "id": "D", "net": "t5" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMT6", "displayName": "MT6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT6 s6 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s6" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR6", "displayName": "MR6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR6 x6 tap6 s6 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x6" }, { "id": "g", "net": "tap6" }, { "id": "s", "net": "s6" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMV6", "displayName": "MV6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMV6 o6 vin s6 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o6" }, { "id": "g", "net": "vin" }, { "id": "s", "net": "s6" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML6", "displayName": "ML6", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XML6 x6 x6 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x6" }, { "id": "g", "net": "x6" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO6", "displayName": "MO6", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMO6 o6 x6 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o6" }, { "id": "g", "net": "x6" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XI6", "displayName": "I6", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XI6 t6 o6 o6 vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "t6" }, { "id": "A", "net": "o6" }, { "id": "B", "net": "o6" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD6", "displayName": "D6", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD6 q6 t6 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q6" }, { "id": "D", "net": "t6" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMT7", "displayName": "MT7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMT7 s7 bn 0 0 sg13_lv_nmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "s7" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR7", "displayName": "MR7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMR7 x7 tap7 s7 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x7" }, { "id": "g", "net": "tap7" }, { "id": "s", "net": "s7" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMV7", "displayName": "MV7", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMV7 o7 vin s7 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o7" }, { "id": "g", "net": "vin" }, { "id": "s", "net": "s7" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XML7", "displayName": "ML7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XML7 x7 x7 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "x7" }, { "id": "g", "net": "x7" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO7", "displayName": "MO7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMO7 o7 x7 vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "o7" }, { "id": "g", "net": "x7" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XI7", "displayName": "I7", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XI7 t7 o7 o7 vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "t7" }, { "id": "A", "net": "o7" }, { "id": "B", "net": "o7" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XD7", "displayName": "D7", "spiceType": "X", "model": "sg13g2_dlhq_1", "parametersOrValue": "", "source": "XD7 q7 t7 clk vdd 0 sg13g2_dlhq_1", "pins": [ { "id": "Q", "net": "q7" }, { "id": "D", "net": "t7" }, { "id": "GATE", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XH1", "displayName": "H1", "spiceType": "X", "model": "sg13g2_nor2b_1", "parametersOrValue": "", "source": "XH1 h1 q2 q1 vdd 0 sg13g2_nor2b_1", "pins": [ { "id": "Y", "net": "h1" }, { "id": "A", "net": "q2" }, { "id": "B_N", "net": "q1" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XH2", "displayName": "H2", "spiceType": "X", "model": "sg13g2_nor2b_1", "parametersOrValue": "", "source": "XH2 h2 q3 q2 vdd 0 sg13g2_nor2b_1", "pins": [ { "id": "Y", "net": "h2" }, { "id": "A", "net": "q3" }, { "id": "B_N", "net": "q2" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XH3", "displayName": "H3", "spiceType": "X", "model": "sg13g2_nor2b_1", "parametersOrValue": "", "source": "XH3 h3 q4 q3 vdd 0 sg13g2_nor2b_1", "pins": [ { "id": "Y", "net": "h3" }, { "id": "A", "net": "q4" }, { "id": "B_N", "net": "q3" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XH4", "displayName": "H4", "spiceType": "X", "model": "sg13g2_nor2b_1", "parametersOrValue": "", "source": "XH4 h4 q5 q4 vdd 0 sg13g2_nor2b_1", "pins": [ { "id": "Y", "net": "h4" }, { "id": "A", "net": "q5" }, { "id": "B_N", "net": "q4" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XH5", "displayName": "H5", "spiceType": "X", "model": "sg13g2_nor2b_1", "parametersOrValue": "", "source": "XH5 h5 q6 q5 vdd 0 sg13g2_nor2b_1", "pins": [ { "id": "Y", "net": "h5" }, { "id": "A", "net": "q6" }, { "id": "B_N", "net": "q5" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XH6", "displayName": "H6", "spiceType": "X", "model": "sg13g2_nor2b_1", "parametersOrValue": "", "source": "XH6 h6 q7 q6 vdd 0 sg13g2_nor2b_1", "pins": [ { "id": "Y", "net": "h6" }, { "id": "A", "net": "q7" }, { "id": "B_N", "net": "q6" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XE0", "displayName": "E0", "spiceType": "X", "model": "sg13g2_or4_1", "parametersOrValue": "", "source": "XE0 b0 h1 h3 h5 q7 vdd 0 sg13g2_or4_1", "pins": [ { "id": "X", "net": "b0" }, { "id": "A", "net": "h1" }, { "id": "B", "net": "h3" }, { "id": "C", "net": "h5" }, { "id": "D", "net": "q7" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XE1", "displayName": "E1", "spiceType": "X", "model": "sg13g2_or4_1", "parametersOrValue": "", "source": "XE1 b1 h2 h3 h6 q7 vdd 0 sg13g2_or4_1", "pins": [ { "id": "X", "net": "b1" }, { "id": "A", "net": "h2" }, { "id": "B", "net": "h3" }, { "id": "C", "net": "h6" }, { "id": "D", "net": "q7" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XE2", "displayName": "E2", "spiceType": "X", "model": "sg13g2_or4_1", "parametersOrValue": "", "source": "XE2 b2 h4 h5 h6 q7 vdd 0 sg13g2_or4_1", "pins": [ { "id": "X", "net": "b2" }, { "id": "A", "net": "h4" }, { "id": "B", "net": "h5" }, { "id": "C", "net": "h6" }, { "id": "D", "net": "q7" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "XML1", "pin": "s" }, { "device": "XML1", "pin": "b" }, { "device": "XMO1", "pin": "s" }, { "device": "XMO1", "pin": "b" }, { "device": "XI1", "pin": "VDD" }, { "device": "XD1", "pin": "VDD" }, { "device": "XML2", "pin": "s" }, { "device": "XML2", "pin": "b" }, { "device": "XMO2", "pin": "s" }, { "device": "XMO2", "pin": "b" }, { "device": "XI2", "pin": "VDD" }, { "device": "XD2", "pin": "VDD" }, { "device": "XML3", "pin": "s" }, { "device": "XML3", "pin": "b" }, { "device": "XMO3", "pin": "s" }, { "device": "XMO3", "pin": "b" }, { "device": "XI3", "pin": "VDD" }, { "device": "XD3", "pin": "VDD" }, { "device": "XML4", "pin": "s" }, { "device": "XML4", "pin": "b" }, { "device": "XMO4", "pin": "s" }, { "device": "XMO4", "pin": "b" }, { "device": "XI4", "pin": "VDD" }, { "device": "XD4", "pin": "VDD" }, { "device": "XML5", "pin": "s" }, { "device": "XML5", "pin": "b" }, { "device": "XMO5", "pin": "s" }, { "device": "XMO5", "pin": "b" }, { "device": "XI5", "pin": "VDD" }, { "device": "XD5", "pin": "VDD" }, { "device": "XML6", "pin": "s" }, { "device": "XML6", "pin": "b" }, { "device": "XMO6", "pin": "s" }, { "device": "XMO6", "pin": "b" }, { "device": "XI6", "pin": "VDD" }, { "device": "XD6", "pin": "VDD" }, { "device": "XML7", "pin": "s" }, { "device": "XML7", "pin": "b" }, { "device": "XMO7", "pin": "s" }, { "device": "XMO7", "pin": "b" }, { "device": "XI7", "pin": "VDD" }, { "device": "XD7", "pin": "VDD" }, { "device": "XH1", "pin": "VDD" }, { "device": "XH2", "pin": "VDD" }, { "device": "XH3", "pin": "VDD" }, { "device": "XH4", "pin": "VDD" }, { "device": "XH5", "pin": "VDD" }, { "device": "XH6", "pin": "VDD" }, { "device": "XE0", "pin": "VDD" }, { "device": "XE1", "pin": "VDD" }, { "device": "XE2", "pin": "VDD" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vrp", "pin": "n" }, { "device": "Vrn", "pin": "n" }, { "device": "Vclk", "pin": "n" }, { "device": "Vin", "pin": "n" }, { "device": "XRL8", "pin": "substrate" }, { "device": "XRL7", "pin": "substrate" }, { "device": "XRL6", "pin": "substrate" }, { "device": "XRL5", "pin": "substrate" }, { "device": "XRL4", "pin": "substrate" }, { "device": "XRL3", "pin": "substrate" }, { "device": "XRL2", "pin": "substrate" }, { "device": "XRL1", "pin": "substrate" }, { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT1", "pin": "s" }, { "device": "XMT1", "pin": "b" }, { "device": "XMR1", "pin": "b" }, { "device": "XMV1", "pin": "b" }, { "device": "XI1", "pin": "VSS" }, { "device": "XD1", "pin": "VSS" }, { "device": "XMT2", "pin": "s" }, { "device": "XMT2", "pin": "b" }, { "device": "XMR2", "pin": "b" }, { "device": "XMV2", "pin": "b" }, { "device": "XI2", "pin": "VSS" }, { "device": "XD2", "pin": "VSS" }, { "device": "XMT3", "pin": "s" }, { "device": "XMT3", "pin": "b" }, { "device": "XMR3", "pin": "b" }, { "device": "XMV3", "pin": "b" }, { "device": "XI3", "pin": "VSS" }, { "device": "XD3", "pin": "VSS" }, { "device": "XMT4", "pin": "s" }, { "device": "XMT4", "pin": "b" }, { "device": "XMR4", "pin": "b" }, { "device": "XMV4", "pin": "b" }, { "device": "XI4", "pin": "VSS" }, { "device": "XD4", "pin": "VSS" }, { "device": "XMT5", "pin": "s" }, { "device": "XMT5", "pin": "b" }, { "device": "XMR5", "pin": "b" }, { "device": "XMV5", "pin": "b" }, { "device": "XI5", "pin": "VSS" }, { "device": "XD5", "pin": "VSS" }, { "device": "XMT6", "pin": "s" }, { "device": "XMT6", "pin": "b" }, { "device": "XMR6", "pin": "b" }, { "device": "XMV6", "pin": "b" }, { "device": "XI6", "pin": "VSS" }, { "device": "XD6", "pin": "VSS" }, { "device": "XMT7", "pin": "s" }, { "device": "XMT7", "pin": "b" }, { "device": "XMR7", "pin": "b" }, { "device": "XMV7", "pin": "b" }, { "device": "XI7", "pin": "VSS" }, { "device": "XD7", "pin": "VSS" }, { "device": "XH1", "pin": "VSS" }, { "device": "XH2", "pin": "VSS" }, { "device": "XH3", "pin": "VSS" }, { "device": "XH4", "pin": "VSS" }, { "device": "XH5", "pin": "VSS" }, { "device": "XH6", "pin": "VSS" }, { "device": "XE0", "pin": "VSS" }, { "device": "XE1", "pin": "VSS" }, { "device": "XE2", "pin": "VSS" } ], "ports": [], "voltageReferences": [] }, { "id": "vrp", "ground": false, "terminals": [ { "device": "Vrp", "pin": "p" }, { "device": "XRL8", "pin": "p" } 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