{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ia-chopper-cc", "name": "Capacitively coupled chopper instrumentation amplifier", "group": "Fully differential", "subgroup": "Instrumentation amplifiers", "title": "Capacitively coupled chopper IA", "summary": "This amplifier measures small, slowly changing voltage differences. Clocked switches move the signal away from low-frequency offset and noise, then move it back after amplification. A capacitor ratio sets the gain, while another capacitor limits the remaining chopping ripple at the output.", "reference": { "kind": "paper", "authors": "Q. Fan, F. Sebastiano, J. H. Huijsing, K. A. A. Makinwa", "title": "A 1.8 uW 60 nV/sqrt(Hz) Capacitively-Coupled Chopper Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor Nodes", "year": 2011, "where": "IEEE Journal of Solid-State Circuits, 46(7):1534-1543", "doi": "10.1109/JSSC.2011.2143610", "takes": "The capacitively coupled chopper amplifier: input and feedback choppers around input and feedback capacitors, the OTA's output chopper between its stages. Ours: the common-mode loop around both stages, and the servo capacitor - a capacitor before a chopper rather than after it - which bounds the moved offset where the paper removes it with a ripple-reduction loop. The sizing is this library's, for SG13G2 at 1.2 V." }, "resources": { "record": "/circuits/ia-chopper-cc.json", "page": "/index.html#ia-chopper-cc", "achieved": "/achieved/ia-chopper-cc.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "inp", "kind": "input" }, { "name": "inn", "kind": "input" }, { "name": "outp", "kind": "output" }, { "name": "outn", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the reference current, drawn out of this pin" }, { "name": "vocm", "kind": "bias", "note": "the output common mode" }, { "name": "vicm", "kind": "bias", "note": "the summing nodes' level, the input pair's common mode" }, { "name": "clk", "kind": "clock", "note": "high: every chopper straight" }, { "name": "clkb", "kind": "clock", "note": "high: every chopper crossed" } ], "devices": [ { "name": "SI1n", "type": "nmos", "nodes": "inp clk xp vss", "sizedBy": [ "Wsi", "Lsi" ], "role": "input chopper, straight while clk is high (NMOS half)", "fingers": 1, "copies": 1 }, { "name": "SI1p", "type": "pmos", "nodes": "inp clkb xp vdd", "sizedBy": [ "Wsi", "Lsi" ], "role": "input chopper, straight while clk is high (PMOS half, twice the NMOS width)", "fingers": 1, "copies": 1 }, { "name": "SI2n", "type": "nmos", "nodes": "inn clk xn vss", "sizedBy": [ "Wsi", "Lsi" ], "role": "input chopper, straight while clk is high (NMOS half)", "fingers": 1, "copies": 1 }, { "name": "SI2p", "type": "pmos", "nodes": "inn clkb xn vdd", "sizedBy": [ "Wsi", "Lsi" ], "role": "input chopper, straight while clk is high (PMOS half, twice the NMOS width)", "fingers": 1, "copies": 1 }, { "name": "SI3n", "type": "nmos", "nodes": "inp clkb xn vss", "sizedBy": [ "Wsi", "Lsi" ], "role": "input chopper, crossed while clkb is high (NMOS half)", "fingers": 1, "copies": 1 }, { "name": "SI3p", "type": "pmos", "nodes": "inp clk xn vdd", "sizedBy": [ "Wsi", "Lsi" ], "role": "input chopper, crossed while clkb is high (PMOS half, twice the NMOS width)", "fingers": 1, "copies": 1 }, { "name": "SI4n", "type": "nmos", "nodes": "inn clkb xp vss", "sizedBy": [ "Wsi", "Lsi" ], "role": "input chopper, crossed while clkb is high (NMOS half)", "fingers": 1, "copies": 1 }, { "name": "SI4p", "type": "pmos", "nodes": "inn clk xp vdd", "sizedBy": [ "Wsi", "Lsi" ], "role": "input chopper, crossed while clkb is high (PMOS half, twice the NMOS width)", "fingers": 1, "copies": 1 }, { "name": "CI1", "type": "capacitor", "nodes": "xp sp", "sizedBy": [ "Cin" ], "role": "input capacitor" }, { "name": "CI2", "type": "capacitor", "nodes": "xn sn", "sizedBy": [ "Cin" ], "role": "input capacitor" }, { "name": "RB1", "type": "resistor", "nodes": "sp vicm", "sizedBy": [ "Rb" ], "role": "summing-node bias, to vicm" }, { "name": "RB2", "type": "resistor", "nodes": "sn vicm", "sizedBy": [ "Rb" ], "role": "summing-node bias, to vicm" }, { "name": "SF1n", "type": "nmos", "nodes": "outp clk yp vss", "sizedBy": [ "Wsf", "Lsi" ], "role": "feedback chopper, straight while clk is high (NMOS half)", "fingers": 1, "copies": 1 }, { "name": "SF1p", "type": "pmos", "nodes": "outp clkb yp vdd", "sizedBy": [ "Wsf", "Lsi" ], "role": "feedback chopper, straight while clk is high (PMOS half, twice the NMOS width)", "fingers": 1, "copies": 1 }, { "name": "SF2n", "type": "nmos", "nodes": "outn clk yn vss", "sizedBy": [ "Wsf", "Lsi" ], "role": "feedback chopper, straight while clk is high (NMOS half)", "fingers": 1, "copies": 1 }, { "name": "SF2p", "type": "pmos", "nodes": "outn clkb yn vdd", "sizedBy": [ "Wsf", "Lsi" ], "role": "feedback chopper, straight while clk is high (PMOS half, twice the NMOS width)", "fingers": 1, "copies": 1 }, { "name": "SF3n", "type": "nmos", "nodes": "outp clkb yn vss", "sizedBy": [ "Wsf", "Lsi" ], "role": "feedback chopper, crossed while clkb is high (NMOS half)", "fingers": 1, "copies": 1 }, { "name": "SF3p", "type": "pmos", "nodes": "outp clk yn vdd", "sizedBy": [ "Wsf", "Lsi" ], "role": "feedback chopper, crossed while clkb is high (PMOS half, twice the NMOS width)", "fingers": 1, "copies": 1 }, { "name": "SF4n", "type": "nmos", "nodes": "outn clkb yp vss", "sizedBy": [ "Wsf", "Lsi" ], "role": "feedback chopper, crossed while clkb is high (NMOS half)", "fingers": 1, "copies": 1 }, { "name": "SF4p", "type": "pmos", "nodes": "outn clk yp vdd", "sizedBy": [ "Wsf", "Lsi" ], "role": "feedback chopper, crossed while clkb is high (PMOS half, twice the NMOS width)", "fingers": 1, "copies": 1 }, { "name": "CF1", "type": "capacitor", "nodes": "yp sn", "sizedBy": [ "Cfb" ], "role": "feedback capacitor, crosswise" }, { "name": "CF2", "type": "capacitor", "nodes": "yn sp", "sizedBy": [ "Cfb" ], "role": "feedback capacitor, crosswise" }, { "name": "CS1", "type": "capacitor", "nodes": "outp wp", "sizedBy": [ "Cs" ], "role": "servo capacitor, before its chopper" }, { "name": "CS2", "type": "capacitor", "nodes": "outn wn", "sizedBy": [ "Cs" ], "role": "servo capacitor, before its chopper" }, { "name": "SS1", "type": "nmos", "nodes": "wp clk sn vss", "sizedBy": [ "Wss", "Lsi" ], "role": "servo chopper, straight while clk is high", "fingers": 1, "copies": 1 }, { "name": "SS2", "type": "nmos", "nodes": "wn clk sp vss", "sizedBy": [ "Wss", "Lsi" ], "role": "servo chopper, straight while clk is high", "fingers": 1, "copies": 1 }, { "name": "SS3", "type": "nmos", "nodes": "wp clkb sp vss", "sizedBy": [ "Wss", "Lsi" ], "role": "servo chopper, crossed while clkb is high", "fingers": 1, "copies": 1 }, { "name": "SS4", "type": "nmos", "nodes": "wn clkb sn vss", "sizedBy": [ "Wss", "Lsi" ], "role": "servo chopper, crossed while clkb is high", "fingers": 1, "copies": 1 }, { "name": "MB", "type": "pmos", "nodes": "ib ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "bias reference, diode-connected: Ib flows out of pin ib through it", "fingers": 2, "copies": 1 }, { "name": "MB1", "type": "pmos", "nodes": "nb ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "bias, a copy of Ib into the NMOS reference", "fingers": 2, "copies": 1 }, { "name": "MB2", "type": "nmos", "nodes": "nb nb vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "bias, the NMOS reference diode", "fingers": 2, "copies": 1 }, { "name": "MB3", "type": "pmos", "nodes": "vcp vcp vdd vdd", "sizedBy": [ "Wdp", "Ldp" ], "role": "bias, long diode setting the PMOS cascode gate", "fingers": 1, "copies": 1 }, { "name": "MB4", "type": "nmos", "nodes": "vcp nb vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "bias, the current through MB3", "fingers": 2, "copies": 1 }, { "name": "MB5", "type": "pmos", "nodes": "vcn ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "bias, the current through MB6", "fingers": 2, "copies": 1 }, { "name": "MB6", "type": "nmos", "nodes": "vcn vcn vss vss", "sizedBy": [ "Wdn", "Ldn" ], "role": "bias, long diode setting the NMOS cascode gate", "fingers": 1, "copies": 1 }, { "name": "MT", "type": "pmos", "nodes": "tail ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "tail current source, two copies of MB", "fingers": 2, "copies": 2 }, { "name": "M1", "type": "pmos", "nodes": "f1 sp tail vdd", "sizedBy": [ "W1", "L1" ], "role": "input pair, non-inverting side", "fingers": 4, "copies": 1 }, { "name": "M2", "type": "pmos", "nodes": "f2 sn tail vdd", "sizedBy": [ "W1", "L1" ], "role": "input pair, inverting side", "fingers": 4, "copies": 1 }, { "name": "M3", "type": "nmos", "nodes": "f1 nb vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "fold current sink, two NMOS units", "fingers": 2, "copies": 2 }, { "name": "M4", "type": "nmos", "nodes": "f2 nb vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "fold current sink, two NMOS units", "fingers": 2, "copies": 2 }, { "name": "M5", "type": "nmos", "nodes": "o1 vcn f1 vss", "sizedBy": [ "Wcn", "Lcn" ], "role": "NMOS cascode", "fingers": 2, "copies": 1 }, { "name": "M6", "type": "nmos", "nodes": "o2 vcn f2 vss", "sizedBy": [ "Wcn", "Lcn" ], "role": "NMOS cascode", "fingers": 2, "copies": 1 }, { "name": "M7", "type": "pmos", "nodes": "k1 vbl vdd vdd", "sizedBy": [ "Wl", "Ll" ], "role": "first-stage load, its gate the common-mode control", "fingers": 4, "copies": 1 }, { "name": "M8", "type": "pmos", "nodes": "k2 vbl vdd vdd", "sizedBy": [ "Wl", "Ll" ], "role": "first-stage load, its gate the common-mode control", "fingers": 4, "copies": 1 }, { "name": "M9", "type": "pmos", "nodes": "o1 vcp k1 vdd", "sizedBy": [ "Wcp", "Lcp" ], "role": "PMOS cascode", "fingers": 2, "copies": 1 }, { "name": "M10", "type": "pmos", "nodes": "o2 vcp k2 vdd", "sizedBy": [ "Wcp", "Lcp" ], "role": "PMOS cascode", "fingers": 2, "copies": 1 }, { "name": "SO1", "type": "nmos", "nodes": "o1 clk g1 vss", "sizedBy": [ "Wso", "Lso" ], "role": "output chopper, straight while clk is high", "fingers": 1, "copies": 1 }, { "name": "SO2", "type": "nmos", "nodes": "o2 clk g2 vss", "sizedBy": [ "Wso", "Lso" ], "role": "output chopper, straight while clk is high", "fingers": 1, "copies": 1 }, { "name": "SO3", "type": "nmos", "nodes": "o1 clkb g2 vss", "sizedBy": [ "Wso", "Lso" ], "role": "output chopper, crossed while clkb is high", "fingers": 1, "copies": 1 }, { "name": "SO4", "type": "nmos", "nodes": "o2 clkb g1 vss", "sizedBy": [ "Wso", "Lso" ], "role": "output chopper, crossed while clkb is high", "fingers": 1, "copies": 1 }, { "name": "M11", "type": "nmos", "nodes": "outp g1 vss vss", "sizedBy": [ "W2", "L2", "N2" ], "role": "second stage, common source; N2 copies of its unit", "fingers": 1, "copies": 4 }, { "name": "M12", "type": "nmos", "nodes": "outn g2 vss vss", "sizedBy": [ "W2", "L2", "N2" ], "role": "second stage, common source; N2 copies of its unit", "fingers": 1, "copies": 4 }, { "name": "M13", "type": "pmos", "nodes": "outp ib vdd vdd", "sizedBy": [ "Wp", "Lp", "N2" ], "role": "second-stage current source, N2 copies of MB", "fingers": 2, "copies": 4 }, { "name": "M14", "type": "pmos", "nodes": "outn ib vdd vdd", "sizedBy": [ "Wp", "Lp", "N2" ], "role": "second-stage current source, N2 copies of MB", "fingers": 2, "copies": 4 }, { "name": "CC1", "type": "capacitor", "nodes": "g1 z1", "sizedBy": [ "Cc" ], "role": "Miller compensation" }, { "name": "CC2", "type": "capacitor", "nodes": "g2 z2", "sizedBy": [ "Cc" ], "role": "Miller compensation" }, { "name": "RZ1", "type": "resistor", "nodes": "z1 outp", "sizedBy": [ "Rz" ], "role": "nulling resistor" }, { "name": "RZ2", "type": "resistor", "nodes": "z2 outn", "sizedBy": [ "Rz" ], "role": "nulling resistor" }, { "name": "RM1", "type": "resistor", "nodes": "outp cms", "sizedBy": [ "Rm" ], "role": "common-mode sense: the outputs averaged on cms" }, { "name": "RM2", "type": "resistor", "nodes": "outn cms", "sizedBy": [ "Rm" ], "role": "common-mode sense: the outputs averaged on cms" }, { "name": "CM1", "type": "capacitor", "nodes": "outp cms", "sizedBy": [ "Cm" ], "role": "common-mode sense, carries the average at high frequency" }, { "name": "CM2", "type": "capacitor", "nodes": "outn cms", "sizedBy": [ "Cm" ], "role": "common-mode sense, carries the average at high frequency" }, { "name": "MC1", "type": "nmos", "nodes": "vbl cms ct vss", "sizedBy": [ "Wc", "Lc" ], "role": "CMFB pair, sensing the output common mode", "fingers": 2, "copies": 1 }, { "name": "MC2", "type": "nmos", "nodes": "cx vocm ct vss", "sizedBy": [ "Wc", "Lc" ], "role": "CMFB pair, the reference side", "fingers": 2, "copies": 1 }, { "name": "MC3", "type": "nmos", "nodes": "ct nb vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "CMFB tail, two NMOS units", "fingers": 2, "copies": 2 }, { "name": "MC4", "type": "pmos", "nodes": "vbl vbl vdd vdd", "sizedBy": [ "Wl", "Ll" ], "role": "CMFB load diode; M7 and M8 copy its current", "fingers": 4, "copies": 1 }, { "name": "MC5", "type": "pmos", "nodes": "cx cx vdd vdd", "sizedBy": [ "Wl", "Ll" ], "role": "CMFB load diode, reference side", "fingers": 4, "copies": 1 } ], "intent": [ { "rule": "ratio", "of": [ "CI1", "CF1", "CI2", "CF2" ], "constraint": "G = C_in/C_fb", "why": "The loop forces the charge the input capacitor draws at each edge back through the feedback capacitor, so the gain is their ratio - two capacitors of one kind, matched in layout - and not the OTA's gain." }, { "rule": "match", "of": [ "M1", "M2" ], "why": "The input pair's mismatch is the OTA's offset - the one the choppers move to the chopping frequency." }, { "rule": "chopper-phases", "of": [ "SI1n", "SF1n", "SO1", "SS1" ], "constraint": "every chopper on one clock pair", "why": "The input, output and feedback choppers must swap together, or the loop is positive feedback for part of each period. At these levels a gate turns off before its partner turns on, so the edges need no separate non-overlapping phases." }, { "rule": "servo", "of": [ "CS1", "CS2", "SS1", "SS2", "SS3", "SS4" ], "constraint": "the capacitor before the chopper: C_s = 4 C_fb", "why": "The OTA's offset sits at the summing nodes as a DC difference, and the bias resistors draw a current from it that only the feedback capacitors could supply - by ramping, so the ripple would grow to a rail. Chopped after it, the servo capacitor passes no charge for the signal (whose output is steady) but a charge 2 C_s (D + V_os) at every edge for the ripple D: a resistor 1/(4 f_ch C_s) that the signal cannot see, which holds the ripple at (1 + R_sc/R_b) V_os." }, { "rule": "bias-resistor", "of": [ "RB1", "RB2" ], "constraint": "R_b = 5 MΩ of high-resistance poly", "why": "It only sets the summing nodes' level: they are a virtual ground, so its value hardly touches the gain. Larger is quieter - its current noise reaches the input as sqrt(4kT/R_b)/(2 pi f_ch C_in), about 45 nV/√Hz on each side at 5 MΩ - and makes the servo's ripple smaller, but 5 MΩ is already 1.5 mm of 0.5 µm poly." }, { "rule": "switch-timing", "of": [ "SF1n", "SI1n" ], "constraint": "R_on,SF C_fb about R_on,SI C_in", "why": "At each edge the input capacitor's charge and the feedback capacitor's must reach the summing node together; a feedback switch as wide as the input one delivers its charge twenty times faster and the output spikes. A narrow feedback switch evens the time constants." }, { "rule": "loop-around-both", "of": [ "MC1", "MC4", "M7", "M8" ], "constraint": "the output common mode corrects the first stage", "why": "Without it the output common mode, fed back through the feedback capacitors, swings both outputs rail to rail; acting on the first stage's loads, one loop defines both stages' levels at every corner." }, { "rule": "headroom", "of": [ "M1", "MT" ], "constraint": "vicm + V_SG,M1 + V_DSAT,MT <= V_DD", "why": "The summing nodes are the PMOS pair's gates: at 0.35 V the tail keeps its headroom down to a 1.08 V supply, while the input capacitors let the source sit anywhere." } ], "specs": [ { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.00012 A", "min": null, "max": 0.00012, "why": "The OTA and its common-mode loop, from one 5 µA reference; the switches draw only charge." }, { "key": "vocm_out", "label": "Output common mode", "unit": "V", "direction": "target", "constraint": ">= 0.57 V, <= 0.63 V", "min": 0.57, "max": 0.63, "why": "The common-mode loop holds the outputs within 30 mV of the 0.6 V asked for, clocked or not." }, { "key": "vsum", "label": "Summing-node level", "unit": "V", "direction": "target", "constraint": ">= 0.33 V, <= 0.37 V", "min": 0.33, "max": 0.37, "why": "The bias resistors hold the pair's gates at vicm, 0.35 V, where the PMOS pair keeps its tail saturated down to a 1.08 V supply; the pair's gate current may shift them a little." }, { "key": "gain", "label": "Gain, clocked", "unit": "V/V", "direction": "target", "constraint": ">= 19.4 V/V, <= 20.6 V/V", "min": 19.4, "max": 20.6, "why": "The gain is the capacitor ratio, 20, to within 3 %: the OTA's finite gain and the pair's gate capacitance take about half a percent off it, and a 0.5 pF feedback capacitor matches its 10 pF input capacitor to about 0.7 % (one sigma)." }, { "key": "gain_err_pct", "label": "Gain against the capacitor ratio", "unit": "%", "direction": "target", "constraint": ">= -3 %, <= 3 %", "min": -3, "max": 3, "why": "Within 3 % of C_in/C_fb at every corner and in every draw: the ratio of two capacitors of one kind, which the process does not move and mismatch moves by fractions of a percent." }, { "key": "zin", "label": "Input impedance, clocked", "unit": "Ω", "direction": "max", "constraint": ">= 2000000 Ω", "min": 2000000, "max": null, "why": "The input capacitors are recharged every half period: 1/(2 f_ch C_in) is 2.5 MΩ at 20 kHz and 10 pF, which the clocked bench finds; the limit leaves room for the capacitors' spread." }, { "key": "excursion", "label": "Output excursion at the edges, peak to peak", "unit": "V", "direction": "min", "constraint": "<= 0.04 V", "min": null, "max": 0.04, "why": "The output spikes at each edge, where the input and feedback charges do not arrive at once; for a 100 mV output it stays under 40 mV and is gone within a microsecond." }, { "key": "vos_left", "label": "Test offset left at baseband, input-referred", "unit": "V", "direction": "target", "constraint": ">= -0.00004 V, <= 0.00004 V", "min": -0.00004, "max": 0.00004, "why": "Chopped, the OTA's offset leaves baseband entirely, test offset and mismatch alike. What stays is the second stage's own offset, which follows the output chopper and is only divided by the first stage's gain: about 8 µV (one sigma) with M11, M12 built of 1.6 µm² units. Five sigma." }, { "key": "ripple", "label": "Offset ripple, peak to peak", "unit": "V", "direction": "min", "constraint": "<= 0.035 V", "min": null, "max": 0.035, "why": "The servo holds the moved offset at 2(1 + R_sc/R_b) V_os peak to peak, R_sc = 1/(4 f_ch C_s) = 6.25 MΩ against R_b = 5 MΩ: 9 mV for the 2 mV test offset alone. A real OTA adds its own, 1.9 mV (one sigma) from its fold sinks mostly: at three sigma the ripple is 35 mV." }, { "key": "ripple_growth", "label": "Ripple growth", "unit": "V/s", "direction": "target", "constraint": ">= -2 V/s, <= 2 V/s", "min": -2, "max": 2, "why": "Bounded: the ripple must not grow. Without the servo it grows at V_os/(R_b C_fb), 0.8 V/ms here, and reaches a rail within a millisecond." } ], "explanation": { "idea": "This amplifier measures small, slowly changing voltage differences. Clocked switches move the signal away from low-frequency offset and noise, then move it back after amplification. A capacitor ratio sets the gain, while another capacitor limits the remaining chopping ripple at the output.", "detail": "An instrumentation amplifier for small, slow sensor signals whose gain is a capacitor ratio. The input chopper turns a DC input difference into a square wave that passes the input capacitors; the OTA amplifies it at the summing nodes, the chopper between its stages brings it back to baseband, and the feedback chopper returns the output onto the feedback capacitors, whose charge must cancel the input capacitors' at every edge. The OTA's own offset leaves at the chopping frequency instead - and a servo capacitor, chopped on its far side, keeps that moved offset from growing through the bias resistors.", "lesson": { "relation": 0, "symbols": "G = v_od/v_id is differential voltage gain; C_in and C_fb are the input and feedback capacitors per side, in F; v_id and v_od are input and output voltage differences.", "assumptions": "The clocked negative-feedback loop settles each half-period, the OTA has sufficient gain, and switches operate in their allowed voltage range. Finite gain, mismatch and parasitics shift the ratio.", "exercise": { "param": "Cfb", "value": 1e-12, "analysis": "chop", "expect": "Doubling the feedback capacitor should reduce gain from about 20 toward 10. Compare the clocked waveform and residual edge spikes, not only its average." }, "limits": "Provide bias, common-mode references and complementary clocks with safe switching timing. AC coupling does not allow arbitrary voltages on the input switches; chopping leaves ripple and unsuppressed second-stage errors." }, "path": [ { "part": "Input chopper", "devices": "SI1n, SI1p, SI2n, SI2p, SI3n, SI3p, SI4n, SI4p", "does": "Transmission gates join inp to xp and inn to xn while clk is high, and cross them while clkb is: a DC input difference becomes a square wave at the chopping frequency." }, { "part": "Input capacitors", "devices": "CI1, CI2", "does": "CI1, CI2 (10 pF) pass the chopped difference to the summing nodes sp, sn and block the source's common mode: at every edge each draws a charge C_in·v_id." }, { "part": "Summing nodes", "devices": "RB1, RB2, M1, M2", "does": "sp and sn are the OTA's pair gates, held at vicm = 0.35 V by RB1, RB2 (5 MΩ); the loop keeps them a virtual ground, so the resistors carry almost no signal." }, { "part": "OTA", "devices": "M3, M5, M7, M9, SO1, SO2, SO3, SO4, M11, M13, CC1, RZ1, MC1, MC4", "does": "The single-loop chopper OTA: its output chopper SO1-SO4, in step with the input chopper, brings the signal back to baseband at g1, g2 and sends the first stage's offset and 1/f noise up to the chopping frequency." }, { "part": "Feedback chopper and capacitors", "devices": "SF1n, SF1p, SF2n, SF2p, SF3n, SF3p, SF4n, SF4p, CF1, CF2", "does": "The outputs are chopped again and returned crosswise through CF1, CF2 (0.5 pF): at each edge each feedback capacitor transfers charge C_fb·v_od, opposing the input charge C_in·v_id, so charge balance gives v_od/v_id ≈ C_in/C_fb. The narrow gates slow this charge to match the input's." }, { "part": "Servo", "devices": "CS1, CS2, SS1, SS2, SS3, SS4", "does": "CS1, CS2 (2 pF) from the outputs, chopped on their far side onto the summing nodes. For the steady signal they carry nothing; for a ripple at the chopping frequency, and for the OTA's offset across the summing nodes, they carry a charge at every edge - a resistor 1/(4 f_ch C_s) from the chopped output to the summing nodes that the signal cannot see." } ], "bias": "The OTA is the single-loop chopper OTA, biased from Ib = 5 µA, its outputs held at vocm = 0.6 V by its common-mode loop. RB1, RB2 hold the summing nodes at vicm = 0.35 V, where the PMOS pair's tail keeps its headroom down to a 1.08 V supply, while the input capacitors separate the source's DC common mode from the OTA bias. The source is at 0.6 V in the benches and must still remain within the input switches' allowed voltage range. Every chopper runs from one complementary clock pair at 20 kHz: the default operating point is checked, but complementary clocks alone do not guarantee non-overlap at every signal voltage; clock timing needs verification before reuse.", "relations": [ { "what": "Gain", "expr": "G = C_in/C_fb", "note": "20 by the capacitors; 19.9 clocked at the defaults - the OTA's finite gain and the pair's gate capacitance take half a percent - and within about 1 % in every corner and draw." }, { "what": "Input impedance", "expr": "Z_in = 1/(2·f_ch·C_in)", "note": "The input capacitors are recharged every half period: 2.5 MΩ at 20 kHz and 10 pF, as the clocked bench measures." }, { "what": "The moved offset", "expr": "D = (1 + R_sc/R_b)·V_os, R_sc = 1/(4·f_ch·C_s)", "note": "The OTA's offset V_os leaves as a square wave of amplitude D at the output: R_sc = 6.25 MΩ against R_b = 5 MΩ holds it at 2.25·V_os - 9 mV peak to peak for the bench's 2 mV." }, { "what": "Without the servo", "expr": "dD/dt = V_os/(R_b·C_fb)", "note": "The current the bias resistors draw from the offset would come off the feedback capacitors: 0.8 V/ms for 2 mV, to a rail within a millisecond." }, { "what": "What chopping cannot move", "expr": "V_os,res ≈ V_os,2/A_1", "note": "The second stage's own offset follows the output chopper: it is only divided by the first stage's gain, about 8 µV (one sigma) at the input with M11, M12 of 1.6 µm² units - the test offset itself leaves none." }, { "what": "Bias-resistor noise", "expr": "v_n,in ≈ √(4kT/R_b)/(2π·f_ch·C_in)", "note": "About 45 nV/√Hz on each side at 5 MΩ, 20 kHz and 10 pF - the price of a resistor short enough to build." } ], "tradeoffs": [ "Input capacitor (Cin): larger raises the gain for the same feedback capacitor and lowers the bias resistors' noise, but lowers the input impedance and takes area.", "Chopping frequency (fch): higher lowers the bias-resistor noise and the servo's resistance, but the input impedance falls with it, and every edge's spike comes more often.", "Servo capacitor (Cs): larger holds the moved offset closer to V_os and settles it in fewer edges, but loads the OTA's output; at 0 the ripple grows until the output hits a rail.", "Bias resistor (Rb): larger is quieter and shrinks the ripple, but costs about 0.31 mm of 0.5 µm poly per MΩ, and lets the pair's gate current move the summing nodes further from vicm." ] }, "sizing": [ { "key": "Cin", "label": "Input capacitor, each side", "unit": "F", "value": 1e-11, "min": 1e-12, "max": 4e-11, "kind": "si" }, { "key": "Cfb", "label": "Feedback capacitor, each side", "unit": "F", "value": 5e-13, "min": 1e-13, "max": 4e-12, "kind": "si" }, { "key": "Cs", "label": "Servo capacitor, each side (0: none)", "unit": "F", "value": 2e-12, "min": 0, "max": 8e-12, "kind": "si" }, { "key": "Rb", "label": "Summing-node bias resistor, each side", "unit": "Ω", "value": 5000000, "min": 500000, "max": 10000000, "kind": "si" }, { "key": "Wsi", "label": "W input-chopper switch, NMOS half (PMOS twice)", "unit": "m", "value": 0.000002, "min": 1.5e-7, "max": 0.00001, "kind": "si" }, { "key": "Wsf", "label": "W feedback-chopper switch, NMOS half (PMOS twice)", "unit": "m", "value": 3e-7, "min": 1.5e-7, "max": 0.00001, "kind": "si" }, { "key": "Lsi", "label": "L input, feedback and servo switches", "unit": "m", "value": 1.3e-7, "min": 1.3e-7, "max": 0.000001, "kind": "si" }, { "key": "Wss", "label": "W servo-chopper switch", "unit": "m", "value": 0.000001, "min": 1.5e-7, "max": 0.00001, "kind": "si" }, { "key": "Ib", "label": "Reference current", "unit": "A", "value": 0.000005, "min": 0.000001, "max": 0.00002, "kind": "si" }, { "key": "Wp", "label": "W PMOS source unit (MB, MT, M13, M14)", "unit": "m", "value": 0.00001, "min": 0.000001, "max": 0.00004, "kind": "si" }, { "key": "Lp", "label": "L PMOS source unit", "unit": "m", "value": 0.000002, "min": 5e-7, "max": 0.000008, "kind": "si" }, { "key": "Wn", "label": "W NMOS unit (MB2, M3, M4, the CMFB tail)", "unit": "m", "value": 0.000008, "min": 0.000001, "max": 0.00004, "kind": "si" }, { "key": "Ln", "label": "L NMOS unit", "unit": "m", "value": 0.000002, "min": 5e-7, "max": 0.000008, "kind": "si" }, { "key": "Wl", "label": "W PMOS load unit (M7, M8 and the diode they copy)", "unit": "m", "value": 0.00002, "min": 0.000002, "max": 0.00006, "kind": "si" }, { "key": "Ll", "label": "L PMOS load unit", "unit": "m", "value": 0.000002, "min": 5e-7, "max": 0.000008, "kind": "si" }, { "key": "W1", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.00002, "min": 0.000002, "max": 0.00008, "kind": "si" }, { "key": "L1", "label": "L input pair", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wcn", "label": "W NMOS cascode (M5, M6)", "unit": "m", "value": 0.000008, "min": 0.000001, "max": 0.00004, "kind": "si" }, { "key": "Lcn", "label": "L NMOS cascode", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.000002, "kind": "si" }, { "key": "Wcp", "label": "W PMOS cascode (M9, M10)", "unit": "m", "value": 0.000006, "min": 0.000001, "max": 0.00004, "kind": "si" }, { "key": "Lcp", "label": "L PMOS cascode", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.000002, "kind": "si" }, { "key": "Wdn", "label": "W diode setting the NMOS cascode gate (MB6)", "unit": "m", "value": 0.0000016, "min": 5e-7, "max": 0.000008, "kind": "si" }, { "key": "Ldn", "label": "L diode setting the NMOS cascode gate", "unit": "m", "value": 0.000004, "min": 0.000001, "max": 0.00001, "kind": "si" }, { "key": "Wdp", "label": "W diode setting the PMOS cascode gate (MB3)", "unit": "m", "value": 0.000004, "min": 5e-7, "max": 0.00001, "kind": "si" }, { "key": "Ldp", "label": "L diode setting the PMOS cascode gate", "unit": "m", "value": 0.000004, "min": 0.000001, "max": 0.00001, "kind": "si" }, { "key": "W2", "label": "W second-stage NMOS unit (M11, M12)", "unit": "m", "value": 8e-7, "min": 3e-7, "max": 0.000004, "kind": "si" }, { "key": "L2", "label": "L second-stage NMOS unit", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.000006, "kind": "si" }, { "key": "N2", "label": "Second-stage current, in Ib", "unit": "", "value": 4, "min": 2, "max": 12, "kind": "int" }, { "key": "Cc", "label": "Miller capacitor, each side", "unit": "F", "value": 3e-12, "min": 5e-13, "max": 1.2e-11, "kind": "si" }, { "key": "Rz", "label": "Nulling resistor, each side", "unit": "Ω", "value": 12000, "min": 2000, "max": 60000, "kind": "si" }, { "key": "Wso", "label": "W output-chopper switch (SO1-SO4)", "unit": "m", "value": 0.000001, "min": 1.5e-7, "max": 0.00001, "kind": "si" }, { "key": "Lso", "label": "L output-chopper switch", "unit": "m", "value": 1.3e-7, "min": 1.3e-7, "max": 0.000001, "kind": "si" }, { "key": "Wc", "label": "W CMFB pair (MC1, MC2)", "unit": "m", "value": 0.00001, "min": 0.000001, "max": 0.00004, "kind": "si" }, { "key": "Lc", "label": "L CMFB pair", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Rm", "label": "Common-mode sense resistor, each side", "unit": "Ω", "value": 1000000, "min": 100000, "max": 5000000, "kind": "si" }, { "key": "Cm", "label": "Common-mode sense capacitor, each side", "unit": "F", "value": 2e-13, "min": 0, "max": 2e-12, "kind": "si" }, { "key": "fch", "label": "Chopping frequency", "unit": "Hz", "value": 20000, "min": 2000, "max": 100000, "kind": "si" }, { "key": "Vid", "label": "Input difference the clocked benches apply", "unit": "V", "value": 0.005, "min": 0.0005, "max": 0.02, "kind": "si" }, { "key": "Vos", "label": "Test offset the offset bench puts in the OTA", "unit": "V", "value": 0.002, "min": -0.01, "max": 0.01, "kind": "si" }, { "key": "INCM", "label": "Input common mode, the source's", "unit": "V", "value": 0.6, "min": 0.2, "max": 1, "kind": "si" }, { "key": "VICM", "label": "Summing-node level", "unit": "V", "value": 0.35, "min": 0.1, "max": 0.6, "kind": "si" }, { "key": "VOCM", "label": "Output common mode", "unit": "V", "value": 0.6, "min": 0.4, "max": 0.8, "kind": "si" }, { "key": "CL", "label": "Load capacitance, each output", "unit": "F", "value": 1e-12, "min": 2e-13, "max": 2e-11, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point, clocks held", "note": "The amplifier with its clocks held in one phase - every chopper straight - and no input: the current it draws and the levels it sits at. Held, the loop has no path at DC but the bias resistors, so this is the operating point the clocked benches start from, not a figure of the running amplifier.", "measures": [], "metricKeys": [ "i_supply", "vocm_out", "vsum" ], "acceptance": [ "i_supply", "vocm_out", "vsum" ], "acceptanceRules": [ { "key": "i_supply", "unit": "A", "min": null, "max": 0.00012, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "vocm_out", "unit": "V", "min": 0.57, "max": 0.63, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "vsum", "unit": "V", "min": 0.33, "max": 0.37, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Capacitively coupled chopper instrumentation amplifier - operating point, clocks held\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 5u\n* the output common mode, and the summing nodes' level\nVocm vocm 0 dc 600m\nVicm vicm 0 dc 350m\n* the clocks held: clk high, clkb low - every chopper straight\nVclk clk 0 dc {VDD}\nVclkb clkb 0 dc 0\n* the source: 0V between the inputs, at 600mV common mode\nVinp inp 0 dc 600m\nVinn inn 0 dc 600m\n.subckt chopia inp inn outp outn vdd vss ib vocm vicm clk clkb\nXSI1n inp clk xp vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXSI1p inp clkb xp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXSI2n inn clk xn vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXSI2p inn clkb xn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXSI3n inp clkb xn vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXSI3p inp clk xn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXSI4n inn clkb xp vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXSI4p inn clk xp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXCI1 xp sp cap_cmim w=28.814u l=28.814u m=8\nXCI2 xn sn cap_cmim w=28.814u l=28.814u m=8\nXRB1 sp vicm vss rhigh w=0.5u l=1544.019u\nXRB2 sn vicm vss rhigh w=0.5u l=1544.019u\nXSF1n outp clk yp vss sg13_lv_nmos w=300n l=130n ng=1 m=1\nXSF1p outp clkb yp vdd sg13_lv_pmos w=600n l=130n ng=1 m=1\nXSF2n outn clk yn vss sg13_lv_nmos w=300n l=130n ng=1 m=1\nXSF2p outn clkb yn vdd sg13_lv_pmos w=600n l=130n ng=1 m=1\nXSF3n outp clkb yn vss sg13_lv_nmos w=300n l=130n ng=1 m=1\nXSF3p outp clk yn vdd sg13_lv_pmos w=600n l=130n ng=1 m=1\nXSF4n outn clkb yp vss sg13_lv_nmos w=300n l=130n ng=1 m=1\nXSF4p outn clk yp vdd sg13_lv_pmos w=600n l=130n ng=1 m=1\nXCF1 yp sn cap_cmim w=18.204u l=18.204u\nXCF2 yn sp cap_cmim w=18.204u l=18.204u\nXCS1 outp wp cap_cmim w=25.767u l=25.767u m=2\nXCS2 outn wn cap_cmim w=25.767u l=25.767u m=2\nXSS1 wp clk sn vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSS2 wn clk sp vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSS3 wp clkb sp vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSS4 wn clkb sn vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXMB ib ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB1 nb ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB2 nb nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1\nXMB3 vcp vcp vdd vdd sg13_lv_pmos w=4u l=4u ng=1 m=1\nXMB4 vcp nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1\nXMB5 vcn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB6 vcn vcn vss vss sg13_lv_nmos w=1.6u l=4u ng=1 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=2\nXM1 f1 sp tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM2 f2 sn tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM3 f1 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2\nXM4 f2 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2\nXM5 o1 vcn f1 vss sg13_lv_nmos w=8u l=500n ng=2 m=1\nXM6 o2 vcn f2 vss sg13_lv_nmos w=8u l=500n ng=2 m=1\nXM7 k1 vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXM8 k2 vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXM9 o1 vcp k1 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1\nXM10 o2 vcp k2 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1\nXSO1 o1 clk g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO2 o2 clk g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO3 o1 clkb g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO4 o2 clkb g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXM11 outp g1 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4\nXM12 outn g2 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4\nXM13 outp ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4\nXM14 outn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4\nXCC1 g1 z1 cap_cmim w=25.767u l=25.767u m=3\nXCC2 g2 z2 cap_cmim w=25.767u l=25.767u m=3\nXRZ1 z1 outp vss rppd w=0.5u l=23.355u\nXRZ2 z2 outn vss rppd w=0.5u l=23.355u\nXRM1 outp cms vss rhigh w=0.5u l=308.725u\nXRM2 outn cms vss rhigh w=0.5u l=308.725u\nXCM1 outp cms cap_cmim w=11.494u l=11.494u\nXCM2 outn cms cap_cmim w=11.494u l=11.494u\nXMC1 vbl cms ct vss sg13_lv_nmos w=10u l=1u ng=2 m=1\nXMC2 cx vocm ct vss sg13_lv_nmos w=10u l=1u ng=2 m=1\nXMC3 ct nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2\nXMC4 vbl vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXMC5 cx cx vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\n.ends\nXdut inp inn outp outn vdd 0 ib vocm vicm clk clkb chopia\nClp outp 0 1p\nCln outn 0 1p\n.op\n.end" }, { "id": "chop", "label": "Clocked: gain and input impedance", "note": "The choppers clocked, a DC difference on the inputs. The gain is the output difference averaged over whole clock periods, against the capacitor ratio that should set it; the input impedance is the input difference over the current the source delivers, averaged the same way - the charge the input capacitors draw at every edge.", "measures": [], "metricKeys": [ "gain", "gain_err_pct", "zin", "excursion", "vocm_out" ], "acceptance": [ "gain", "gain_err_pct", "zin", "excursion", "vocm_out" ], "acceptanceRules": [ { "key": "gain", "unit": "V/V", "min": 19.4, "max": 20.6, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "gain_err_pct", "unit": "%", "min": -3, "max": 3, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "zin", "unit": "Ω", "min": 2000000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "excursion", "unit": "V", "min": null, "max": 0.04, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "vocm_out", "unit": "V", "min": 0.57, "max": 0.63, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Capacitively coupled chopper instrumentation amplifier - clocked, a DC input: gain and input impedance\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 5u\n* the output common mode, and the summing nodes' level\nVocm vocm 0 dc 600m\nVicm vicm 0 dc 350m\n* the clocks: 20kHz, clk high (straight) for the first half period, 20ns edges\nVclk clk 0 pulse({VDD} 0 25u 20n 20n 24.98u 50u)\nVclkb clkb 0 pulse(0 {VDD} 25u 20n 20n 24.98u 50u)\n* the source: 5mV between the inputs, at 600mV common mode\nVinp inp 0 dc 602.5m\nVinn inn 0 dc 597.5m\n.subckt chopia inp inn outp outn vdd vss ib vocm vicm clk clkb\nXSI1n inp clk xp vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXSI1p inp clkb xp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXSI2n inn clk xn vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXSI2p inn clkb xn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXSI3n inp clkb xn vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXSI3p inp clk xn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXSI4n inn clkb xp vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXSI4p inn clk xp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXCI1 xp sp cap_cmim w=28.814u l=28.814u m=8\nXCI2 xn sn cap_cmim w=28.814u l=28.814u m=8\nXRB1 sp vicm vss rhigh w=0.5u l=1544.019u\nXRB2 sn vicm vss rhigh w=0.5u l=1544.019u\nXSF1n outp clk yp vss sg13_lv_nmos w=300n l=130n ng=1 m=1\nXSF1p outp clkb yp vdd sg13_lv_pmos w=600n l=130n ng=1 m=1\nXSF2n outn clk yn vss sg13_lv_nmos w=300n l=130n ng=1 m=1\nXSF2p outn clkb yn vdd sg13_lv_pmos w=600n l=130n ng=1 m=1\nXSF3n outp clkb yn vss sg13_lv_nmos w=300n l=130n ng=1 m=1\nXSF3p outp clk yn vdd sg13_lv_pmos w=600n l=130n ng=1 m=1\nXSF4n outn clkb yp vss sg13_lv_nmos w=300n l=130n ng=1 m=1\nXSF4p outn clk yp vdd sg13_lv_pmos w=600n l=130n ng=1 m=1\nXCF1 yp sn cap_cmim w=18.204u l=18.204u\nXCF2 yn sp cap_cmim w=18.204u l=18.204u\nXCS1 outp wp cap_cmim w=25.767u l=25.767u m=2\nXCS2 outn wn cap_cmim w=25.767u l=25.767u m=2\nXSS1 wp clk sn vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSS2 wn clk sp vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSS3 wp clkb sp vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSS4 wn clkb sn vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXMB ib ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB1 nb ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB2 nb nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1\nXMB3 vcp vcp vdd vdd sg13_lv_pmos w=4u l=4u ng=1 m=1\nXMB4 vcp nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1\nXMB5 vcn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB6 vcn vcn vss vss sg13_lv_nmos w=1.6u l=4u ng=1 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=2\nXM1 f1 sp tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM2 f2 sn tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM3 f1 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2\nXM4 f2 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2\nXM5 o1 vcn f1 vss sg13_lv_nmos w=8u l=500n ng=2 m=1\nXM6 o2 vcn f2 vss sg13_lv_nmos w=8u l=500n ng=2 m=1\nXM7 k1 vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXM8 k2 vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXM9 o1 vcp k1 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1\nXM10 o2 vcp k2 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1\nXSO1 o1 clk g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO2 o2 clk g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO3 o1 clkb g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO4 o2 clkb g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXM11 outp g1 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4\nXM12 outn g2 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4\nXM13 outp ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4\nXM14 outn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4\nXCC1 g1 z1 cap_cmim w=25.767u l=25.767u m=3\nXCC2 g2 z2 cap_cmim w=25.767u l=25.767u m=3\nXRZ1 z1 outp vss rppd w=0.5u l=23.355u\nXRZ2 z2 outn vss rppd w=0.5u l=23.355u\nXRM1 outp cms vss rhigh w=0.5u l=308.725u\nXRM2 outn cms vss rhigh w=0.5u l=308.725u\nXCM1 outp cms cap_cmim w=11.494u l=11.494u\nXCM2 outn cms cap_cmim w=11.494u l=11.494u\nXMC1 vbl cms ct vss sg13_lv_nmos w=10u l=1u ng=2 m=1\nXMC2 cx vocm ct vss sg13_lv_nmos w=10u l=1u ng=2 m=1\nXMC3 ct nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2\nXMC4 vbl vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXMC5 cx cx vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\n.ends\nXdut inp inn outp outn vdd 0 ib vocm vicm clk clkb chopia\nClp outp 0 1p\nCln outn 0 1p\n.save v(outp) v(outn) i(vinp) i(vinn)\n.tran 50n 500u 0 250n\n.end" }, { "id": "offset", "label": "Clocked: the moved offset", "note": "The choppers clocked, no input, and a test source (Vos, 2 mV by default) in series with the gate of M1 inside the amplifier: an OTA offset of known size. Chopped, it should leave baseband and come out as a ripple at the chopping frequency; the bench reads what is left of it at baseband, how large the ripple is, and whether it grows - an offset held on the feedback capacitors that leaks away through the bias resistors grows without end.", "measures": [], "metricKeys": [ "vos_left", "ripple", "ripple_growth" ], "acceptance": [ "vos_left", "ripple", "ripple_growth" ], "acceptanceRules": [ { "key": "vos_left", "unit": "V", "min": -0.00004, "max": 0.00004, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "ripple", "unit": "V", "min": null, "max": 0.035, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "ripple_growth", "unit": "V/s", "min": -2, "max": 2, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Capacitively coupled chopper instrumentation amplifier - clocked, a 2mV test offset in the OTA\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 5u\n* the output common mode, and the summing nodes' level\nVocm vocm 0 dc 600m\nVicm vicm 0 dc 350m\n* the clocks: 20kHz, clk high (straight) for the first half period, 20ns edges\nVclk clk 0 pulse({VDD} 0 25u 20n 20n 24.98u 50u)\nVclkb clkb 0 pulse(0 {VDD} 25u 20n 20n 24.98u 50u)\n* the source: 0V between the inputs, at 600mV common mode\nVinp inp 0 dc 600m\nVinn inn 0 dc 600m\n.subckt chopia inp inn outp outn vdd vss ib vocm vicm clk clkb\nXSI1n inp clk xp vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXSI1p inp clkb xp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXSI2n inn clk xn vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXSI2p inn clkb xn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXSI3n inp clkb xn vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXSI3p inp clk xn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXSI4n inn clkb xp vss sg13_lv_nmos w=2u l=130n ng=1 m=1\nXSI4p inn clk xp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXCI1 xp sp cap_cmim w=28.814u l=28.814u m=8\nXCI2 xn sn cap_cmim w=28.814u l=28.814u m=8\nXRB1 sp vicm vss rhigh w=0.5u l=1544.019u\nXRB2 sn vicm vss rhigh w=0.5u l=1544.019u\nXSF1n outp clk yp vss sg13_lv_nmos w=300n l=130n ng=1 m=1\nXSF1p outp clkb yp vdd sg13_lv_pmos w=600n l=130n ng=1 m=1\nXSF2n outn clk yn vss sg13_lv_nmos w=300n l=130n ng=1 m=1\nXSF2p outn clkb yn vdd sg13_lv_pmos w=600n l=130n ng=1 m=1\nXSF3n outp clkb yn vss sg13_lv_nmos w=300n l=130n ng=1 m=1\nXSF3p outp clk yn vdd sg13_lv_pmos w=600n l=130n ng=1 m=1\nXSF4n outn clkb yp vss sg13_lv_nmos w=300n l=130n ng=1 m=1\nXSF4p outn clk yp vdd sg13_lv_pmos w=600n l=130n ng=1 m=1\nXCF1 yp sn cap_cmim w=18.204u l=18.204u\nXCF2 yn sp cap_cmim w=18.204u l=18.204u\nXCS1 outp wp cap_cmim w=25.767u l=25.767u m=2\nXCS2 outn wn cap_cmim w=25.767u l=25.767u m=2\nXSS1 wp clk sn vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSS2 wn clk sp vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSS3 wp clkb sp vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSS4 wn clkb sn vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXMB ib ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB1 nb ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB2 nb nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1\nXMB3 vcp vcp vdd vdd sg13_lv_pmos w=4u l=4u ng=1 m=1\nXMB4 vcp nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1\nXMB5 vcn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXMB6 vcn vcn vss vss sg13_lv_nmos w=1.6u l=4u ng=1 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=2\nXM1 f1 gt tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM2 f2 sn tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM3 f1 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2\nXM4 f2 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2\nXM5 o1 vcn f1 vss sg13_lv_nmos w=8u l=500n ng=2 m=1\nXM6 o2 vcn f2 vss sg13_lv_nmos w=8u l=500n ng=2 m=1\nXM7 k1 vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXM8 k2 vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXM9 o1 vcp k1 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1\nXM10 o2 vcp k2 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1\nXSO1 o1 clk g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO2 o2 clk g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO3 o1 clkb g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSO4 o2 clkb g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1\nXM11 outp g1 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4\nXM12 outn g2 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4\nXM13 outp ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4\nXM14 outn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4\nXCC1 g1 z1 cap_cmim w=25.767u l=25.767u m=3\nXCC2 g2 z2 cap_cmim w=25.767u l=25.767u m=3\nXRZ1 z1 outp vss rppd w=0.5u l=23.355u\nXRZ2 z2 outn vss rppd w=0.5u l=23.355u\nXRM1 outp cms vss rhigh w=0.5u l=308.725u\nXRM2 outn cms vss rhigh w=0.5u l=308.725u\nXCM1 outp cms cap_cmim w=11.494u l=11.494u\nXCM2 outn cms cap_cmim w=11.494u l=11.494u\nXMC1 vbl cms ct vss sg13_lv_nmos w=10u l=1u ng=2 m=1\nXMC2 cx vocm ct vss sg13_lv_nmos w=10u l=1u ng=2 m=1\nXMC3 ct nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2\nXMC4 vbl vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\nXMC5 cx cx vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1\n* the bench's test offset, in series with the gate of M1\nVos gt sp dc 2m\n.ends\nXdut inp inn outp outn vdd 0 ib vocm vicm clk clkb chopia\nClp outp 0 1p\nCln outn 0 1p\n.save v(outp) v(outn) i(vinp) i(vinn)\n.tran 50n 900u 0 250n\n.end" } ], "measurements": { "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.00012 } }, "vocm_out": { "label": "Output common mode", "unit": "V", "spec": { "min": 0.57, "max": 0.63 } }, "vsum": { "label": "Summing-node level", "unit": "V", "spec": { "min": 0.33, "max": 0.37 } }, "gain": { "label": "Gain, clocked", "unit": "V/V", "spec": { "min": 19.4, "max": 20.6 } }, "gain_err_pct": { "label": "Gain against the capacitor ratio", "unit": "%", "spec": { "min": -3, "max": 3 } }, "zin": { "label": "Input impedance, clocked", "unit": "Ω", "spec": { "min": 2000000, "max": null } }, "excursion": { "label": "Output excursion at the edges, peak to peak", "unit": "V", "spec": { "min": null, "max": 0.04 } }, "vos_left": { "label": "Test offset left at baseband, input-referred", "unit": "V", "spec": { "min": -0.00004, "max": 0.00004 } }, "ripple": { "label": "Offset ripple, peak to peak", "unit": "V", "spec": { "min": null, "max": 0.035 } }, "ripple_growth": { "label": "Ripple growth", "unit": "V/s", "spec": { "min": -2, "max": 2 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "cfc444bc20fa91cff36b83ed99203a4a0acb808a92667c6e870d28f69951e019" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ia-chopper-cc.js", "sha256": "dc406a2247aa22caac93e2306dfc76753896d3a50b52f0f876a7087571beab48" }, "simulationFingerprints": { "op": "187f432e76d7fbd4e6ed4eb90faf6fefcd96581161a82ab3686fd53551550912", "chop": "4257413b2f7f9788176825f39b362b83ef103a94be50276d0f9c58413ce22c11", "offset": "0f5362a8c5013f737bb87838b19eb5ec0ca838dd2305acd4689e81ff6476130b" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "e400e4ff2e4f6c2d0f7e2c00c53d3e5b4f07570b36434cd54ce08fc1005ea8fd", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ia-chopper-cc", "parameters": { "Cin": 1e-11, "Cfb": 5e-13, "Cs": 2e-12, "Rb": 5000000, "Wsi": 0.000002, "Wsf": 3e-7, "Lsi": 1.3e-7, "Wss": 0.000001, "Ib": 0.000005, "Wp": 0.00001, "Lp": 0.000002, "Wn": 0.000008, "Ln": 0.000002, "Wl": 0.00002, "Ll": 0.000002, "W1": 0.00002, "L1": 0.000001, "Wcn": 0.000008, "Lcn": 5e-7, "Wcp": 0.000006, "Lcp": 5e-7, "Wdn": 0.0000016, "Ldn": 0.000004, "Wdp": 0.000004, "Ldp": 0.000004, "W2": 8e-7, "L2": 0.000002, "N2": 4, "Cc": 3e-12, "Rz": 12000, "Wso": 0.000001, "Lso": 1.3e-7, "Wc": 0.00001, "Lc": 0.000001, "Rm": 1000000, "Cm": 2e-13, "fch": 20000, "Vid": 0.005, "Vos": 0.002, "INCM": 0.6, "VICM": 0.35, "VOCM": 0.6, "CL": 1e-12 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ia-chopper-cc/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "chopia", "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "outp", "net": "outp", "kind": "output" }, { "name": "outn", "net": "outn", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" }, { "name": "vocm", "net": "vocm", "kind": "bias" }, { "name": "vicm", "net": "vicm", "kind": "bias" }, { "name": "clk", "net": "clk", "kind": "clock" }, { "name": "clkb", "net": "clkb", "kind": "clock" } ], "definitions": [], "devices": [ { "id": "XSI1n", "displayName": "SI1n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI1n inp clk xp vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI1p", "displayName": "SI1p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI1p inp clkb xp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI2n", "displayName": "SI2n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI2n inn clk xn vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI2p", "displayName": "SI2p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI2p inn clkb xn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI3n", "displayName": "SI3n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI3n inp clkb xn vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI3p", "displayName": "SI3p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI3p inp clk xn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI4n", "displayName": "SI4n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI4n inn clkb xp vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI4p", "displayName": "SI4p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI4p inn clk xp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCI1", "displayName": "CI1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=8", "source": "XCI1 xp sp cap_cmim w=28.814u l=28.814u m=8", "pins": [ { "id": "p", "net": "xp" }, { "id": "n", "net": "sp" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCI2", "displayName": "CI2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=8", "source": "XCI2 xn sn cap_cmim w=28.814u l=28.814u m=8", "pins": [ { "id": "p", "net": "xn" }, { "id": "n", "net": "sn" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRB1", "displayName": "RB1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRB1 sp vicm vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "sp" }, { "id": "n", "net": "vicm" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRB2", "displayName": "RB2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRB2 sn vicm vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "sn" }, { "id": "n", "net": "vicm" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XSF1n", "displayName": "SF1n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF1n outp clk yp vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF1p", "displayName": "SF1p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF1p outp clkb yp vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF2n", "displayName": "SF2n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF2n outn clk yn vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF2p", "displayName": "SF2p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF2p outn clkb yn vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF3n", "displayName": "SF3n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF3n outp clkb yn vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF3p", "displayName": "SF3p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF3p outp clk yn vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF4n", "displayName": "SF4n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF4n outn clkb yp vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF4p", "displayName": "SF4p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF4p outn clk yp vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCF1", "displayName": "CF1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=18.204u l=18.204u", "source": "XCF1 yp sn cap_cmim w=18.204u l=18.204u", "pins": [ { "id": "p", "net": "yp" }, { "id": "n", "net": "sn" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCF2", "displayName": "CF2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=18.204u l=18.204u", "source": "XCF2 yn sp cap_cmim w=18.204u l=18.204u", "pins": [ { "id": "p", "net": "yn" }, { "id": "n", "net": "sp" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCS1", "displayName": "CS1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCS1 outp wp cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "wp" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCS2", "displayName": "CS2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCS2 outn wn cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "wn" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XSS1", "displayName": "SS1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS1 wp clk sn vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "sn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSS2", "displayName": "SS2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS2 wn clk sp vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "sp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSS3", "displayName": "SS3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS3 wp clkb sp vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "sp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSS4", "displayName": "SS4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS4 wn clkb sn vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "sn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB2 nb nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMB3 vcp vcp vdd vdd sg13_lv_pmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB4", "displayName": "MB4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB4 vcp nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB5", "displayName": "MB5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB5 vcn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB6", "displayName": "MB6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.6u l=4u ng=1 m=1", "source": "XMB6 vcn vcn vss vss sg13_lv_nmos w=1.6u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM1 f1 sp tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "sp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM2 f2 sn tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "sn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM5 o1 vcn f1 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM6 o2 vcn f2 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM7 k1 vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "vbl" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM8 k2 vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "vbl" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM9 o1 vcp k1 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM10 o2 vcp k2 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO1", "displayName": "SO1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO1 o1 clk g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO2", "displayName": "SO2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO2 o2 clk g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO3", "displayName": "SO3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO3 o1 clkb g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO4", "displayName": "SO4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO4 o2 clkb g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM11 outp g1 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "g1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM12 outn g2 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "g2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM13 outp ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM14 outn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC1 g1 z1 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC2 g2 z2 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRM1", "displayName": "RM1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XRM1 outp cms vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cms" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRM2", "displayName": "RM2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XRM2 outn cms vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cms" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCM1", "displayName": "CM1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XCM1 outp cms cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cms" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCM2", "displayName": "CM2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XCM2 outn cms cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cms" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XMC1 vbl cms ct vss sg13_lv_nmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbl" }, { "id": "g", "net": "cms" }, { "id": "s", "net": "ct" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XMC2 cx vocm ct vss sg13_lv_nmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cx" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "ct" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC3", "displayName": "MC3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XMC3 ct nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "ct" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC4", "displayName": "MC4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XMC4 vbl vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "vbl" }, { "id": "g", "net": "vbl" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC5", "displayName": "MC5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XMC5 cx cx vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "cx" }, { "id": "g", "net": "cx" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "inp", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "d" }, { "device": "XSI1p", "pin": "d" }, { "device": "XSI3n", "pin": "d" }, { "device": "XSI3p", "pin": "d" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "g" }, { "device": "XSI2n", "pin": "g" }, { "device": "XSI3p", "pin": "g" }, { "device": "XSI4p", "pin": "g" }, { "device": "XSF1n", "pin": "g" }, { "device": "XSF2n", "pin": "g" }, { "device": "XSF3p", "pin": "g" }, { "device": "XSF4p", "pin": "g" }, { "device": "XSS1", "pin": "g" }, { "device": "XSS2", "pin": "g" }, { "device": "XSO1", "pin": "g" }, { "device": "XSO2", "pin": "g" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "xp", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "s" }, { "device": "XSI1p", "pin": "s" }, { "device": "XSI4n", "pin": "s" }, { "device": "XSI4p", "pin": "s" }, { "device": "XCI1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "b" }, { "device": "XSI2n", "pin": "b" }, { "device": "XSI3n", "pin": "b" }, { "device": "XSI4n", "pin": "b" }, { "device": "XRB1", "pin": "substrate" }, { "device": "XRB2", "pin": "substrate" }, { "device": "XSF1n", "pin": "b" }, { "device": "XSF2n", "pin": "b" }, { "device": "XSF3n", "pin": "b" }, { "device": "XSF4n", "pin": "b" }, { "device": "XSS1", "pin": "b" }, { "device": "XSS2", "pin": "b" }, { "device": "XSS3", "pin": "b" }, { "device": "XSS4", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMB4", "pin": "s" }, { "device": "XMB4", "pin": "b" }, { "device": "XMB6", "pin": "s" }, { "device": "XMB6", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XSO1", "pin": "b" }, { "device": "XSO2", "pin": "b" }, { "device": "XSO3", "pin": "b" }, { "device": "XSO4", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XRZ1", "pin": "substrate" }, { "device": "XRZ2", "pin": "substrate" }, { "device": "XRM1", "pin": "substrate" }, { "device": "XRM2", "pin": "substrate" }, { "device": "XMC1", "pin": "b" }, { "device": "XMC2", "pin": "b" }, { "device": "XMC3", "pin": "s" }, { "device": "XMC3", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "XSI1p", "pin": "g" }, { "device": "XSI2p", "pin": "g" }, { "device": "XSI3n", "pin": "g" }, { "device": "XSI4n", "pin": "g" }, { "device": "XSF1p", "pin": "g" }, { "device": "XSF2p", "pin": "g" }, { "device": "XSF3n", "pin": "g" }, { "device": "XSF4n", "pin": "g" }, { "device": "XSS3", "pin": "g" }, { "device": "XSS4", "pin": "g" }, { "device": "XSO3", "pin": "g" }, { "device": "XSO4", "pin": "g" } ], "ports": [ "clkb" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XSI1p", "pin": "b" }, { "device": "XSI2p", "pin": "b" }, { "device": "XSI3p", "pin": "b" }, { "device": "XSI4p", "pin": "b" }, { "device": "XSF1p", "pin": "b" }, { "device": "XSF2p", "pin": "b" }, { "device": "XSF3p", "pin": "b" }, { "device": "XSF4p", "pin": "b" }, { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XMB5", "pin": "s" }, { "device": "XMB5", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" }, { "device": "XMC4", "pin": "s" }, { "device": "XMC4", "pin": "b" }, { "device": "XMC5", "pin": "s" }, { "device": "XMC5", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XSI2n", "pin": "d" }, { "device": "XSI2p", "pin": "d" }, { "device": "XSI4n", "pin": "d" }, { "device": "XSI4p", "pin": "d" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "xn", "ground": false, "terminals": [ { "device": "XSI2n", "pin": "s" }, { "device": "XSI2p", "pin": "s" }, { "device": "XSI3n", "pin": "s" }, { "device": "XSI3p", "pin": "s" }, { "device": "XCI2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "sp", "ground": false, "terminals": [ { "device": "XCI1", "pin": "n" }, { "device": "XRB1", "pin": "p" }, { "device": "XCF2", "pin": "n" }, { "device": "XSS2", "pin": "s" }, { "device": "XSS3", "pin": "s" }, { "device": "XM1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "sn", "ground": false, "terminals": [ { "device": "XCI2", "pin": "n" }, { "device": "XRB2", "pin": "p" }, { "device": "XCF1", "pin": "n" }, { "device": "XSS1", "pin": "s" }, { "device": "XSS4", "pin": "s" }, { "device": "XM2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vicm", "ground": false, "terminals": [ { "device": "XRB1", "pin": "n" }, { "device": "XRB2", "pin": "n" } ], "ports": [ "vicm" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XSF1n", "pin": "d" }, { "device": "XSF1p", "pin": "d" }, { "device": "XSF3n", "pin": "d" }, { "device": "XSF3p", "pin": "d" }, { "device": "XCS1", "pin": "p" }, { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XRZ1", "pin": "n" }, { "device": "XRM1", "pin": "p" }, { "device": "XCM1", "pin": "p" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "yp", "ground": false, "terminals": [ { "device": "XSF1n", "pin": "s" }, { "device": "XSF1p", "pin": "s" }, { "device": "XSF4n", "pin": "s" }, { "device": "XSF4p", "pin": "s" }, { "device": "XCF1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XSF2n", "pin": "d" }, { "device": "XSF2p", "pin": "d" }, { "device": "XSF4n", "pin": "d" }, { "device": "XSF4p", "pin": "d" }, { "device": "XCS2", "pin": "p" }, { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XRZ2", "pin": "n" }, { "device": "XRM2", "pin": "p" }, { "device": "XCM2", "pin": "p" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "yn", "ground": false, "terminals": [ { "device": "XSF2n", "pin": "s" }, { "device": "XSF2p", "pin": "s" }, { "device": "XSF3n", "pin": "s" }, { "device": "XSF3p", "pin": "s" }, { "device": "XCF2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "wp", "ground": false, "terminals": [ { "device": "XCS1", "pin": "n" }, { "device": "XSS1", "pin": "d" }, { "device": "XSS3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "wn", "ground": false, "terminals": [ { "device": "XCS2", "pin": "n" }, { "device": "XSS2", "pin": "d" }, { "device": "XSS4", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB5", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM13", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMB2", "pin": "d" }, { "device": "XMB2", "pin": "g" }, { "device": "XMB4", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XMC3", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" }, { "device": "XMB4", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB5", "pin": "d" }, { "device": "XMB6", "pin": "d" }, { "device": "XMB6", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM9", "pin": "d" }, { "device": "XSO1", "pin": "d" }, { "device": "XSO3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XSO2", "pin": "d" }, { "device": "XSO4", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vbl", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XMC1", "pin": "d" }, { "device": "XMC4", "pin": "d" }, { "device": "XMC4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "g1", "ground": false, "terminals": [ { "device": "XSO1", "pin": "s" }, { "device": "XSO4", "pin": "s" }, { "device": "XM11", "pin": "g" }, { "device": "XCC1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "g2", "ground": false, "terminals": [ { "device": "XSO2", "pin": "s" }, { "device": "XSO3", "pin": "s" }, { "device": "XM12", "pin": "g" }, { "device": "XCC2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z1", "ground": false, "terminals": [ { "device": "XCC1", "pin": "n" }, { "device": "XRZ1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z2", "ground": false, "terminals": [ { "device": "XCC2", "pin": "n" }, { "device": "XRZ2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cms", "ground": false, "terminals": [ { "device": "XRM1", "pin": "n" }, { "device": "XRM2", "pin": "n" }, { "device": "XCM1", "pin": "n" }, { "device": "XCM2", "pin": "n" }, { "device": "XMC1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "ct", "ground": false, "terminals": [ { "device": "XMC1", "pin": "s" }, { "device": "XMC2", "pin": "s" }, { "device": "XMC3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cx", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XMC5", "pin": "d" }, { "device": "XMC5", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XMC2", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ib ib 0 5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vocm vocm 0 dc 600m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 350m", "source": "Vicm vicm 0 dc 350m", "pins": [ { "id": "p", "net": "vicm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclk", "displayName": "Vclk", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vclk clk 0 dc {VDD}", "pins": [ { "id": "p", "net": "clk" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclkb", "displayName": "Vclkb", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vclkb clkb 0 dc 0", "pins": [ { "id": "p", "net": "clkb" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vinp", "displayName": "Vinp", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vinp inp 0 dc 600m", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vinn", "displayName": "Vinn", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vinn inn 0 dc 600m", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "chopia", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 ib vocm vicm clk clkb chopia", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" }, { "id": "vocm", "net": "vocm" }, { "id": "vicm", "net": "vicm" }, { "id": "clk", "net": "clk" }, { "id": "clkb", "net": "clkb" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/chopia" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "1p", "source": "Clp outp 0 1p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "1p", "source": "Cln outn 0 1p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Vicm", "pin": "n" }, { "device": "Vclk", "pin": "n" }, { "device": "Vclkb", "pin": "n" }, { "device": "Vinp", "pin": "n" }, { "device": "Vinn", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" }, { "device": "Xdut", "pin": "vocm" } ], "ports": [], "voltageReferences": [] }, { "id": "vicm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Xdut", "pin": "vicm" } ], "ports": [], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "Vclk", "pin": "p" }, { "device": "Xdut", "pin": "clk" } ], "ports": [], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "Vclkb", "pin": "p" }, { "device": "Xdut", "pin": "clkb" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Vinp", "pin": "p" }, { "device": "Xdut", "pin": "inp" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Vinn", "pin": "p" }, { "device": "Xdut", "pin": "inn" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/chopia", "name": "chopia", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" }, { "name": "vocm", "net": "vocm" }, { "name": "vicm", "net": "vicm" }, { "name": "clk", "net": "clk" }, { "name": "clkb", "net": "clkb" } ], "definitions": [], "devices": [ { "id": "XSI1n", "displayName": "SI1n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI1n inp clk xp vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI1p", "displayName": "SI1p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI1p inp clkb xp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI2n", "displayName": "SI2n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI2n inn clk xn vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI2p", "displayName": "SI2p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI2p inn clkb xn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI3n", "displayName": "SI3n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI3n inp clkb xn vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI3p", "displayName": "SI3p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI3p inp clk xn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI4n", "displayName": "SI4n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI4n inn clkb xp vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI4p", "displayName": "SI4p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI4p inn clk xp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCI1", "displayName": "CI1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=8", "source": "XCI1 xp sp cap_cmim w=28.814u l=28.814u m=8", "pins": [ { "id": "p", "net": "xp" }, { "id": "n", "net": "sp" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCI2", "displayName": "CI2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=8", "source": "XCI2 xn sn cap_cmim w=28.814u l=28.814u m=8", "pins": [ { "id": "p", "net": "xn" }, { "id": "n", "net": "sn" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRB1", "displayName": "RB1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRB1 sp vicm vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "sp" }, { "id": "n", "net": "vicm" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRB2", "displayName": "RB2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRB2 sn vicm vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "sn" }, { "id": "n", "net": "vicm" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XSF1n", "displayName": "SF1n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF1n outp clk yp vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF1p", "displayName": "SF1p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF1p outp clkb yp vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF2n", "displayName": "SF2n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF2n outn clk yn vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF2p", "displayName": "SF2p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF2p outn clkb yn vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF3n", "displayName": "SF3n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF3n outp clkb yn vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF3p", "displayName": "SF3p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF3p outp clk yn vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF4n", "displayName": "SF4n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF4n outn clkb yp vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF4p", "displayName": "SF4p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF4p outn clk yp vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCF1", "displayName": "CF1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=18.204u l=18.204u", "source": "XCF1 yp sn cap_cmim w=18.204u l=18.204u", "pins": [ { "id": "p", "net": "yp" }, { "id": "n", "net": "sn" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCF2", "displayName": "CF2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=18.204u l=18.204u", "source": "XCF2 yn sp cap_cmim w=18.204u l=18.204u", "pins": [ { "id": "p", "net": "yn" }, { "id": "n", "net": "sp" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCS1", "displayName": "CS1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCS1 outp wp cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "wp" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCS2", "displayName": "CS2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCS2 outn wn cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "wn" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XSS1", "displayName": "SS1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS1 wp clk sn vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "sn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSS2", "displayName": "SS2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS2 wn clk sp vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "sp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSS3", "displayName": "SS3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS3 wp clkb sp vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "sp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSS4", "displayName": "SS4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS4 wn clkb sn vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "sn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB2 nb nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMB3 vcp vcp vdd vdd sg13_lv_pmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB4", "displayName": "MB4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB4 vcp nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB5", "displayName": "MB5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB5 vcn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB6", "displayName": "MB6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.6u l=4u ng=1 m=1", "source": "XMB6 vcn vcn vss vss sg13_lv_nmos w=1.6u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM1 f1 sp tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "sp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM2 f2 sn tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "sn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM5 o1 vcn f1 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM6 o2 vcn f2 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM7 k1 vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "vbl" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM8 k2 vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "vbl" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM9 o1 vcp k1 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM10 o2 vcp k2 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO1", "displayName": "SO1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO1 o1 clk g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO2", "displayName": "SO2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO2 o2 clk g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO3", "displayName": "SO3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO3 o1 clkb g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO4", "displayName": "SO4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO4 o2 clkb g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM11 outp g1 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "g1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM12 outn g2 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "g2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM13 outp ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM14 outn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC1 g1 z1 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC2 g2 z2 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRM1", "displayName": "RM1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XRM1 outp cms vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cms" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRM2", "displayName": "RM2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XRM2 outn cms vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cms" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCM1", "displayName": "CM1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XCM1 outp cms cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cms" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCM2", "displayName": "CM2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XCM2 outn cms cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cms" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XMC1 vbl cms ct vss sg13_lv_nmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbl" }, { "id": "g", "net": "cms" }, { "id": "s", "net": "ct" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XMC2 cx vocm ct vss sg13_lv_nmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cx" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "ct" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC3", "displayName": "MC3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XMC3 ct nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "ct" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC4", "displayName": "MC4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XMC4 vbl vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "vbl" }, { "id": "g", "net": "vbl" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC5", "displayName": "MC5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XMC5 cx cx vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "cx" }, { "id": "g", "net": "cx" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "inp", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "d" }, { "device": "XSI1p", "pin": "d" }, { "device": "XSI3n", "pin": "d" }, { "device": "XSI3p", "pin": "d" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "g" }, { "device": "XSI2n", "pin": "g" }, { "device": "XSI3p", "pin": "g" }, { "device": "XSI4p", "pin": "g" }, { "device": "XSF1n", "pin": "g" }, { "device": "XSF2n", "pin": "g" }, { "device": "XSF3p", "pin": "g" }, { "device": "XSF4p", "pin": "g" }, { "device": "XSS1", "pin": "g" }, { "device": "XSS2", "pin": "g" }, { "device": "XSO1", "pin": "g" }, { "device": "XSO2", "pin": "g" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "xp", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "s" }, { "device": "XSI1p", "pin": "s" }, { "device": "XSI4n", "pin": "s" }, { "device": "XSI4p", "pin": "s" }, { "device": "XCI1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "b" }, { "device": "XSI2n", "pin": "b" }, { "device": "XSI3n", "pin": "b" }, { "device": "XSI4n", "pin": "b" }, { "device": "XRB1", "pin": "substrate" }, { "device": "XRB2", "pin": "substrate" }, { "device": "XSF1n", "pin": "b" }, { "device": "XSF2n", "pin": "b" }, { "device": "XSF3n", "pin": "b" }, { "device": "XSF4n", "pin": "b" }, { "device": "XSS1", "pin": "b" }, { "device": "XSS2", "pin": "b" }, { "device": "XSS3", "pin": "b" }, { "device": "XSS4", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMB4", "pin": "s" }, { "device": "XMB4", "pin": "b" }, { "device": "XMB6", "pin": "s" }, { "device": "XMB6", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XSO1", "pin": "b" }, { "device": "XSO2", "pin": "b" }, { "device": "XSO3", "pin": "b" }, { "device": "XSO4", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XRZ1", "pin": "substrate" }, { "device": "XRZ2", "pin": "substrate" }, { "device": "XRM1", "pin": "substrate" }, { "device": "XRM2", "pin": "substrate" }, { "device": "XMC1", "pin": "b" }, { "device": "XMC2", "pin": "b" }, { "device": "XMC3", "pin": "s" }, { "device": "XMC3", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "XSI1p", "pin": "g" }, { "device": "XSI2p", "pin": "g" }, { "device": "XSI3n", "pin": "g" }, { "device": "XSI4n", "pin": "g" }, { "device": "XSF1p", "pin": "g" }, { "device": "XSF2p", "pin": "g" }, { "device": "XSF3n", "pin": "g" }, { "device": "XSF4n", "pin": "g" }, { "device": "XSS3", "pin": "g" }, { "device": "XSS4", "pin": "g" }, { "device": "XSO3", "pin": "g" }, { "device": "XSO4", "pin": "g" } ], "ports": [ "clkb" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XSI1p", "pin": "b" }, { "device": "XSI2p", "pin": "b" }, { "device": "XSI3p", "pin": "b" }, { "device": "XSI4p", "pin": "b" }, { "device": "XSF1p", "pin": "b" }, { "device": "XSF2p", "pin": "b" }, { "device": "XSF3p", "pin": "b" }, { "device": "XSF4p", "pin": "b" }, { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XMB5", "pin": "s" }, { "device": "XMB5", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" }, { "device": "XMC4", "pin": "s" }, { "device": "XMC4", "pin": "b" }, { "device": "XMC5", "pin": "s" }, { "device": "XMC5", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XSI2n", "pin": "d" }, { "device": "XSI2p", "pin": "d" }, { "device": "XSI4n", "pin": "d" }, { "device": "XSI4p", "pin": "d" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "xn", "ground": false, "terminals": [ { "device": "XSI2n", "pin": "s" }, { "device": "XSI2p", "pin": "s" }, { "device": "XSI3n", "pin": "s" }, { "device": "XSI3p", "pin": "s" }, { "device": "XCI2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "sp", "ground": false, "terminals": [ { "device": "XCI1", "pin": "n" }, { "device": "XRB1", "pin": "p" }, { "device": "XCF2", "pin": "n" }, { "device": "XSS2", "pin": "s" }, { "device": "XSS3", "pin": "s" }, { "device": "XM1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "sn", "ground": false, "terminals": [ { "device": "XCI2", "pin": "n" }, { "device": "XRB2", "pin": "p" }, { "device": "XCF1", "pin": "n" }, { "device": "XSS1", "pin": "s" }, { "device": "XSS4", "pin": "s" }, { "device": "XM2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vicm", "ground": false, "terminals": [ { "device": "XRB1", "pin": "n" }, { "device": "XRB2", "pin": "n" } ], "ports": [ "vicm" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XSF1n", "pin": "d" }, { "device": "XSF1p", "pin": "d" }, { "device": "XSF3n", "pin": "d" }, { "device": "XSF3p", "pin": "d" }, { "device": "XCS1", "pin": "p" }, { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XRZ1", "pin": "n" }, { "device": "XRM1", "pin": "p" }, { "device": "XCM1", "pin": "p" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "yp", "ground": false, "terminals": [ { "device": "XSF1n", "pin": "s" }, { "device": "XSF1p", "pin": "s" }, { "device": "XSF4n", "pin": "s" }, { "device": "XSF4p", "pin": "s" }, { "device": "XCF1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XSF2n", "pin": "d" }, { "device": "XSF2p", "pin": "d" }, { "device": "XSF4n", "pin": "d" }, { "device": "XSF4p", "pin": "d" }, { "device": "XCS2", "pin": "p" }, { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XRZ2", "pin": "n" }, { "device": "XRM2", "pin": "p" }, { "device": "XCM2", "pin": "p" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "yn", "ground": false, "terminals": [ { "device": "XSF2n", "pin": "s" }, { "device": "XSF2p", "pin": "s" }, { "device": "XSF3n", "pin": "s" }, { "device": "XSF3p", "pin": "s" }, { "device": "XCF2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "wp", "ground": false, "terminals": [ { "device": "XCS1", "pin": "n" }, { "device": "XSS1", "pin": "d" }, { "device": "XSS3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "wn", "ground": false, "terminals": [ { "device": "XCS2", "pin": "n" }, { "device": "XSS2", "pin": "d" }, { "device": "XSS4", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB5", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM13", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMB2", "pin": "d" }, { "device": "XMB2", "pin": "g" }, { "device": "XMB4", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XMC3", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" }, { "device": "XMB4", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB5", "pin": "d" }, { "device": "XMB6", "pin": "d" }, { "device": "XMB6", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM9", "pin": "d" }, { "device": "XSO1", "pin": "d" }, { "device": "XSO3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XSO2", "pin": "d" }, { "device": "XSO4", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vbl", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XMC1", "pin": "d" }, { "device": "XMC4", "pin": "d" }, { "device": "XMC4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "g1", "ground": false, "terminals": [ { "device": "XSO1", "pin": "s" }, { "device": "XSO4", "pin": "s" }, { "device": "XM11", "pin": "g" }, { "device": "XCC1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "g2", "ground": false, "terminals": [ { "device": "XSO2", "pin": "s" }, { "device": "XSO3", "pin": "s" }, { "device": "XM12", "pin": "g" }, { "device": "XCC2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z1", "ground": false, "terminals": [ { "device": "XCC1", "pin": "n" }, { "device": "XRZ1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z2", "ground": false, "terminals": [ { "device": "XCC2", "pin": "n" }, { "device": "XRZ2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cms", "ground": false, "terminals": [ { "device": "XRM1", "pin": "n" }, { "device": "XRM2", "pin": "n" }, { "device": "XCM1", "pin": "n" }, { "device": "XCM2", "pin": "n" }, { "device": "XMC1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "ct", "ground": false, "terminals": [ { "device": "XMC1", "pin": "s" }, { "device": "XMC2", "pin": "s" }, { "device": "XMC3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cx", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XMC5", "pin": "d" }, { "device": "XMC5", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XMC2", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/chopia" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Input chopper", "devices": [ { "scope": "dut", "device": "XSI1n" }, { "scope": "dut", "device": "XSI1p" }, { "scope": "dut", "device": "XSI2n" }, { "scope": "dut", "device": "XSI2p" }, { "scope": "dut", "device": "XSI3n" }, { "scope": "dut", "device": "XSI3p" }, { "scope": "dut", "device": "XSI4n" }, { "scope": "dut", "device": "XSI4p" } ], "inferredStages": [ 1 ] }, { "id": "block-2", "label": "Input capacitor", "devices": [ { "scope": "dut", "device": "XCI1" }, { "scope": "dut", "device": "XCI2" } ], "inferredStages": [ "bias" ] }, { "id": "block-3", "label": "Summing-node bias", "devices": [ { "scope": "dut", "device": "XRB1" }, { "scope": "dut", "device": "XRB2" } ], "inferredStages": [ "bias" ] }, { "id": "block-4", "label": "Feedback chopper", "devices": [ { "scope": "dut", "device": "XSF1n" }, { "scope": "dut", "device": "XSF1p" }, { "scope": "dut", "device": "XSF2n" }, { "scope": "dut", "device": "XSF2p" }, { "scope": "dut", "device": "XSF3n" }, { "scope": "dut", "device": "XSF3p" }, { "scope": "dut", "device": "XSF4n" }, { "scope": "dut", "device": "XSF4p" } ], "inferredStages": [ "bias" ] }, { "id": "block-5", "label": "Feedback capacitor", "devices": [ { "scope": "dut", "device": "XCF1" }, { "scope": "dut", "device": "XCF2" } ], "inferredStages": [ "bias" ] }, { "id": "block-6", "label": "Servo capacitor", "devices": [ { "scope": "dut", "device": "XCS1" }, { "scope": "dut", "device": "XCS2" } ], "inferredStages": [ "bias" ] }, { "id": "block-7", "label": "Servo chopper", "devices": [ { "scope": "dut", "device": "XSS1" }, { "scope": "dut", "device": "XSS2" }, { "scope": "dut", "device": "XSS3" }, { "scope": "dut", "device": "XSS4" } ], "inferredStages": [ "bias" ] }, { "id": "block-8", "label": "Bias reference", "devices": [ { "scope": "dut", "device": "XMB" } ], "inferredStages": [ "bias" ] }, { "id": "block-9", "label": "Bias", "devices": [ { "scope": "dut", "device": "XMB1" }, { "scope": "dut", "device": "XMB2" }, { "scope": "dut", "device": "XMB3" }, { "scope": "dut", "device": "XMB4" }, { "scope": "dut", "device": "XMB5" }, { "scope": "dut", "device": "XMB6" } ], "inferredStages": [ "bias" ] }, { "id": "block-10", "label": "Tail current source", "devices": [ { "scope": "dut", "device": "XMT" } ], "inferredStages": [ "bias" ] }, { "id": "block-11", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ "bias" ] }, { "id": "block-12", "label": "Fold current sink", "devices": [ { "scope": "dut", "device": "XM3" }, { "scope": "dut", "device": "XM4" } ], "inferredStages": [ "bias" ] }, { "id": "block-13", "label": "NMOS cascode", "devices": [ { "scope": "dut", "device": "XM5" }, { "scope": "dut", "device": "XM6" } ], "inferredStages": [ "bias" ] }, { "id": "block-14", "label": "First-stage load", "devices": [ { "scope": "dut", "device": "XM7" }, { "scope": "dut", "device": "XM8" } ], "inferredStages": [ "bias" ] }, { "id": "block-15", "label": "PMOS cascode", "devices": [ { "scope": "dut", "device": "XM9" }, { "scope": "dut", "device": "XM10" } ], "inferredStages": [ "bias" ] }, { "id": "block-16", "label": "Output chopper", "devices": [ { "scope": "dut", "device": "XSO1" }, { "scope": "dut", "device": "XSO2" }, { "scope": "dut", "device": "XSO3" }, { "scope": "dut", "device": "XSO4" } ], "inferredStages": [ "bias" ] }, { "id": "block-17", "label": "Second stage", "devices": [ { "scope": "dut", "device": "XM11" }, { "scope": "dut", "device": "XM12" } ], "inferredStages": [ "bias" ] }, { "id": "block-18", "label": "Second-stage current source", "devices": [ { "scope": "dut", "device": "XM13" }, { "scope": "dut", "device": "XM14" } ], "inferredStages": [ "bias" ] }, { "id": "block-19", "label": "Miller compensation", "devices": [ { "scope": "dut", "device": "XCC1" }, { "scope": "dut", "device": "XCC2" } ], "inferredStages": [ "bias" ] }, { "id": "block-20", "label": "Nulling resistor", "devices": [ { "scope": "dut", "device": "XRZ1" }, { "scope": "dut", "device": "XRZ2" } ], "inferredStages": [ "bias" ] }, { "id": "block-21", "label": "Common-mode sense: the outputs averaged on cms", "devices": [ { "scope": "dut", "device": "XRM1" }, { "scope": "dut", "device": "XRM2" } ], "inferredStages": [ "bias" ] }, { "id": "block-22", "label": "Common-mode sense", "devices": [ { "scope": "dut", "device": "XCM1" }, { "scope": "dut", "device": "XCM2" } ], "inferredStages": [ "bias" ] }, { "id": "block-23", "label": "CMFB pair", "devices": [ { "scope": "dut", "device": "XMC1" }, { "scope": "dut", "device": "XMC2" } ], "inferredStages": [ "bias" ] }, { "id": "block-24", "label": "CMFB tail", "devices": [ { "scope": "dut", "device": "XMC3" } ], "inferredStages": [ "bias" ] }, { "id": "block-25", "label": "CMFB load diode; M7 and M8 copy its current", "devices": [ { "scope": "dut", "device": "XMC4" } ], "inferredStages": [ "bias" ] }, { "id": "block-26", "label": "CMFB load diode", "devices": [ { "scope": "dut", "device": "XMC5" } ], "inferredStages": [ "bias" ] } ], "edges": [ { "id": "net-1", "net": "clk", "nodes": [ "block-1", "block-4", "block-7", "block-16" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "xp", "nodes": [ "block-1", "block-2" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "clkb", "nodes": [ "block-1", "block-4", "block-7", "block-16" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "xn", "nodes": [ "block-1", "block-2" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "sp", "nodes": [ "block-2", "block-3", "block-5", "block-7", "block-11" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "sn", "nodes": [ "block-2", "block-3", "block-5", "block-7", "block-11" ], "direction": "undirected-shared-net" }, { "id": "net-7", "net": "outp", "nodes": [ "block-4", "block-6", "block-17", "block-18", "block-20", "block-21", "block-22" ], "direction": "undirected-shared-net" }, { "id": "net-8", "net": "yp", "nodes": [ "block-4", "block-5" ], "direction": "undirected-shared-net" }, { "id": "net-9", "net": "outn", "nodes": [ "block-4", "block-6", "block-17", "block-18", "block-20", "block-21", "block-22" ], "direction": "undirected-shared-net" }, { "id": "net-10", "net": "yn", "nodes": [ "block-4", "block-5" ], "direction": "undirected-shared-net" }, { "id": "net-11", "net": "wp", "nodes": [ "block-6", "block-7" ], "direction": "undirected-shared-net" }, { "id": "net-12", "net": "wn", "nodes": [ "block-6", "block-7" ], "direction": "undirected-shared-net" }, { "id": "net-13", "net": "ib", "nodes": [ "block-8", "block-9", "block-10", "block-18" ], "direction": "undirected-shared-net" }, { "id": "net-14", "net": "nb", "nodes": [ "block-9", "block-12", "block-24" ], "direction": "undirected-shared-net" }, { "id": "net-15", "net": "vcp", "nodes": [ "block-9", "block-15" ], "direction": "undirected-shared-net" }, { "id": "net-16", "net": "vcn", "nodes": [ "block-9", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-17", "net": "tail", "nodes": [ "block-10", "block-11" ], "direction": "undirected-shared-net" }, { "id": "net-18", "net": "f1", "nodes": [ "block-11", "block-12", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-19", "net": "f2", "nodes": [ "block-11", "block-12", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-20", "net": "o1", "nodes": [ "block-13", "block-15", "block-16" ], "direction": "undirected-shared-net" }, { "id": "net-21", "net": "o2", "nodes": [ "block-13", "block-15", "block-16" ], "direction": "undirected-shared-net" }, { "id": "net-22", "net": "k1", "nodes": [ "block-14", "block-15" ], "direction": "undirected-shared-net" }, { "id": "net-23", "net": "vbl", "nodes": [ "block-14", "block-23", "block-25" ], "direction": "undirected-shared-net" }, { "id": "net-24", "net": "k2", "nodes": [ "block-14", "block-15" ], "direction": "undirected-shared-net" }, { "id": "net-25", "net": "g1", "nodes": [ "block-16", "block-17", "block-19" ], "direction": "undirected-shared-net" }, { "id": "net-26", "net": "g2", "nodes": [ "block-16", "block-17", "block-19" ], "direction": "undirected-shared-net" }, { "id": "net-27", "net": "z1", "nodes": [ "block-19", "block-20" ], "direction": "undirected-shared-net" }, { "id": "net-28", "net": "z2", "nodes": [ "block-19", "block-20" ], "direction": "undirected-shared-net" }, { "id": "net-29", "net": "cms", "nodes": [ "block-21", "block-22", "block-23" ], "direction": "undirected-shared-net" }, { "id": "net-30", "net": "ct", "nodes": [ "block-23", "block-24" ], "direction": "undirected-shared-net" }, { "id": "net-31", "net": "cx", "nodes": [ "block-23", "block-26" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "outp", "net": "outp", "kind": "output" }, { "name": "outn", "net": "outn", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" }, { "name": "vocm", "net": "vocm", "kind": "bias" }, { "name": "vicm", "net": "vicm", "kind": "bias" }, { "name": "clk", "net": "clk", "kind": "clock" }, { "name": "clkb", "net": "clkb", "kind": "clock" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ib ib 0 5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vocm vocm 0 dc 600m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 350m", "source": "Vicm vicm 0 dc 350m", "pins": [ { "id": "p", "net": "vicm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclk", "displayName": "Vclk", "spiceType": "V", "model": null, "parametersOrValue": "pulse({VDD} 0 25u 20n 20n 24.98u 50u)", "source": "Vclk clk 0 pulse({VDD} 0 25u 20n 20n 24.98u 50u)", "pins": [ { "id": "p", "net": "clk" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclkb", "displayName": "Vclkb", "spiceType": "V", "model": null, "parametersOrValue": "pulse(0 {VDD} 25u 20n 20n 24.98u 50u)", "source": "Vclkb clkb 0 pulse(0 {VDD} 25u 20n 20n 24.98u 50u)", "pins": [ { "id": "p", "net": "clkb" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vinp", "displayName": "Vinp", "spiceType": "V", "model": null, "parametersOrValue": "dc 602.5m", "source": "Vinp inp 0 dc 602.5m", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vinn", "displayName": "Vinn", "spiceType": "V", "model": null, "parametersOrValue": "dc 597.5m", "source": "Vinn inn 0 dc 597.5m", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "chopia", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 ib vocm vicm clk clkb chopia", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" }, { "id": "vocm", "net": "vocm" }, { "id": "vicm", "net": "vicm" }, { "id": "clk", "net": "clk" }, { "id": "clkb", "net": "clkb" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/chopia" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "1p", "source": "Clp outp 0 1p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "1p", "source": "Cln outn 0 1p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Vicm", "pin": "n" }, { "device": "Vclk", "pin": "n" }, { "device": "Vclkb", "pin": "n" }, { "device": "Vinp", "pin": "n" }, { "device": "Vinn", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" }, { "device": "Xdut", "pin": "vocm" } ], "ports": [], "voltageReferences": [] }, { "id": "vicm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Xdut", "pin": "vicm" } ], "ports": [], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "Vclk", "pin": "p" }, { "device": "Xdut", "pin": "clk" } ], "ports": [], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "Vclkb", "pin": "p" }, { "device": "Xdut", "pin": "clkb" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Vinp", "pin": "p" }, { "device": "Xdut", "pin": "inp" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Vinn", "pin": "p" }, { "device": "Xdut", "pin": "inn" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/chopia", "name": "chopia", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" }, { "name": "vocm", "net": "vocm" }, { "name": "vicm", "net": "vicm" }, { "name": "clk", "net": "clk" }, { "name": "clkb", "net": "clkb" } ], "definitions": [], "devices": [ { "id": "XSI1n", "displayName": "SI1n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI1n inp clk xp vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI1p", "displayName": "SI1p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI1p inp clkb xp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI2n", "displayName": "SI2n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI2n inn clk xn vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI2p", "displayName": "SI2p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI2p inn clkb xn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI3n", "displayName": "SI3n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI3n inp clkb xn vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI3p", "displayName": "SI3p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI3p inp clk xn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI4n", "displayName": "SI4n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI4n inn clkb xp vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI4p", "displayName": "SI4p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI4p inn clk xp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCI1", "displayName": "CI1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=8", "source": "XCI1 xp sp cap_cmim w=28.814u l=28.814u m=8", "pins": [ { "id": "p", "net": "xp" }, { "id": "n", "net": "sp" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCI2", "displayName": "CI2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=8", "source": "XCI2 xn sn cap_cmim w=28.814u l=28.814u m=8", "pins": [ { "id": "p", "net": "xn" }, { "id": "n", "net": "sn" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRB1", "displayName": "RB1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRB1 sp vicm vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "sp" }, { "id": "n", "net": "vicm" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRB2", "displayName": "RB2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRB2 sn vicm vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "sn" }, { "id": "n", "net": "vicm" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XSF1n", "displayName": "SF1n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF1n outp clk yp vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF1p", "displayName": "SF1p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF1p outp clkb yp vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF2n", "displayName": "SF2n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF2n outn clk yn vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF2p", "displayName": "SF2p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF2p outn clkb yn vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF3n", "displayName": "SF3n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF3n outp clkb yn vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF3p", "displayName": "SF3p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF3p outp clk yn vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF4n", "displayName": "SF4n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF4n outn clkb yp vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF4p", "displayName": "SF4p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF4p outn clk yp vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCF1", "displayName": "CF1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=18.204u l=18.204u", "source": "XCF1 yp sn cap_cmim w=18.204u l=18.204u", "pins": [ { "id": "p", "net": "yp" }, { "id": "n", "net": "sn" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCF2", "displayName": "CF2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=18.204u l=18.204u", "source": "XCF2 yn sp cap_cmim w=18.204u l=18.204u", "pins": [ { "id": "p", "net": "yn" }, { "id": "n", "net": "sp" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCS1", "displayName": "CS1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCS1 outp wp cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "wp" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCS2", "displayName": "CS2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCS2 outn wn cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "wn" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XSS1", "displayName": "SS1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS1 wp clk sn vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "sn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSS2", "displayName": "SS2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS2 wn clk sp vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "sp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSS3", "displayName": "SS3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS3 wp clkb sp vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "sp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSS4", "displayName": "SS4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS4 wn clkb sn vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "sn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB2 nb nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMB3 vcp vcp vdd vdd sg13_lv_pmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB4", "displayName": "MB4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB4 vcp nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB5", "displayName": "MB5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB5 vcn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB6", "displayName": "MB6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.6u l=4u ng=1 m=1", "source": "XMB6 vcn vcn vss vss sg13_lv_nmos w=1.6u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM1 f1 sp tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "sp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM2 f2 sn tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "sn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM5 o1 vcn f1 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM6 o2 vcn f2 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM7 k1 vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "vbl" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM8 k2 vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "vbl" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM9 o1 vcp k1 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM10 o2 vcp k2 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO1", "displayName": "SO1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO1 o1 clk g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO2", "displayName": "SO2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO2 o2 clk g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO3", "displayName": "SO3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO3 o1 clkb g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO4", "displayName": "SO4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO4 o2 clkb g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM11 outp g1 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "g1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM12 outn g2 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "g2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM13 outp ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM14 outn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC1 g1 z1 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC2 g2 z2 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRM1", "displayName": "RM1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XRM1 outp cms vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cms" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRM2", "displayName": "RM2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XRM2 outn cms vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cms" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCM1", "displayName": "CM1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XCM1 outp cms cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cms" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCM2", "displayName": "CM2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XCM2 outn cms cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cms" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XMC1 vbl cms ct vss sg13_lv_nmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbl" }, { "id": "g", "net": "cms" }, { "id": "s", "net": "ct" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XMC2 cx vocm ct vss sg13_lv_nmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cx" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "ct" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC3", "displayName": "MC3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XMC3 ct nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "ct" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC4", "displayName": "MC4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XMC4 vbl vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "vbl" }, { "id": "g", "net": "vbl" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC5", "displayName": "MC5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XMC5 cx cx vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "cx" }, { "id": "g", "net": "cx" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "inp", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "d" }, { "device": "XSI1p", "pin": "d" }, { "device": "XSI3n", "pin": "d" }, { "device": "XSI3p", "pin": "d" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "g" }, { "device": "XSI2n", "pin": "g" }, { "device": "XSI3p", "pin": "g" }, { "device": "XSI4p", "pin": "g" }, { "device": "XSF1n", "pin": "g" }, { "device": "XSF2n", "pin": "g" }, { "device": "XSF3p", "pin": "g" }, { "device": "XSF4p", "pin": "g" }, { "device": "XSS1", "pin": "g" }, { "device": "XSS2", "pin": "g" }, { "device": "XSO1", "pin": "g" }, { "device": "XSO2", "pin": "g" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "xp", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "s" }, { "device": "XSI1p", "pin": "s" }, { "device": "XSI4n", "pin": "s" }, { "device": "XSI4p", "pin": "s" }, { "device": "XCI1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "b" }, { "device": "XSI2n", "pin": "b" }, { "device": "XSI3n", "pin": "b" }, { "device": "XSI4n", "pin": "b" }, { "device": "XRB1", "pin": "substrate" }, { "device": "XRB2", "pin": "substrate" }, { "device": "XSF1n", "pin": "b" }, { "device": "XSF2n", "pin": "b" }, { "device": "XSF3n", "pin": "b" }, { "device": "XSF4n", "pin": "b" }, { "device": "XSS1", "pin": "b" }, { "device": "XSS2", "pin": "b" }, { "device": "XSS3", "pin": "b" }, { "device": "XSS4", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMB4", "pin": "s" }, { "device": "XMB4", "pin": "b" }, { "device": "XMB6", "pin": "s" }, { "device": "XMB6", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XSO1", "pin": "b" }, { "device": "XSO2", "pin": "b" }, { "device": "XSO3", "pin": "b" }, { "device": "XSO4", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XRZ1", "pin": "substrate" }, { "device": "XRZ2", "pin": "substrate" }, { "device": "XRM1", "pin": "substrate" }, { "device": "XRM2", "pin": "substrate" }, { "device": "XMC1", "pin": "b" }, { "device": "XMC2", "pin": "b" }, { "device": "XMC3", "pin": "s" }, { "device": "XMC3", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "XSI1p", "pin": "g" }, { "device": "XSI2p", "pin": "g" }, { "device": "XSI3n", "pin": "g" }, { "device": "XSI4n", "pin": "g" }, { "device": "XSF1p", "pin": "g" }, { "device": "XSF2p", "pin": "g" }, { "device": "XSF3n", "pin": "g" }, { "device": "XSF4n", "pin": "g" }, { "device": "XSS3", "pin": "g" }, { "device": "XSS4", "pin": "g" }, { "device": "XSO3", "pin": "g" }, { "device": "XSO4", "pin": "g" } ], "ports": [ "clkb" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XSI1p", "pin": "b" }, { "device": "XSI2p", "pin": "b" }, { "device": "XSI3p", "pin": "b" }, { "device": "XSI4p", "pin": "b" }, { "device": "XSF1p", "pin": "b" }, { "device": "XSF2p", "pin": "b" }, { "device": "XSF3p", "pin": "b" }, { "device": "XSF4p", "pin": "b" }, { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XMB5", "pin": "s" }, { "device": "XMB5", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" }, { "device": "XMC4", "pin": "s" }, { "device": "XMC4", "pin": "b" }, { "device": "XMC5", "pin": "s" }, { "device": "XMC5", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XSI2n", "pin": "d" }, { "device": "XSI2p", "pin": "d" }, { "device": "XSI4n", "pin": "d" }, { "device": "XSI4p", "pin": "d" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "xn", "ground": false, "terminals": [ { "device": "XSI2n", "pin": "s" }, { "device": "XSI2p", "pin": "s" }, { "device": "XSI3n", "pin": "s" }, { "device": "XSI3p", "pin": "s" }, { "device": "XCI2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "sp", "ground": false, "terminals": [ { "device": "XCI1", "pin": "n" }, { "device": "XRB1", "pin": "p" }, { "device": "XCF2", "pin": "n" }, { "device": "XSS2", "pin": "s" }, { "device": "XSS3", "pin": "s" }, { "device": "XM1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "sn", "ground": false, "terminals": [ { "device": "XCI2", "pin": "n" }, { "device": "XRB2", "pin": "p" }, { "device": "XCF1", "pin": "n" }, { "device": "XSS1", "pin": "s" }, { "device": "XSS4", "pin": "s" }, { "device": "XM2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vicm", "ground": false, "terminals": [ { "device": "XRB1", "pin": "n" }, { "device": "XRB2", "pin": "n" } ], "ports": [ "vicm" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XSF1n", "pin": "d" }, { "device": "XSF1p", "pin": "d" }, { "device": "XSF3n", "pin": "d" }, { "device": "XSF3p", "pin": "d" }, { "device": "XCS1", "pin": "p" }, { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XRZ1", "pin": "n" }, { "device": "XRM1", "pin": "p" }, { "device": "XCM1", "pin": "p" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "yp", "ground": false, "terminals": [ { "device": "XSF1n", "pin": "s" }, { "device": "XSF1p", "pin": "s" }, { "device": "XSF4n", "pin": "s" }, { "device": "XSF4p", "pin": "s" }, { "device": "XCF1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XSF2n", "pin": "d" }, { "device": "XSF2p", "pin": "d" }, { "device": "XSF4n", "pin": "d" }, { "device": "XSF4p", "pin": "d" }, { "device": "XCS2", "pin": "p" }, { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XRZ2", "pin": "n" }, { "device": "XRM2", "pin": "p" }, { "device": "XCM2", "pin": "p" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "yn", "ground": false, "terminals": [ { "device": "XSF2n", "pin": "s" }, { "device": "XSF2p", "pin": "s" }, { "device": "XSF3n", "pin": "s" }, { "device": "XSF3p", "pin": "s" }, { "device": "XCF2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "wp", "ground": false, "terminals": [ { "device": "XCS1", "pin": "n" }, { "device": "XSS1", "pin": "d" }, { "device": "XSS3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "wn", "ground": false, "terminals": [ { "device": "XCS2", "pin": "n" }, { "device": "XSS2", "pin": "d" }, { "device": "XSS4", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB5", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM13", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMB2", "pin": "d" }, { "device": "XMB2", "pin": "g" }, { "device": "XMB4", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XMC3", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" }, { "device": "XMB4", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB5", "pin": "d" }, { "device": "XMB6", "pin": "d" }, { "device": "XMB6", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM9", "pin": "d" }, { "device": "XSO1", "pin": "d" }, { "device": "XSO3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XSO2", "pin": "d" }, { "device": "XSO4", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vbl", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XMC1", "pin": "d" }, { "device": "XMC4", "pin": "d" }, { "device": "XMC4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "g1", "ground": false, "terminals": [ { "device": "XSO1", "pin": "s" }, { "device": "XSO4", "pin": "s" }, { "device": "XM11", "pin": "g" }, { "device": "XCC1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "g2", "ground": false, "terminals": [ { "device": "XSO2", "pin": "s" }, { "device": "XSO3", "pin": "s" }, { "device": "XM12", "pin": "g" }, { "device": "XCC2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z1", "ground": false, "terminals": [ { "device": "XCC1", "pin": "n" }, { "device": "XRZ1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z2", "ground": false, "terminals": [ { "device": "XCC2", "pin": "n" }, { "device": "XRZ2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cms", "ground": false, "terminals": [ { "device": "XRM1", "pin": "n" }, { "device": "XRM2", "pin": "n" }, { "device": "XCM1", "pin": "n" }, { "device": "XCM2", "pin": "n" }, { "device": "XMC1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "ct", "ground": false, "terminals": [ { "device": "XMC1", "pin": "s" }, { "device": "XMC2", "pin": "s" }, { "device": "XMC3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cx", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XMC5", "pin": "d" }, { "device": "XMC5", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XMC2", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/chopia" } }, { "id": "graph-5", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "chopia", "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "outp", "net": "outp", "kind": "output" }, { "name": "outn", "net": "outn", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" }, { "name": "vocm", "net": "vocm", "kind": "bias" }, { "name": "vicm", "net": "vicm", "kind": "bias" }, { "name": "clk", "net": "clk", "kind": "clock" }, { "name": "clkb", "net": "clkb", "kind": "clock" } ], "definitions": [], "devices": [ { "id": "XSI1n", "displayName": "SI1n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI1n inp clk xp vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI1p", "displayName": "SI1p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI1p inp clkb xp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI2n", "displayName": "SI2n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI2n inn clk xn vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI2p", "displayName": "SI2p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI2p inn clkb xn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI3n", "displayName": "SI3n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI3n inp clkb xn vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI3p", "displayName": "SI3p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI3p inp clk xn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI4n", "displayName": "SI4n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI4n inn clkb xp vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI4p", "displayName": "SI4p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI4p inn clk xp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCI1", "displayName": "CI1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=8", "source": "XCI1 xp sp cap_cmim w=28.814u l=28.814u m=8", "pins": [ { "id": "p", "net": "xp" }, { "id": "n", "net": "sp" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCI2", "displayName": "CI2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=8", "source": "XCI2 xn sn cap_cmim w=28.814u l=28.814u m=8", "pins": [ { "id": "p", "net": "xn" }, { "id": "n", "net": "sn" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRB1", "displayName": "RB1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRB1 sp vicm vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "sp" }, { "id": "n", "net": "vicm" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRB2", "displayName": "RB2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRB2 sn vicm vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "sn" }, { "id": "n", "net": "vicm" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XSF1n", "displayName": "SF1n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF1n outp clk yp vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF1p", "displayName": "SF1p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF1p outp clkb yp vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF2n", "displayName": "SF2n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF2n outn clk yn vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF2p", "displayName": "SF2p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF2p outn clkb yn vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF3n", "displayName": "SF3n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF3n outp clkb yn vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF3p", "displayName": "SF3p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF3p outp clk yn vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF4n", "displayName": "SF4n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF4n outn clkb yp vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF4p", "displayName": "SF4p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF4p outn clk yp vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCF1", "displayName": "CF1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=18.204u l=18.204u", "source": "XCF1 yp sn cap_cmim w=18.204u l=18.204u", "pins": [ { "id": "p", "net": "yp" }, { "id": "n", "net": "sn" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCF2", "displayName": "CF2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=18.204u l=18.204u", "source": "XCF2 yn sp cap_cmim w=18.204u l=18.204u", "pins": [ { "id": "p", "net": "yn" }, { "id": "n", "net": "sp" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCS1", "displayName": "CS1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCS1 outp wp cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "wp" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCS2", "displayName": "CS2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCS2 outn wn cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "wn" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XSS1", "displayName": "SS1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS1 wp clk sn vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "sn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSS2", "displayName": "SS2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS2 wn clk sp vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "sp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSS3", "displayName": "SS3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS3 wp clkb sp vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "sp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSS4", "displayName": "SS4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS4 wn clkb sn vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "sn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB2 nb nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMB3 vcp vcp vdd vdd sg13_lv_pmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB4", "displayName": "MB4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB4 vcp nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB5", "displayName": "MB5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB5 vcn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB6", "displayName": "MB6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.6u l=4u ng=1 m=1", "source": "XMB6 vcn vcn vss vss sg13_lv_nmos w=1.6u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM1 f1 gt tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "gt" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM2 f2 sn tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "sn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM5 o1 vcn f1 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM6 o2 vcn f2 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM7 k1 vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "vbl" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM8 k2 vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "vbl" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM9 o1 vcp k1 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM10 o2 vcp k2 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO1", "displayName": "SO1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO1 o1 clk g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO2", "displayName": "SO2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO2 o2 clk g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO3", "displayName": "SO3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO3 o1 clkb g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO4", "displayName": "SO4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO4 o2 clkb g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM11 outp g1 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "g1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM12 outn g2 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "g2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM13 outp ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM14 outn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC1 g1 z1 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC2 g2 z2 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRM1", "displayName": "RM1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XRM1 outp cms vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cms" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRM2", "displayName": "RM2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XRM2 outn cms vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cms" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCM1", "displayName": "CM1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XCM1 outp cms cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cms" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCM2", "displayName": "CM2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XCM2 outn cms cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cms" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XMC1 vbl cms ct vss sg13_lv_nmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbl" }, { "id": "g", "net": "cms" }, { "id": "s", "net": "ct" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XMC2 cx vocm ct vss sg13_lv_nmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cx" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "ct" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC3", "displayName": "MC3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XMC3 ct nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "ct" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC4", "displayName": "MC4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XMC4 vbl vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "vbl" }, { "id": "g", "net": "vbl" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC5", "displayName": "MC5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XMC5 cx cx vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "cx" }, { "id": "g", "net": "cx" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "Vos", "displayName": "Vos", "spiceType": "V", "model": null, "parametersOrValue": "dc 2m", "source": "Vos gt sp dc 2m", "pins": [ { "id": "p", "net": "gt" }, { "id": "n", "net": "sp" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "inp", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "d" }, { "device": "XSI1p", "pin": "d" }, { "device": "XSI3n", "pin": "d" }, { "device": "XSI3p", "pin": "d" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "g" }, { "device": "XSI2n", "pin": "g" }, { "device": "XSI3p", "pin": "g" }, { "device": "XSI4p", "pin": "g" }, { "device": "XSF1n", "pin": "g" }, { "device": "XSF2n", "pin": "g" }, { "device": "XSF3p", "pin": "g" }, { "device": "XSF4p", "pin": "g" }, { "device": "XSS1", "pin": "g" }, { "device": "XSS2", "pin": "g" }, { "device": "XSO1", "pin": "g" }, { "device": "XSO2", "pin": "g" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "xp", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "s" }, { "device": "XSI1p", "pin": "s" }, { "device": "XSI4n", "pin": "s" }, { "device": "XSI4p", "pin": "s" }, { "device": "XCI1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "b" }, { "device": "XSI2n", "pin": "b" }, { "device": "XSI3n", "pin": "b" }, { "device": "XSI4n", "pin": "b" }, { "device": "XRB1", "pin": "substrate" }, { "device": "XRB2", "pin": "substrate" }, { "device": "XSF1n", "pin": "b" }, { "device": "XSF2n", "pin": "b" }, { "device": "XSF3n", "pin": "b" }, { "device": "XSF4n", "pin": "b" }, { "device": "XSS1", "pin": "b" }, { "device": "XSS2", "pin": "b" }, { "device": "XSS3", "pin": "b" }, { "device": "XSS4", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMB4", "pin": "s" }, { "device": "XMB4", "pin": "b" }, { "device": "XMB6", "pin": "s" }, { "device": "XMB6", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XSO1", "pin": "b" }, { "device": "XSO2", "pin": "b" }, { "device": "XSO3", "pin": "b" }, { "device": "XSO4", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XRZ1", "pin": "substrate" }, { "device": "XRZ2", "pin": "substrate" }, { "device": "XRM1", "pin": "substrate" }, { "device": "XRM2", "pin": "substrate" }, { "device": "XMC1", "pin": "b" }, { "device": "XMC2", "pin": "b" }, { "device": "XMC3", "pin": "s" }, { "device": "XMC3", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "XSI1p", "pin": "g" }, { "device": "XSI2p", "pin": "g" }, { "device": "XSI3n", "pin": "g" }, { "device": "XSI4n", "pin": "g" }, { "device": "XSF1p", "pin": "g" }, { "device": "XSF2p", "pin": "g" }, { "device": "XSF3n", "pin": "g" }, { "device": "XSF4n", "pin": "g" }, { "device": "XSS3", "pin": "g" }, { "device": "XSS4", "pin": "g" }, { "device": "XSO3", "pin": "g" }, { "device": "XSO4", "pin": "g" } ], "ports": [ "clkb" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XSI1p", "pin": "b" }, { "device": "XSI2p", "pin": "b" }, { "device": "XSI3p", "pin": "b" }, { "device": "XSI4p", "pin": "b" }, { "device": "XSF1p", "pin": "b" }, { "device": "XSF2p", "pin": "b" }, { "device": "XSF3p", "pin": "b" }, { "device": "XSF4p", "pin": "b" }, { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XMB5", "pin": "s" }, { "device": "XMB5", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" }, { "device": "XMC4", "pin": "s" }, { "device": "XMC4", "pin": "b" }, { "device": "XMC5", "pin": "s" }, { "device": "XMC5", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XSI2n", "pin": "d" }, { "device": "XSI2p", "pin": "d" }, { "device": "XSI4n", "pin": "d" }, { "device": "XSI4p", "pin": "d" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "xn", "ground": false, "terminals": [ { "device": "XSI2n", "pin": "s" }, { "device": "XSI2p", "pin": "s" }, { "device": "XSI3n", "pin": "s" }, { "device": "XSI3p", "pin": "s" }, { "device": "XCI2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "sp", "ground": false, "terminals": [ { "device": "XCI1", "pin": "n" }, { "device": "XRB1", "pin": "p" }, { "device": "XCF2", "pin": "n" }, { "device": "XSS2", "pin": "s" }, { "device": "XSS3", "pin": "s" }, { "device": "Vos", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "sn", "ground": false, "terminals": [ { "device": "XCI2", "pin": "n" }, { "device": "XRB2", "pin": "p" }, { "device": "XCF1", "pin": "n" }, { "device": "XSS1", "pin": "s" }, { "device": "XSS4", "pin": "s" }, { "device": "XM2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vicm", "ground": false, "terminals": [ { "device": "XRB1", "pin": "n" }, { "device": "XRB2", "pin": "n" } ], "ports": [ "vicm" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XSF1n", "pin": "d" }, { "device": "XSF1p", "pin": "d" }, { "device": "XSF3n", "pin": "d" }, { "device": "XSF3p", "pin": "d" }, { "device": "XCS1", "pin": "p" }, { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XRZ1", "pin": "n" }, { "device": "XRM1", "pin": "p" }, { "device": "XCM1", "pin": "p" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "yp", "ground": false, "terminals": [ { "device": "XSF1n", "pin": "s" }, { "device": "XSF1p", "pin": "s" }, { "device": "XSF4n", "pin": "s" }, { "device": "XSF4p", "pin": "s" }, { "device": "XCF1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XSF2n", "pin": "d" }, { "device": "XSF2p", "pin": "d" }, { "device": "XSF4n", "pin": "d" }, { "device": "XSF4p", "pin": "d" }, { "device": "XCS2", "pin": "p" }, { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XRZ2", "pin": "n" }, { "device": "XRM2", "pin": "p" }, { "device": "XCM2", "pin": "p" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "yn", "ground": false, "terminals": [ { "device": "XSF2n", "pin": "s" }, { "device": "XSF2p", "pin": "s" }, { "device": "XSF3n", "pin": "s" }, { "device": "XSF3p", "pin": "s" }, { "device": "XCF2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "wp", "ground": false, "terminals": [ { "device": "XCS1", "pin": "n" }, { "device": "XSS1", "pin": "d" }, { "device": "XSS3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "wn", "ground": false, "terminals": [ { "device": "XCS2", "pin": "n" }, { "device": "XSS2", "pin": "d" }, { "device": "XSS4", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB5", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM13", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMB2", "pin": "d" }, { "device": "XMB2", "pin": "g" }, { "device": "XMB4", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XMC3", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" }, { "device": "XMB4", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB5", "pin": "d" }, { "device": "XMB6", "pin": "d" }, { "device": "XMB6", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "gt", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "Vos", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM9", "pin": "d" }, { "device": "XSO1", "pin": "d" }, { "device": "XSO3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XSO2", "pin": "d" }, { "device": "XSO4", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vbl", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XMC1", "pin": "d" }, { "device": "XMC4", "pin": "d" }, { "device": "XMC4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "g1", "ground": false, "terminals": [ { "device": "XSO1", "pin": "s" }, { "device": "XSO4", "pin": "s" }, { "device": "XM11", "pin": "g" }, { "device": "XCC1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "g2", "ground": false, "terminals": [ { "device": "XSO2", "pin": "s" }, { "device": "XSO3", "pin": "s" }, { "device": "XM12", "pin": "g" }, { "device": "XCC2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z1", "ground": false, "terminals": [ { "device": "XCC1", "pin": "n" }, { "device": "XRZ1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z2", "ground": false, "terminals": [ { "device": "XCC2", "pin": "n" }, { "device": "XRZ2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cms", "ground": false, "terminals": [ { "device": "XRM1", "pin": "n" }, { "device": "XRM2", "pin": "n" }, { "device": "XCM1", "pin": "n" }, { "device": "XCM2", "pin": "n" }, { "device": "XMC1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "ct", "ground": false, "terminals": [ { "device": "XMC1", "pin": "s" }, { "device": "XMC2", "pin": "s" }, { "device": "XMC3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cx", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XMC5", "pin": "d" }, { "device": "XMC5", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XMC2", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ] }, { "id": "graph-6", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ib ib 0 5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vocm", "displayName": "Vocm", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vocm vocm 0 dc 600m", "pins": [ { "id": "p", "net": "vocm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vicm", "displayName": "Vicm", "spiceType": "V", "model": null, "parametersOrValue": "dc 350m", "source": "Vicm vicm 0 dc 350m", "pins": [ { "id": "p", "net": "vicm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclk", "displayName": "Vclk", "spiceType": "V", "model": null, "parametersOrValue": "pulse({VDD} 0 25u 20n 20n 24.98u 50u)", "source": "Vclk clk 0 pulse({VDD} 0 25u 20n 20n 24.98u 50u)", "pins": [ { "id": "p", "net": "clk" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclkb", "displayName": "Vclkb", "spiceType": "V", "model": null, "parametersOrValue": "pulse(0 {VDD} 25u 20n 20n 24.98u 50u)", "source": "Vclkb clkb 0 pulse(0 {VDD} 25u 20n 20n 24.98u 50u)", "pins": [ { "id": "p", "net": "clkb" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vinp", "displayName": "Vinp", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vinp inp 0 dc 600m", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vinn", "displayName": "Vinn", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vinn inn 0 dc 600m", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "chopia", "parametersOrValue": "", "source": "Xdut inp inn outp outn vdd 0 ib vocm vicm clk clkb chopia", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "outp", "net": "outp" }, { "id": "outn", "net": "outn" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" }, { "id": "vocm", "net": "vocm" }, { "id": "vicm", "net": "vicm" }, { "id": "clk", "net": "clk" }, { "id": "clkb", "net": "clkb" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/chopia" }, { "id": "Clp", "displayName": "Clp", "spiceType": "C", "model": null, "parametersOrValue": "1p", "source": "Clp outp 0 1p", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cln", "displayName": "Cln", "spiceType": "C", "model": null, "parametersOrValue": "1p", "source": "Cln outn 0 1p", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Vocm", "pin": "n" }, { "device": "Vicm", "pin": "n" }, { "device": "Vclk", "pin": "n" }, { "device": "Vclkb", "pin": "n" }, { "device": "Vinp", "pin": "n" }, { "device": "Vinn", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Clp", "pin": "n" }, { "device": "Cln", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "Vocm", "pin": "p" }, { "device": "Xdut", "pin": "vocm" } ], "ports": [], "voltageReferences": [] }, { "id": "vicm", "ground": false, "terminals": [ { "device": "Vicm", "pin": "p" }, { "device": "Xdut", "pin": "vicm" } ], "ports": [], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "Vclk", "pin": "p" }, { "device": "Xdut", "pin": "clk" } ], "ports": [], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "Vclkb", "pin": "p" }, { "device": "Xdut", "pin": "clkb" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Vinp", "pin": "p" }, { "device": "Xdut", "pin": "inp" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Vinn", "pin": "p" }, { "device": "Xdut", "pin": "inn" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outp" }, { "device": "Clp", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "outn" }, { "device": "Cln", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/chopia", "name": "chopia", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "outp", "net": "outp" }, { "name": "outn", "net": "outn" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" }, { "name": "vocm", "net": "vocm" }, { "name": "vicm", "net": "vicm" }, { "name": "clk", "net": "clk" }, { "name": "clkb", "net": "clkb" } ], "definitions": [], "devices": [ { "id": "XSI1n", "displayName": "SI1n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI1n inp clk xp vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI1p", "displayName": "SI1p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI1p inp clkb xp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI2n", "displayName": "SI2n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI2n inn clk xn vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI2p", "displayName": "SI2p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI2p inn clkb xn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI3n", "displayName": "SI3n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI3n inp clkb xn vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI3p", "displayName": "SI3p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI3p inp clk xn vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI4n", "displayName": "SI4n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSI4n inn clkb xp vss sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSI4p", "displayName": "SI4p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSI4p inn clk xp vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "inn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "xp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCI1", "displayName": "CI1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=8", "source": "XCI1 xp sp cap_cmim w=28.814u l=28.814u m=8", "pins": [ { "id": "p", "net": "xp" }, { "id": "n", "net": "sp" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCI2", "displayName": "CI2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=8", "source": "XCI2 xn sn cap_cmim w=28.814u l=28.814u m=8", "pins": [ { "id": "p", "net": "xn" }, { "id": "n", "net": "sn" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRB1", "displayName": "RB1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRB1 sp vicm vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "sp" }, { "id": "n", "net": "vicm" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRB2", "displayName": "RB2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRB2 sn vicm vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "sn" }, { "id": "n", "net": "vicm" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XSF1n", "displayName": "SF1n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF1n outp clk yp vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF1p", "displayName": "SF1p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF1p outp clkb yp vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF2n", "displayName": "SF2n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF2n outn clk yn vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF2p", "displayName": "SF2p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF2p outn clkb yn vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF3n", "displayName": "SF3n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF3n outp clkb yn vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF3p", "displayName": "SF3p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF3p outp clk yn vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yn" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF4n", "displayName": "SF4n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=300n l=130n ng=1 m=1", "source": "XSF4n outn clkb yp vss sg13_lv_nmos w=300n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSF4p", "displayName": "SF4p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=600n l=130n ng=1 m=1", "source": "XSF4p outn clk yp vdd sg13_lv_pmos w=600n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "yp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCF1", "displayName": "CF1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=18.204u l=18.204u", "source": "XCF1 yp sn cap_cmim w=18.204u l=18.204u", "pins": [ { "id": "p", "net": "yp" }, { "id": "n", "net": "sn" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCF2", "displayName": "CF2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=18.204u l=18.204u", "source": "XCF2 yn sp cap_cmim w=18.204u l=18.204u", "pins": [ { "id": "p", "net": "yn" }, { "id": "n", "net": "sp" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCS1", "displayName": "CS1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCS1 outp wp cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "wp" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCS2", "displayName": "CS2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=2", "source": "XCS2 outn wn cap_cmim w=25.767u l=25.767u m=2", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "wn" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XSS1", "displayName": "SS1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS1 wp clk sn vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "sn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSS2", "displayName": "SS2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS2 wn clk sp vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "sp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSS3", "displayName": "SS3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS3 wp clkb sp vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wp" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "sp" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSS4", "displayName": "SS4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSS4 wn clkb sn vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "wn" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "sn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB2 nb nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB3", "displayName": "MB3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMB3 vcp vcp vdd vdd sg13_lv_pmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB4", "displayName": "MB4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=1", "source": "XMB4 vcp nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB5", "displayName": "MB5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMB5 vcn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB6", "displayName": "MB6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.6u l=4u ng=1 m=1", "source": "XMB6 vcn vcn vss vss sg13_lv_nmos w=1.6u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vcn" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM1 f1 gt tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "gt" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM2 f2 sn tail vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "sn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM5 o1 vcn f1 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=500n ng=2 m=1", "source": "XM6 o2 vcn f2 vss sg13_lv_nmos w=8u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM7 k1 vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k1" }, { "id": "g", "net": "vbl" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM8 k2 vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "k2" }, { "id": "g", "net": "vbl" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM9 o1 vcp k1 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=500n ng=2 m=1", "source": "XM10 o2 vcp k2 vdd sg13_lv_pmos w=6u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "vcp" }, { "id": "s", "net": "k2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO1", "displayName": "SO1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO1 o1 clk g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO2", "displayName": "SO2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO2 o2 clk g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO3", "displayName": "SO3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO3 o1 clkb g2 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSO4", "displayName": "SO4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSO4 o2 clkb g1 vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "g1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM11 outp g1 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "g1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=800n l=2u ng=1 m=4", "source": "XM12 outn g2 vss vss sg13_lv_nmos w=800n l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "g2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM13 outp ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM14 outn ib vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC1", "displayName": "CC1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC1 g1 z1 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g1" }, { "id": "n", "net": "z1" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCC2", "displayName": "CC2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCC2 g2 z2 cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "g2" }, { "id": "n", "net": "z2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ1", "displayName": "RZ1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ1 z1 outp vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z1" }, { "id": "n", "net": "outp" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRZ2", "displayName": "RZ2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=23.355u", "source": "XRZ2 z2 outn vss rppd w=0.5u l=23.355u", "pins": [ { "id": "p", "net": "z2" }, { "id": "n", "net": "outn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRM1", "displayName": "RM1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XRM1 outp cms vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cms" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRM2", "displayName": "RM2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=308.725u", "source": "XRM2 outn cms vss rhigh w=0.5u l=308.725u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cms" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCM1", "displayName": "CM1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XCM1 outp cms cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "cms" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCM2", "displayName": "CM2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XCM2 outn cms cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "cms" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XMC1 vbl cms ct vss sg13_lv_nmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbl" }, { "id": "g", "net": "cms" }, { "id": "s", "net": "ct" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XMC2 cx vocm ct vss sg13_lv_nmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cx" }, { "id": "g", "net": "vocm" }, { "id": "s", "net": "ct" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC3", "displayName": "MC3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=2u ng=2 m=2", "source": "XMC3 ct nb vss vss sg13_lv_nmos w=8u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "ct" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC4", "displayName": "MC4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XMC4 vbl vbl vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "vbl" }, { "id": "g", "net": "vbl" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC5", "displayName": "MC5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XMC5 cx cx vdd vdd sg13_lv_pmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "cx" }, { "id": "g", "net": "cx" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "Vos", "displayName": "Vos", "spiceType": "V", "model": null, "parametersOrValue": "dc 2m", "source": "Vos gt sp dc 2m", "pins": [ { "id": "p", "net": "gt" }, { "id": "n", "net": "sp" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "inp", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "d" }, { "device": "XSI1p", "pin": "d" }, { "device": "XSI3n", "pin": "d" }, { "device": "XSI3p", "pin": "d" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "g" }, { "device": "XSI2n", "pin": "g" }, { "device": "XSI3p", "pin": "g" }, { "device": "XSI4p", "pin": "g" }, { "device": "XSF1n", "pin": "g" }, { "device": "XSF2n", "pin": "g" }, { "device": "XSF3p", "pin": "g" }, { "device": "XSF4p", "pin": "g" }, { "device": "XSS1", "pin": "g" }, { "device": "XSS2", "pin": "g" }, { "device": "XSO1", "pin": "g" }, { "device": "XSO2", "pin": "g" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "xp", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "s" }, { "device": "XSI1p", "pin": "s" }, { "device": "XSI4n", "pin": "s" }, { "device": "XSI4p", "pin": "s" }, { "device": "XCI1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XSI1n", "pin": "b" }, { "device": "XSI2n", "pin": "b" }, { "device": "XSI3n", "pin": "b" }, { "device": "XSI4n", "pin": "b" }, { "device": "XRB1", "pin": "substrate" }, { "device": "XRB2", "pin": "substrate" }, { "device": "XSF1n", "pin": "b" }, { "device": "XSF2n", "pin": "b" }, { "device": "XSF3n", "pin": "b" }, { "device": "XSF4n", "pin": "b" }, { "device": "XSS1", "pin": "b" }, { "device": "XSS2", "pin": "b" }, { "device": "XSS3", "pin": "b" }, { "device": "XSS4", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMB4", "pin": "s" }, { "device": "XMB4", "pin": "b" }, { "device": "XMB6", "pin": "s" }, { "device": "XMB6", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XSO1", "pin": "b" }, { "device": "XSO2", "pin": "b" }, { "device": "XSO3", "pin": "b" }, { "device": "XSO4", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XRZ1", "pin": "substrate" }, { "device": "XRZ2", "pin": "substrate" }, { "device": "XRM1", "pin": "substrate" }, { "device": "XRM2", "pin": "substrate" }, { "device": "XMC1", "pin": "b" }, { "device": "XMC2", "pin": "b" }, { "device": "XMC3", "pin": "s" }, { "device": "XMC3", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "XSI1p", "pin": "g" }, { "device": "XSI2p", "pin": "g" }, { "device": "XSI3n", "pin": "g" }, { "device": "XSI4n", "pin": "g" }, { "device": "XSF1p", "pin": "g" }, { "device": "XSF2p", "pin": "g" }, { "device": "XSF3n", "pin": "g" }, { "device": "XSF4n", "pin": "g" }, { "device": "XSS3", "pin": "g" }, { "device": "XSS4", "pin": "g" }, { "device": "XSO3", "pin": "g" }, { "device": "XSO4", "pin": "g" } ], "ports": [ "clkb" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XSI1p", "pin": "b" }, { "device": "XSI2p", "pin": "b" }, { "device": "XSI3p", "pin": "b" }, { "device": "XSI4p", "pin": "b" }, { "device": "XSF1p", "pin": "b" }, { "device": "XSF2p", "pin": "b" }, { "device": "XSF3p", "pin": "b" }, { "device": "XSF4p", "pin": "b" }, { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB3", "pin": "s" }, { "device": "XMB3", "pin": "b" }, { "device": "XMB5", "pin": "s" }, { "device": "XMB5", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" }, { "device": "XMC4", "pin": "s" }, { "device": "XMC4", "pin": "b" }, { "device": "XMC5", "pin": "s" }, { "device": "XMC5", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XSI2n", "pin": "d" }, { "device": "XSI2p", "pin": "d" }, { "device": "XSI4n", "pin": "d" }, { "device": "XSI4p", "pin": "d" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "xn", "ground": false, "terminals": [ { "device": "XSI2n", "pin": "s" }, { "device": "XSI2p", "pin": "s" }, { "device": "XSI3n", "pin": "s" }, { "device": "XSI3p", "pin": "s" }, { "device": "XCI2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "sp", "ground": false, "terminals": [ { "device": "XCI1", "pin": "n" }, { "device": "XRB1", "pin": "p" }, { "device": "XCF2", "pin": "n" }, { "device": "XSS2", "pin": "s" }, { "device": "XSS3", "pin": "s" }, { "device": "Vos", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "sn", "ground": false, "terminals": [ { "device": "XCI2", "pin": "n" }, { "device": "XRB2", "pin": "p" }, { "device": "XCF1", "pin": "n" }, { "device": "XSS1", "pin": "s" }, { "device": "XSS4", "pin": "s" }, { "device": "XM2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vicm", "ground": false, "terminals": [ { "device": "XRB1", "pin": "n" }, { "device": "XRB2", "pin": "n" } ], "ports": [ "vicm" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XSF1n", "pin": "d" }, { "device": "XSF1p", "pin": "d" }, { "device": "XSF3n", "pin": "d" }, { "device": "XSF3p", "pin": "d" }, { "device": "XCS1", "pin": "p" }, { "device": "XM11", "pin": "d" }, { "device": "XM13", "pin": "d" }, { "device": "XRZ1", "pin": "n" }, { "device": "XRM1", "pin": "p" }, { "device": "XCM1", "pin": "p" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "yp", "ground": false, "terminals": [ { "device": "XSF1n", "pin": "s" }, { "device": "XSF1p", "pin": "s" }, { "device": "XSF4n", "pin": "s" }, { "device": "XSF4p", "pin": "s" }, { "device": "XCF1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XSF2n", "pin": "d" }, { "device": "XSF2p", "pin": "d" }, { "device": "XSF4n", "pin": "d" }, { "device": "XSF4p", "pin": "d" }, { "device": "XCS2", "pin": "p" }, { "device": "XM12", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XRZ2", "pin": "n" }, { "device": "XRM2", "pin": "p" }, { "device": "XCM2", "pin": "p" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "yn", "ground": false, "terminals": [ { "device": "XSF2n", "pin": "s" }, { "device": "XSF2p", "pin": "s" }, { "device": "XSF3n", "pin": "s" }, { "device": "XSF3p", "pin": "s" }, { "device": "XCF2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "wp", "ground": false, "terminals": [ { "device": "XCS1", "pin": "n" }, { "device": "XSS1", "pin": "d" }, { "device": "XSS3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "wn", "ground": false, "terminals": [ { "device": "XCS2", "pin": "n" }, { "device": "XSS2", "pin": "d" }, { "device": "XSS4", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB5", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM13", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMB2", "pin": "d" }, { "device": "XMB2", "pin": "g" }, { "device": "XMB4", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XMC3", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vcp", "ground": false, "terminals": [ { "device": "XMB3", "pin": "d" }, { "device": "XMB3", "pin": "g" }, { "device": "XMB4", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vcn", "ground": false, "terminals": [ { "device": "XMB5", "pin": "d" }, { "device": "XMB6", "pin": "d" }, { "device": "XMB6", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "gt", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "Vos", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM9", "pin": "d" }, { "device": "XSO1", "pin": "d" }, { "device": "XSO3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XSO2", "pin": "d" }, { "device": "XSO4", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "k1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vbl", "ground": false, "terminals": [ { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XMC1", "pin": "d" }, { "device": "XMC4", "pin": "d" }, { "device": "XMC4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "k2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "g1", "ground": false, "terminals": [ { "device": "XSO1", "pin": "s" }, { "device": "XSO4", "pin": "s" }, { "device": "XM11", "pin": "g" }, { "device": "XCC1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "g2", "ground": false, "terminals": [ { "device": "XSO2", "pin": "s" }, { "device": "XSO3", "pin": "s" }, { "device": "XM12", "pin": "g" }, { "device": "XCC2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z1", "ground": false, "terminals": [ { "device": "XCC1", "pin": "n" }, { "device": "XRZ1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "z2", "ground": false, "terminals": [ { "device": "XCC2", "pin": "n" }, { "device": "XRZ2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "cms", "ground": false, "terminals": [ { "device": "XRM1", "pin": "n" }, { "device": "XRM2", "pin": "n" }, { "device": "XCM1", "pin": "n" }, { "device": "XCM2", "pin": "n" }, { "device": "XMC1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "ct", "ground": false, "terminals": [ { "device": "XMC1", "pin": "s" }, { "device": "XMC2", "pin": "s" }, { "device": "XMC3", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cx", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XMC5", "pin": "d" }, { "device": "XMC5", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vocm", "ground": false, "terminals": [ { "device": "XMC2", "pin": "g" } ], "ports": [ "vocm" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/chopia" } }, { "id": "graph-7", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Input chopper", "devices": [ { "scope": "dut", "device": "XSI1n" }, { "scope": "dut", "device": "XSI1p" }, { "scope": "dut", "device": "XSI2n" }, { "scope": "dut", "device": "XSI2p" }, { "scope": "dut", "device": "XSI3n" }, { "scope": "dut", "device": "XSI3p" }, { "scope": "dut", "device": "XSI4n" }, { "scope": "dut", "device": "XSI4p" } ], "inferredStages": [ 1 ] }, { "id": "block-2", "label": "Input capacitor", "devices": [ { "scope": "dut", "device": "XCI1" }, { "scope": "dut", "device": "XCI2" } ], "inferredStages": [ "bias" ] }, { "id": "block-3", "label": "Summing-node bias", "devices": [ { "scope": "dut", "device": "XRB1" }, { "scope": "dut", "device": "XRB2" } ], "inferredStages": [ "bias" ] }, { "id": "block-4", "label": "Feedback chopper", "devices": [ { "scope": "dut", "device": "XSF1n" }, { "scope": "dut", "device": "XSF1p" }, { "scope": "dut", "device": "XSF2n" }, { "scope": "dut", "device": "XSF2p" }, { "scope": "dut", "device": "XSF3n" }, { "scope": "dut", "device": "XSF3p" }, { "scope": "dut", "device": "XSF4n" }, { "scope": "dut", "device": "XSF4p" } ], "inferredStages": [ "bias" ] }, { "id": "block-5", "label": "Feedback capacitor", "devices": [ { "scope": "dut", "device": "XCF1" }, { "scope": "dut", "device": "XCF2" } ], "inferredStages": [ "bias" ] }, { "id": "block-6", "label": "Servo capacitor", "devices": [ { "scope": "dut", "device": "XCS1" }, { "scope": "dut", "device": "XCS2" } ], "inferredStages": [ "bias" ] }, { "id": "block-7", "label": "Servo chopper", "devices": [ { "scope": "dut", "device": "XSS1" }, { "scope": "dut", "device": "XSS2" }, { "scope": "dut", "device": "XSS3" }, { "scope": "dut", "device": "XSS4" } ], "inferredStages": [ "bias" ] }, { "id": "block-8", "label": "Bias reference", "devices": [ { "scope": "dut", "device": "XMB" } ], "inferredStages": [ "bias" ] }, { "id": "block-9", "label": "Bias", "devices": [ { "scope": "dut", "device": "XMB1" }, { "scope": "dut", "device": "XMB2" }, { "scope": "dut", "device": "XMB3" }, { "scope": "dut", "device": "XMB4" }, { "scope": "dut", "device": "XMB5" }, { "scope": "dut", "device": "XMB6" } ], "inferredStages": [ "bias" ] }, { "id": "block-10", "label": "Tail current source", "devices": [ { "scope": "dut", "device": "XMT" } ], "inferredStages": [ "bias" ] }, { "id": "block-11", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ "bias" ] }, { "id": "block-12", "label": "Fold current sink", "devices": [ { "scope": "dut", "device": "XM3" }, { "scope": "dut", "device": "XM4" } ], "inferredStages": [ "bias" ] }, { "id": "block-13", "label": "NMOS cascode", "devices": [ { "scope": "dut", "device": "XM5" }, { "scope": "dut", "device": "XM6" } ], "inferredStages": [ "bias" ] }, { "id": "block-14", "label": "First-stage load", "devices": [ { "scope": "dut", "device": "XM7" }, { "scope": "dut", "device": "XM8" } ], "inferredStages": [ "bias" ] }, { "id": "block-15", "label": "PMOS cascode", "devices": [ { "scope": "dut", "device": "XM9" }, { "scope": "dut", "device": "XM10" } ], "inferredStages": [ "bias" ] }, { "id": "block-16", "label": "Output chopper", "devices": [ { "scope": "dut", "device": "XSO1" }, { "scope": "dut", "device": "XSO2" }, { "scope": "dut", "device": "XSO3" }, { "scope": "dut", "device": "XSO4" } ], "inferredStages": [ "bias" ] }, { "id": "block-17", "label": "Second stage", "devices": [ { "scope": "dut", "device": "XM11" }, { "scope": "dut", "device": "XM12" } ], "inferredStages": [ "bias" ] }, { "id": "block-18", "label": "Second-stage current source", "devices": [ { "scope": "dut", "device": "XM13" }, { "scope": "dut", "device": "XM14" } ], "inferredStages": [ "bias" ] }, { "id": "block-19", "label": "Miller compensation", "devices": [ { "scope": "dut", "device": "XCC1" }, { "scope": "dut", "device": "XCC2" } ], "inferredStages": [ "bias" ] }, { "id": "block-20", "label": "Nulling resistor", "devices": [ { "scope": "dut", "device": "XRZ1" }, { "scope": "dut", "device": "XRZ2" } ], "inferredStages": [ "bias" ] }, { "id": "block-21", "label": "Common-mode sense: the outputs averaged on cms", "devices": [ { "scope": "dut", "device": "XRM1" }, { "scope": "dut", "device": "XRM2" } ], "inferredStages": [ "bias" ] }, { "id": "block-22", "label": "Common-mode sense", "devices": [ { "scope": "dut", "device": "XCM1" }, { "scope": "dut", "device": "XCM2" } ], "inferredStages": [ "bias" ] }, { "id": "block-23", "label": "CMFB pair", "devices": [ { "scope": "dut", "device": "XMC1" }, { "scope": "dut", "device": "XMC2" } ], "inferredStages": [ "bias" ] }, { "id": "block-24", "label": "CMFB tail", "devices": [ { "scope": "dut", "device": "XMC3" } ], "inferredStages": [ "bias" ] }, { "id": "block-25", "label": "CMFB load diode; M7 and M8 copy its current", "devices": [ { "scope": "dut", "device": "XMC4" } ], "inferredStages": [ "bias" ] }, { "id": "block-26", "label": "CMFB load diode", "devices": [ { "scope": "dut", "device": "XMC5" } ], "inferredStages": [ "bias" ] }, { "id": "block-27", "label": "source", "devices": [ { "scope": "dut", "device": "Vos" } ], "inferredStages": [ "bias" ] } ], "edges": [ { "id": "net-1", "net": "clk", "nodes": [ "block-1", "block-4", "block-7", "block-16" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "xp", "nodes": [ "block-1", "block-2" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "clkb", "nodes": [ "block-1", "block-4", "block-7", "block-16" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "xn", "nodes": [ "block-1", "block-2" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "sp", "nodes": [ "block-2", "block-3", "block-5", "block-7", "block-27" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "sn", "nodes": [ "block-2", "block-3", "block-5", "block-7", "block-11" ], "direction": "undirected-shared-net" }, { "id": "net-7", "net": "outp", "nodes": [ "block-4", "block-6", "block-17", "block-18", "block-20", "block-21", "block-22" ], "direction": "undirected-shared-net" }, { "id": "net-8", "net": "yp", "nodes": [ "block-4", "block-5" ], "direction": "undirected-shared-net" }, { "id": "net-9", "net": "outn", "nodes": [ "block-4", "block-6", "block-17", "block-18", "block-20", "block-21", "block-22" ], "direction": "undirected-shared-net" }, { "id": "net-10", "net": "yn", "nodes": [ "block-4", "block-5" ], "direction": "undirected-shared-net" }, { "id": "net-11", "net": "wp", "nodes": [ "block-6", "block-7" ], "direction": "undirected-shared-net" }, { "id": "net-12", "net": "wn", "nodes": [ "block-6", "block-7" ], "direction": "undirected-shared-net" }, { "id": "net-13", "net": "ib", "nodes": [ "block-8", "block-9", "block-10", "block-18" ], "direction": "undirected-shared-net" }, { "id": "net-14", "net": "nb", "nodes": [ "block-9", "block-12", "block-24" ], "direction": "undirected-shared-net" }, { "id": "net-15", "net": "vcp", "nodes": [ "block-9", "block-15" ], "direction": "undirected-shared-net" }, { "id": "net-16", "net": "vcn", "nodes": [ "block-9", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-17", "net": "tail", "nodes": [ "block-10", "block-11" ], "direction": "undirected-shared-net" }, { "id": "net-18", "net": "f1", "nodes": [ "block-11", "block-12", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-19", "net": "gt", "nodes": [ "block-11", "block-27" ], "direction": "undirected-shared-net" }, { "id": "net-20", "net": "f2", "nodes": [ "block-11", "block-12", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-21", "net": "o1", "nodes": [ "block-13", "block-15", "block-16" ], "direction": "undirected-shared-net" }, { "id": "net-22", "net": "o2", "nodes": [ "block-13", "block-15", "block-16" ], "direction": "undirected-shared-net" }, { "id": "net-23", "net": "k1", "nodes": [ "block-14", "block-15" ], "direction": "undirected-shared-net" }, { "id": "net-24", "net": "vbl", "nodes": [ "block-14", "block-23", "block-25" ], "direction": "undirected-shared-net" }, { "id": "net-25", "net": "k2", "nodes": [ "block-14", "block-15" ], "direction": "undirected-shared-net" }, { "id": "net-26", "net": "g1", "nodes": [ "block-16", "block-17", "block-19" ], "direction": "undirected-shared-net" }, { "id": "net-27", "net": "g2", "nodes": [ "block-16", "block-17", "block-19" ], "direction": "undirected-shared-net" }, { "id": "net-28", "net": "z1", "nodes": [ "block-19", "block-20" ], "direction": "undirected-shared-net" }, { "id": "net-29", "net": "z2", "nodes": [ "block-19", "block-20" ], "direction": "undirected-shared-net" }, { "id": "net-30", "net": "cms", "nodes": [ "block-21", "block-22", "block-23" ], "direction": "undirected-shared-net" }, { "id": "net-31", "net": "ct", "nodes": [ "block-23", "block-24" ], "direction": "undirected-shared-net" }, { "id": "net-32", "net": "cx", "nodes": [ "block-23", "block-26" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "outp", "net": "outp", "kind": "output" }, { "name": "outn", "net": "outn", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" }, { "name": "vocm", "net": "vocm", "kind": "bias" }, { "name": "vicm", "net": "vicm", "kind": "bias" }, { "name": "clk", "net": "clk", "kind": "clock" }, { "name": "clkb", "net": "clkb", "kind": "clock" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." } ], "views": [ { "bench": "op", "source": { "recordField": "testbenches", "id": "op", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ia-chopper-cc/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Capacitively coupled chopper instrumentation amplifier", "instances": [] } ] }, "benchDiagram": { "graph": "graph-2", "svg": { "url": "/circuits/ia-chopper-cc/op-bench.svg", "asset": "op-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ia-chopper-cc/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "chop", "source": { "recordField": "testbenches", "id": "chop", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ia-chopper-cc/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Capacitively coupled chopper instrumentation amplifier", "instances": [] } ] }, "benchDiagram": { "graph": "graph-4", "svg": { "url": "/circuits/ia-chopper-cc/chop-bench.svg", "asset": "chop-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ia-chopper-cc/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "offset", "source": { "recordField": "testbenches", "id": "offset", "field": "netlist" }, "schematic": { "graph": "graph-5", "svg": { "url": "/circuits/ia-chopper-cc/offset-schematic.svg", "asset": "offset-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Capacitively coupled chopper instrumentation amplifier", "instances": [] } ] }, "benchDiagram": { "graph": "graph-6", "svg": { "url": "/circuits/ia-chopper-cc/offset-bench.svg", "asset": "offset-bench.svg" } }, "blockDiagram": { "graph": "graph-7", "electricalGraph": "graph-5", "svg": { "url": "/circuits/ia-chopper-cc/offset-block.svg", "asset": "offset-block.svg" } } } ] } }