{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "inverter-quantizer", "name": "Inverter quantizer", "group": "Comparators", "subgroup": "Continuous-time", "title": "Inverter quantizer", "summary": "A CMOS inverter can make a simple voltage decision: low input gives high output, and high input gives low output. Transistor sizing sets its approximate switching point. Unlike a comparator with a separate reference, that threshold moves with supply, temperature and process.", "reference": { "kind": "book", "authors": "J. M. Rabaey, A. Chandrakasan, B. Nikolić", "title": "Digital Integrated Circuits: A Design Perspective", "edition": "2nd ed.", "publisher": "Prentice Hall", "year": 2003, "where": "Ch. 5 'The CMOS Inverter': its voltage-transfer characteristic, switching threshold V_M and gain in the transition region", "takes": "The CMOS inverter and the result that its switching threshold is set by the pull-up to pull-down strength ratio, with the transition's steepness set by the gain there - which is what lets it serve as a one-bit quantizer against a threshold of its own. The sizing is this library's, for SG13G2 at 1.2 V." }, "resources": { "record": "/circuits/inverter-quantizer.json", "page": "/index.html#inverter-quantizer", "achieved": "/achieved/inverter-quantizer.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice" ], "ports": [ { "name": "in", "kind": "input" }, { "name": "out", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" } ], "devices": [ { "name": "M1", "type": "nmos", "nodes": "out in vss vss", "sizedBy": [ "Wn", "L", "M" ], "role": "pull-down", "fingers": 1, "copies": 2 }, { "name": "M2", "type": "pmos", "nodes": "out in vdd vdd", "sizedBy": [ "Wp", "L", "M" ], "role": "pull-up", "fingers": 1, "copies": 2 } ], "intent": [ { "rule": "ratio", "of": [ "M1", "M2" ], "constraint": "W_p/W_n sets V_M = V_DD/2", "why": "The threshold is where the two devices carry equal current: the width ratio is the reference, so it is chosen to put V_M in the middle of the supply at the typical corner, where a flash converter's ladder would expect it." }, { "rule": "match", "of": [ "M1", "M2" ], "constraint": "one length for both", "why": "Short-channel effects move each device's threshold with its length; at one length they move together, and V_M holds its place better than with two." }, { "rule": "gain", "of": [ "M1", "M2" ], "constraint": "|A_v| = (g_m1 + g_m2)(r_o1 ∥ r_o2) at V_M", "why": "The inverter's gain at its threshold decides how close an input can come to V_M and still give a logic level: a longer channel raises it, and slows the output." } ], "specs": [ { "key": "vth_rel", "label": "Threshold, in V_DD", "unit": "%", "direction": "target", "constraint": ">= 45 %, <= 55 %", "min": 45, "max": 55, "why": "The threshold in the middle of the supply: 50 % at tt, by the width ratio. A skewed corner strengthens one device against the other and moves it by 3 %; the supply moves it with itself, which is why it is quoted as a fraction of V_DD." }, { "key": "v_band", "label": "Transition width, 10-90 %", "unit": "V", "direction": "min", "constraint": "<= 0.12 V", "min": null, "max": 0.12, "why": "The input span over which the output is neither a 0 nor a 1, about V_DD over the inverter's gain: 78 mV at tt, widest at 125 °C." }, { "key": "t_dec", "label": "Decision time", "unit": "s", "direction": "min", "constraint": "<= 2.5e-10 s", "min": null, "max": 2.5e-10, "why": "100 mV past the threshold into 10 fF: two copies of a minimum inverter decide in about 110 ps, and in under 200 ps at the slowest corner." }, { "key": "t_dec_small", "label": "Decision time, smallest overdrive", "unit": "s", "direction": "min", "constraint": "<= 1e-9 s", "min": null, "max": 1e-9, "why": "20 mV past the threshold the inverter's gain drives the output only a few hundred millivolts past half the supply, with a fraction of the current: about three times the time." }, { "key": "voh", "label": "Output high level", "unit": "V", "direction": "max", "constraint": ">= 1.05 V", "min": 1.05, "max": null, "why": "A logic level: the output reaches the supply when the input is well below the threshold, at every supply the corners take it to." }, { "key": "vol", "label": "Output low level", "unit": "V", "direction": "min", "constraint": "<= 0.05 V", "min": null, "max": 0.05, "why": "And ground when it is well above." }, { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.000001 A", "min": null, "max": 0.000001, "why": "Only a small residual current remains once the input is 0.4 V from the switching point; leakage grows at high temperature and the fast corner." } ], "explanation": { "idea": "A CMOS inverter can make a simple voltage decision: low input gives high output, and high input gives low output. Transistor sizing sets its approximate switching point. Unlike a comparator with a separate reference, that threshold moves with supply, temperature and process.", "detail": "A comparator made of one CMOS inverter. Its threshold is its own switching point V_M, where the pull-down M1 and the pull-up M2 carry the same current; near V_M both are saturated and the inverter has its full gain, so a sufficient input change drives the output towards a logic level. The nominal reference is established by relative transistor strengths, not an independent voltage reference. It moves with process, supply and temperature; mismatch moves individual devices' thresholds too.", "lesson": { "relation": 0, "symbols": "V_M is the inverter switching point; V_TN and V_TP are NMOS and PMOS threshold voltages; V_DD is supply voltage; β_n and β_p describe the devices' current strength; r is the square root of their ratio.", "assumptions": "This square-law estimate assumes both devices are saturated and ignores short-channel effects and output conductance. Use the simulated transfer for the actual 130 nm switching point and transition width.", "exercise": { "param": "Wp", "value": 0.000002, "analysis": "sweep", "expect": "A stronger PMOS pull-up should move the switching point to a higher input voltage. Compare the threshold and transition width with their default values." }, "limits": "There is no independent reference or input-pair common-mode rejection. Inputs near the switching point can produce intermediate output levels and substantial current. The 10–90% transition width is not a complete digital noise-margin specification." }, "path": [ { "part": "Pull-down", "devices": "M1", "does": "On once in rises past its threshold; it pulls out towards ground, harder the further in rises past V_M." }, { "part": "Pull-up", "devices": "M2", "does": "On while in is more than |V_TP| below V_DD; its width, 1.41 times M1's at one length, puts V_M in the middle of the supply." }, { "part": "Decision", "devices": "M1, M2", "does": "Near V_M both conduct and out moves steeply: an input a transition width past V_M gives a logic level, one closer leaves out in between." } ], "bias": "There is no separate bias generator: the supply and the two widths set V_M, about 0.60 V at nominal from 1.2 V. Both devices conduct near the switching point. Farther from it, one device is mostly off, but leakage remains: the nominal operating-point bench records about 21 nA at an input 0.4 V from V_M.", "relations": [ { "what": "Switching threshold", "expr": "V_M = (V_TN + r (V_DD − |V_TP|))/(1 + r), r = √(β_p/β_n)", "note": "square law; at 130 nm velocity saturation narrows the gap between the two devices, and W_p = 1.41 W_n centres V_M" }, { "what": "Gain at V_M", "expr": "A_v = −(g_m1 + g_m2)(r_o1 ∥ r_o2)", "note": "it sets how steep the transfer is at the threshold" }, { "what": "Transition width", "expr": "ΔV_in(10–90 %) ≈ 0.8 V_DD/|A_v|", "note": "the output moves from 90% to 10% of supply over about 78 mV of input at nominal, a total band roughly centred on V_M; this is not a separately established logic noise-margin criterion" }, { "what": "Decision time", "expr": "t_d ≈ C_L (V_DD/2)/I_D", "note": "I_D at the level the input steps to: 110 ps at 100 mV past V_M into 10 fF, 350 ps at 20 mV" }, { "what": "Supply sensitivity", "expr": "dV_M/dV_DD ≈ r/(1 + r) ≈ 0.5", "note": "the threshold follows the supply at half its rate: this quantizer rejects nothing on V_DD" } ], "tradeoffs": [ "Width ratio (Wp over Wn): sets V_M; the skewed process corners still move it by ±3 % of V_DD whatever the ratio, since they strengthen one device against the other.", "Copies (M): more copies drive the load faster and average the mismatch - the threshold's spread from it falls as 1/√M - at more input capacitance for whatever drives the input.", "Length (L): longer channels add area and capacitance but barely steepen the transition, which the devices leaving saturation near the rails set as much as the gain at V_M does." ] }, "sizing": [ { "key": "Wn", "label": "W pull-down (M1)", "unit": "m", "value": 0.000001, "min": 1.5e-7, "max": 0.00002, "kind": "si" }, { "key": "Wp", "label": "W pull-up (M2)", "unit": "m", "value": 0.00000141, "min": 1.5e-7, "max": 0.00004, "kind": "si" }, { "key": "L", "label": "L, both", "unit": "m", "value": 1.3e-7, "min": 1.3e-7, "max": 0.000002, "kind": "si" }, { "key": "M", "label": "Copies of the pair", "unit": "", "value": 2, "min": 1, "max": 16, "kind": "int" }, { "key": "CL", "label": "Load capacitance", "unit": "F", "value": 1e-14, "min": 1e-15, "max": 5e-13, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Decided states", "note": "The comparator with its input well past its thresholds, each way: the output levels and the current it draws in each state.", "measures": [], "metricKeys": [ "voh", "vol", "i_supply" ], "acceptance": [ "voh", "vol", "i_supply" ], "acceptanceRules": [ { "key": "voh", "unit": "V", "min": 1.05, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "vol", "unit": "V", "min": null, "max": 0.05, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "i_supply", "unit": "A", "min": null, "max": 0.000001, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Inverter quantizer - decided states\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n.subckt invq in out vdd vss\n* pull-down and pull-up: out falls as in rises past V_M\nXM1 out in vss vss sg13_lv_nmos w=1u l=130n ng=1 m=2\nXM2 out in vdd vdd sg13_lv_pmos w=1.41u l=130n ng=1 m=2\n.ends\nXdut in out vdd 0 invq\nCl out 0 10f\nVin in 0 dc 1\n* two points: V_in 400mV below its nominal threshold, and 400mV above\n.dc Vin 200m 1 800m\n.end" }, { "id": "sweep", "label": "Thresholds", "note": "V_in swept slowly across its thresholds, up and back down: where the output flips each way, the hysteresis between them, and the threshold at their midpoint.", "measures": [], "metricKeys": [ "vtrip_hi", "vtrip_lo", "v_hyst", "vth", "vth_rel", "v_band" ], "acceptance": [ "vth_rel", "v_band" ], "acceptanceRules": [ { "key": "vth_rel", "unit": "%", "min": 45, "max": 55, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "v_band", "unit": "V", "min": null, "max": 0.12, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Inverter quantizer - thresholds, V_in swept slowly up and back down\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n.subckt invq in out vdd vss\n* pull-down and pull-up: out falls as in rises past V_M\nXM1 out in vss vss sg13_lv_nmos w=1u l=130n ng=1 m=2\nXM2 out in vdd vdd sg13_lv_pmos w=1.41u l=130n ng=1 m=2\n.ends\nXdut in out vdd 0 invq\nCl out 0 10f\nVin in 0 pwl(0 250m 10u 950m 20u 250m)\n.tran 5n 20u\n.end" }, { "id": "delay", "label": "Decision time", "note": "The thresholds found first; then, for each overdrive from 20 mV to 300 mV, a step past each of them from 400 mV the other side, timed to the output at half the supply. 6 runs.", "measures": [], "metricKeys": [ "t_dec", "t_dec_small" ], "acceptance": [ "t_dec", "t_dec_small" ], "acceptanceRules": [ { "key": "t_dec", "unit": "s", "min": null, "max": 2.5e-10, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "t_dec_small", "unit": "s", "min": null, "max": 1e-9, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Inverter quantizer - decision time at 100 mV overdrive\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n.subckt invq in out vdd vss\n* pull-down and pull-up: out falls as in rises past V_M\nXM1 out in vss vss sg13_lv_nmos w=1u l=130n ng=1 m=2\nXM2 out in vdd vdd sg13_lv_pmos w=1.41u l=130n ng=1 m=2\n.ends\nXdut in out vdd 0 invq\nCl out 0 10f\n* 400 mV below the lower threshold, a step to 100 mV past the upper one, then to 100 mV past the lower\nVin in 0 pwl(0 200m 2n 200m 2.02n 700m 22n 700m 22.02n 500m 42n 500m)\n.tran 5p 42n\n.end" } ], "measurements": { "vth_rel": { "label": "Threshold, in V_DD", "unit": "%", "spec": { "min": 45, "max": 55 } }, "v_band": { "label": "Transition width, 10-90 %", "unit": "V", "spec": { "min": null, "max": 0.12 } }, "t_dec": { "label": "Decision time", "unit": "s", "spec": { "min": null, "max": 2.5e-10 } }, "t_dec_small": { "label": "Decision time, smallest overdrive", "unit": "s", "spec": { "min": null, "max": 1e-9 } }, "voh": { "label": "Output high level", "unit": "V", "spec": { "min": 1.05, "max": null } }, "vol": { "label": "Output low level", "unit": "V", "spec": { "min": null, "max": 0.05 } }, "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.000001 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "c2ff5f020afdd1dcc0da4ffa7bafd129feea57e2a8c0a1fe1f2b24dc11ec8ae8" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/inverter-quantizer.js", "sha256": "d3768e0b5e89469ac75fd35a6f5872f9b16ff72d27f50995bb410d9f173b10fc" }, "simulationFingerprints": { "op": "3bb14aeea65c8e36b198f8e9b6245fd2c3b64ada265ac4f14e8276fbac84bb28", "sweep": "d5d0f578fc6f4471c8c49b0788639168a5b3f63fa87899a717e176dad9e29f42", "delay": "ff014a966e90d6bfcefc8e7eaaecbd0b907f3f5f0d435a5892b2165b46c29076" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "152c8140dd2758faee011538290a4d67348188f6188fbf8b30adffda46625e25", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "inverter-quantizer", "parameters": { "Wn": 0.000001, "Wp": 0.00000141, "L": 1.3e-7, "M": 2, "CL": 1e-14 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/inverter-quantizer/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. 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