{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ldo-bufref-hv", "name": "Buffered-reference LDO, 2.5 V from 3.3 V", "group": "Voltage regulators", "subgroup": "LDOs", "title": "Buffered-reference LDO, 2.5 V from 3.3 V", "summary": "Regulates 3.3 V down to about 2.5 V. A buffer doubles and filters the reference before a two-stage error amplifier drives the PMOS pass device. High loop gain improves regulation, but the reference filter slows start-up and a large external output capacitor is required.", "reference": { "kind": "book", "authors": "G. A. Rincon-Mora", "title": "Analog IC Design with Low-Dropout Regulators", "edition": "2nd", "publisher": "McGraw-Hill", "year": 2014, "where": "the LDO's reference and error amplifier: buffering and filtering the reference, the error amplifier's gain stages and their compensation", "takes": "The topology: a reference buffer with gain, an RC filter after it, a two-stage error amplifier with a Miller network across its second stage, unity feedback, a PMOS pass device, an on-chip capacitor and a bleed on the output. The bias - every current a copy of one - the sizing and the specs are this library's, on SG13G2's 3.3 V devices." }, "resources": { "record": "/circuits/ldo-bufref-hv.json", "page": "/index.html#ldo-bufref-hv", "achieved": "/achieved/ldo-bufref-hv.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_hv_tt.spice", "url": "/sg13g2_hv_tt.spice", "sha256": "e9b858ad4f7bba550467f1eddb6ca496bcc5f4644474f41240d63927934928ad" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "ref", "kind": "input", "note": "the reference voltage, which the buffer doubles" }, { "name": "sense", "kind": "input", "note": "the output as the regulator reads it" }, { "name": "out", "kind": "output" }, { "name": "vdd", "kind": "supply", "note": "the unregulated 3.3 V input" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the bias current, driven into this pin" } ], "devices": [ { "name": "MB", "type": "nmos", "model": "sg13_hv_nmos", "nodes": "ib ib vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "bias reference, diode-connected", "fingers": 2, "copies": 1 }, { "name": "MTA", "type": "nmos", "model": "sg13_hv_nmos", "nodes": "ta ib vss vss", "sizedBy": [ "Wn", "Ln", "NA" ], "role": "buffer tail", "fingers": 2, "copies": 2 }, { "name": "MSA", "type": "nmos", "model": "sg13_hv_nmos", "nodes": "vbuf ib vss vss", "sizedBy": [ "Wn", "Ln", "NS" ], "role": "buffer second-stage sink", "fingers": 2, "copies": 4 }, { "name": "MTE", "type": "nmos", "model": "sg13_hv_nmos", "nodes": "te ib vss vss", "sizedBy": [ "Wn", "Ln", "NE" ], "role": "error amplifier tail", "fingers": 2, "copies": 4 }, { "name": "MSE", "type": "nmos", "model": "sg13_hv_nmos", "nodes": "gate ib vss vss", "sizedBy": [ "Wn", "Ln", "NK" ], "role": "error amplifier second-stage sink", "fingers": 2, "copies": 8 }, { "name": "MA1", "type": "nmos", "model": "sg13_hv_nmos", "nodes": "da fbb ta vss", "sizedBy": [ "WA1", "LA1" ], "role": "buffer input pair, the fed-back half", "fingers": 8, "copies": 1 }, { "name": "MA2", "type": "nmos", "model": "sg13_hv_nmos", "nodes": "xa ref ta vss", "sizedBy": [ "WA1", "LA1" ], "role": "buffer input pair, the reference", "fingers": 8, "copies": 1 }, { "name": "MA3", "type": "pmos", "model": "sg13_hv_pmos", "nodes": "da da vdd vdd", "sizedBy": [ "WA3", "LA3" ], "role": "buffer mirror, diode-connected", "fingers": 8, "copies": 1 }, { "name": "MA4", "type": "pmos", "model": "sg13_hv_pmos", "nodes": "xa da vdd vdd", "sizedBy": [ "WA3", "LA3" ], "role": "buffer mirror, first-stage output", "fingers": 8, "copies": 1 }, { "name": "MA5", "type": "pmos", "model": "sg13_hv_pmos", "nodes": "vbuf xa vdd vdd", "sizedBy": [ "WA3", "LA3", "NS", "NA" ], "role": "buffer second stage, common source", "fingers": 8, "copies": 4 }, { "name": "RzA", "type": "resistor", "nodes": "xa za", "sizedBy": [ "RzA" ], "role": "buffer zero resistor" }, { "name": "CcA", "type": "capacitor", "nodes": "za vbuf", "sizedBy": [ "CcA" ], "role": "buffer Miller capacitor" }, { "name": "RA1", "type": "resistor", "nodes": "vbuf fbb", "sizedBy": [ "Ru" ], "role": "buffer feedback, upper unit" }, { "name": "RA2", "type": "resistor", "nodes": "fbb vss", "sizedBy": [ "Ru" ], "role": "buffer feedback, lower unit" }, { "name": "Rf", "type": "resistor", "nodes": "vbuf vflt", "sizedBy": [ "Rf" ], "role": "reference filter resistor" }, { "name": "Cf", "type": "capacitor", "nodes": "vflt vss", "sizedBy": [ "Cf" ], "role": "reference filter capacitor" }, { "name": "ME1", "type": "nmos", "model": "sg13_hv_nmos", "nodes": "de vflt te vss", "sizedBy": [ "WE1", "LE1" ], "role": "error amplifier input pair, the filtered reference", "fingers": 16, "copies": 1 }, { "name": "ME2", "type": "nmos", "model": "sg13_hv_nmos", "nodes": "xe sense te vss", "sizedBy": [ "WE1", "LE1" ], "role": "error amplifier input pair, the output", "fingers": 16, "copies": 1 }, { "name": "ME3", "type": "pmos", "model": "sg13_hv_pmos", "nodes": "de de vdd vdd", "sizedBy": [ "WE3", "LE3" ], "role": "error amplifier mirror, diode-connected", "fingers": 8, "copies": 1 }, { "name": "ME4", "type": "pmos", "model": "sg13_hv_pmos", "nodes": "xe de vdd vdd", "sizedBy": [ "WE3", "LE3" ], "role": "error amplifier mirror, first-stage output", "fingers": 8, "copies": 1 }, { "name": "ME5", "type": "pmos", "model": "sg13_hv_pmos", "nodes": "gate xe vdd vdd", "sizedBy": [ "WE3", "LE3", "NK", "NE" ], "role": "error amplifier second stage, common source, drives the pass gate", "fingers": 8, "copies": 4 }, { "name": "RzE", "type": "resistor", "nodes": "xe ze", "sizedBy": [ "RzE" ], "role": "error amplifier zero resistor" }, { "name": "CcE", "type": "capacitor", "nodes": "ze gate", "sizedBy": [ "CcE" ], "role": "error amplifier Miller capacitor" }, { "name": "MP", "type": "pmos", "model": "sg13_hv_pmos", "nodes": "out gate vdd vdd", "sizedBy": [ "Wpass", "Lpass" ], "role": "pass device", "fingers": 120, "copies": 1 }, { "name": "Co", "type": "capacitor", "nodes": "out vss", "sizedBy": [ "Co" ], "role": "on-chip output capacitor" }, { "name": "Rb", "type": "resistor", "nodes": "out vss", "sizedBy": [ "Rb" ], "role": "bleed: the least MP always carries" } ], "intent": [ { "rule": "match", "of": [ "ME1", "ME2" ], "why": "The error amplifier's input pair: with unity feedback, its offset is the output's error one for one." }, { "rule": "match", "of": [ "MA1", "MA2" ], "why": "The buffer's input pair: its offset is doubled onto the output." }, { "rule": "unit-copies", "of": [ "RA1", "RA2" ], "constraint": "two copies of one resistor: vbuf = 2 V_ref", "why": "Only their ratio sets the output, so they are one resistor repeated, one material, matched." }, { "rule": "unit-copies", "of": [ "MB", "MTA", "MSA", "MTE", "MSE" ], "constraint": "every tail and sink a copy of MB", "why": "Referencing the tails and sinks to Ib reduces supply dependence compared with diode-only bias. Finite output resistance and other currents still vary with supply." }, { "rule": "ratio", "of": [ "MA5", "MA3", "ME5", "ME3" ], "constraint": "MA5 = 2 NS/NA copies of MA3's unit; ME5 = 2 NK/NE of ME3's", "why": "Each second stage carries its sink's current with the same current density as its mirror, to reduce systematic offset; finite output resistance, divider loading and mismatch leave residual error." }, { "rule": "integrator-zero", "of": [ "RzE", "CcE", "MP" ], "constraint": "1/(2π RzE CcE) well below the no-load crossover, g_m,ME2 RzE g_m,MP/(2π C_L)", "why": "Below the zero the error amplifier integrates and the output capacitor's pole adds a second 90°; the zero gives it back. The crossover falls with MP's transconductance, so the zero is placed against the no-load crossover." }, { "rule": "filter", "of": [ "Rf", "Cf" ], "constraint": "corner 1/(2π Rf Cf) of a few hundred hertz; Cf of 100 pF", "why": "Below the corner the buffer's and the reference's noise pass whole, above it they are attenuated; the filter leaves its own kT/Cf, 6 µV at 100 pF." }, { "rule": "buffer-loop", "of": [ "RzA", "CcA", "MA5" ], "constraint": "the buffer settles a reference step with no overshoot", "why": "The buffer's loop is not cut by any of the regulator's benches; its own bench holds it to settling without ringing." } ], "specs": [ { "key": "vout", "label": "Output voltage", "unit": "V", "direction": "target", "constraint": ">= 2.45 V, <= 2.55 V", "min": 2.45, "max": 2.55, "why": "Twice the 1.25 V reference, within ±2 %: the buffer's resistor ratio and offsets, and the error amplifier's." }, { "key": "i_q", "label": "Quiescent current", "unit": "A", "direction": "min", "constraint": "<= 0.00045 A", "min": null, "max": 0.00045, "why": "Two two-stage amplifiers and the 250 µA bleed; the amplifier currents referenced to Ib, with residual supply dependence from real devices." }, { "key": "load_reg", "label": "Load regulation", "unit": "V/A", "direction": "min", "constraint": "<= 0.02 V/A", "min": null, "max": 0.02, "why": "At most 0.2 mV from no load to 10 mA: the error amplifier integrates, so its DC gain is enormous." }, { "key": "line_reg", "label": "Line regulation", "unit": "%/V", "direction": "min", "constraint": "<= 0.02 %/V", "min": null, "max": 0.02, "why": "At most 0.33 mV across the rated 2.97 to 3.63 V input." }, { "key": "dropout", "label": "Dropout at full load", "unit": "V", "direction": "min", "constraint": "<= 0.3 V", "min": null, "max": 0.3, "why": "At 10 mA the output holds down to 2.8 V in: 0.17 V of margin below the lowest rated input." }, { "key": "loop_gain_db", "label": "DC loop gain at full load", "unit": "dB", "direction": "max", "constraint": ">= 80 dB", "min": 80, "max": null, "why": "The integrating error amplifier makes the DC loop gain as large as its own." }, { "key": "loop_ugf_hz", "label": "Loop crossover at full load", "unit": "Hz", "direction": "max", "constraint": ">= 50000 Hz", "min": 50000, "max": null, "why": "g_m,ME2 RzE g_m,MP over the output capacitance, at full load; lower at light load." }, { "key": "loop_pm_deg", "label": "Loop phase margin, worst load", "unit": "deg", "direction": "max", "constraint": ">= 60 deg", "min": 60, "max": null, "why": "At every load, the least at no load: the zero RzE CcE must stay well below the crossover, which falls with MP's transconductance." }, { "key": "ring_pct", "label": "Ringing after a kick, worst load", "unit": "%", "direction": "min", "constraint": "<= 5 %", "min": null, "max": 5, "why": "No load of the range may leave the output ringing after a small step." }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 45 dB", "min": 45, "max": null, "why": "At 1 kHz: the loop's large gain." }, { "key": "psrr_hf_db", "label": "Supply rejection at 1 MHz", "unit": "dB", "direction": "max", "constraint": ">= 45 dB", "min": 45, "max": null, "why": "At 1 MHz: the 1 µF output capacitor against the pass device's output resistance." }, { "key": "undershoot", "label": "Undershoot on the load step", "unit": "V", "direction": "min", "constraint": "<= 0.04 V", "min": null, "max": 0.04, "why": "For a 0 to 10 mA step in 1 µs on 1 µF." }, { "key": "overshoot", "label": "Overshoot on the load release", "unit": "V", "direction": "min", "constraint": "<= 0.04 V", "min": null, "max": 0.04, "why": "For the release in 1 µs." }, { "key": "t_recover", "label": "Settling after the load step", "unit": "s", "direction": "min", "constraint": "<= 0.00001 s", "min": null, "max": 0.00001, "why": "Back within 1 % after the step; the zero leaves a slow tail, which stays inside that band." }, { "key": "t_release", "label": "Settling after the load release", "unit": "s", "direction": "min", "constraint": "<= 0.00001 s", "min": null, "max": 0.00001, "why": "Back within 1 % after the release, at no load." }, { "key": "line_step", "label": "Output step for an input step", "unit": "V", "direction": "min", "constraint": "<= 0.01 V", "min": null, "max": 0.01, "why": "For the input stepped across its whole rated range in 1 µs at full load." }, { "key": "vn_out", "label": "Output noise, 10 Hz to 100 kHz", "unit": "V", "direction": "min", "constraint": "<= 0.00005 V", "min": null, "max": 0.00005, "why": "10 Hz to 100 kHz, rms: the error amplifier's own noise and what the filter lets through below its 320 Hz corner." }, { "key": "buf_overshoot", "label": "Buffer overshoot on a reference step", "unit": "%", "direction": "min", "constraint": "<= 5 %", "min": null, "max": 5, "why": "The buffer is a loop of its own: it must settle cleanly, since a ringing buffer would be filtered into noise and pass unnoticed." }, { "key": "buf_settle", "label": "Buffer settling, 1 %", "unit": "s", "direction": "min", "constraint": "<= 0.000003 s", "min": null, "max": 0.000003, "why": "Within 1 % of its step." } ], "explanation": { "idea": "Regulates 3.3 V down to about 2.5 V. A buffer doubles and filters the reference before a two-stage error amplifier drives the PMOS pass device. High loop gain improves regulation, but the reference filter slows start-up and a large external output capacitor is required.", "detail": "A 2.5 V supply from the 3.3 V I/O supply, whose reference is buffered, scaled and filtered before the loop sees it. A two-stage buffer doubles the 1.25 V reference with two equal resistors, an RC low-pass attenuates the buffer's noise above a few hundred hertz, and the main loop - with unity feedback - makes the output copy the filtered level. Its error amplifier is itself a two-stage amplifier compensated as an integrator with a zero, so the loop has a very large DC gain, and the 1 µF output capacitor sets its other pole.", "lesson": { "relation": 0, "symbols": "V_out is regulated output; V_ref is external reference; RA1 and RA2 are the reference buffer's feedback resistors.", "assumptions": "Matched resistors, large DC gain in both amplifiers, negligible input loading and enough voltage headroom. Offset and finite gain leave residual error.", "exercise": { "param": "Vref", "value": 1.2, "analysis": "op", "expect": "The output should fall toward 2.4 V, twice the new reference. The fixed 2.5 V default-design target will not describe this changed setting." }, "limits": "Needs external bias, reference and a large external output capacitor; Co is only the small on-chip capacitor. The reference filter attenuates high-frequency noise but slows changes in the reference." }, "path": [ { "part": "Reference buffer", "devices": "MA1, MA2, MA3, MA4, MA5, RA1, RA2, RzA, CcA", "does": "A two-stage op amp with a gain of two set by RA1 and RA2, Miller-compensated by RzA and CcA: vbuf = 2 · V_ref from a low impedance." }, { "part": "Reference filter", "devices": "Rf, Cf", "does": "Low-pass filters vbuf into vflt, corner 1/(2π · Rf · Cf) = 320 Hz: the buffer's and reference's noise above it is attenuated, not eliminated." }, { "part": "Error amplifier", "devices": "ME1, ME2, ME3, ME4, ME5, MTE, MSE", "does": "ME1 takes vflt, ME2 the output; the mirror ME3, ME4 feeds xe, which falls as the output rises; the common-source ME5 inverts it onto gate." }, { "part": "Integrator and zero", "devices": "RzE, CcE", "does": "Across ME5, CcE makes the amplifier an integrator and RzE adds a zero at 1/(2π · RzE · CcE): below it the loop gain is enormous, above it the loop is proportional and the output capacitor sets the crossover." }, { "part": "Pass device and output", "devices": "MP, Co, Rb", "does": "A 3.3 V PMOS from the input; Co is the regulator's own capacitor on the output, Rb the bleed." } ], "bias": "Ib, 5 µA from outside, into MB; the buffer's tail and sink are 2 and 4 copies of it, the error amplifier's 4 and 8. The amplifier currents are referenced to Ib, reducing but not eliminating supply dependence. The reference is an input, 1.25 V; the input is 3.3 V (2.97 to 3.63 V).", "relations": [ { "what": "Output voltage", "expr": "V_out = V_ref · (1 + RA1/RA2) = 2 · V_ref", "note": "The gain is in the buffer; the main loop has unity feedback." }, { "what": "Loop crossover", "expr": "f_c ≈ g_m,ME2 · RzE · g_m,MP/(2π · C_L)", "note": "Above the zero the amplifier is proportional, gain g_m,ME2 · RzE; g_m,MP falls at light load, and so does f_c." }, { "what": "Margin", "expr": "PM ≈ atan(f_c/f_z), f_z = 1/(2π · RzE · CcE)", "note": "The integrator and the output pole take 180° below the zero; the zero must sit well below the lowest crossover, at no load." }, { "what": "Filter noise", "expr": "v_n ≈ sqrt(k · T/Cf)", "note": "Whatever Rf is, the filter leaves kT/C of its own: 6 µV rms for 100 pF." } ], "tradeoffs": [ "Rf, Cf: a lower corner attenuates more of the buffer's noise but settles the output more slowly at start-up; Cf sets the filter's own kT/C floor.", "RzE, CcE: a lower zero adds margin at light load but leaves a slower tail after a load step; RzE also sets the proportional gain and the crossover.", "CcA, RzA: the buffer's own compensation - it must settle without ringing, since a ringing buffer would be filtered into noise and pass unnoticed.", "Rb: the bleed sets g_m,MP at no load, the lowest crossover and so the margin there." ] }, "sizing": [ { "key": "Ib", "label": "Bias current", "unit": "A", "value": 0.000005, "min": 0.000001, "max": 0.00005, "kind": "si" }, { "key": "Wn", "label": "W NMOS bias unit", "unit": "m", "value": 0.000008, "min": 5e-7, "max": 0.00004, "kind": "si" }, { "key": "Ln", "label": "L NMOS bias unit", "unit": "m", "value": 0.000001, "min": 4.5e-7, "max": 0.000004, "kind": "si" }, { "key": "NA", "label": "Buffer tail, in Ib", "unit": "", "value": 2, "min": 1, "max": 20, "kind": "int" }, { "key": "NS", "label": "Buffer second stage, in Ib", "unit": "", "value": 4, "min": 1, "max": 40, "kind": "int" }, { "key": "WA1", "label": "W buffer pair (MA1, MA2)", "unit": "m", "value": 0.00004, "min": 0.000001, "max": 0.0002, "kind": "si" }, { "key": "LA1", "label": "L buffer pair", "unit": "m", "value": 0.000004, "min": 4.5e-7, "max": 0.000008, "kind": "si" }, { "key": "WA3", "label": "W buffer PMOS unit (MA3, MA4, MA5)", "unit": "m", "value": 0.00004, "min": 0.000001, "max": 0.0002, "kind": "si" }, { "key": "LA3", "label": "L buffer PMOS unit", "unit": "m", "value": 0.000004, "min": 4.5e-7, "max": 0.000008, "kind": "si" }, { "key": "RzA", "label": "Buffer zero resistor", "unit": "Ω", "value": 20000, "min": 1000, "max": 500000, "kind": "si" }, { "key": "CcA", "label": "Buffer Miller capacitor", "unit": "F", "value": 5e-12, "min": 5e-13, "max": 5e-11, "kind": "si" }, { "key": "Ru", "label": "Buffer feedback unit resistor", "unit": "Ω", "value": 200000, "min": 20000, "max": 1000000, "kind": "si" }, { "key": "Rf", "label": "Filter resistor", "unit": "Ω", "value": 5000000, "min": 50000, "max": 10000000, "kind": "si" }, { "key": "Cf", "label": "Filter capacitor", "unit": "F", "value": 1e-10, "min": 1e-12, "max": 2e-10, "kind": "si" }, { "key": "NE", "label": "Error amplifier tail, in Ib", "unit": "", "value": 4, "min": 1, "max": 20, "kind": "int" }, { "key": "NK", "label": "Error amplifier second stage, in Ib", "unit": "", "value": 8, "min": 1, "max": 40, "kind": "int" }, { "key": "WE1", "label": "W error amplifier pair (ME1, ME2)", "unit": "m", "value": 0.00008, "min": 0.000001, "max": 0.0002, "kind": "si" }, { "key": "LE1", "label": "L error amplifier pair", "unit": "m", "value": 0.000004, "min": 4.5e-7, "max": 0.000008, "kind": "si" }, { "key": "WE3", "label": "W error amplifier PMOS unit (ME3, ME4, ME5)", "unit": "m", "value": 0.00004, "min": 0.000001, "max": 0.0002, "kind": "si" }, { "key": "LE3", "label": "L error amplifier PMOS unit", "unit": "m", "value": 0.000004, "min": 4.5e-7, "max": 0.000008, "kind": "si" }, { "key": "RzE", "label": "Error amplifier zero resistor", "unit": "Ω", "value": 350000, "min": 1000, "max": 2000000, "kind": "si" }, { "key": "CcE", "label": "Error amplifier Miller capacitor", "unit": "F", "value": 1e-10, "min": 1e-12, "max": 3e-10, "kind": "si" }, { "key": "Wpass", "label": "W pass device", "unit": "m", "value": 0.0006, "min": 0.00002, "max": 0.004, "kind": "si" }, { "key": "Lpass", "label": "L pass device", "unit": "m", "value": 4.5e-7, "min": 4.5e-7, "max": 0.000002, "kind": "si" }, { "key": "Co", "label": "On-chip output capacitor", "unit": "F", "value": 1e-10, "min": 1e-12, "max": 5e-10, "kind": "si" }, { "key": "Rb", "label": "Bleed resistor", "unit": "Ω", "value": 10000, "min": 1000, "max": 200000, "kind": "si" }, { "key": "Vref", "label": "Reference", "unit": "V", "value": 1.25, "min": 1, "max": 1.4, "kind": "si" }, { "key": "IL", "label": "Full load", "unit": "A", "value": 0.01, "min": 0.001, "max": 0.03, "kind": "si" }, { "key": "CL", "label": "Output capacitor", "unit": "F", "value": 0.000001, "min": 1e-7, "max": 0.00001, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The regulator at its nominal input and its lightest load: the output it holds and the current it draws to hold it.", "measures": [], "metricKeys": [ "vout", "i_q" ], "acceptance": [ "vout", "i_q" ], "acceptanceRules": [ { "key": "vout", "unit": "V", "min": 2.45, "max": 2.55, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "i_q", "unit": "A", "min": null, "max": 0.00045, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Buffered-reference LDO, 2.5 V from 3.3 V - operating point at the lightest load\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 1.25\nIb vdd ib dc 5u\n.subckt ldobufref ref sense out vdd vss ib\n* bias: tails and sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2\nXMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\n* reference buffer: fbb on the diode side, a PMOS common-source second stage, gain 2\nXMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzA xa za vss rhigh w=0.5u l=6.078u\nXCcA za vbuf cap_cmim w=28.814u l=28.814u m=4\nXRA1 vbuf fbb vss rhigh w=0.5u l=61.666u\nXRA2 fbb vss vss rhigh w=0.5u l=61.666u\n* the filter between the buffer and the loop\nXRf vbuf vflt vss rhigh w=0.5u l=1544.019u\nXCf vflt vss cap_cmim w=29.962u l=29.962u m=74\n* error amplifier: the filtered reference on the diode side, the output on the other\nXME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzE xe ze vss rhigh w=0.5u l=107.989u\nXCcE ze gate cap_cmim w=29.962u l=29.962u m=74\n* the pass device, the capacitor the regulator carries on its output, and the bleed\nXMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1\nXCo out vss cap_cmim w=29.962u l=29.962u m=74\nXRb out vss vss rppd w=0.5u l=19.417u\n.ends\nXdut ref sense out vdd 0 ib ldobufref\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 1u\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 0\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.op\n.end" }, { "id": "load_reg", "label": "Load regulation", "note": "The load is swept from lightest to full at nominal input. Regulation is the magnitude of the endpoint output change per ampere; a large output rise fails just as a large fall does.", "measures": [], "metricKeys": [ "load_reg" ], "acceptance": [ "load_reg" ], "acceptanceRules": [ { "key": "load_reg", "unit": "V/A", "min": null, "max": 0.02, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Buffered-reference LDO, 2.5 V from 3.3 V - output against load current\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 1.25\nIb vdd ib dc 5u\n.subckt ldobufref ref sense out vdd vss ib\n* bias: tails and sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2\nXMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\n* reference buffer: fbb on the diode side, a PMOS common-source second stage, gain 2\nXMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzA xa za vss rhigh w=0.5u l=6.078u\nXCcA za vbuf cap_cmim w=28.814u l=28.814u m=4\nXRA1 vbuf fbb vss rhigh w=0.5u l=61.666u\nXRA2 fbb vss vss rhigh w=0.5u l=61.666u\n* the filter between the buffer and the loop\nXRf vbuf vflt vss rhigh w=0.5u l=1544.019u\nXCf vflt vss cap_cmim w=29.962u l=29.962u m=74\n* error amplifier: the filtered reference on the diode side, the output on the other\nXME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzE xe ze vss rhigh w=0.5u l=107.989u\nXCcE ze gate cap_cmim w=29.962u l=29.962u m=74\n* the pass device, the capacitor the regulator carries on its output, and the bleed\nXMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1\nXCo out vss cap_cmim w=29.962u l=29.962u m=74\nXRb out vss vss rppd w=0.5u l=19.417u\n.ends\nXdut ref sense out vdd 0 ib ldobufref\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 1u\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 0\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.dc Vload 0 10m 100u\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc v_light FIND v(out) AT=0\n.meas dc v_full FIND v(out) AT=10m\n.end" }, { "id": "line_reg", "label": "Line regulation", "note": "The input swept across its rated range, at the lightest and at the full load: how much of the input's change reaches the output.", "measures": [], "metricKeys": [ "line_reg" ], "acceptance": [ "line_reg" ], "acceptanceRules": [ { "key": "line_reg", "unit": "%/V", "min": null, "max": 0.02, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Buffered-reference LDO, 2.5 V from 3.3 V - output against input voltage\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n* the input swept across its rated range, 2.97V to 3.63V\nVdd vdd 0 dc 3.3\nVref ref 0 dc 1.25\nIb vdd ib dc 5u\n.subckt ldobufref ref sense out vdd vss ib\n* bias: tails and sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2\nXMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\n* reference buffer: fbb on the diode side, a PMOS common-source second stage, gain 2\nXMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzA xa za vss rhigh w=0.5u l=6.078u\nXCcA za vbuf cap_cmim w=28.814u l=28.814u m=4\nXRA1 vbuf fbb vss rhigh w=0.5u l=61.666u\nXRA2 fbb vss vss rhigh w=0.5u l=61.666u\n* the filter between the buffer and the loop\nXRf vbuf vflt vss rhigh w=0.5u l=1544.019u\nXCf vflt vss cap_cmim w=29.962u l=29.962u m=74\n* error amplifier: the filtered reference on the diode side, the output on the other\nXME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzE xe ze vss rhigh w=0.5u l=107.989u\nXCcE ze gate cap_cmim w=29.962u l=29.962u m=74\n* the pass device, the capacitor the regulator carries on its output, and the bleed\nXMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1\nXCo out vss cap_cmim w=29.962u l=29.962u m=74\nXRb out vss vss rppd w=0.5u l=19.417u\n.ends\nXdut ref sense out vdd 0 ib ldobufref\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 1u\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 0\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n* the input swept at each of two loads: the lightest, then the full load\n.dc Vdd 2.97 3.63 13.75m Vload 0 10m 10m\n.end" }, { "id": "dropout", "label": "Dropout", "note": "The input lowered at full load until the output has fallen 2 % below the level it holds at the nominal input: the input-to-output voltage left there is the dropout.", "measures": [], "metricKeys": [ "dropout" ], "acceptance": [ "dropout" ], "acceptanceRules": [ { "key": "dropout", "unit": "V", "min": null, "max": 0.3, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Buffered-reference LDO, 2.5 V from 3.3 V - dropout at full load\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n* the input swept down to below the output: 2.2V to 3.63V\nVdd vdd 0 dc 3.3\nVref ref 0 dc 1.25\nIb vdd ib dc 5u\n.subckt ldobufref ref sense out vdd vss ib\n* bias: tails and sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2\nXMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\n* reference buffer: fbb on the diode side, a PMOS common-source second stage, gain 2\nXMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzA xa za vss rhigh w=0.5u l=6.078u\nXCcA za vbuf cap_cmim w=28.814u l=28.814u m=4\nXRA1 vbuf fbb vss rhigh w=0.5u l=61.666u\nXRA2 fbb vss vss rhigh w=0.5u l=61.666u\n* the filter between the buffer and the loop\nXRf vbuf vflt vss rhigh w=0.5u l=1544.019u\nXCf vflt vss cap_cmim w=29.962u l=29.962u m=74\n* error amplifier: the filtered reference on the diode side, the output on the other\nXME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzE xe ze vss rhigh w=0.5u l=107.989u\nXCcE ze gate cap_cmim w=29.962u l=29.962u m=74\n* the pass device, the capacitor the regulator carries on its output, and the bleed\nXMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1\nXCo out vss cap_cmim w=29.962u l=29.962u m=74\nXRb out vss vss rppd w=0.5u l=19.417u\n.ends\nXdut ref sense out vdd 0 ib ldobufref\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 1u\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 10m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.dc Vdd 2.2 3.63 7.15m\n.end" }, { "id": "loop", "label": "Loop gain", "note": "The loop gain at loads across the whole range, from the lightest to the full load: the loop is cut at the sense line and measured by Middlebrook's double injection - a voltage in series there, then a current into out - which gives it exactly, with every loading in place. The phase and gain margins are the worst over the loads.", "measures": [], "metricKeys": [ "loop_gain_db", "loop_ugf_hz", "loop_pm_deg", "loop_gm_db" ], "acceptance": [ "loop_gain_db", "loop_ugf_hz", "loop_pm_deg" ], "acceptanceRules": [ { "key": "loop_gain_db", "unit": "dB", "min": 80, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "loop_ugf_hz", "unit": "Hz", "min": 50000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "loop_pm_deg", "unit": "deg", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Buffered-reference LDO, 2.5 V from 3.3 V - loop gain at 10mA, voltage injection\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 1.25\nIb vdd ib dc 5u\n.subckt ldobufref ref sense out vdd vss ib\n* bias: tails and sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2\nXMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\n* reference buffer: fbb on the diode side, a PMOS common-source second stage, gain 2\nXMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzA xa za vss rhigh w=0.5u l=6.078u\nXCcA za vbuf cap_cmim w=28.814u l=28.814u m=4\nXRA1 vbuf fbb vss rhigh w=0.5u l=61.666u\nXRA2 fbb vss vss rhigh w=0.5u l=61.666u\n* the filter between the buffer and the loop\nXRf vbuf vflt vss rhigh w=0.5u l=1544.019u\nXCf vflt vss cap_cmim w=29.962u l=29.962u m=74\n* error amplifier: the filtered reference on the diode side, the output on the other\nXME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzE xe ze vss rhigh w=0.5u l=107.989u\nXCcE ze gate cap_cmim w=29.962u l=29.962u m=74\n* the pass device, the capacitor the regulator carries on its output, and the bleed\nXMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1\nXCo out vss cap_cmim w=29.962u l=29.962u m=74\nXRb out vss vss rppd w=0.5u l=19.417u\n.ends\nXdut ref sense out vdd 0 ib ldobufref\n* the sense line cut by a 1 V ac source in series: T_v = -v(out)/v(sense)\nVinj sense out dc 0 ac 1\nCl out 0 1u\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 10m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.ac dec 20 0.1 1g\n.end" }, { "id": "ring", "label": "Ringing across the loads", "note": "The loads the loop bench visits, in a staircase from the lightest to the full load; at each, once the output has settled, a small step - a tenth more load. How far the output overshoots its new level on the way back, and what is left moving at the end of each step, show whether the regulator is damped at that load: a loop inside it that the sense line does not pass through, and so the loop gain cannot see, shows here.", "measures": [], "metricKeys": [ "ring_pct" ], "acceptance": [ "ring_pct" ], "acceptanceRules": [ { "key": "ring_pct", "unit": "%", "min": null, "max": 5, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Buffered-reference LDO, 2.5 V from 3.3 V - a small load step at each load\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 1.25\nIb vdd ib dc 5u\n.subckt ldobufref ref sense out vdd vss ib\n* bias: tails and sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2\nXMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\n* reference buffer: fbb on the diode side, a PMOS common-source second stage, gain 2\nXMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzA xa za vss rhigh w=0.5u l=6.078u\nXCcA za vbuf cap_cmim w=28.814u l=28.814u m=4\nXRA1 vbuf fbb vss rhigh w=0.5u l=61.666u\nXRA2 fbb vss vss rhigh w=0.5u l=61.666u\n* the filter between the buffer and the loop\nXRf vbuf vflt vss rhigh w=0.5u l=1544.019u\nXCf vflt vss cap_cmim w=29.962u l=29.962u m=74\n* error amplifier: the filtered reference on the diode side, the output on the other\nXME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzE xe ze vss rhigh w=0.5u l=107.989u\nXCcE ze gate cap_cmim w=29.962u l=29.962u m=74\n* the pass device, the capacitor the regulator carries on its output, and the bleed\nXMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1\nXCo out vss cap_cmim w=29.962u l=29.962u m=74\nXRb out vss vss rppd w=0.5u l=19.417u\n.ends\nXdut ref sense out vdd 0 ib ldobufref\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 1u\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 pwl(0 0 400u 0 401u 40u 1m 40u 1.001m 10u 1.4m 10u 1.401m 50u 2m 50u 2.001m 100u 2.4m 100u 2.401m 140u 3m 140u 3.001m 1m 3.4m 1m 3.401m 1.1m 4m 1.1m 4.001m 10m 4.4m 10m 4.401m 11m 5m 11m)\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.tran 500n 5m\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on the input, at the lightest and at the full load: how much of it reaches the output.", "measures": [], "metricKeys": [ "psrr_db", "psrr_hf_db" ], "acceptance": [ "psrr_db", "psrr_hf_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 45, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "psrr_hf_db", "unit": "dB", "min": 45, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Buffered-reference LDO, 2.5 V from 3.3 V - supply rejection at 10mA\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD} ac 1\nVref ref 0 dc 1.25\nIb vdd ib dc 5u\n.subckt ldobufref ref sense out vdd vss ib\n* bias: tails and sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2\nXMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\n* reference buffer: fbb on the diode side, a PMOS common-source second stage, gain 2\nXMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzA xa za vss rhigh w=0.5u l=6.078u\nXCcA za vbuf cap_cmim w=28.814u l=28.814u m=4\nXRA1 vbuf fbb vss rhigh w=0.5u l=61.666u\nXRA2 fbb vss vss rhigh w=0.5u l=61.666u\n* the filter between the buffer and the loop\nXRf vbuf vflt vss rhigh w=0.5u l=1544.019u\nXCf vflt vss cap_cmim w=29.962u l=29.962u m=74\n* error amplifier: the filtered reference on the diode side, the output on the other\nXME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzE xe ze vss rhigh w=0.5u l=107.989u\nXCcE ze gate cap_cmim w=29.962u l=29.962u m=74\n* the pass device, the capacitor the regulator carries on its output, and the bleed\nXMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1\nXCo out vss cap_cmim w=29.962u l=29.962u m=74\nXRb out vss vss rppd w=0.5u l=19.417u\n.ends\nXdut ref sense out vdd 0 ib ldobufref\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 1u\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 10m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.ac dec 20 1 100meg\n.end" }, { "id": "load_step", "label": "Load step", "note": "The load stepped from the lightest to the full load and back, each edge 1.00 µs: how far the output dips and peaks, and how long it takes to settle within 1 % after each edge. A loop that rings or oscillates at either load shows here, whatever the loop gain says.", "measures": [], "metricKeys": [ "undershoot", "overshoot", "t_recover", "t_release" ], "acceptance": [ "undershoot", "overshoot", "t_recover", "t_release" ], "acceptanceRules": [ { "key": "undershoot", "unit": "V", "min": null, "max": 0.04, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "overshoot", "unit": "V", "min": null, "max": 0.04, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "t_recover", "unit": "s", "min": null, "max": 0.00001, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "t_release", "unit": "s", "min": null, "max": 0.00001, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Buffered-reference LDO, 2.5 V from 3.3 V - load step\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 1.25\nIb vdd ib dc 5u\n.subckt ldobufref ref sense out vdd vss ib\n* bias: tails and sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2\nXMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\n* reference buffer: fbb on the diode side, a PMOS common-source second stage, gain 2\nXMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzA xa za vss rhigh w=0.5u l=6.078u\nXCcA za vbuf cap_cmim w=28.814u l=28.814u m=4\nXRA1 vbuf fbb vss rhigh w=0.5u l=61.666u\nXRA2 fbb vss vss rhigh w=0.5u l=61.666u\n* the filter between the buffer and the loop\nXRf vbuf vflt vss rhigh w=0.5u l=1544.019u\nXCf vflt vss cap_cmim w=29.962u l=29.962u m=74\n* error amplifier: the filtered reference on the diode side, the output on the other\nXME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzE xe ze vss rhigh w=0.5u l=107.989u\nXCcE ze gate cap_cmim w=29.962u l=29.962u m=74\n* the pass device, the capacitor the regulator carries on its output, and the bleed\nXMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1\nXCo out vss cap_cmim w=29.962u l=29.962u m=74\nXRb out vss vss rppd w=0.5u l=19.417u\n.ends\nXdut ref sense out vdd 0 ib ldobufref\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 1u\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 pulse(0 10m 20u 1u 1u 89u 400u)\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.tran 40n 200u\n.end" }, { "id": "line_step", "label": "Line step", "note": "The input stepped across its rated range, 2.97 V to 3.63 V, and back, each edge 1.00 µs, at full load: how far the output moves.", "measures": [], "metricKeys": [ "line_step" ], "acceptance": [ "line_step" ], "acceptanceRules": [ { "key": "line_step", "unit": "V", "min": null, "max": 0.01, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Buffered-reference LDO, 2.5 V from 3.3 V - line step at full load\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n* the input steps across its rated range and back\nVdd vdd 0 pulse(2.97 3.63 20u 1u 1u 89u 400u)\nVref ref 0 dc 1.25\nIb vdd ib dc 5u\n.subckt ldobufref ref sense out vdd vss ib\n* bias: tails and sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2\nXMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\n* reference buffer: fbb on the diode side, a PMOS common-source second stage, gain 2\nXMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzA xa za vss rhigh w=0.5u l=6.078u\nXCcA za vbuf cap_cmim w=28.814u l=28.814u m=4\nXRA1 vbuf fbb vss rhigh w=0.5u l=61.666u\nXRA2 fbb vss vss rhigh w=0.5u l=61.666u\n* the filter between the buffer and the loop\nXRf vbuf vflt vss rhigh w=0.5u l=1544.019u\nXCf vflt vss cap_cmim w=29.962u l=29.962u m=74\n* error amplifier: the filtered reference on the diode side, the output on the other\nXME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzE xe ze vss rhigh w=0.5u l=107.989u\nXCcE ze gate cap_cmim w=29.962u l=29.962u m=74\n* the pass device, the capacitor the regulator carries on its output, and the bleed\nXMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1\nXCo out vss cap_cmim w=29.962u l=29.962u m=74\nXRb out vss vss rppd w=0.5u l=19.417u\n.ends\nXdut ref sense out vdd 0 ib ldobufref\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 1u\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 10m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.tran 40n 200u\n.end" }, { "id": "noise", "label": "Output noise", "note": "The noise at the output at full load: its density at 1 kHz and its total from 10 Hz to 100 kHz. The reference is an ideal, noiseless source, so this is the regulator's own noise.", "measures": [], "metricKeys": [ "vn_out", "vn_out_1k" ], "acceptance": [ "vn_out" ], "acceptanceRules": [ { "key": "vn_out", "unit": "V", "min": null, "max": 0.00005, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Buffered-reference LDO, 2.5 V from 3.3 V - output noise at full load\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\n* ac 1 only because ngspice's noise analysis names an input; the output noise does not depend on it\nVdd vdd 0 dc {VDD} ac 1\nVref ref 0 dc 1.25\nIb vdd ib dc 5u\n.subckt ldobufref ref sense out vdd vss ib\n* bias: tails and sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2\nXMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\n* reference buffer: fbb on the diode side, a PMOS common-source second stage, gain 2\nXMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzA xa za vss rhigh w=0.5u l=6.078u\nXCcA za vbuf cap_cmim w=28.814u l=28.814u m=4\nXRA1 vbuf fbb vss rhigh w=0.5u l=61.666u\nXRA2 fbb vss vss rhigh w=0.5u l=61.666u\n* the filter between the buffer and the loop\nXRf vbuf vflt vss rhigh w=0.5u l=1544.019u\nXCf vflt vss cap_cmim w=29.962u l=29.962u m=74\n* error amplifier: the filtered reference on the diode side, the output on the other\nXME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzE xe ze vss rhigh w=0.5u l=107.989u\nXCcE ze gate cap_cmim w=29.962u l=29.962u m=74\n* the pass device, the capacitor the regulator carries on its output, and the bleed\nXMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1\nXCo out vss cap_cmim w=29.962u l=29.962u m=74\nXRb out vss vss rppd w=0.5u l=19.417u\n.ends\nXdut ref sense out vdd 0 ib ldobufref\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 1u\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 10m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.control\nnoise v(out) Vdd dec 20 10 100k\nsetplot noise1\n* 20 points a decade from 10 Hz: point 40 is 1 kHz\nlet vn_1k = onoise_spectrum[40]\nprint vn_1k\nsetplot noise2\nprint onoise_total\n.endc\n.op\n.end" }, { "id": "buffer", "label": "Reference buffer", "note": "A 50 mV step on the reference, and the buffer's own output, vbuf, inside the regulator: it should double the step and settle without ringing. Its loop is inside the regulator, and none of the other benches cuts it.", "measures": [], "metricKeys": [ "buf_overshoot", "buf_settle" ], "acceptance": [ "buf_overshoot", "buf_settle" ], "acceptanceRules": [ { "key": "buf_overshoot", "unit": "%", "min": null, "max": 5, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "buf_settle", "unit": "s", "min": null, "max": 0.000003, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Buffered-reference LDO from 3.3 V - step response of the reference buffer\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD}\n* the reference steps up by 50 mV; the buffer doubles it\nVref ref 0 pulse(1.25 1.3 1u 100n 100n 20u 40u)\nIb vdd ib dc 5u\n.subckt ldobufref ref sense out vdd vss ib\n* bias: tails and sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2\nXMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\n* reference buffer: fbb on the diode side, a PMOS common-source second stage, gain 2\nXMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1\nXMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzA xa za vss rhigh w=0.5u l=6.078u\nXCcA za vbuf cap_cmim w=28.814u l=28.814u m=4\nXRA1 vbuf fbb vss rhigh w=0.5u l=61.666u\nXRA2 fbb vss vss rhigh w=0.5u l=61.666u\n* the filter between the buffer and the loop\nXRf vbuf vflt vss rhigh w=0.5u l=1544.019u\nXCf vflt vss cap_cmim w=29.962u l=29.962u m=74\n* error amplifier: the filtered reference on the diode side, the output on the other\nXME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1\nXME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1\nXME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4\nXRzE xe ze vss rhigh w=0.5u l=107.989u\nXCcE ze gate cap_cmim w=29.962u l=29.962u m=74\n* the pass device, the capacitor the regulator carries on its output, and the bleed\nXMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1\nXCo out vss cap_cmim w=29.962u l=29.962u m=74\nXRb out vss vss rppd w=0.5u l=19.417u\n.ends\nXdut ref sense out vdd 0 ib ldobufref\nVsense sense out 0\nCl out 0 1u\n.tran 5n 6u\n.end" } ], "measurements": { "vout": { "label": "Output voltage", "unit": "V", "spec": { "min": 2.45, "max": 2.55 } }, "i_q": { "label": "Quiescent current", "unit": "A", "spec": { "min": null, "max": 0.00045 } }, "load_reg": { "label": "Load regulation", "unit": "V/A", "spec": { "min": null, "max": 0.02 } }, "line_reg": { "label": "Line regulation", "unit": "%/V", "spec": { "min": null, "max": 0.02 } }, "dropout": { "label": "Dropout at full load", "unit": "V", "spec": { "min": null, "max": 0.3 } }, "loop_gain_db": { "label": "DC loop gain at full load", "unit": "dB", "spec": { "min": 80, "max": null } }, "loop_ugf_hz": { "label": "Loop crossover at full load", "unit": "Hz", "spec": { "min": 50000, "max": null } }, "loop_pm_deg": { "label": "Loop phase margin, worst load", "unit": "deg", "spec": { "min": 60, "max": null } }, "ring_pct": { "label": "Ringing after a kick, worst load", "unit": "%", "spec": { "min": null, "max": 5 } }, "psrr_db": { "label": "Supply rejection at 1 kHz", "unit": "dB", "spec": { "min": 45, "max": null } }, "psrr_hf_db": { "label": "Supply rejection at 1 MHz", "unit": "dB", "spec": { "min": 45, "max": null } }, "undershoot": { "label": "Undershoot on the load step", "unit": "V", "spec": { "min": null, "max": 0.04 } }, "overshoot": { "label": "Overshoot on the load release", "unit": "V", "spec": { "min": null, "max": 0.04 } }, "t_recover": { "label": "Settling after the load step", "unit": "s", "spec": { "min": null, "max": 0.00001 } }, "t_release": { "label": "Settling after the load release", "unit": "s", "spec": { "min": null, "max": 0.00001 } }, "line_step": { "label": "Output step for an input step", "unit": "V", "spec": { "min": null, "max": 0.01 } }, "vn_out": { "label": "Output noise, 10 Hz to 100 kHz", "unit": "V", "spec": { "min": null, "max": 0.00005 } }, "buf_overshoot": { "label": "Buffer overshoot on a reference step", "unit": "%", "spec": { "min": null, "max": 5 } }, "buf_settle": { "label": "Buffer settling, 1 %", "unit": "s", "spec": { "min": null, "max": 0.000003 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "f2d6825fb42545a4ff0c929d6f8a03e969af545eaca48c5a434e89b633887e2a" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ldo-bufref-hv.js", "sha256": "4ed741b578119215d9874e774a41757686ba06a4dc7296fd104cdaf72f87cb3c" }, "simulationFingerprints": { "op": "8d48ff0e2f868cbd58b968cbf79d4836ce3745553cea8ef6c61eddff2ccb4316", "load_reg": "85183f33a4830c162c1375f73a03d0b4cafc0994d8e49234421d222f7fd3c382", "line_reg": "81e3f02f184e5e33f093ae7d2950f5a893bfa584bfd4018e581119510a06efa1", "dropout": "5c8c27fbd7995131173d48c95dd473d796c163f08ac0eb6ccbde4920e95ddf7c", "loop": "3f193d33835ca5d341acc8c0d6baede2c9f5fae716176fa27aa0616aa5cae0e1", "ring": "09b03561e54ab036223515067d2db24ee3fff7642b182533f56072a378ef44b0", "psrr": "413ea54c469cf11138d53577238a69b3272b182990ac528a79392d5064847c14", "load_step": "83901f8a3493739ce81c87481fd1ee6b9a12f9d492332830735dd2eed6ba6b37", "line_step": "9fd8690e3ae836e5f454320206503adb77eaaef7811fcd50b10234496228a8f6", "noise": "af804afd08a68b8f9ce96bf84d207a8c6fcfcad077019fcda0ef647f7f853631", "buffer": "b240d2922adf48029929e1046ea0c590418254b04f9e6ed4e0fb4682dff7b09c" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "a00b7bed7beb4934a98e45a896e686c4085ea26159111b1be5b143054cc64c56", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ldo-bufref-hv", "parameters": { "Ib": 0.000005, "Wn": 0.000008, "Ln": 0.000001, "NA": 2, "NS": 4, "WA1": 0.00004, "LA1": 0.000004, "WA3": 0.00004, "LA3": 0.000004, "RzA": 20000, "CcA": 5e-12, "Ru": 200000, "Rf": 5000000, "Cf": 1e-10, "NE": 4, "NK": 8, "WE1": 0.00008, "LE1": 0.000004, "WE3": 0.00004, "LE3": 0.000004, "RzE": 350000, "CcE": 1e-10, "Wpass": 0.0006, "Lpass": 4.5e-7, "Co": 1e-10, "Rb": 10000, "Vref": 1.25, "IL": 0.01, "CL": 0.000001 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ldo-bufref-hv/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=3.3" ], "scopes": [ { "id": "dut", "name": "ldobufref", "ports": [ { "name": "ref", "net": "ref", "kind": "input" }, { "name": "sense", "net": "sense", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTA", "displayName": "MTA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "ta" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSA", "displayName": "MSA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTE", "displayName": "MTE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "te" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSE", "displayName": "MSE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=8", "source": "XMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "fbb" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA3", "displayName": "MA3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA4", "displayName": "MA4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA5", "displayName": "MA5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "xa" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzA", "displayName": "RzA", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRzA xa za vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "xa" }, { "id": "n", "net": "za" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcA", "displayName": "CcA", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=4", "source": "XCcA za vbuf cap_cmim w=28.814u l=28.814u m=4", "pins": [ { "id": "p", "net": "za" }, { "id": "n", "net": "vbuf" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRA1", "displayName": "RA1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA1 vbuf fbb vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "fbb" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRA2", "displayName": "RA2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA2 fbb vss vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "fbb" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRf", "displayName": "Rf", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRf vbuf vflt vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "vflt" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCf vflt vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "vflt" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XME1", "displayName": "ME1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "vflt" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME2", "displayName": "ME2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME3", "displayName": "ME3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME4", "displayName": "ME4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME5", "displayName": "ME5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "xe" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzE", "displayName": "RzE", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=107.989u", "source": "XRzE xe ze vss rhigh w=0.5u l=107.989u", "pins": [ { "id": "p", "net": "xe" }, { "id": "n", "net": "ze" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcE", "displayName": "CcE", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCcE ze gate cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "ze" }, { "id": "n", "net": "gate" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=600u l=450n ng=120 m=1", "source": "XMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCo", "displayName": "Co", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCo out vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XRb out vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMTA", "pin": "g" }, { "device": "XMSA", "pin": "g" }, { "device": "XMTE", "pin": "g" }, { "device": "XMSE", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMTA", "pin": "s" }, { "device": "XMTA", "pin": "b" }, { "device": "XMSA", "pin": "s" }, { "device": "XMSA", "pin": "b" }, { "device": "XMTE", "pin": "s" }, { "device": "XMTE", "pin": "b" }, { "device": "XMSE", "pin": "s" }, { "device": "XMSE", "pin": "b" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "b" }, { "device": "XRzA", "pin": "substrate" }, { "device": "XRA1", "pin": "substrate" }, { "device": "XRA2", "pin": "n" }, { "device": "XRA2", "pin": "substrate" }, { "device": "XRf", "pin": "substrate" }, { "device": "XCf", "pin": "n" }, { "device": "XME1", "pin": "b" }, { "device": "XME2", "pin": "b" }, { "device": "XRzE", "pin": "substrate" }, { "device": "XCo", "pin": "n" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "ta", "ground": false, "terminals": [ { "device": "XMTA", "pin": "d" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vbuf", "ground": false, "terminals": [ { "device": "XMSA", "pin": "d" }, { "device": "XMA5", "pin": "d" }, { "device": "XCcA", "pin": "n" }, { "device": "XRA1", "pin": "p" }, { "device": "XRf", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "te", "ground": false, "terminals": [ { "device": "XMTE", "pin": "d" }, { "device": "XME1", "pin": "s" }, { "device": "XME2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XMSE", "pin": "d" }, { "device": "XME5", "pin": "d" }, { "device": "XCcE", "pin": "n" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "da", "ground": false, "terminals": [ { "device": "XMA1", "pin": "d" }, { "device": "XMA3", "pin": "d" }, { "device": "XMA3", "pin": "g" }, { "device": "XMA4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "fbb", "ground": false, "terminals": [ { "device": "XMA1", "pin": "g" }, { "device": "XRA1", "pin": "n" }, { "device": "XRA2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "xa", "ground": false, "terminals": [ { "device": "XMA2", "pin": "d" }, { "device": "XMA4", "pin": "d" }, { "device": "XMA5", "pin": "g" }, { "device": "XRzA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XMA2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMA3", "pin": "s" }, { "device": "XMA3", "pin": "b" }, { "device": "XMA4", "pin": "s" }, { "device": "XMA4", "pin": "b" }, { "device": "XMA5", "pin": "s" }, { "device": "XMA5", "pin": "b" }, { "device": "XME3", "pin": "s" }, { "device": "XME3", "pin": "b" }, { "device": "XME4", "pin": "s" }, { "device": "XME4", "pin": "b" }, { "device": "XME5", "pin": "s" }, { "device": "XME5", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "za", "ground": false, "terminals": [ { "device": "XRzA", "pin": "n" }, { "device": "XCcA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vflt", "ground": false, "terminals": [ { "device": "XRf", "pin": "n" }, { "device": "XCf", "pin": "p" }, { "device": "XME1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "de", "ground": false, "terminals": [ { "device": "XME1", "pin": "d" }, { "device": "XME3", "pin": "d" }, { "device": "XME3", "pin": "g" }, { "device": "XME4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "xe", "ground": false, "terminals": [ { "device": "XME2", "pin": "d" }, { "device": "XME4", "pin": "d" }, { "device": "XME5", "pin": "g" }, { "device": "XRzE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XME2", "pin": "g" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "ze", "ground": false, "terminals": [ { "device": "XRzE", "pin": "n" }, { "device": "XCcE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCo", "pin": "p" }, { "device": "XRb", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=3.3" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=3.3" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.25", "source": "Vref ref 0 dc 1.25", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib vdd ib dc 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldobufref", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldobufref", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldobufref" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "1u", "source": "Cl out 0 1u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vload il 0 dc 0", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldobufref", "name": "ldobufref", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTA", "displayName": "MTA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "ta" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSA", "displayName": "MSA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTE", "displayName": "MTE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "te" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSE", "displayName": "MSE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=8", "source": "XMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "fbb" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA3", "displayName": "MA3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA4", "displayName": "MA4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA5", "displayName": "MA5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "xa" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzA", "displayName": "RzA", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRzA xa za vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "xa" }, { "id": "n", "net": "za" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcA", "displayName": "CcA", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=4", "source": "XCcA za vbuf cap_cmim w=28.814u l=28.814u m=4", "pins": [ { "id": "p", "net": "za" }, { "id": "n", "net": "vbuf" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRA1", "displayName": "RA1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA1 vbuf fbb vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "fbb" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRA2", "displayName": "RA2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA2 fbb vss vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "fbb" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRf", "displayName": "Rf", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRf vbuf vflt vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "vflt" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCf vflt vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "vflt" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XME1", "displayName": "ME1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "vflt" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME2", "displayName": "ME2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME3", "displayName": "ME3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME4", "displayName": "ME4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME5", "displayName": "ME5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "xe" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzE", "displayName": "RzE", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=107.989u", "source": "XRzE xe ze vss rhigh w=0.5u l=107.989u", "pins": [ { "id": "p", "net": "xe" }, { "id": "n", "net": "ze" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcE", "displayName": "CcE", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCcE ze gate cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "ze" }, { "id": "n", "net": "gate" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=600u l=450n ng=120 m=1", "source": "XMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCo", "displayName": "Co", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCo out vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XRb out vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMTA", "pin": "g" }, { "device": "XMSA", "pin": "g" }, { "device": "XMTE", "pin": "g" }, { "device": "XMSE", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMTA", "pin": "s" }, { "device": "XMTA", "pin": "b" }, { "device": "XMSA", "pin": "s" }, { "device": "XMSA", "pin": "b" }, { "device": "XMTE", "pin": "s" }, { "device": "XMTE", "pin": "b" }, { "device": "XMSE", "pin": "s" }, { "device": "XMSE", "pin": "b" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "b" }, { "device": "XRzA", "pin": "substrate" }, { "device": "XRA1", "pin": "substrate" }, { "device": "XRA2", "pin": "n" }, { "device": "XRA2", "pin": "substrate" }, { "device": "XRf", "pin": "substrate" }, { "device": "XCf", "pin": "n" }, { "device": "XME1", "pin": "b" }, { "device": "XME2", "pin": "b" }, { "device": "XRzE", "pin": "substrate" }, { "device": "XCo", "pin": "n" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "ta", "ground": false, "terminals": [ { "device": "XMTA", "pin": "d" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vbuf", "ground": false, "terminals": [ { "device": "XMSA", "pin": "d" }, { "device": "XMA5", "pin": "d" }, { "device": "XCcA", "pin": "n" }, { "device": "XRA1", "pin": "p" }, { "device": "XRf", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "te", "ground": false, "terminals": [ { "device": "XMTE", "pin": "d" }, { "device": "XME1", "pin": "s" }, { "device": "XME2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XMSE", "pin": "d" }, { "device": "XME5", "pin": "d" }, { "device": "XCcE", "pin": "n" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "da", "ground": false, "terminals": [ { "device": "XMA1", "pin": "d" }, { "device": "XMA3", "pin": "d" }, { "device": "XMA3", "pin": "g" }, { "device": "XMA4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "fbb", "ground": false, "terminals": [ { "device": "XMA1", "pin": "g" }, { "device": "XRA1", "pin": "n" }, { "device": "XRA2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "xa", "ground": false, "terminals": [ { "device": "XMA2", "pin": "d" }, { "device": "XMA4", "pin": "d" }, { "device": "XMA5", "pin": "g" }, { "device": "XRzA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XMA2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMA3", "pin": "s" }, { "device": "XMA3", "pin": "b" }, { "device": "XMA4", "pin": "s" }, { "device": "XMA4", "pin": "b" }, { "device": "XMA5", "pin": "s" }, { "device": "XMA5", "pin": "b" }, { "device": "XME3", "pin": "s" }, { "device": "XME3", "pin": "b" }, { "device": "XME4", "pin": "s" }, { "device": "XME4", "pin": "b" }, { "device": "XME5", "pin": "s" }, { "device": "XME5", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "za", "ground": false, "terminals": [ { "device": "XRzA", "pin": "n" }, { "device": "XCcA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vflt", "ground": false, "terminals": [ { "device": "XRf", "pin": "n" }, { "device": "XCf", "pin": "p" }, { "device": "XME1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "de", "ground": false, "terminals": [ { "device": "XME1", "pin": "d" }, { "device": "XME3", "pin": "d" }, { "device": "XME3", "pin": "g" }, { "device": "XME4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "xe", "ground": false, "terminals": [ { "device": "XME2", "pin": "d" }, { "device": "XME4", "pin": "d" }, { "device": "XME5", "pin": "g" }, { "device": "XRzE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XME2", "pin": "g" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "ze", "ground": false, "terminals": [ { "device": "XRzE", "pin": "n" }, { "device": "XCcE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCo", "pin": "p" }, { "device": "XRb", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldobufref" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Bias reference", "devices": [ { "scope": "dut", "device": "XMB" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "Buffer tail", "devices": [ { "scope": "dut", "device": "XMTA" } ], "inferredStages": [ 1 ] }, { "id": "block-3", "label": "Buffer second-stage sink", "devices": [ { "scope": "dut", "device": "XMSA" } ], "inferredStages": [ 2 ] }, { "id": "block-4", "label": "Error amplifier tail", "devices": [ { "scope": "dut", "device": "XMTE" } ], "inferredStages": [ 1 ] }, { "id": "block-5", "label": "Error amplifier second-stage sink", "devices": [ { "scope": "dut", "device": "XMSE" } ], "inferredStages": [ 2 ] }, { "id": "block-6", "label": "Buffer input pair", "devices": [ { "scope": "dut", "device": "XMA1" }, { "scope": "dut", "device": "XMA2" } ], "inferredStages": [ 2, 1 ] }, { "id": "block-7", "label": "Buffer mirror", "devices": [ { "scope": "dut", "device": "XMA3" }, { "scope": "dut", "device": "XMA4" } ], "inferredStages": [ 2, 1 ] }, { "id": "block-8", "label": "Buffer second stage", "devices": [ { "scope": "dut", "device": "XMA5" } ], "inferredStages": [ 2 ] }, { "id": "block-9", "label": "Buffer zero resistor", "devices": [ { "scope": "dut", "device": "XRzA" } ], "inferredStages": [ "comp" ] }, { "id": "block-10", "label": "Buffer Miller capacitor", "devices": [ { "scope": "dut", "device": "XCcA" } ], "inferredStages": [ "comp" ] }, { "id": "block-11", "label": "Buffer feedback", "devices": [ { "scope": "dut", "device": "XRA1" }, { "scope": "dut", "device": "XRA2" } ], "inferredStages": [ 2 ] }, { "id": "block-12", "label": "Reference filter resistor", "devices": [ { "scope": "dut", "device": "XRf" } ], "inferredStages": [ 2 ] }, { "id": "block-13", "label": "Reference filter capacitor", "devices": [ { "scope": "dut", "device": "XCf" } ], "inferredStages": [ 2 ] }, { "id": "block-14", "label": "Error amplifier input pair", "devices": [ { "scope": "dut", "device": "XME1" }, { "scope": "dut", "device": "XME2" } ], "inferredStages": [ 2, 1 ] }, { "id": "block-15", "label": "Error amplifier mirror", "devices": [ { "scope": "dut", "device": "XME3" }, { "scope": "dut", "device": "XME4" } ], "inferredStages": [ 2, 1 ] }, { "id": "block-16", "label": "Error amplifier second stage", "devices": [ { "scope": "dut", "device": "XME5" } ], "inferredStages": [ 2 ] }, { "id": "block-17", "label": "Error amplifier zero resistor", "devices": [ { "scope": "dut", "device": "XRzE" } ], "inferredStages": [ "comp" ] }, { "id": "block-18", "label": "Error amplifier Miller capacitor", "devices": [ { "scope": "dut", "device": "XCcE" } ], "inferredStages": [ "comp" ] }, { "id": "block-19", "label": "Pass device", "devices": [ { "scope": "dut", "device": "XMP" } ], "inferredStages": [ 3 ] }, { "id": "block-20", "label": "On-chip output capacitor", "devices": [ { "scope": "dut", "device": "XCo" } ], "inferredStages": [ 3 ] }, { "id": "block-21", "label": "Bleed: the least MP always carries", "devices": [ { "scope": "dut", "device": "XRb" } ], "inferredStages": [ 3 ] } ], "edges": [ { "id": "net-1", "net": "ib", "nodes": [ "block-1", "block-2", "block-3", "block-4", "block-5" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "ta", "nodes": [ "block-2", "block-6" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "vbuf", "nodes": [ "block-3", "block-8", "block-10", "block-11", "block-12" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "te", "nodes": [ "block-4", "block-14" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "gate", "nodes": [ "block-5", "block-16", "block-18", "block-19" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "da", "nodes": [ "block-6", "block-7" ], "direction": "undirected-shared-net" }, { "id": "net-7", "net": "fbb", "nodes": [ "block-6", "block-11" ], "direction": "undirected-shared-net" }, { "id": "net-8", "net": "xa", "nodes": [ "block-6", "block-7", "block-8", "block-9" ], "direction": "undirected-shared-net" }, { "id": "net-9", "net": "za", "nodes": [ "block-9", "block-10" ], "direction": "undirected-shared-net" }, { "id": "net-10", "net": "vflt", "nodes": [ "block-12", "block-13", "block-14" ], "direction": "undirected-shared-net" }, { "id": "net-11", "net": "de", "nodes": [ "block-14", "block-15" ], "direction": "undirected-shared-net" }, { "id": "net-12", "net": "xe", "nodes": [ "block-14", "block-15", "block-16", "block-17" ], "direction": "undirected-shared-net" }, { "id": "net-13", "net": "ze", "nodes": [ "block-17", "block-18" ], "direction": "undirected-shared-net" }, { "id": "net-14", "net": "out", "nodes": [ "block-19", "block-20", "block-21" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "ref", "net": "ref", "kind": "input" }, { "name": "sense", "net": "sense", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [], "scopes": [ { "id": "dut", "name": "ldobufref", "ports": [ { "name": "ref", "net": "ref", "kind": "input" }, { "name": "sense", "net": "sense", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTA", "displayName": "MTA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "ta" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSA", "displayName": "MSA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTE", "displayName": "MTE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "te" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSE", "displayName": "MSE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=8", "source": "XMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "fbb" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA3", "displayName": "MA3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA4", "displayName": "MA4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA5", "displayName": "MA5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "xa" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzA", "displayName": "RzA", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRzA xa za vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "xa" }, { "id": "n", "net": "za" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcA", "displayName": "CcA", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=4", "source": "XCcA za vbuf cap_cmim w=28.814u l=28.814u m=4", "pins": [ { "id": "p", "net": "za" }, { "id": "n", "net": "vbuf" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRA1", "displayName": "RA1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA1 vbuf fbb vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "fbb" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRA2", "displayName": "RA2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA2 fbb vss vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "fbb" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRf", "displayName": "Rf", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRf vbuf vflt vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "vflt" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCf vflt vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "vflt" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XME1", "displayName": "ME1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "vflt" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME2", "displayName": "ME2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME3", "displayName": "ME3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME4", "displayName": "ME4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME5", "displayName": "ME5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "xe" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzE", "displayName": "RzE", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=107.989u", "source": "XRzE xe ze vss rhigh w=0.5u l=107.989u", "pins": [ { "id": "p", "net": "xe" }, { "id": "n", "net": "ze" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcE", "displayName": "CcE", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCcE ze gate cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "ze" }, { "id": "n", "net": "gate" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=600u l=450n ng=120 m=1", "source": "XMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCo", "displayName": "Co", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCo out vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XRb out vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMTA", "pin": "g" }, { "device": "XMSA", "pin": "g" }, { "device": "XMTE", "pin": "g" }, { "device": "XMSE", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMTA", "pin": "s" }, { "device": "XMTA", "pin": "b" }, { "device": "XMSA", "pin": "s" }, { "device": "XMSA", "pin": "b" }, { "device": "XMTE", "pin": "s" }, { "device": "XMTE", "pin": "b" }, { "device": "XMSE", "pin": "s" }, { "device": "XMSE", "pin": "b" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "b" }, { "device": "XRzA", "pin": "substrate" }, { "device": "XRA1", "pin": "substrate" }, { "device": "XRA2", "pin": "n" }, { "device": "XRA2", "pin": "substrate" }, { "device": "XRf", "pin": "substrate" }, { "device": "XCf", "pin": "n" }, { "device": "XME1", "pin": "b" }, { "device": "XME2", "pin": "b" }, { "device": "XRzE", "pin": "substrate" }, { "device": "XCo", "pin": "n" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "ta", "ground": false, "terminals": [ { "device": "XMTA", "pin": "d" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vbuf", "ground": false, "terminals": [ { "device": "XMSA", "pin": "d" }, { "device": "XMA5", "pin": "d" }, { "device": "XCcA", "pin": "n" }, { "device": "XRA1", "pin": "p" }, { "device": "XRf", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "te", "ground": false, "terminals": [ { "device": "XMTE", "pin": "d" }, { "device": "XME1", "pin": "s" }, { "device": "XME2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XMSE", "pin": "d" }, { "device": "XME5", "pin": "d" }, { "device": "XCcE", "pin": "n" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "da", "ground": false, "terminals": [ { "device": "XMA1", "pin": "d" }, { "device": "XMA3", "pin": "d" }, { "device": "XMA3", "pin": "g" }, { "device": "XMA4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "fbb", "ground": false, "terminals": [ { "device": "XMA1", "pin": "g" }, { "device": "XRA1", "pin": "n" }, { "device": "XRA2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "xa", "ground": false, "terminals": [ { "device": "XMA2", "pin": "d" }, { "device": "XMA4", "pin": "d" }, { "device": "XMA5", "pin": "g" }, { "device": "XRzA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XMA2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMA3", "pin": "s" }, { "device": "XMA3", "pin": "b" }, { "device": "XMA4", "pin": "s" }, { "device": "XMA4", "pin": "b" }, { "device": "XMA5", "pin": "s" }, { "device": "XMA5", "pin": "b" }, { "device": "XME3", "pin": "s" }, { "device": "XME3", "pin": "b" }, { "device": "XME4", "pin": "s" }, { "device": "XME4", "pin": "b" }, { "device": "XME5", "pin": "s" }, { "device": "XME5", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "za", "ground": false, "terminals": [ { "device": "XRzA", "pin": "n" }, { "device": "XCcA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vflt", "ground": false, "terminals": [ { "device": "XRf", "pin": "n" }, { "device": "XCf", "pin": "p" }, { "device": "XME1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "de", "ground": false, "terminals": [ { "device": "XME1", "pin": "d" }, { "device": "XME3", "pin": "d" }, { "device": "XME3", "pin": "g" }, { "device": "XME4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "xe", "ground": false, "terminals": [ { "device": "XME2", "pin": "d" }, { "device": "XME4", "pin": "d" }, { "device": "XME5", "pin": "g" }, { "device": "XRzE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XME2", "pin": "g" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "ze", "ground": false, "terminals": [ { "device": "XRzE", "pin": "n" }, { "device": "XCcE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCo", "pin": "p" }, { "device": "XRb", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ] }, { "id": "graph-5", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc 3.3", "source": "Vdd vdd 0 dc 3.3", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.25", "source": "Vref ref 0 dc 1.25", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib vdd ib dc 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldobufref", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldobufref", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldobufref" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "1u", "source": "Cl out 0 1u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vload il 0 dc 0", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldobufref", "name": "ldobufref", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTA", "displayName": "MTA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "ta" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSA", "displayName": "MSA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTE", "displayName": "MTE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "te" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSE", "displayName": "MSE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=8", "source": "XMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "fbb" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA3", "displayName": "MA3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA4", "displayName": "MA4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA5", "displayName": "MA5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "xa" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzA", "displayName": "RzA", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRzA xa za vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "xa" }, { "id": "n", "net": "za" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcA", "displayName": "CcA", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=4", "source": "XCcA za vbuf cap_cmim w=28.814u l=28.814u m=4", "pins": [ { "id": "p", "net": "za" }, { "id": "n", "net": "vbuf" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRA1", "displayName": "RA1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA1 vbuf fbb vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "fbb" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRA2", "displayName": "RA2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA2 fbb vss vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "fbb" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRf", "displayName": "Rf", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRf vbuf vflt vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "vflt" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCf vflt vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "vflt" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XME1", "displayName": "ME1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "vflt" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME2", "displayName": "ME2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME3", "displayName": "ME3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME4", "displayName": "ME4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME5", "displayName": "ME5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "xe" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzE", "displayName": "RzE", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=107.989u", "source": "XRzE xe ze vss rhigh w=0.5u l=107.989u", "pins": [ { "id": "p", "net": "xe" }, { "id": "n", "net": "ze" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcE", "displayName": "CcE", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCcE ze gate cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "ze" }, { "id": "n", "net": "gate" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=600u l=450n ng=120 m=1", "source": "XMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCo", "displayName": "Co", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCo out vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XRb out vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMTA", "pin": "g" }, { "device": "XMSA", "pin": "g" }, { "device": "XMTE", "pin": "g" }, { "device": "XMSE", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMTA", "pin": "s" }, { "device": "XMTA", "pin": "b" }, { "device": "XMSA", "pin": "s" }, { "device": "XMSA", "pin": "b" }, { "device": "XMTE", "pin": "s" }, { "device": "XMTE", "pin": "b" }, { "device": "XMSE", "pin": "s" }, { "device": "XMSE", "pin": "b" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "b" }, { "device": "XRzA", "pin": "substrate" }, { "device": "XRA1", "pin": "substrate" }, { "device": "XRA2", "pin": "n" }, { "device": "XRA2", "pin": "substrate" }, { "device": "XRf", "pin": "substrate" }, { "device": "XCf", "pin": "n" }, { "device": "XME1", "pin": "b" }, { "device": "XME2", "pin": "b" }, { "device": "XRzE", "pin": "substrate" }, { "device": "XCo", "pin": "n" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "ta", "ground": false, "terminals": [ { "device": "XMTA", "pin": "d" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vbuf", "ground": false, "terminals": [ { "device": "XMSA", "pin": "d" }, { "device": "XMA5", "pin": "d" }, { "device": "XCcA", "pin": "n" }, { "device": "XRA1", "pin": "p" }, { "device": "XRf", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "te", "ground": false, "terminals": [ { "device": "XMTE", "pin": "d" }, { "device": "XME1", "pin": "s" }, { "device": "XME2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XMSE", "pin": "d" }, { "device": "XME5", "pin": "d" }, { "device": "XCcE", "pin": "n" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "da", "ground": false, "terminals": [ { "device": "XMA1", "pin": "d" }, { "device": "XMA3", "pin": "d" }, { "device": "XMA3", "pin": "g" }, { "device": "XMA4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "fbb", "ground": false, "terminals": [ { "device": "XMA1", "pin": "g" }, { "device": "XRA1", "pin": "n" }, { "device": "XRA2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "xa", "ground": false, "terminals": [ { "device": "XMA2", "pin": "d" }, { "device": "XMA4", "pin": "d" }, { "device": "XMA5", "pin": "g" }, { "device": "XRzA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XMA2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMA3", "pin": "s" }, { "device": "XMA3", "pin": "b" }, { "device": "XMA4", "pin": "s" }, { "device": "XMA4", "pin": "b" }, { "device": "XMA5", "pin": "s" }, { "device": "XMA5", "pin": "b" }, { "device": "XME3", "pin": "s" }, { "device": "XME3", "pin": "b" }, { "device": "XME4", "pin": "s" }, { "device": "XME4", "pin": "b" }, { "device": "XME5", "pin": "s" }, { "device": "XME5", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "za", "ground": false, "terminals": [ { "device": "XRzA", "pin": "n" }, { "device": "XCcA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vflt", "ground": false, "terminals": [ { "device": "XRf", "pin": "n" }, { "device": "XCf", "pin": "p" }, { "device": "XME1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "de", "ground": false, "terminals": [ { "device": "XME1", "pin": "d" }, { "device": "XME3", "pin": "d" }, { "device": "XME3", "pin": "g" }, { "device": "XME4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "xe", "ground": false, "terminals": [ { "device": "XME2", "pin": "d" }, { "device": "XME4", "pin": "d" }, { "device": "XME5", "pin": "g" }, { "device": "XRzE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XME2", "pin": "g" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "ze", "ground": false, "terminals": [ { "device": "XRzE", "pin": "n" }, { "device": "XCcE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCo", "pin": "p" }, { "device": "XRb", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldobufref" } }, { "id": "graph-6", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc 3.3", "source": "Vdd vdd 0 dc 3.3", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.25", "source": "Vref ref 0 dc 1.25", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib vdd ib dc 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldobufref", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldobufref", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldobufref" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "1u", "source": "Cl out 0 1u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "dc 10m", "source": "Vload il 0 dc 10m", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldobufref", "name": "ldobufref", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTA", "displayName": "MTA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "ta" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSA", "displayName": "MSA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTE", "displayName": "MTE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "te" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSE", "displayName": "MSE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=8", "source": "XMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "fbb" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA3", "displayName": "MA3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA4", "displayName": "MA4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA5", "displayName": "MA5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "xa" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzA", "displayName": "RzA", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRzA xa za vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "xa" }, { "id": "n", "net": "za" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcA", "displayName": "CcA", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=4", "source": "XCcA za vbuf cap_cmim w=28.814u l=28.814u m=4", "pins": [ { "id": "p", "net": "za" }, { "id": "n", "net": "vbuf" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRA1", "displayName": "RA1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA1 vbuf fbb vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "fbb" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRA2", "displayName": "RA2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA2 fbb vss vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "fbb" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRf", "displayName": "Rf", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRf vbuf vflt vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "vflt" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCf vflt vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "vflt" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XME1", "displayName": "ME1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "vflt" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME2", "displayName": "ME2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME3", "displayName": "ME3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME4", "displayName": "ME4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME5", "displayName": "ME5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "xe" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzE", "displayName": "RzE", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=107.989u", "source": "XRzE xe ze vss rhigh w=0.5u l=107.989u", "pins": [ { "id": "p", "net": "xe" }, { "id": "n", "net": "ze" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcE", "displayName": "CcE", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCcE ze gate cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "ze" }, { "id": "n", "net": "gate" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=600u l=450n ng=120 m=1", "source": "XMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCo", "displayName": "Co", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCo out vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XRb out vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMTA", "pin": "g" }, { "device": "XMSA", "pin": "g" }, { "device": "XMTE", "pin": "g" }, { "device": "XMSE", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMTA", "pin": "s" }, { "device": "XMTA", "pin": "b" }, { "device": "XMSA", "pin": "s" }, { "device": "XMSA", "pin": "b" }, { "device": "XMTE", "pin": "s" }, { "device": "XMTE", "pin": "b" }, { "device": "XMSE", "pin": "s" }, { "device": "XMSE", "pin": "b" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "b" }, { "device": "XRzA", "pin": "substrate" }, { "device": "XRA1", "pin": "substrate" }, { "device": "XRA2", "pin": "n" }, { "device": "XRA2", "pin": "substrate" }, { "device": "XRf", "pin": "substrate" }, { "device": "XCf", "pin": "n" }, { "device": "XME1", "pin": "b" }, { "device": "XME2", "pin": "b" }, { "device": "XRzE", "pin": "substrate" }, { "device": "XCo", "pin": "n" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "ta", "ground": false, "terminals": [ { "device": "XMTA", "pin": "d" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vbuf", "ground": false, "terminals": [ { "device": "XMSA", "pin": "d" }, { "device": "XMA5", "pin": "d" }, { "device": "XCcA", "pin": "n" }, { "device": "XRA1", "pin": "p" }, { "device": "XRf", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "te", "ground": false, "terminals": [ { "device": "XMTE", "pin": "d" }, { "device": "XME1", "pin": "s" }, { "device": "XME2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XMSE", "pin": "d" }, { "device": "XME5", "pin": "d" }, { "device": "XCcE", "pin": "n" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "da", "ground": false, "terminals": [ { "device": "XMA1", "pin": "d" }, { "device": "XMA3", "pin": "d" }, { "device": "XMA3", "pin": "g" }, { "device": "XMA4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "fbb", "ground": false, "terminals": [ { "device": "XMA1", "pin": "g" }, { "device": "XRA1", "pin": "n" }, { "device": "XRA2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "xa", "ground": false, "terminals": [ { "device": "XMA2", "pin": "d" }, { "device": "XMA4", "pin": "d" }, { "device": "XMA5", "pin": "g" }, { "device": "XRzA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XMA2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMA3", "pin": "s" }, { "device": "XMA3", "pin": "b" }, { "device": "XMA4", "pin": "s" }, { "device": "XMA4", "pin": "b" }, { "device": "XMA5", "pin": "s" }, { "device": "XMA5", "pin": "b" }, { "device": "XME3", "pin": "s" }, { "device": "XME3", "pin": "b" }, { "device": "XME4", "pin": "s" }, { "device": "XME4", "pin": "b" }, { "device": "XME5", "pin": "s" }, { "device": "XME5", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "za", "ground": false, "terminals": [ { "device": "XRzA", "pin": "n" }, { "device": "XCcA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vflt", "ground": false, "terminals": [ { "device": "XRf", "pin": "n" }, { "device": "XCf", "pin": "p" }, { "device": "XME1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "de", "ground": false, "terminals": [ { "device": "XME1", "pin": "d" }, { "device": "XME3", "pin": "d" }, { "device": "XME3", "pin": "g" }, { "device": "XME4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "xe", "ground": false, "terminals": [ { "device": "XME2", "pin": "d" }, { "device": "XME4", "pin": "d" }, { "device": "XME5", "pin": "g" }, { "device": "XRzE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XME2", "pin": "g" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "ze", "ground": false, "terminals": [ { "device": "XRzE", "pin": "n" }, { "device": "XCcE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCo", "pin": "p" }, { "device": "XRb", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldobufref" } }, { "id": "graph-7", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=3.3" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=3.3" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.25", "source": "Vref ref 0 dc 1.25", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib vdd ib dc 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldobufref", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldobufref", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldobufref" }, { "id": "Vinj", "displayName": "Vinj", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Vinj sense out dc 0 ac 1", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "1u", "source": "Cl out 0 1u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "dc 10m", "source": "Vload il 0 dc 10m", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vinj", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vinj", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldobufref", "name": "ldobufref", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTA", "displayName": "MTA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "ta" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSA", "displayName": "MSA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTE", "displayName": "MTE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "te" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSE", "displayName": "MSE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=8", "source": "XMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "fbb" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA3", "displayName": "MA3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA4", "displayName": "MA4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA5", "displayName": "MA5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "xa" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzA", "displayName": "RzA", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRzA xa za vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "xa" }, { "id": "n", "net": "za" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcA", "displayName": "CcA", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=4", "source": "XCcA za vbuf cap_cmim w=28.814u l=28.814u m=4", "pins": [ { "id": "p", "net": "za" }, { "id": "n", "net": "vbuf" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRA1", "displayName": "RA1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA1 vbuf fbb vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "fbb" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRA2", "displayName": "RA2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA2 fbb vss vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "fbb" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRf", "displayName": "Rf", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRf vbuf vflt vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "vflt" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCf vflt vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "vflt" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XME1", "displayName": "ME1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "vflt" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME2", "displayName": "ME2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME3", "displayName": "ME3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME4", "displayName": "ME4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME5", "displayName": "ME5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "xe" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzE", "displayName": "RzE", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=107.989u", "source": "XRzE xe ze vss rhigh w=0.5u l=107.989u", "pins": [ { "id": "p", "net": "xe" }, { "id": "n", "net": "ze" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcE", "displayName": "CcE", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCcE ze gate cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "ze" }, { "id": "n", "net": "gate" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=600u l=450n ng=120 m=1", "source": "XMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCo", "displayName": "Co", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCo out vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XRb out vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMTA", "pin": "g" }, { "device": "XMSA", "pin": "g" }, { "device": "XMTE", "pin": "g" }, { "device": "XMSE", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMTA", "pin": "s" }, { "device": "XMTA", "pin": "b" }, { "device": "XMSA", "pin": "s" }, { "device": "XMSA", "pin": "b" }, { "device": "XMTE", "pin": "s" }, { "device": "XMTE", "pin": "b" }, { "device": "XMSE", "pin": "s" }, { "device": "XMSE", "pin": "b" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "b" }, { "device": "XRzA", "pin": "substrate" }, { "device": "XRA1", "pin": "substrate" }, { "device": "XRA2", "pin": "n" }, { "device": "XRA2", "pin": "substrate" }, { "device": "XRf", "pin": "substrate" }, { "device": "XCf", "pin": "n" }, { "device": "XME1", "pin": "b" }, { "device": "XME2", "pin": "b" }, { "device": "XRzE", "pin": "substrate" }, { "device": "XCo", "pin": "n" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "ta", "ground": false, "terminals": [ { "device": "XMTA", "pin": "d" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vbuf", "ground": false, "terminals": [ { "device": "XMSA", "pin": "d" }, { "device": "XMA5", "pin": "d" }, { "device": "XCcA", "pin": "n" }, { "device": "XRA1", "pin": "p" }, { "device": "XRf", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "te", "ground": false, "terminals": [ { "device": "XMTE", "pin": "d" }, { "device": "XME1", "pin": "s" }, { "device": "XME2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XMSE", "pin": "d" }, { "device": "XME5", "pin": "d" }, { "device": "XCcE", "pin": "n" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "da", "ground": false, "terminals": [ { "device": "XMA1", "pin": "d" }, { "device": "XMA3", "pin": "d" }, { "device": "XMA3", "pin": "g" }, { "device": "XMA4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "fbb", "ground": false, "terminals": [ { "device": "XMA1", "pin": "g" }, { "device": "XRA1", "pin": "n" }, { "device": "XRA2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "xa", "ground": false, "terminals": [ { "device": "XMA2", "pin": "d" }, { "device": "XMA4", "pin": "d" }, { "device": "XMA5", "pin": "g" }, { "device": "XRzA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XMA2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMA3", "pin": "s" }, { "device": "XMA3", "pin": "b" }, { "device": "XMA4", "pin": "s" }, { "device": "XMA4", "pin": "b" }, { "device": "XMA5", "pin": "s" }, { "device": "XMA5", "pin": "b" }, { "device": "XME3", "pin": "s" }, { "device": "XME3", "pin": "b" }, { "device": "XME4", "pin": "s" }, { "device": "XME4", "pin": "b" }, { "device": "XME5", "pin": "s" }, { "device": "XME5", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "za", "ground": false, "terminals": [ { "device": "XRzA", "pin": "n" }, { "device": "XCcA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vflt", "ground": false, "terminals": [ { "device": "XRf", "pin": "n" }, { "device": "XCf", "pin": "p" }, { "device": "XME1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "de", "ground": false, "terminals": [ { "device": "XME1", "pin": "d" }, { "device": "XME3", "pin": "d" }, { "device": "XME3", "pin": "g" }, { "device": "XME4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "xe", "ground": false, "terminals": [ { "device": "XME2", "pin": "d" }, { "device": "XME4", "pin": "d" }, { "device": "XME5", "pin": "g" }, { "device": "XRzE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XME2", "pin": "g" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "ze", "ground": false, "terminals": [ { "device": "XRzE", "pin": "n" }, { "device": "XCcE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCo", "pin": "p" }, { "device": "XRb", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldobufref" } }, { "id": "graph-8", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=3.3" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=3.3" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.25", "source": "Vref ref 0 dc 1.25", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib vdd ib dc 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldobufref", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldobufref", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldobufref" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "1u", "source": "Cl out 0 1u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "pwl(0 0 400u 0 401u 40u 1m 40u 1.001m 10u 1.4m 10u 1.401m 50u 2m 50u 2.001m 100u 2.4m 100u 2.401m 140u 3m 140u 3.001m 1m 3.4m 1m 3.401m 1.1m 4m 1.1m 4.001m 10m 4.4m 10m 4.401m 11m 5m 11m)", "source": "Vload il 0 pwl(0 0 400u 0 401u 40u 1m 40u 1.001m 10u 1.4m 10u 1.401m 50u 2m 50u 2.001m 100u 2.4m 100u 2.401m 140u 3m 140u 3.001m 1m 3.4m 1m 3.401m 1.1m 4m 1.1m 4.001m 10m 4.4m 10m 4.401m 11m 5m 11m)", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldobufref", "name": "ldobufref", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTA", "displayName": "MTA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "ta" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSA", "displayName": "MSA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTE", "displayName": "MTE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "te" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSE", "displayName": "MSE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=8", "source": "XMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "fbb" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA3", "displayName": "MA3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA4", "displayName": "MA4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA5", "displayName": "MA5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "xa" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzA", "displayName": "RzA", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRzA xa za vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "xa" }, { "id": "n", "net": "za" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcA", "displayName": "CcA", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=4", "source": "XCcA za vbuf cap_cmim w=28.814u l=28.814u m=4", "pins": [ { "id": "p", "net": "za" }, { "id": "n", "net": "vbuf" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRA1", "displayName": "RA1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA1 vbuf fbb vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "fbb" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRA2", "displayName": "RA2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA2 fbb vss vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "fbb" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRf", "displayName": "Rf", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRf vbuf vflt vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "vflt" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCf vflt vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "vflt" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XME1", "displayName": "ME1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "vflt" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME2", "displayName": "ME2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME3", "displayName": "ME3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME4", "displayName": "ME4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME5", "displayName": "ME5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "xe" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzE", "displayName": "RzE", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=107.989u", "source": "XRzE xe ze vss rhigh w=0.5u l=107.989u", "pins": [ { "id": "p", "net": "xe" }, { "id": "n", "net": "ze" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcE", "displayName": "CcE", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCcE ze gate cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "ze" }, { "id": "n", "net": "gate" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=600u l=450n ng=120 m=1", "source": "XMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCo", "displayName": "Co", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCo out vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XRb out vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMTA", "pin": "g" }, { "device": "XMSA", "pin": "g" }, { "device": "XMTE", "pin": "g" }, { "device": "XMSE", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMTA", "pin": "s" }, { "device": "XMTA", "pin": "b" }, { "device": "XMSA", "pin": "s" }, { "device": "XMSA", "pin": "b" }, { "device": "XMTE", "pin": "s" }, { "device": "XMTE", "pin": "b" }, { "device": "XMSE", "pin": "s" }, { "device": "XMSE", "pin": "b" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "b" }, { "device": "XRzA", "pin": "substrate" }, { "device": "XRA1", "pin": "substrate" }, { "device": "XRA2", "pin": "n" }, { "device": "XRA2", "pin": "substrate" }, { "device": "XRf", "pin": "substrate" }, { "device": "XCf", "pin": "n" }, { "device": "XME1", "pin": "b" }, { "device": "XME2", "pin": "b" }, { "device": "XRzE", "pin": "substrate" }, { "device": "XCo", "pin": "n" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "ta", "ground": false, "terminals": [ { "device": "XMTA", "pin": "d" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vbuf", "ground": false, "terminals": [ { "device": "XMSA", "pin": "d" }, { "device": "XMA5", "pin": "d" }, { "device": "XCcA", "pin": "n" }, { "device": "XRA1", "pin": "p" }, { "device": "XRf", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "te", "ground": false, "terminals": [ { "device": "XMTE", "pin": "d" }, { "device": "XME1", "pin": "s" }, { "device": "XME2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XMSE", "pin": "d" }, { "device": "XME5", "pin": "d" }, { "device": "XCcE", "pin": "n" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "da", "ground": false, "terminals": [ { "device": "XMA1", "pin": "d" }, { "device": "XMA3", "pin": "d" }, { "device": "XMA3", "pin": "g" }, { "device": "XMA4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "fbb", "ground": false, "terminals": [ { "device": "XMA1", "pin": "g" }, { "device": "XRA1", "pin": "n" }, { "device": "XRA2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "xa", "ground": false, "terminals": [ { "device": "XMA2", "pin": "d" }, { "device": "XMA4", "pin": "d" }, { "device": "XMA5", "pin": "g" }, { "device": "XRzA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XMA2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMA3", "pin": "s" }, { "device": "XMA3", "pin": "b" }, { "device": "XMA4", "pin": "s" }, { "device": "XMA4", "pin": "b" }, { "device": "XMA5", "pin": "s" }, { "device": "XMA5", "pin": "b" }, { "device": "XME3", "pin": "s" }, { "device": "XME3", "pin": "b" }, { "device": "XME4", "pin": "s" }, { "device": "XME4", "pin": "b" }, { "device": "XME5", "pin": "s" }, { "device": "XME5", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "za", "ground": false, "terminals": [ { "device": "XRzA", "pin": "n" }, { "device": "XCcA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vflt", "ground": false, "terminals": [ { "device": "XRf", "pin": "n" }, { "device": "XCf", "pin": "p" }, { "device": "XME1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "de", "ground": false, "terminals": [ { "device": "XME1", "pin": "d" }, { "device": "XME3", "pin": "d" }, { "device": "XME3", "pin": "g" }, { "device": "XME4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "xe", "ground": false, "terminals": [ { "device": "XME2", "pin": "d" }, { "device": "XME4", "pin": "d" }, { "device": "XME5", "pin": "g" }, { "device": "XRzE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XME2", "pin": "g" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "ze", "ground": false, "terminals": [ { "device": "XRzE", "pin": "n" }, { "device": "XCcE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCo", "pin": "p" }, { "device": "XRb", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldobufref" } }, { "id": "graph-9", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=3.3" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=3.3" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD} ac 1", "source": "Vdd vdd 0 dc {VDD} ac 1", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.25", "source": "Vref ref 0 dc 1.25", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib vdd ib dc 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldobufref", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldobufref", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldobufref" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "1u", "source": "Cl out 0 1u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "dc 10m", "source": "Vload il 0 dc 10m", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldobufref", "name": "ldobufref", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTA", "displayName": "MTA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "ta" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSA", "displayName": "MSA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTE", "displayName": "MTE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "te" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSE", "displayName": "MSE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=8", "source": "XMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "fbb" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA3", "displayName": "MA3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA4", "displayName": "MA4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA5", "displayName": "MA5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "xa" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzA", "displayName": "RzA", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRzA xa za vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "xa" }, { "id": "n", "net": "za" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcA", "displayName": "CcA", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=4", "source": "XCcA za vbuf cap_cmim w=28.814u l=28.814u m=4", "pins": [ { "id": "p", "net": "za" }, { "id": "n", "net": "vbuf" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRA1", "displayName": "RA1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA1 vbuf fbb vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "fbb" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRA2", "displayName": "RA2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA2 fbb vss vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "fbb" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRf", "displayName": "Rf", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRf vbuf vflt vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "vflt" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCf vflt vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "vflt" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XME1", "displayName": "ME1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "vflt" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME2", "displayName": "ME2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME3", "displayName": "ME3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME4", "displayName": "ME4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME5", "displayName": "ME5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "xe" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzE", "displayName": "RzE", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=107.989u", "source": "XRzE xe ze vss rhigh w=0.5u l=107.989u", "pins": [ { "id": "p", "net": "xe" }, { "id": "n", "net": "ze" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcE", "displayName": "CcE", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCcE ze gate cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "ze" }, { "id": "n", "net": "gate" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=600u l=450n ng=120 m=1", "source": "XMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCo", "displayName": "Co", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCo out vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XRb out vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMTA", "pin": "g" }, { "device": "XMSA", "pin": "g" }, { "device": "XMTE", "pin": "g" }, { "device": "XMSE", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMTA", "pin": "s" }, { "device": "XMTA", "pin": "b" }, { "device": "XMSA", "pin": "s" }, { "device": "XMSA", "pin": "b" }, { "device": "XMTE", "pin": "s" }, { "device": "XMTE", "pin": "b" }, { "device": "XMSE", "pin": "s" }, { "device": "XMSE", "pin": "b" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "b" }, { "device": "XRzA", "pin": "substrate" }, { "device": "XRA1", "pin": "substrate" }, { "device": "XRA2", "pin": "n" }, { "device": "XRA2", "pin": "substrate" }, { "device": "XRf", "pin": "substrate" }, { "device": "XCf", "pin": "n" }, { "device": "XME1", "pin": "b" }, { "device": "XME2", "pin": "b" }, { "device": "XRzE", "pin": "substrate" }, { "device": "XCo", "pin": "n" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "ta", "ground": false, "terminals": [ { "device": "XMTA", "pin": "d" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vbuf", "ground": false, "terminals": [ { "device": "XMSA", "pin": "d" }, { "device": "XMA5", "pin": "d" }, { "device": "XCcA", "pin": "n" }, { "device": "XRA1", "pin": "p" }, { "device": "XRf", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "te", "ground": false, "terminals": [ { "device": "XMTE", "pin": "d" }, { "device": "XME1", "pin": "s" }, { "device": "XME2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XMSE", "pin": "d" }, { "device": "XME5", "pin": "d" }, { "device": "XCcE", "pin": "n" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "da", "ground": false, "terminals": [ { "device": "XMA1", "pin": "d" }, { "device": "XMA3", "pin": "d" }, { "device": "XMA3", "pin": "g" }, { "device": "XMA4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "fbb", "ground": false, "terminals": [ { "device": "XMA1", "pin": "g" }, { "device": "XRA1", "pin": "n" }, { "device": "XRA2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "xa", "ground": false, "terminals": [ { "device": "XMA2", "pin": "d" }, { "device": "XMA4", "pin": "d" }, { "device": "XMA5", "pin": "g" }, { "device": "XRzA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XMA2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMA3", "pin": "s" }, { "device": "XMA3", "pin": "b" }, { "device": "XMA4", "pin": "s" }, { "device": "XMA4", "pin": "b" }, { "device": "XMA5", "pin": "s" }, { "device": "XMA5", "pin": "b" }, { "device": "XME3", "pin": "s" }, { "device": "XME3", "pin": "b" }, { "device": "XME4", "pin": "s" }, { "device": "XME4", "pin": "b" }, { "device": "XME5", "pin": "s" }, { "device": "XME5", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "za", "ground": false, "terminals": [ { "device": "XRzA", "pin": "n" }, { "device": "XCcA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vflt", "ground": false, "terminals": [ { "device": "XRf", "pin": "n" }, { "device": "XCf", "pin": "p" }, { "device": "XME1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "de", "ground": false, "terminals": [ { "device": "XME1", "pin": "d" }, { "device": "XME3", "pin": "d" }, { "device": "XME3", "pin": "g" }, { "device": "XME4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "xe", "ground": false, "terminals": [ { "device": "XME2", "pin": "d" }, { "device": "XME4", "pin": "d" }, { "device": "XME5", "pin": "g" }, { "device": "XRzE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XME2", "pin": "g" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "ze", "ground": false, "terminals": [ { "device": "XRzE", "pin": "n" }, { "device": "XCcE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCo", "pin": "p" }, { "device": "XRb", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldobufref" } }, { "id": "graph-10", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=3.3" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=3.3" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.25", "source": "Vref ref 0 dc 1.25", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib vdd ib dc 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldobufref", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldobufref", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldobufref" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "1u", "source": "Cl out 0 1u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "pulse(0 10m 20u 1u 1u 89u 400u)", "source": "Vload il 0 pulse(0 10m 20u 1u 1u 89u 400u)", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldobufref", "name": "ldobufref", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTA", "displayName": "MTA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "ta" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSA", "displayName": "MSA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTE", "displayName": "MTE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "te" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSE", "displayName": "MSE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=8", "source": "XMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "fbb" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA3", "displayName": "MA3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA4", "displayName": "MA4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA5", "displayName": "MA5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "xa" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzA", "displayName": "RzA", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRzA xa za vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "xa" }, { "id": "n", "net": "za" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcA", "displayName": "CcA", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=4", "source": "XCcA za vbuf cap_cmim w=28.814u l=28.814u m=4", "pins": [ { "id": "p", "net": "za" }, { "id": "n", "net": "vbuf" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRA1", "displayName": "RA1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA1 vbuf fbb vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "fbb" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRA2", "displayName": "RA2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA2 fbb vss vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "fbb" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRf", "displayName": "Rf", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRf vbuf vflt vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "vflt" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCf vflt vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "vflt" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XME1", "displayName": "ME1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "vflt" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME2", "displayName": "ME2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME3", "displayName": "ME3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME4", "displayName": "ME4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME5", "displayName": "ME5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "xe" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzE", "displayName": "RzE", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=107.989u", "source": "XRzE xe ze vss rhigh w=0.5u l=107.989u", "pins": [ { "id": "p", "net": "xe" }, { "id": "n", "net": "ze" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcE", "displayName": "CcE", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCcE ze gate cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "ze" }, { "id": "n", "net": "gate" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=600u l=450n ng=120 m=1", "source": "XMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCo", "displayName": "Co", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCo out vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XRb out vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMTA", "pin": "g" }, { "device": "XMSA", "pin": "g" }, { "device": "XMTE", "pin": "g" }, { "device": "XMSE", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMTA", "pin": "s" }, { "device": "XMTA", "pin": "b" }, { "device": "XMSA", "pin": "s" }, { "device": "XMSA", "pin": "b" }, { "device": "XMTE", "pin": "s" }, { "device": "XMTE", "pin": "b" }, { "device": "XMSE", "pin": "s" }, { "device": "XMSE", "pin": "b" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "b" }, { "device": "XRzA", "pin": "substrate" }, { "device": "XRA1", "pin": "substrate" }, { "device": "XRA2", "pin": "n" }, { "device": "XRA2", "pin": "substrate" }, { "device": "XRf", "pin": "substrate" }, { "device": "XCf", "pin": "n" }, { "device": "XME1", "pin": "b" }, { "device": "XME2", "pin": "b" }, { "device": "XRzE", "pin": "substrate" }, { "device": "XCo", "pin": "n" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "ta", "ground": false, "terminals": [ { "device": "XMTA", "pin": "d" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vbuf", "ground": false, "terminals": [ { "device": "XMSA", "pin": "d" }, { "device": "XMA5", "pin": "d" }, { "device": "XCcA", "pin": "n" }, { "device": "XRA1", "pin": "p" }, { "device": "XRf", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "te", "ground": false, "terminals": [ { "device": "XMTE", "pin": "d" }, { "device": "XME1", "pin": "s" }, { "device": "XME2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XMSE", "pin": "d" }, { "device": "XME5", "pin": "d" }, { "device": "XCcE", "pin": "n" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "da", "ground": false, "terminals": [ { "device": "XMA1", "pin": "d" }, { "device": "XMA3", "pin": "d" }, { "device": "XMA3", "pin": "g" }, { "device": "XMA4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "fbb", "ground": false, "terminals": [ { "device": "XMA1", "pin": "g" }, { "device": "XRA1", "pin": "n" }, { "device": "XRA2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "xa", "ground": false, "terminals": [ { "device": "XMA2", "pin": "d" }, { "device": "XMA4", "pin": "d" }, { "device": "XMA5", "pin": "g" }, { "device": "XRzA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XMA2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMA3", "pin": "s" }, { "device": "XMA3", "pin": "b" }, { "device": "XMA4", "pin": "s" }, { "device": "XMA4", "pin": "b" }, { "device": "XMA5", "pin": "s" }, { "device": "XMA5", "pin": "b" }, { "device": "XME3", "pin": "s" }, { "device": "XME3", "pin": "b" }, { "device": "XME4", "pin": "s" }, { "device": "XME4", "pin": "b" }, { "device": "XME5", "pin": "s" }, { "device": "XME5", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "za", "ground": false, "terminals": [ { "device": "XRzA", "pin": "n" }, { "device": "XCcA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vflt", "ground": false, "terminals": [ { "device": "XRf", "pin": "n" }, { "device": "XCf", "pin": "p" }, { "device": "XME1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "de", "ground": false, "terminals": [ { "device": "XME1", "pin": "d" }, { "device": "XME3", "pin": "d" }, { "device": "XME3", "pin": "g" }, { "device": "XME4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "xe", "ground": false, "terminals": [ { "device": "XME2", "pin": "d" }, { "device": "XME4", "pin": "d" }, { "device": "XME5", "pin": "g" }, { "device": "XRzE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XME2", "pin": "g" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "ze", "ground": false, "terminals": [ { "device": "XRzE", "pin": "n" }, { "device": "XCcE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCo", "pin": "p" }, { "device": "XRb", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldobufref" } }, { "id": "graph-11", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "pulse(2.97 3.63 20u 1u 1u 89u 400u)", "source": "Vdd vdd 0 pulse(2.97 3.63 20u 1u 1u 89u 400u)", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.25", "source": "Vref ref 0 dc 1.25", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib vdd ib dc 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldobufref", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldobufref", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldobufref" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "1u", "source": "Cl out 0 1u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "dc 10m", "source": "Vload il 0 dc 10m", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldobufref", "name": "ldobufref", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTA", "displayName": "MTA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "ta" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSA", "displayName": "MSA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTE", "displayName": "MTE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "te" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSE", "displayName": "MSE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=8", "source": "XMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "fbb" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA3", "displayName": "MA3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA4", "displayName": "MA4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA5", "displayName": "MA5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "xa" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzA", "displayName": "RzA", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRzA xa za vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "xa" }, { "id": "n", "net": "za" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcA", "displayName": "CcA", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=4", "source": "XCcA za vbuf cap_cmim w=28.814u l=28.814u m=4", "pins": [ { "id": "p", "net": "za" }, { "id": "n", "net": "vbuf" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRA1", "displayName": "RA1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA1 vbuf fbb vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "fbb" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRA2", "displayName": "RA2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA2 fbb vss vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "fbb" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRf", "displayName": "Rf", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRf vbuf vflt vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "vflt" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCf vflt vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "vflt" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XME1", "displayName": "ME1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "vflt" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME2", "displayName": "ME2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME3", "displayName": "ME3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME4", "displayName": "ME4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME5", "displayName": "ME5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "xe" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzE", "displayName": "RzE", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=107.989u", "source": "XRzE xe ze vss rhigh w=0.5u l=107.989u", "pins": [ { "id": "p", "net": "xe" }, { "id": "n", "net": "ze" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcE", "displayName": "CcE", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCcE ze gate cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "ze" }, { "id": "n", "net": "gate" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=600u l=450n ng=120 m=1", "source": "XMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCo", "displayName": "Co", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCo out vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XRb out vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMTA", "pin": "g" }, { "device": "XMSA", "pin": "g" }, { "device": "XMTE", "pin": "g" }, { "device": "XMSE", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMTA", "pin": "s" }, { "device": "XMTA", "pin": "b" }, { "device": "XMSA", "pin": "s" }, { "device": "XMSA", "pin": "b" }, { "device": "XMTE", "pin": "s" }, { "device": "XMTE", "pin": "b" }, { "device": "XMSE", "pin": "s" }, { "device": "XMSE", "pin": "b" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "b" }, { "device": "XRzA", "pin": "substrate" }, { "device": "XRA1", "pin": "substrate" }, { "device": "XRA2", "pin": "n" }, { "device": "XRA2", "pin": "substrate" }, { "device": "XRf", "pin": "substrate" }, { "device": "XCf", "pin": "n" }, { "device": "XME1", "pin": "b" }, { "device": "XME2", "pin": "b" }, { "device": "XRzE", "pin": "substrate" }, { "device": "XCo", "pin": "n" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "ta", "ground": false, "terminals": [ { "device": "XMTA", "pin": "d" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vbuf", "ground": false, "terminals": [ { "device": "XMSA", "pin": "d" }, { "device": "XMA5", "pin": "d" }, { "device": "XCcA", "pin": "n" }, { "device": "XRA1", "pin": "p" }, { "device": "XRf", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "te", "ground": false, "terminals": [ { "device": "XMTE", "pin": "d" }, { "device": "XME1", "pin": "s" }, { "device": "XME2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XMSE", "pin": "d" }, { "device": "XME5", "pin": "d" }, { "device": "XCcE", "pin": "n" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "da", "ground": false, "terminals": [ { "device": "XMA1", "pin": "d" }, { "device": "XMA3", "pin": "d" }, { "device": "XMA3", "pin": "g" }, { "device": "XMA4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "fbb", "ground": false, "terminals": [ { "device": "XMA1", "pin": "g" }, { "device": "XRA1", "pin": "n" }, { "device": "XRA2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "xa", "ground": false, "terminals": [ { "device": "XMA2", "pin": "d" }, { "device": "XMA4", "pin": "d" }, { "device": "XMA5", "pin": "g" }, { "device": "XRzA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XMA2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMA3", "pin": "s" }, { "device": "XMA3", "pin": "b" }, { "device": "XMA4", "pin": "s" }, { "device": "XMA4", "pin": "b" }, { "device": "XMA5", "pin": "s" }, { "device": "XMA5", "pin": "b" }, { "device": "XME3", "pin": "s" }, { "device": "XME3", "pin": "b" }, { "device": "XME4", "pin": "s" }, { "device": "XME4", "pin": "b" }, { "device": "XME5", "pin": "s" }, { "device": "XME5", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "za", "ground": false, "terminals": [ { "device": "XRzA", "pin": "n" }, { "device": "XCcA", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vflt", "ground": false, "terminals": [ { "device": "XRf", "pin": "n" }, { "device": "XCf", "pin": "p" }, { "device": "XME1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "de", "ground": false, "terminals": [ { "device": "XME1", "pin": "d" }, { "device": "XME3", "pin": "d" }, { "device": "XME3", "pin": "g" }, { "device": "XME4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "xe", "ground": false, "terminals": [ { "device": "XME2", "pin": "d" }, { "device": "XME4", "pin": "d" }, { "device": "XME5", "pin": "g" }, { "device": "XRzE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XME2", "pin": "g" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "ze", "ground": false, "terminals": [ { "device": "XRzE", "pin": "n" }, { "device": "XCcE", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCo", "pin": "p" }, { "device": "XRb", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldobufref" } }, { "id": "graph-12", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=3.3" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=3.3" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "pulse(1.25 1.3 1u 100n 100n 20u 40u)", "source": "Vref ref 0 pulse(1.25 1.3 1u 100n 100n 20u 40u)", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib vdd ib dc 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldobufref", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldobufref", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldobufref" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "1u", "source": "Cl out 0 1u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ldobufref", "name": "ldobufref", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTA", "displayName": "MTA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=2", "source": "XMTA ta ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=2", "pins": [ { "id": "d", "net": "ta" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSA", "displayName": "MSA", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMSA vbuf ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMTE", "displayName": "MTE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMTE te ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "te" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMSE", "displayName": "MSE", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=8", "source": "XMSE gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA1 da fbb ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "fbb" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA2 xa ref ta vss sg13_hv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ta" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA3", "displayName": "MA3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA3 da da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "da" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA4", "displayName": "MA4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XMA4 xa da vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xa" }, { "id": "g", "net": "da" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA5", "displayName": "MA5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XMA5 vbuf xa vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "vbuf" }, { "id": "g", "net": "xa" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzA", "displayName": "RzA", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRzA xa za vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "xa" }, { "id": "n", "net": "za" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcA", "displayName": "CcA", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=4", "source": "XCcA za vbuf cap_cmim w=28.814u l=28.814u m=4", "pins": [ { "id": "p", "net": "za" }, { "id": "n", "net": "vbuf" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRA1", "displayName": "RA1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA1 vbuf fbb vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "fbb" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRA2", "displayName": "RA2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRA2 fbb vss vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "fbb" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRf", "displayName": "Rf", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=1544.019u", "source": "XRf vbuf vflt vss rhigh w=0.5u l=1544.019u", "pins": [ { "id": "p", "net": "vbuf" }, { "id": "n", "net": "vflt" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCf vflt vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "vflt" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XME1", "displayName": "ME1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME1 de vflt te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "vflt" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME2", "displayName": "ME2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=80u l=4u ng=16 m=1", "source": "XME2 xe sense te vss sg13_hv_nmos w=80u l=4u ng=16 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "te" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME3", "displayName": "ME3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME3 de de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "de" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME4", "displayName": "ME4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XME4 xe de vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "xe" }, { "id": "g", "net": "de" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XME5", "displayName": "ME5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=40u l=4u ng=8 m=4", "source": "XME5 gate xe vdd vdd sg13_hv_pmos w=40u l=4u ng=8 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "xe" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRzE", "displayName": "RzE", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=107.989u", "source": "XRzE xe ze vss rhigh w=0.5u l=107.989u", "pins": [ { "id": "p", "net": "xe" }, { "id": "n", "net": "ze" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCcE", "displayName": "CcE", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCcE ze gate cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "ze" }, { "id": "n", "net": "gate" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=600u l=450n ng=120 m=1", "source": "XMP out gate vdd vdd sg13_hv_pmos w=600u l=450n ng=120 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCo", "displayName": "Co", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=74", "source": "XCo out vss cap_cmim w=29.962u l=29.962u m=74", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XRb out vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMTA", "pin": "g" }, { "device": "XMSA", "pin": "g" }, { "device": "XMTE", "pin": "g" }, { "device": "XMSE", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMTA", "pin": "s" }, { "device": "XMTA", "pin": "b" }, { "device": "XMSA", "pin": "s" }, { "device": "XMSA", "pin": "b" }, { "device": "XMTE", "pin": "s" }, { "device": "XMTE", "pin": "b" }, { "device": "XMSE", "pin": "s" }, { "device": "XMSE", "pin": "b" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "b" }, { "device": "XRzA", "pin": "substrate" }, { "device": "XRA1", "pin": "substrate" }, { "device": "XRA2", "pin": "n" }, { "device": "XRA2", "pin": "substrate" }, { "device": "XRf", "pin": "substrate" }, { "device": "XCf", "pin": "n" }, { "device": "XME1", "pin": "b" }, { "device": "XME2", "pin": "b" }, { "device": "XRzE", "pin": "substrate" }, { "device": "XCo", "pin": "n" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "ta", "ground": false, "terminals": [ { "device": "XMTA", "pin": "d" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vbuf", "ground": false, "terminals": [ { "device": "XMSA", "pin": "d" }, { "device": "XMA5", "pin": "d" }, { "device": "XCcA", "pin": "n" }, { "device": "XRA1", "pin": "p" }, { "device": "XRf", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "te", "ground": false, "terminals": [ { "device": "XMTE", "pin": "d" }, { "device": "XME1", "pin": "s" }, { "device": "XME2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XMSE", "pin": "d" }, { "device": "XME5", "pin": "d" }, { "device": "XCcE", "pin": "n" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "da", "ground": false, "terminals": [ { "device": "XMA1", "pin": "d" }, { "device": "XMA3", "pin": "d" }, { "device": "XMA3", "pin": "g" }, { "device": "XMA4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "fbb", "ground": false, "terminals": [ { "device": "XMA1", "pin": "g" }, { "device": "XRA1", "pin": "n" }, { "device": "XRA2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "xa", "ground": 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