{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ldo-capless-fc", "name": "Capless LDO, folded cascode and follower", "group": "Voltage regulators", "subgroup": "LDOs", "title": "Capless LDO, folded cascode and follower", "summary": "Regulates 1.2 V down to about 0.8 V without a large output capacitor. A folded-cascode amplifier senses the output and a follower drives the PMOS pass gate. Internal compensation stabilizes the loop, but small output capacitance makes load transients larger.", "reference": { "kind": "paper", "authors": "J. Li, H. Zhi, R. Lyu, W. Li, Z. Bi, K. Zhu, Y. Zeng, W. Shan, C. Yan, F. Yang, Y. Li, X. Zeng", "title": "AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis", "year": 2024, "where": "Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD '24), article 59, pp. 1-9", "doi": "10.1145/3676536.3697117", "takes": "The topology: a folded-cascode error amplifier with a PMOS input pair, a PMOS source follower driving the pass gate, and compensation from the output into the source of a cascode. Cx - the capacitor on the amplifier's output that keeps the second loop the compensation closes stable - the separate bleed, the sizing and the specs are this library's, for SG13G2 at 1.2 V." }, "resources": { "record": "/circuits/ldo-capless-fc.json", "page": "/index.html#ldo-capless-fc", "achieved": "/achieved/ldo-capless-fc.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "ref", "kind": "input", "note": "the reference voltage" }, { "name": "sense", "kind": "input", "note": "the output as the regulator reads it; the divider hangs from it" }, { "name": "out", "kind": "output" }, { "name": "vdd", "kind": "supply", "note": "the unregulated input" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the bias current, drawn out of this pin" } ], "devices": [ { "name": "MBP", "type": "pmos", "nodes": "ib ib vdd vdd", "sizedBy": [ "Wbp", "Lbp" ], "role": "bias reference, diode-connected", "fingers": 2, "copies": 1 }, { "name": "MT", "type": "pmos", "nodes": "ts ib vdd vdd", "sizedBy": [ "Wbp", "Lbp", "N" ], "role": "tail, N copies of MBP", "fingers": 2, "copies": 6 }, { "name": "MBF", "type": "pmos", "nodes": "pg ib vdd vdd", "sizedBy": [ "Wbp", "Lbp", "F" ], "role": "the follower's current source, F copies of MBP", "fingers": 2, "copies": 4 }, { "name": "MBQ", "type": "pmos", "nodes": "vbc ib vdd vdd", "sizedBy": [ "Wbp", "Lbp" ], "role": "a copy of Ib for the NMOS bias", "fingers": 2, "copies": 1 }, { "name": "Rq", "type": "resistor", "nodes": "vbc vbn", "sizedBy": [ "Rq" ], "role": "lifts the cascodes' gate above MBN's by Ib Rq" }, { "name": "MBN", "type": "nmos", "nodes": "vbn vbn vss vss", "sizedBy": [ "Wbn", "Lbn" ], "role": "NMOS bias, diode-connected", "fingers": 1, "copies": 1 }, { "name": "MN1", "type": "nmos", "nodes": "f1 vbn vss vss", "sizedBy": [ "Wbn", "Lbn", "K" ], "role": "sink under the fed-back half, K copies of MBN", "fingers": 1, "copies": 8 }, { "name": "MN2", "type": "nmos", "nodes": "f2 vbn vss vss", "sizedBy": [ "Wbn", "Lbn", "K" ], "role": "sink under the reference half, K copies of MBN", "fingers": 1, "copies": 8 }, { "name": "M1", "type": "pmos", "nodes": "f1 div ts vdd", "sizedBy": [ "W1", "L1" ], "role": "input pair, the divided output", "fingers": 16, "copies": 1 }, { "name": "M2", "type": "pmos", "nodes": "f2 ref ts vdd", "sizedBy": [ "W1", "L1" ], "role": "input pair, the reference", "fingers": 16, "copies": 1 }, { "name": "MC1", "type": "nmos", "nodes": "m1 vbc f1 vss", "sizedBy": [ "Wc", "Lc" ], "role": "cascode, mirror side", "fingers": 4, "copies": 1 }, { "name": "MC2", "type": "nmos", "nodes": "x vbc f2 vss", "sizedBy": [ "Wc", "Lc" ], "role": "cascode, output side; Cc returns into its source", "fingers": 4, "copies": 1 }, { "name": "M3", "type": "pmos", "nodes": "m1 m1 vdd vdd", "sizedBy": [ "Wm", "Lm" ], "role": "mirror, diode-connected", "fingers": 8, "copies": 1 }, { "name": "M4", "type": "pmos", "nodes": "x m1 vdd vdd", "sizedBy": [ "Wm", "Lm" ], "role": "mirror, the amplifier's output", "fingers": 8, "copies": 1 }, { "name": "MF", "type": "pmos", "nodes": "vss x pg pg", "sizedBy": [ "Wf", "Lf" ], "role": "source follower driving the pass gate", "fingers": 400, "copies": 1 }, { "name": "MP", "type": "pmos", "nodes": "out pg vdd vdd", "sizedBy": [ "Wpass", "Lpass" ], "role": "pass device", "fingers": 600, "copies": 1 }, { "name": "Cc", "type": "capacitor", "nodes": "out f2", "sizedBy": [ "Cc" ], "role": "compensation, returned into the cascode's source" }, { "name": "Cx", "type": "capacitor", "nodes": "x vss", "sizedBy": [ "Cx" ], "role": "load on the amplifier's output, damping the loop through Cc" }, { "name": "R1", "type": "resistor", "nodes": "sense div", "sizedBy": [ "Ru" ], "role": "divider, upper unit" }, { "name": "R2", "type": "resistor", "nodes": "div vss", "sizedBy": [ "Ru" ], "role": "divider, lower unit" }, { "name": "Rb", "type": "resistor", "nodes": "out vss", "sizedBy": [ "Rb" ], "role": "bleed: the least MP always carries" } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "The input pair: its offset reaches the output doubled by the divider." }, { "rule": "match", "of": [ "MN1", "MN2" ], "why": "The sinks under the folded branches: a difference between their currents is an offset the mirror cannot tell from signal." }, { "rule": "match", "of": [ "M3", "M4" ], "why": "The mirror on top: long, for matching and for low noise." }, { "rule": "unit-copies", "of": [ "MBP", "MT", "MBF", "MBQ" ], "constraint": "MT = N, MBF = F copies of MBP", "why": "Every PMOS current is a copy of Ib." }, { "rule": "unit-copies", "of": [ "MBN", "MN1", "MN2" ], "constraint": "MN1 = MN2 = K copies of MBN", "why": "The sinks copy the NMOS bias; their current must exceed half the tail's so the cascodes always carry some." }, { "rule": "unit-copies", "of": [ "R1", "R2" ], "constraint": "two copies of one resistor: V_out = 2 V_ref", "why": "Only the ratio sets the output. They are 10 kΩ each - large enough in area to match - and a separate bleed carries the current the pass device's leakage needs." }, { "rule": "inner-loop", "of": [ "Cc", "Cx", "MC2", "MF", "MP" ], "constraint": "Cx near Cc", "why": "Cc closes a second loop the sense line does not pass through: out, Cc, the cascode MC2, x, the follower MF, the pass device, out. Its gain at high frequency is about Cc/Cx times the pass stage's; with x lightly loaded it crosses 0 dB near 25 MHz with no margin and the regulator oscillates at light load behind a good loop gain. Cx holds that loop down." }, { "rule": "gate-drive", "of": [ "MF", "MP", "MC2", "MN2" ], "constraint": "5 mA at a 1.08 V input with the gate at x + V_SG,MF", "why": "The follower can only lift the gate one V_SG above x, and x cannot go below the cascode's source plus its saturation voltage. MF runs wide and at low current density for the smallest V_SG, and MP is wide enough to carry the full load with what is left." }, { "rule": "leakage", "of": [ "MF", "MP", "Rb" ], "constraint": "MF long enough not to leak; Rb above MP's hot leakage", "why": "Hot and fast, a short follower leaks enough at no V_SG to hold the gate below the supply, and the wide pass device then leaks more than the bleed: MF is 0.4 µm long, and Rb draws 90 µA." } ], "specs": [ { "key": "vout", "label": "Output voltage", "unit": "V", "direction": "target", "constraint": ">= 0.78 V, <= 0.82 V", "min": 0.78, "max": 0.82, "why": "Twice the 0.4 V reference, within ±20 mV: the amplifier's offset doubled by the divider, at every corner and load." }, { "key": "i_q", "label": "Quiescent current", "unit": "A", "direction": "min", "constraint": "<= 0.0003 A", "min": null, "max": 0.0003, "why": "The folded cascode, the follower's 20 µA, the divider and the 90 µA bleed that holds the wide pass device's hot leakage." }, { "key": "load_reg", "label": "Load regulation", "unit": "V/A", "direction": "min", "constraint": "<= 1.5 V/A", "min": null, "max": 1.5, "why": "At most 7.5 mV from no load to 5 mA." }, { "key": "line_reg", "label": "Line regulation", "unit": "%/V", "direction": "min", "constraint": "<= 2 %/V", "min": null, "max": 2, "why": "At most 3.8 mV across the rated 1.08 to 1.32 V input; the slow corner's full-load curve bends near its bottom." }, { "key": "dropout", "label": "Dropout at full load", "unit": "V", "direction": "min", "constraint": "<= 0.26 V", "min": null, "max": 0.26, "why": "Below the 0.28 V between the output and the lowest rated input: the gate reaches only the follower's V_SG above the amplifier's lowest output, and the pass device is sized for that." }, { "key": "loop_gain_db", "label": "DC loop gain at full load", "unit": "dB", "direction": "max", "constraint": ">= 50 dB", "min": 50, "max": null, "why": "The folded cascode gives the error amplifier most of it." }, { "key": "loop_ugf_hz", "label": "Loop crossover at full load", "unit": "Hz", "direction": "max", "constraint": ">= 300000 Hz", "min": 300000, "max": null, "why": "β g_m1/Cc: the compensation current enters at the cascode's source." }, { "key": "loop_pm_deg", "label": "Loop phase margin, worst load", "unit": "deg", "direction": "max", "constraint": ">= 60 deg", "min": 60, "max": null, "why": "At every load - and no loop inside the regulator unstable, which the output impedance's phase would show." }, { "key": "ring_pct", "label": "Ringing after a kick, worst load", "unit": "%", "direction": "min", "constraint": "<= 5 %", "min": null, "max": 5, "why": "The loop Cc closes through x, the follower and the pass device is not cut by the loop bench; this is its test at every load." }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 35 dB", "min": 35, "max": null, "why": "At 1 kHz, the loop's gain; above the crossover a capless regulator passes the ripple nearly whole." }, { "key": "undershoot", "label": "Undershoot on the load step", "unit": "V", "direction": "min", "constraint": "<= 0.18 V", "min": null, "max": 0.18, "why": "For a 0 to 5 mA step in 1 µs on 100 pF: no large capacitor, so the loop alone holds the output." }, { "key": "overshoot", "label": "Overshoot on the load release", "unit": "V", "direction": "min", "constraint": "<= 0.2 V", "min": null, "max": 0.2, "why": "For the release in 1 µs." }, { "key": "t_recover", "label": "Settling after the load step", "unit": "s", "direction": "min", "constraint": "<= 0.000003 s", "min": null, "max": 0.000003, "why": "Back within 1 % after the step." }, { "key": "t_release", "label": "Settling after the load release", "unit": "s", "direction": "min", "constraint": "<= 0.000003 s", "min": null, "max": 0.000003, "why": "Back within 1 % after the release, at no load." }, { "key": "line_step", "label": "Output step for an input step", "unit": "V", "direction": "min", "constraint": "<= 0.12 V", "min": null, "max": 0.12, "why": "For the input stepped across its whole rated range in 1 µs at full load." }, { "key": "vn_out", "label": "Output noise, 10 Hz to 100 kHz", "unit": "V", "direction": "min", "constraint": "<= 0.00007 V", "min": null, "max": 0.00007, "why": "10 Hz to 100 kHz, rms: the pair and the folded branches' sinks, doubled by the divider." } ], "explanation": { "idea": "Regulates 1.2 V down to about 0.8 V without a large output capacitor. A folded-cascode amplifier senses the output and a follower drives the PMOS pass gate. Internal compensation stabilizes the loop, but small output capacitance makes load transients larger.", "detail": "An LDO that needs no large external output capacitor: 0.8 V from 1.2 V at up to 5 mA into 100 pF. A folded-cascode error amplifier gives the loop its gain; a PMOS source follower MF drives the wide pass device's gate from a low impedance, so the large gate is not the amplifier's load; and the compensation current is fed from the output into f2, the source of the cascode MC2, which passes it to the amplifier's output x. That splits the poles like a Miller capacitor without feeding the output forward - but it closes a second loop, which Cx on x keeps stable.", "lesson": { "relation": 0, "symbols": "V_out is regulated output voltage; V_ref is the external reference voltage; the factor two comes from two equal feedback resistors.", "assumptions": "High DC loop gain, matched divider resistors, small amplifier offset and enough pass-device headroom.", "exercise": { "param": "Vref", "value": 0.42, "analysis": "op", "expect": "The output should rise toward 0.84 V, twice the new reference. The fixed 0.8 V default-design target will no longer apply to this experiment." }, "limits": "Needs external reference and bias inputs, plus a connection from out to sense. Capless means no large external capacitor, not zero capacitance; the default load is 100 pF." }, "path": [ { "part": "Feedback divider and bleed", "devices": "R1, R2, Rb", "does": "Two copies of one resistor: div is half the output, held at V_ref. Rb is the bleed that keeps the wide pass device's hot leakage from lifting the unloaded output." }, { "part": "Folded-cascode amplifier", "devices": "M1, M2, MN1, MN2, MC1, MC2, M3, M4", "does": "The PMOS pair M1 (div), M2 (ref) folds into the sinks MN1, MN2; the cascodes MC1, MC2 carry the rest up to the mirror M3, M4, whose output is x. A rise in div lifts x." }, { "part": "Follower", "devices": "MF, MBF", "does": "MF, with its well on its source, repeats x one V_SG higher on pg, the pass gate; MBF feeds it from the supply." }, { "part": "Pass device", "devices": "MP", "does": "A wide PMOS from the input to the output: a higher pg means less current." }, { "part": "Compensation", "devices": "Cc, Cx", "does": "Cc from the output into f2: its current reaches x through MC2, splitting the poles. Cx on x holds down the loop Cc closes through x, MF and MP." } ], "bias": "Ib, 5 µA, is drawn out of the ib pin through the PMOS diode MBP; MT (6 copies) is the tail, MBF (4) feeds the follower, MBQ (1) feeds the NMOS diode MBN through Rq, which sets the cascodes' gate vbc = V_GS,MBN + Ib · Rq. The sinks MN1, MN2 are 8 copies of MBN each. The reference is an input, 0.4 V.", "relations": [ { "what": "Output voltage", "expr": "V_out ≈ 2 · V_ref", "note": "Two equal units in the divider." }, { "what": "Crossover", "expr": "f_c ≈ (1/2) · g_m1/(2π · Cc)", "note": "The compensation current enters at the cascode's low-impedance source." }, { "what": "Inner loop", "expr": "L_in ≈ (Cc/Cx) · g_m,MP · Z_out", "note": "At high frequency; without Cx it exceeds 0 dB up to about 25 MHz with no phase left, and the regulator oscillates at light load." }, { "what": "Gate drive", "expr": "V_SG,MP ≤ V_DD − (V_f2 + V_DSAT,MC2 + V_SG,MF)", "note": "The follower costs one V_SG of drive: MP is wide, MF wide and long, to leave enough at a 1.08 V input." } ], "tradeoffs": [ "Cx: too small and the inner loop rings or oscillates at light load; too large and the main loop's crossover and margin fall, and the load step dips further.", "Cc: sets the crossover; with Cx it sets the inner loop too, so the two scale together.", "Wf, Lf (MF): wider needs less V_SG and gives the pass device more drive; too short and it leaks, hot, enough to keep the pass gate below the supply at no load.", "Wpass: wider carries the load with less V_SG, but leaks more hot, which Rb must absorb.", "Lbn, Lm: long sinks and mirror lower the folded cascode's noise, at the price of saturation voltage the gate drive needs." ] }, "sizing": [ { "key": "Ib", "label": "Bias current", "unit": "A", "value": 0.000005, "min": 0.000001, "max": 0.00005, "kind": "si" }, { "key": "Wbp", "label": "W PMOS bias unit (MBP, MT, MBF, MBQ)", "unit": "m", "value": 0.000008, "min": 5e-7, "max": 0.00004, "kind": "si" }, { "key": "Lbp", "label": "L PMOS bias unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "N", "label": "Tail current, in Ib", "unit": "", "value": 6, "min": 1, "max": 20, "kind": "int" }, { "key": "F", "label": "Follower current, in Ib", "unit": "", "value": 4, "min": 1, "max": 40, "kind": "int" }, { "key": "Rq", "label": "Cascode-bias resistor", "unit": "Ω", "value": 30000, "min": 1000, "max": 200000, "kind": "si" }, { "key": "Wbn", "label": "W NMOS bias unit (MBN, MN1, MN2)", "unit": "m", "value": 0.000004, "min": 5e-7, "max": 0.00004, "kind": "si" }, { "key": "Lbn", "label": "L NMOS bias unit", "unit": "m", "value": 0.000004, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "K", "label": "Sink current, in Ib", "unit": "", "value": 8, "min": 1, "max": 40, "kind": "int" }, { "key": "W1", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.00008, "min": 0.000001, "max": 0.0002, "kind": "si" }, { "key": "L1", "label": "L input pair", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wc", "label": "W cascodes (MC1, MC2)", "unit": "m", "value": 0.00002, "min": 0.000001, "max": 0.0001, "kind": "si" }, { "key": "Lc", "label": "L cascodes", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wm", "label": "W mirror (M3, M4)", "unit": "m", "value": 0.00004, "min": 0.000001, "max": 0.0002, "kind": "si" }, { "key": "Lm", "label": "L mirror", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wf", "label": "W follower MF", "unit": "m", "value": 0.002, "min": 0.00001, "max": 0.004, "kind": "si" }, { "key": "Lf", "label": "L follower", "unit": "m", "value": 4e-7, "min": 1.3e-7, "max": 0.000002, "kind": "si" }, { "key": "Wpass", "label": "W pass device", "unit": "m", "value": 0.003, "min": 0.00005, "max": 0.006, "kind": "si" }, { "key": "Lpass", "label": "L pass device", "unit": "m", "value": 1.8e-7, "min": 1.3e-7, "max": 0.000001, "kind": "si" }, { "key": "Cc", "label": "Compensation capacitor", "unit": "F", "value": 3e-11, "min": 2e-13, "max": 1e-10, "kind": "si" }, { "key": "Cx", "label": "Capacitor on the amplifier's output", "unit": "F", "value": 3e-11, "min": 2e-13, "max": 1e-10, "kind": "si" }, { "key": "Ru", "label": "Divider unit resistor", "unit": "Ω", "value": 10000, "min": 1000, "max": 200000, "kind": "si" }, { "key": "Rb", "label": "Bleed resistor", "unit": "Ω", "value": 9000, "min": 1000, "max": 200000, "kind": "si" }, { "key": "Vref", "label": "Reference", "unit": "V", "value": 0.4, "min": 0.3, "max": 0.5, "kind": "si" }, { "key": "IL", "label": "Full load", "unit": "A", "value": 0.005, "min": 0.0005, "max": 0.02, "kind": "si" }, { "key": "CL", "label": "Load capacitance", "unit": "F", "value": 1e-10, "min": 1e-11, "max": 1e-9, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The regulator at its nominal input and its lightest load: the output it holds and the current it draws to hold it.", "measures": [], "metricKeys": [ "vout", "i_q" ], "acceptance": [ "vout", "i_q" ], "acceptanceRules": [ { "key": "vout", "unit": "V", "min": 0.78, "max": 0.82, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "i_q", "unit": "A", "min": null, "max": 0.0003, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Capless LDO, folded cascode and follower - operating point at the lightest load\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 400m\nIb ib 0 dc 5u\n.subckt ldocapless ref sense out vdd vss ib\n* bias: PMOS copies of the reference Ib, and the NMOS bias they feed\nXMBP ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMT ts ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=6\nXMBF pg ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=4\nXMBQ vbc ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXRq vbc vbn vss rhigh w=0.5u l=9.166u\nXMBN vbn vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1\nXMN1 f1 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\nXMN2 f2 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\n* error amplifier: a PMOS pair folded into NMOS cascodes, a PMOS mirror on top\nXM1 f1 div ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM2 f2 ref ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXMC1 m1 vbc f1 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXMC2 x vbc f2 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXM3 m1 m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\nXM4 x m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\n* the buffer: a PMOS follower, its well on its source, drives the pass gate\nXMF vss x pg pg sg13_lv_pmos w=2m l=400n ng=400 m=1\n* the pass device\nXMP out pg vdd vdd sg13_lv_pmos w=3m l=180n ng=600 m=1\n* compensation: from the output into the cascode's source; Cx holds down the loop it closes through x\nXCc out f2 cap_cmim w=29.435u l=29.435u m=23\nXCx x vss cap_cmim w=29.435u l=29.435u m=23\n* the divider: two copies of one resistor, div = half the output; and the bleed\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div vss vss rppd w=0.5u l=19.417u\nXRb out vss vss rppd w=0.5u l=17.447u\n.ends\nXdut ref sense out vdd 0 ib ldocapless\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 0\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.op\n.end" }, { "id": "load_reg", "label": "Load regulation", "note": "The load is swept from lightest to full at nominal input. Regulation is the magnitude of the endpoint output change per ampere; a large output rise fails just as a large fall does.", "measures": [], "metricKeys": [ "load_reg" ], "acceptance": [ "load_reg" ], "acceptanceRules": [ { "key": "load_reg", "unit": "V/A", "min": null, "max": 1.5, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Capless LDO, folded cascode and follower - output against load current\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 400m\nIb ib 0 dc 5u\n.subckt ldocapless ref sense out vdd vss ib\n* bias: PMOS copies of the reference Ib, and the NMOS bias they feed\nXMBP ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMT ts ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=6\nXMBF pg ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=4\nXMBQ vbc ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXRq vbc vbn vss rhigh w=0.5u l=9.166u\nXMBN vbn vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1\nXMN1 f1 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\nXMN2 f2 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\n* error amplifier: a PMOS pair folded into NMOS cascodes, a PMOS mirror on top\nXM1 f1 div ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM2 f2 ref ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXMC1 m1 vbc f1 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXMC2 x vbc f2 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXM3 m1 m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\nXM4 x m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\n* the buffer: a PMOS follower, its well on its source, drives the pass gate\nXMF vss x pg pg sg13_lv_pmos w=2m l=400n ng=400 m=1\n* the pass device\nXMP out pg vdd vdd sg13_lv_pmos w=3m l=180n ng=600 m=1\n* compensation: from the output into the cascode's source; Cx holds down the loop it closes through x\nXCc out f2 cap_cmim w=29.435u l=29.435u m=23\nXCx x vss cap_cmim w=29.435u l=29.435u m=23\n* the divider: two copies of one resistor, div = half the output; and the bleed\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div vss vss rppd w=0.5u l=19.417u\nXRb out vss vss rppd w=0.5u l=17.447u\n.ends\nXdut ref sense out vdd 0 ib ldocapless\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 0\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.dc Vload 0 5m 50u\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc v_light FIND v(out) AT=0\n.meas dc v_full FIND v(out) AT=5m\n.end" }, { "id": "line_reg", "label": "Line regulation", "note": "The input swept across its rated range, at the lightest and at the full load: how much of the input's change reaches the output.", "measures": [], "metricKeys": [ "line_reg" ], "acceptance": [ "line_reg" ], "acceptanceRules": [ { "key": "line_reg", "unit": "%/V", "min": null, "max": 2, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Capless LDO, folded cascode and follower - output against input voltage\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n* the input swept across its rated range, 1.08V to 1.32V\nVdd vdd 0 dc 1.2\nVref ref 0 dc 400m\nIb ib 0 dc 5u\n.subckt ldocapless ref sense out vdd vss ib\n* bias: PMOS copies of the reference Ib, and the NMOS bias they feed\nXMBP ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMT ts ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=6\nXMBF pg ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=4\nXMBQ vbc ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXRq vbc vbn vss rhigh w=0.5u l=9.166u\nXMBN vbn vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1\nXMN1 f1 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\nXMN2 f2 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\n* error amplifier: a PMOS pair folded into NMOS cascodes, a PMOS mirror on top\nXM1 f1 div ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM2 f2 ref ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXMC1 m1 vbc f1 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXMC2 x vbc f2 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXM3 m1 m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\nXM4 x m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\n* the buffer: a PMOS follower, its well on its source, drives the pass gate\nXMF vss x pg pg sg13_lv_pmos w=2m l=400n ng=400 m=1\n* the pass device\nXMP out pg vdd vdd sg13_lv_pmos w=3m l=180n ng=600 m=1\n* compensation: from the output into the cascode's source; Cx holds down the loop it closes through x\nXCc out f2 cap_cmim w=29.435u l=29.435u m=23\nXCx x vss cap_cmim w=29.435u l=29.435u m=23\n* the divider: two copies of one resistor, div = half the output; and the bleed\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div vss vss rppd w=0.5u l=19.417u\nXRb out vss vss rppd w=0.5u l=17.447u\n.ends\nXdut ref sense out vdd 0 ib ldocapless\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 0\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n* the input swept at each of two loads: the lightest, then the full load\n.dc Vdd 1.08 1.32 5m Vload 0 5m 5m\n.end" }, { "id": "dropout", "label": "Dropout", "note": "The input lowered at full load until the output has fallen 2 % below the level it holds at the nominal input: the input-to-output voltage left there is the dropout.", "measures": [], "metricKeys": [ "dropout" ], "acceptance": [ "dropout" ], "acceptanceRules": [ { "key": "dropout", "unit": "V", "min": null, "max": 0.26, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Capless LDO, folded cascode and follower - dropout at full load\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n* the input swept down to below the output: 500mV to 1.32V\nVdd vdd 0 dc 1.2\nVref ref 0 dc 400m\nIb ib 0 dc 5u\n.subckt ldocapless ref sense out vdd vss ib\n* bias: PMOS copies of the reference Ib, and the NMOS bias they feed\nXMBP ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMT ts ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=6\nXMBF pg ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=4\nXMBQ vbc ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXRq vbc vbn vss rhigh w=0.5u l=9.166u\nXMBN vbn vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1\nXMN1 f1 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\nXMN2 f2 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\n* error amplifier: a PMOS pair folded into NMOS cascodes, a PMOS mirror on top\nXM1 f1 div ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM2 f2 ref ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXMC1 m1 vbc f1 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXMC2 x vbc f2 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXM3 m1 m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\nXM4 x m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\n* the buffer: a PMOS follower, its well on its source, drives the pass gate\nXMF vss x pg pg sg13_lv_pmos w=2m l=400n ng=400 m=1\n* the pass device\nXMP out pg vdd vdd sg13_lv_pmos w=3m l=180n ng=600 m=1\n* compensation: from the output into the cascode's source; Cx holds down the loop it closes through x\nXCc out f2 cap_cmim w=29.435u l=29.435u m=23\nXCx x vss cap_cmim w=29.435u l=29.435u m=23\n* the divider: two copies of one resistor, div = half the output; and the bleed\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div vss vss rppd w=0.5u l=19.417u\nXRb out vss vss rppd w=0.5u l=17.447u\n.ends\nXdut ref sense out vdd 0 ib ldocapless\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 5m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.dc Vdd 500m 1.32 4.1m\n.end" }, { "id": "loop", "label": "Loop gain", "note": "The loop gain at loads across the whole range, from the lightest to the full load: the loop is cut at the sense line and measured by Middlebrook's double injection - a voltage in series there, then a current into out - which gives it exactly, with every loading in place. The phase and gain margins are the worst over the loads.", "measures": [], "metricKeys": [ "loop_gain_db", "loop_ugf_hz", "loop_pm_deg", "loop_gm_db" ], "acceptance": [ "loop_gain_db", "loop_ugf_hz", "loop_pm_deg" ], "acceptanceRules": [ { "key": "loop_gain_db", "unit": "dB", "min": 50, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "loop_ugf_hz", "unit": "Hz", "min": 300000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "loop_pm_deg", "unit": "deg", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Capless LDO, folded cascode and follower - loop gain at 5mA, voltage injection\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 400m\nIb ib 0 dc 5u\n.subckt ldocapless ref sense out vdd vss ib\n* bias: PMOS copies of the reference Ib, and the NMOS bias they feed\nXMBP ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMT ts ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=6\nXMBF pg ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=4\nXMBQ vbc ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXRq vbc vbn vss rhigh w=0.5u l=9.166u\nXMBN vbn vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1\nXMN1 f1 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\nXMN2 f2 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\n* error amplifier: a PMOS pair folded into NMOS cascodes, a PMOS mirror on top\nXM1 f1 div ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM2 f2 ref ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXMC1 m1 vbc f1 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXMC2 x vbc f2 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXM3 m1 m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\nXM4 x m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\n* the buffer: a PMOS follower, its well on its source, drives the pass gate\nXMF vss x pg pg sg13_lv_pmos w=2m l=400n ng=400 m=1\n* the pass device\nXMP out pg vdd vdd sg13_lv_pmos w=3m l=180n ng=600 m=1\n* compensation: from the output into the cascode's source; Cx holds down the loop it closes through x\nXCc out f2 cap_cmim w=29.435u l=29.435u m=23\nXCx x vss cap_cmim w=29.435u l=29.435u m=23\n* the divider: two copies of one resistor, div = half the output; and the bleed\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div vss vss rppd w=0.5u l=19.417u\nXRb out vss vss rppd w=0.5u l=17.447u\n.ends\nXdut ref sense out vdd 0 ib ldocapless\n* the sense line cut by a 1 V ac source in series: T_v = -v(out)/v(sense)\nVinj sense out dc 0 ac 1\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 5m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.ac dec 20 0.1 1g\n.end" }, { "id": "ring", "label": "Ringing across the loads", "note": "The loads the loop bench visits, in a staircase from the lightest to the full load; at each, once the output has settled, a small step - a tenth more load. How far the output overshoots its new level on the way back, and what is left moving at the end of each step, show whether the regulator is damped at that load: a loop inside it that the sense line does not pass through, and so the loop gain cannot see, shows here.", "measures": [], "metricKeys": [ "ring_pct" ], "acceptance": [ "ring_pct" ], "acceptanceRules": [ { "key": "ring_pct", "unit": "%", "min": null, "max": 5, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Capless LDO, folded cascode and follower - a small load step at each load\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 400m\nIb ib 0 dc 5u\n.subckt ldocapless ref sense out vdd vss ib\n* bias: PMOS copies of the reference Ib, and the NMOS bias they feed\nXMBP ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMT ts ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=6\nXMBF pg ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=4\nXMBQ vbc ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXRq vbc vbn vss rhigh w=0.5u l=9.166u\nXMBN vbn vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1\nXMN1 f1 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\nXMN2 f2 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\n* error amplifier: a PMOS pair folded into NMOS cascodes, a PMOS mirror on top\nXM1 f1 div ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM2 f2 ref ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXMC1 m1 vbc f1 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXMC2 x vbc f2 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXM3 m1 m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\nXM4 x m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\n* the buffer: a PMOS follower, its well on its source, drives the pass gate\nXMF vss x pg pg sg13_lv_pmos w=2m l=400n ng=400 m=1\n* the pass device\nXMP out pg vdd vdd sg13_lv_pmos w=3m l=180n ng=600 m=1\n* compensation: from the output into the cascode's source; Cx holds down the loop it closes through x\nXCc out f2 cap_cmim w=29.435u l=29.435u m=23\nXCx x vss cap_cmim w=29.435u l=29.435u m=23\n* the divider: two copies of one resistor, div = half the output; and the bleed\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div vss vss rppd w=0.5u l=19.417u\nXRb out vss vss rppd w=0.5u l=17.447u\n.ends\nXdut ref sense out vdd 0 ib ldocapless\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 pwl(0 0 8u 0 8.4u 20u 20u 20u 20.4u 5u 28u 5u 28.4u 25u 40u 25u 40.4u 50u 48u 50u 48.4u 70u 60u 70u 60.4u 500u 68u 500u 68.4u 550u 80u 550u 80.4u 5m 88u 5m 88.4u 5.5m 100u 5.5m)\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.tran 10n 100u\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on the input, at the lightest and at the full load: how much of it reaches the output.", "measures": [], "metricKeys": [ "psrr_db", "psrr_hf_db" ], "acceptance": [ "psrr_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 35, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Capless LDO, folded cascode and follower - supply rejection at 5mA\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD} ac 1\nVref ref 0 dc 400m\nIb ib 0 dc 5u\n.subckt ldocapless ref sense out vdd vss ib\n* bias: PMOS copies of the reference Ib, and the NMOS bias they feed\nXMBP ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMT ts ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=6\nXMBF pg ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=4\nXMBQ vbc ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXRq vbc vbn vss rhigh w=0.5u l=9.166u\nXMBN vbn vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1\nXMN1 f1 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\nXMN2 f2 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\n* error amplifier: a PMOS pair folded into NMOS cascodes, a PMOS mirror on top\nXM1 f1 div ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM2 f2 ref ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXMC1 m1 vbc f1 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXMC2 x vbc f2 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXM3 m1 m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\nXM4 x m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\n* the buffer: a PMOS follower, its well on its source, drives the pass gate\nXMF vss x pg pg sg13_lv_pmos w=2m l=400n ng=400 m=1\n* the pass device\nXMP out pg vdd vdd sg13_lv_pmos w=3m l=180n ng=600 m=1\n* compensation: from the output into the cascode's source; Cx holds down the loop it closes through x\nXCc out f2 cap_cmim w=29.435u l=29.435u m=23\nXCx x vss cap_cmim w=29.435u l=29.435u m=23\n* the divider: two copies of one resistor, div = half the output; and the bleed\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div vss vss rppd w=0.5u l=19.417u\nXRb out vss vss rppd w=0.5u l=17.447u\n.ends\nXdut ref sense out vdd 0 ib ldocapless\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 5m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.ac dec 20 1 100meg\n.end" }, { "id": "load_step", "label": "Load step", "note": "The load stepped from the lightest to the full load and back, each edge 1.00 µs: how far the output dips and peaks, and how long it takes to settle within 1 % after each edge. A loop that rings or oscillates at either load shows here, whatever the loop gain says.", "measures": [], "metricKeys": [ "undershoot", "overshoot", "t_recover", "t_release" ], "acceptance": [ "undershoot", "overshoot", "t_recover", "t_release" ], "acceptanceRules": [ { "key": "undershoot", "unit": "V", "min": null, "max": 0.18, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "overshoot", "unit": "V", "min": null, "max": 0.2, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "t_recover", "unit": "s", "min": null, "max": 0.000003, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "t_release", "unit": "s", "min": null, "max": 0.000003, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Capless LDO, folded cascode and follower - load step\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 400m\nIb ib 0 dc 5u\n.subckt ldocapless ref sense out vdd vss ib\n* bias: PMOS copies of the reference Ib, and the NMOS bias they feed\nXMBP ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMT ts ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=6\nXMBF pg ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=4\nXMBQ vbc ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXRq vbc vbn vss rhigh w=0.5u l=9.166u\nXMBN vbn vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1\nXMN1 f1 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\nXMN2 f2 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\n* error amplifier: a PMOS pair folded into NMOS cascodes, a PMOS mirror on top\nXM1 f1 div ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM2 f2 ref ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXMC1 m1 vbc f1 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXMC2 x vbc f2 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXM3 m1 m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\nXM4 x m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\n* the buffer: a PMOS follower, its well on its source, drives the pass gate\nXMF vss x pg pg sg13_lv_pmos w=2m l=400n ng=400 m=1\n* the pass device\nXMP out pg vdd vdd sg13_lv_pmos w=3m l=180n ng=600 m=1\n* compensation: from the output into the cascode's source; Cx holds down the loop it closes through x\nXCc out f2 cap_cmim w=29.435u l=29.435u m=23\nXCx x vss cap_cmim w=29.435u l=29.435u m=23\n* the divider: two copies of one resistor, div = half the output; and the bleed\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div vss vss rppd w=0.5u l=19.417u\nXRb out vss vss rppd w=0.5u l=17.447u\n.ends\nXdut ref sense out vdd 0 ib ldocapless\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 pulse(0 5m 4u 1u 1u 17u 80u)\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.tran 8n 40u\n.end" }, { "id": "line_step", "label": "Line step", "note": "The input stepped across its rated range, 1.08 V to 1.32 V, and back, each edge 1.00 µs, at full load: how far the output moves.", "measures": [], "metricKeys": [ "line_step" ], "acceptance": [ "line_step" ], "acceptanceRules": [ { "key": "line_step", "unit": "V", "min": null, "max": 0.12, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Capless LDO, folded cascode and follower - line step at full load\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n* the input steps across its rated range and back\nVdd vdd 0 pulse(1.08 1.32 4u 1u 1u 17u 80u)\nVref ref 0 dc 400m\nIb ib 0 dc 5u\n.subckt ldocapless ref sense out vdd vss ib\n* bias: PMOS copies of the reference Ib, and the NMOS bias they feed\nXMBP ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMT ts ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=6\nXMBF pg ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=4\nXMBQ vbc ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXRq vbc vbn vss rhigh w=0.5u l=9.166u\nXMBN vbn vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1\nXMN1 f1 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\nXMN2 f2 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\n* error amplifier: a PMOS pair folded into NMOS cascodes, a PMOS mirror on top\nXM1 f1 div ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM2 f2 ref ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXMC1 m1 vbc f1 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXMC2 x vbc f2 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXM3 m1 m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\nXM4 x m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\n* the buffer: a PMOS follower, its well on its source, drives the pass gate\nXMF vss x pg pg sg13_lv_pmos w=2m l=400n ng=400 m=1\n* the pass device\nXMP out pg vdd vdd sg13_lv_pmos w=3m l=180n ng=600 m=1\n* compensation: from the output into the cascode's source; Cx holds down the loop it closes through x\nXCc out f2 cap_cmim w=29.435u l=29.435u m=23\nXCx x vss cap_cmim w=29.435u l=29.435u m=23\n* the divider: two copies of one resistor, div = half the output; and the bleed\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div vss vss rppd w=0.5u l=19.417u\nXRb out vss vss rppd w=0.5u l=17.447u\n.ends\nXdut ref sense out vdd 0 ib ldocapless\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 5m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.tran 8n 40u\n.end" }, { "id": "noise", "label": "Output noise", "note": "The noise at the output at full load: its density at 1 kHz and its total from 10 Hz to 100 kHz. The reference is an ideal, noiseless source, so this is the regulator's own noise.", "measures": [], "metricKeys": [ "vn_out", "vn_out_1k" ], "acceptance": [ "vn_out" ], "acceptanceRules": [ { "key": "vn_out", "unit": "V", "min": null, "max": 0.00007, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Capless LDO, folded cascode and follower - output noise at full load\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\n* ac 1 only because ngspice's noise analysis names an input; the output noise does not depend on it\nVdd vdd 0 dc {VDD} ac 1\nVref ref 0 dc 400m\nIb ib 0 dc 5u\n.subckt ldocapless ref sense out vdd vss ib\n* bias: PMOS copies of the reference Ib, and the NMOS bias they feed\nXMBP ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXMT ts ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=6\nXMBF pg ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=4\nXMBQ vbc ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXRq vbc vbn vss rhigh w=0.5u l=9.166u\nXMBN vbn vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1\nXMN1 f1 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\nXMN2 f2 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8\n* error amplifier: a PMOS pair folded into NMOS cascodes, a PMOS mirror on top\nXM1 f1 div ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXM2 f2 ref ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1\nXMC1 m1 vbc f1 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXMC2 x vbc f2 vss sg13_lv_nmos w=20u l=500n ng=4 m=1\nXM3 m1 m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\nXM4 x m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1\n* the buffer: a PMOS follower, its well on its source, drives the pass gate\nXMF vss x pg pg sg13_lv_pmos w=2m l=400n ng=400 m=1\n* the pass device\nXMP out pg vdd vdd sg13_lv_pmos w=3m l=180n ng=600 m=1\n* compensation: from the output into the cascode's source; Cx holds down the loop it closes through x\nXCc out f2 cap_cmim w=29.435u l=29.435u m=23\nXCx x vss cap_cmim w=29.435u l=29.435u m=23\n* the divider: two copies of one resistor, div = half the output; and the bleed\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div vss vss rppd w=0.5u l=19.417u\nXRb out vss vss rppd w=0.5u l=17.447u\n.ends\nXdut ref sense out vdd 0 ib ldocapless\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 5m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.control\nnoise v(out) Vdd dec 20 10 100k\nsetplot noise1\n* 20 points a decade from 10 Hz: point 40 is 1 kHz\nlet vn_1k = onoise_spectrum[40]\nprint vn_1k\nsetplot noise2\nprint onoise_total\n.endc\n.op\n.end" } ], "measurements": { "vout": { "label": "Output voltage", "unit": "V", "spec": { "min": 0.78, "max": 0.82 } }, "i_q": { "label": "Quiescent current", "unit": "A", "spec": { "min": null, "max": 0.0003 } }, "load_reg": { "label": "Load regulation", "unit": "V/A", "spec": { "min": null, "max": 1.5 } }, "line_reg": { "label": "Line regulation", "unit": "%/V", "spec": { "min": null, "max": 2 } }, "dropout": { "label": "Dropout at full load", "unit": "V", "spec": { "min": null, "max": 0.26 } }, "loop_gain_db": { "label": "DC loop gain at full load", "unit": "dB", "spec": { "min": 50, "max": null } }, "loop_ugf_hz": { "label": "Loop crossover at full load", "unit": "Hz", "spec": { "min": 300000, "max": null } }, "loop_pm_deg": { "label": "Loop phase margin, worst load", "unit": "deg", "spec": { "min": 60, "max": null } }, "ring_pct": { "label": "Ringing after a kick, worst load", "unit": "%", "spec": { "min": null, "max": 5 } }, "psrr_db": { "label": "Supply rejection at 1 kHz", "unit": "dB", "spec": { "min": 35, "max": null } }, "undershoot": { "label": "Undershoot on the load step", "unit": "V", "spec": { "min": null, "max": 0.18 } }, "overshoot": { "label": "Overshoot on the load release", "unit": "V", "spec": { "min": null, "max": 0.2 } }, "t_recover": { "label": "Settling after the load step", "unit": "s", "spec": { "min": null, "max": 0.000003 } }, "t_release": { "label": "Settling after the load release", "unit": "s", "spec": { "min": null, "max": 0.000003 } }, "line_step": { "label": "Output step for an input step", "unit": "V", "spec": { "min": null, "max": 0.12 } }, "vn_out": { "label": "Output noise, 10 Hz to 100 kHz", "unit": "V", "spec": { "min": null, "max": 0.00007 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "25e38ade874fe184e3102df0e225a0501f781540c87fa6e38d70b49ae14f55a0" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ldo-capless-fc.js", "sha256": "a21011fc4684d144347903b65f6b99f5014bd552a8509237cc3e4cd9ba86c2ad" }, "simulationFingerprints": { "op": "136d5dc9f0b8f21b6288118abd08d0338d3f43183dacde87e247489374e91c61", "load_reg": "438ded6a1037d93d86def32c5132d91d4ce966e6f859dcd8c34450a433f43234", "line_reg": "c4c5970d7b544e63d635cc8ddc0a98c7f209c51ca18d157a12fde8e725a4f0a6", "dropout": "08a70afc761ab33dc0233f7e02cd3d26cd6bd7624774c3b4b5ad7e5678003e58", "loop": "1d2f4916d3affb484cabaf377f854c589b0849f3f41d289028cc6b3caf64e9d4", "ring": "a2383b470597d60bb4ba68410dc534a596a7f6f79905038e87f953a54b58d6ac", "psrr": "60926d59c9335e8b4c32b9e2dddb3fe341d6d10454b928e16dc5915cdc9082c5", "load_step": "5c2ed44912bfb2ab96060fcc25a0c230c62f4f434884b08f2007befaeb2b36e9", "line_step": "550b2715f4a8322b523eb96ce3768ccf50dba8da16a9a8230e69f20eaf85db95", "noise": "72380cdbc5abadefcabba46c8f993e34031d6eeb54d6e4f9ed6735e8180b6a05" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "66d6159ad2ed6d53705d6fb65defe0c7dc5b379ad66daa12a44abade212e8e98", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ldo-capless-fc", "parameters": { "Ib": 0.000005, "Wbp": 0.000008, "Lbp": 0.000001, "N": 6, "F": 4, "Rq": 30000, "Wbn": 0.000004, "Lbn": 0.000004, "K": 8, "W1": 0.00008, "L1": 0.000001, "Wc": 0.00002, "Lc": 5e-7, "Wm": 0.00004, "Lm": 0.000002, "Wf": 0.002, "Lf": 4e-7, "Wpass": 0.003, "Lpass": 1.8e-7, "Cc": 3e-11, "Cx": 3e-11, "Ru": 10000, "Rb": 9000, "Vref": 0.4, "IL": 0.005, "CL": 1e-10 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ldo-capless-fc/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "ldocapless", "ports": [ { "name": "ref", "net": "ref", "kind": "input" }, { "name": "sense", "net": "sense", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMBP", "displayName": "MBP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMBP ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=6", "source": "XMT ts ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=6", "pins": [ { "id": "d", "net": "ts" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBF", "displayName": "MBF", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMBF pg ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "pg" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBQ", "displayName": "MBQ", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMBQ vbc ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRq", "displayName": "Rq", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=9.166u", "source": "XRq vbc vbn vss rhigh w=0.5u l=9.166u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMBN", "displayName": "MBN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMBN vbn vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN1", "displayName": "MN1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=8", "source": "XMN1 f1 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=8", "source": "XMN2 f2 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM1 f1 div ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "div" }, { "id": "s", "net": "ts" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM2 f2 ref ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ts" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=500n ng=4 m=1", "source": "XMC1 m1 vbc f1 vss sg13_lv_nmos w=20u l=500n ng=4 m=1", "pins": [ { "id": "d", "net": "m1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=500n ng=4 m=1", "source": "XMC2 x vbc f2 vss sg13_lv_nmos w=20u l=500n ng=4 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM3 m1 m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "m1" }, { "id": "g", "net": "m1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM4 x m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "m1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMF", "displayName": "MF", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2m l=400n ng=400 m=1", "source": "XMF vss x pg pg sg13_lv_pmos w=2m l=400n ng=400 m=1", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "x" }, { "id": "s", "net": "pg" }, { "id": "b", "net": "pg" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3m l=180n ng=600 m=1", "source": "XMP out pg vdd vdd sg13_lv_pmos w=3m l=180n ng=600 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "pg" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.435u l=29.435u m=23", "source": "XCc out f2 cap_cmim w=29.435u l=29.435u m=23", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "f2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCx", "displayName": "Cx", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.435u l=29.435u m=23", "source": "XCx x vss cap_cmim w=29.435u l=29.435u m=23", "pins": [ { "id": "p", "net": "x" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR1 sense div vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "div" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR2 div vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "div" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=17.447u", "source": "XRb out vss vss rppd w=0.5u l=17.447u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMBP", "pin": "d" }, { "device": "XMBP", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMBF", "pin": "g" }, { "device": "XMBQ", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMBP", "pin": "s" }, { "device": "XMBP", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMBF", "pin": "s" }, { "device": "XMBF", "pin": "b" }, { "device": "XMBQ", "pin": "s" }, { "device": "XMBQ", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "ts", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "pg", "ground": false, "terminals": [ { "device": "XMBF", "pin": "d" }, { "device": "XMF", "pin": "s" }, { "device": "XMF", "pin": "b" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XMBQ", "pin": "d" }, { "device": "XRq", "pin": "p" }, { "device": "XMC1", "pin": "g" }, { "device": "XMC2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRq", "pin": "n" }, { "device": "XMBN", "pin": "d" }, { "device": "XMBN", "pin": "g" }, { "device": "XMN1", "pin": "g" }, { "device": "XMN2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRq", "pin": "substrate" }, { "device": "XMBN", "pin": "s" }, { "device": "XMBN", "pin": "b" }, { "device": "XMN1", "pin": "s" }, { "device": "XMN1", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XMC1", "pin": "b" }, { "device": "XMC2", "pin": "b" }, { "device": "XMF", "pin": "d" }, { "device": "XCx", "pin": "n" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR2", "pin": "n" }, { "device": "XR2", "pin": "substrate" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XMN1", "pin": "d" }, { "device": "XM1", "pin": "d" }, { "device": "XMC1", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XM2", "pin": "d" }, { "device": "XMC2", "pin": "s" }, { "device": "XCc", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "div", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XR1", "pin": "n" }, { "device": "XR2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "m1", "ground": false, "terminals": [ { "device": "XMC1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XMF", "pin": "g" }, { "device": "XCx", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCc", "pin": "p" }, { "device": "XRb", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XR1", "pin": "p" } ], "ports": [ "sense" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m", "source": "Vref ref 0 dc 400m", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib ib 0 dc 5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldocapless", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldocapless", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldocapless" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "100p", "source": "Cl out 0 100p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vload il 0 dc 0", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldocapless", "name": "ldocapless", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMBP", "displayName": "MBP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMBP ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=6", "source": "XMT ts ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=6", "pins": [ { "id": "d", "net": "ts" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBF", "displayName": "MBF", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMBF pg ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "pg" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBQ", "displayName": "MBQ", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMBQ vbc ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRq", "displayName": "Rq", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=9.166u", "source": "XRq vbc vbn vss rhigh w=0.5u l=9.166u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMBN", "displayName": "MBN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMBN vbn vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN1", "displayName": "MN1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=8", "source": "XMN1 f1 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=8", "source": "XMN2 f2 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM1 f1 div ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "div" }, { "id": "s", "net": "ts" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM2 f2 ref ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ts" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=500n ng=4 m=1", "source": "XMC1 m1 vbc f1 vss sg13_lv_nmos w=20u l=500n ng=4 m=1", "pins": [ { "id": "d", "net": "m1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=500n ng=4 m=1", "source": "XMC2 x vbc f2 vss sg13_lv_nmos w=20u l=500n ng=4 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM3 m1 m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "m1" }, { "id": "g", "net": "m1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM4 x m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "m1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMF", "displayName": "MF", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2m l=400n ng=400 m=1", "source": "XMF vss x pg pg sg13_lv_pmos w=2m l=400n ng=400 m=1", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "x" }, { "id": "s", "net": "pg" }, { "id": "b", "net": "pg" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3m l=180n ng=600 m=1", "source": "XMP out pg vdd vdd sg13_lv_pmos w=3m l=180n ng=600 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "pg" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.435u l=29.435u m=23", "source": "XCc out f2 cap_cmim w=29.435u l=29.435u m=23", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "f2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCx", "displayName": "Cx", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.435u l=29.435u m=23", "source": "XCx x vss cap_cmim w=29.435u l=29.435u m=23", "pins": [ { "id": "p", "net": "x" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR1 sense div vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "div" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR2 div vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "div" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=17.447u", "source": "XRb out vss vss rppd w=0.5u l=17.447u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMBP", "pin": "d" }, { "device": "XMBP", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMBF", "pin": "g" }, { "device": "XMBQ", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMBP", "pin": "s" }, { "device": "XMBP", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMBF", "pin": "s" }, { "device": "XMBF", "pin": "b" }, { "device": "XMBQ", "pin": "s" }, { "device": "XMBQ", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "ts", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "pg", "ground": false, "terminals": [ { "device": "XMBF", "pin": "d" }, { "device": "XMF", "pin": "s" }, { "device": "XMF", "pin": "b" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XMBQ", "pin": "d" }, { "device": "XRq", "pin": "p" }, { "device": "XMC1", "pin": "g" }, { "device": "XMC2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRq", "pin": "n" }, { "device": "XMBN", "pin": "d" }, { "device": "XMBN", "pin": "g" }, { "device": "XMN1", "pin": "g" }, { "device": "XMN2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRq", "pin": "substrate" }, { "device": "XMBN", "pin": "s" }, { "device": "XMBN", "pin": "b" }, { "device": "XMN1", "pin": "s" }, { "device": "XMN1", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XMC1", "pin": "b" }, { "device": "XMC2", "pin": "b" }, { "device": "XMF", "pin": "d" }, { "device": "XCx", "pin": "n" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR2", "pin": "n" }, { "device": "XR2", "pin": "substrate" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XMN1", "pin": "d" }, { "device": "XM1", "pin": "d" }, { "device": "XMC1", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XM2", "pin": "d" }, { "device": "XMC2", "pin": "s" }, { "device": "XCc", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "div", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XR1", "pin": "n" }, { "device": "XR2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "m1", "ground": false, "terminals": [ { "device": "XMC1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XMF", "pin": "g" }, { "device": "XCx", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCc", "pin": "p" }, { "device": "XRb", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XR1", "pin": "p" } ], "ports": [ "sense" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldocapless" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Bias reference", "devices": [ { "scope": "dut", "device": "XMBP" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "Tail", "devices": [ { "scope": "dut", "device": "XMT" } ], "inferredStages": [ 1 ] }, { "id": "block-3", "label": "The follower's current source", "devices": [ { "scope": "dut", "device": "XMBF" } ], "inferredStages": [ 3 ] }, { "id": "block-4", "label": "A copy of Ib for the NMOS bias", "devices": [ { "scope": "dut", "device": "XMBQ" } ], "inferredStages": [ "bias" ] }, { "id": "block-5", "label": "Lifts the cascodes' gate above MBN's by Ib Rq", "devices": [ { "scope": "dut", "device": "XRq" } ], "inferredStages": [ "bias" ] }, { "id": "block-6", "label": "NMOS bias", "devices": [ { "scope": "dut", "device": "XMBN" } ], "inferredStages": [ "bias" ] }, { "id": "block-7", "label": "Sink under the fed-back half", "devices": [ { "scope": "dut", "device": "XMN1" } ], "inferredStages": [ 2 ] }, { "id": "block-8", "label": "Sink under the reference half", "devices": [ { "scope": "dut", "device": "XMN2" } ], "inferredStages": [ 1 ] }, { "id": "block-9", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 2, 1 ] }, { "id": "block-10", "label": "Cascode", "devices": [ { "scope": "dut", "device": "XMC1" }, { "scope": "dut", "device": "XMC2" } ], "inferredStages": [ 3, 2 ] }, { "id": "block-11", "label": "Mirror", "devices": [ { "scope": "dut", "device": "XM3" }, { "scope": "dut", "device": "XM4" } ], "inferredStages": [ 3, 2 ] }, { "id": "block-12", "label": "Source follower driving the pass gate", "devices": [ { "scope": "dut", "device": "XMF" } ], "inferredStages": [ 3 ] }, { "id": "block-13", "label": "Pass device", "devices": [ { "scope": "dut", "device": "XMP" } ], "inferredStages": [ 4 ] }, { "id": "block-14", "label": "Compensation", "devices": [ { "scope": "dut", "device": "XCc" } ], "inferredStages": [ "comp" ] }, { "id": "block-15", "label": "Load on the amplifier's output", "devices": [ { "scope": "dut", "device": "XCx" } ], "inferredStages": [ 2 ] }, { "id": "block-16", "label": "Divider", "devices": [ { "scope": "dut", "device": "XR1" }, { "scope": "dut", "device": "XR2" } ], "inferredStages": [ 1 ] }, { "id": "block-17", "label": "Bleed: the least MP always carries", "devices": [ { "scope": "dut", "device": "XRb" } ], "inferredStages": [ 4 ] } ], "edges": [ { "id": "net-1", "net": "ib", "nodes": [ "block-1", "block-2", "block-3", "block-4" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "ts", "nodes": [ "block-2", "block-9" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "pg", "nodes": [ "block-3", "block-12", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "vbc", "nodes": [ "block-4", "block-5", "block-10" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "vbn", "nodes": [ "block-5", "block-6", "block-7", "block-8" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "f1", "nodes": [ "block-7", "block-9", "block-10" ], "direction": "undirected-shared-net" }, { "id": "net-7", "net": "f2", "nodes": [ "block-8", "block-9", "block-10", "block-14" ], "direction": "undirected-shared-net" }, { "id": "net-8", "net": "div", "nodes": [ "block-9", "block-16" ], "direction": "undirected-shared-net" }, { "id": "net-9", "net": "m1", "nodes": [ "block-10", "block-11" ], "direction": "undirected-shared-net" }, { "id": "net-10", "net": "x", "nodes": [ "block-10", "block-11", "block-12", "block-15" ], "direction": "undirected-shared-net" }, { "id": "net-11", "net": "out", "nodes": [ "block-13", "block-14", "block-17" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "ref", "net": "ref", "kind": "input" }, { "name": "sense", "net": "sense", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [], "scopes": [ { "id": "dut", "name": "ldocapless", "ports": [ { "name": "ref", "net": "ref", "kind": "input" }, { "name": "sense", "net": "sense", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMBP", "displayName": "MBP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMBP ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=6", "source": "XMT ts ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=6", "pins": [ { "id": "d", "net": "ts" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBF", "displayName": "MBF", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMBF pg ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "pg" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBQ", "displayName": "MBQ", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMBQ vbc ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRq", "displayName": "Rq", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=9.166u", "source": "XRq vbc vbn vss rhigh w=0.5u l=9.166u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMBN", "displayName": "MBN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMBN vbn vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN1", "displayName": "MN1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=8", "source": "XMN1 f1 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=8", "source": "XMN2 f2 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM1 f1 div ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "div" }, { "id": "s", "net": "ts" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM2 f2 ref ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ts" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=500n ng=4 m=1", "source": "XMC1 m1 vbc f1 vss sg13_lv_nmos w=20u l=500n ng=4 m=1", "pins": [ { "id": "d", "net": "m1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=500n ng=4 m=1", "source": "XMC2 x vbc f2 vss sg13_lv_nmos w=20u l=500n ng=4 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM3 m1 m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "m1" }, { "id": "g", "net": "m1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM4 x m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "m1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMF", "displayName": "MF", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2m l=400n ng=400 m=1", "source": "XMF vss x pg pg sg13_lv_pmos w=2m l=400n ng=400 m=1", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "x" }, { "id": "s", "net": "pg" }, { "id": "b", "net": "pg" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3m l=180n ng=600 m=1", "source": "XMP out pg vdd vdd sg13_lv_pmos w=3m l=180n ng=600 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "pg" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.435u l=29.435u m=23", "source": "XCc out f2 cap_cmim w=29.435u l=29.435u m=23", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "f2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCx", "displayName": "Cx", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.435u l=29.435u m=23", "source": "XCx x vss cap_cmim w=29.435u l=29.435u m=23", "pins": [ { "id": "p", "net": "x" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR1 sense div vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "div" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR2 div vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "div" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=17.447u", "source": "XRb out vss vss rppd w=0.5u l=17.447u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMBP", "pin": "d" }, { "device": "XMBP", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMBF", "pin": "g" }, { "device": "XMBQ", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMBP", "pin": "s" }, { "device": "XMBP", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMBF", "pin": "s" }, { "device": "XMBF", "pin": "b" }, { "device": "XMBQ", "pin": "s" }, { "device": "XMBQ", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "ts", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "pg", "ground": false, "terminals": [ { "device": "XMBF", "pin": "d" }, { "device": "XMF", "pin": "s" }, { "device": "XMF", "pin": "b" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XMBQ", "pin": "d" }, { "device": "XRq", "pin": "p" }, { "device": "XMC1", "pin": "g" }, { "device": "XMC2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRq", "pin": "n" }, { "device": "XMBN", "pin": "d" }, { "device": "XMBN", "pin": "g" }, { "device": "XMN1", "pin": "g" }, { "device": "XMN2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRq", "pin": "substrate" }, { "device": "XMBN", "pin": "s" }, { "device": "XMBN", "pin": "b" }, { "device": "XMN1", "pin": "s" }, { "device": "XMN1", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XMC1", "pin": "b" }, { "device": "XMC2", "pin": "b" }, { "device": "XMF", "pin": "d" }, { "device": "XCx", "pin": "n" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR2", "pin": "n" }, { "device": "XR2", "pin": "substrate" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XMN1", "pin": "d" }, { "device": "XM1", "pin": "d" }, { "device": "XMC1", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XM2", "pin": "d" }, { "device": "XMC2", "pin": "s" }, { "device": "XCc", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "div", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XR1", "pin": "n" }, { "device": "XR2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "m1", "ground": false, "terminals": [ { "device": "XMC1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XMF", "pin": "g" }, { "device": "XCx", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCc", "pin": "p" }, { "device": "XRb", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XR1", "pin": "p" } ], "ports": [ "sense" ], "voltageReferences": [] } ] } ] }, { "id": "graph-5", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.2", "source": "Vdd vdd 0 dc 1.2", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m", "source": "Vref ref 0 dc 400m", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib ib 0 dc 5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldocapless", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldocapless", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldocapless" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "100p", "source": "Cl out 0 100p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vload il 0 dc 0", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldocapless", "name": "ldocapless", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMBP", "displayName": "MBP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMBP ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=6", "source": "XMT ts ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=6", "pins": [ { "id": "d", "net": "ts" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBF", "displayName": "MBF", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMBF pg ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "pg" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBQ", "displayName": "MBQ", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMBQ vbc ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRq", "displayName": "Rq", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=9.166u", "source": "XRq vbc vbn vss rhigh w=0.5u l=9.166u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMBN", "displayName": "MBN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMBN vbn vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN1", "displayName": "MN1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=8", "source": "XMN1 f1 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=8", "source": "XMN2 f2 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM1 f1 div ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "div" }, { "id": "s", "net": "ts" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM2 f2 ref ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ts" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=500n ng=4 m=1", "source": "XMC1 m1 vbc f1 vss sg13_lv_nmos w=20u l=500n ng=4 m=1", "pins": [ { "id": "d", "net": "m1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=500n ng=4 m=1", "source": "XMC2 x vbc f2 vss sg13_lv_nmos w=20u l=500n ng=4 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM3 m1 m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "m1" }, { "id": "g", "net": "m1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM4 x m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "m1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMF", "displayName": "MF", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2m l=400n ng=400 m=1", "source": "XMF vss x pg pg sg13_lv_pmos w=2m l=400n ng=400 m=1", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "x" }, { "id": "s", "net": "pg" }, { "id": "b", "net": "pg" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3m l=180n ng=600 m=1", "source": "XMP out pg vdd vdd sg13_lv_pmos w=3m l=180n ng=600 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "pg" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.435u l=29.435u m=23", "source": "XCc out f2 cap_cmim w=29.435u l=29.435u m=23", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "f2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCx", "displayName": "Cx", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.435u l=29.435u m=23", "source": "XCx x vss cap_cmim w=29.435u l=29.435u m=23", "pins": [ { "id": "p", "net": "x" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR1 sense div vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "div" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR2 div vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "div" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=17.447u", "source": "XRb out vss vss rppd w=0.5u l=17.447u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMBP", "pin": "d" }, { "device": "XMBP", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMBF", "pin": "g" }, { "device": "XMBQ", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMBP", "pin": "s" }, { "device": "XMBP", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMBF", "pin": "s" }, { "device": "XMBF", "pin": "b" }, { "device": "XMBQ", "pin": "s" }, { "device": "XMBQ", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "ts", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "pg", "ground": false, "terminals": [ { "device": "XMBF", "pin": "d" }, { "device": "XMF", "pin": "s" }, { "device": "XMF", "pin": "b" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XMBQ", "pin": "d" }, { "device": "XRq", "pin": "p" }, { "device": "XMC1", "pin": "g" }, { "device": "XMC2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRq", "pin": "n" }, { "device": "XMBN", "pin": "d" }, { "device": "XMBN", "pin": "g" }, { "device": "XMN1", "pin": "g" }, { "device": "XMN2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRq", "pin": "substrate" }, { "device": "XMBN", "pin": "s" }, { "device": "XMBN", "pin": "b" }, { "device": "XMN1", "pin": "s" }, { "device": "XMN1", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XMC1", "pin": "b" }, { "device": "XMC2", "pin": "b" }, { "device": "XMF", "pin": "d" }, { "device": "XCx", "pin": "n" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR2", "pin": "n" }, { "device": "XR2", "pin": "substrate" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XMN1", "pin": "d" }, { "device": "XM1", "pin": "d" }, { "device": "XMC1", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XM2", "pin": "d" }, { "device": "XMC2", "pin": "s" }, { "device": "XCc", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "div", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XR1", "pin": "n" }, { "device": "XR2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "m1", "ground": false, "terminals": [ { "device": "XMC1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XMF", "pin": "g" }, { "device": "XCx", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCc", "pin": "p" }, { "device": "XRb", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XR1", "pin": "p" } ], "ports": [ "sense" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldocapless" } }, { "id": "graph-6", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.2", "source": "Vdd vdd 0 dc 1.2", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m", "source": "Vref ref 0 dc 400m", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib ib 0 dc 5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": 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5m", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldocapless", "name": "ldocapless", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMBP", "displayName": "MBP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMBP ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=6", "source": "XMT ts ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=6", "pins": [ { "id": "d", "net": "ts" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBF", "displayName": "MBF", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMBF pg ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "pg" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBQ", "displayName": "MBQ", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMBQ vbc ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRq", "displayName": "Rq", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=9.166u", "source": "XRq vbc vbn vss rhigh w=0.5u l=9.166u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMBN", "displayName": "MBN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMBN vbn vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN1", "displayName": "MN1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=8", "source": "XMN1 f1 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=8", "source": "XMN2 f2 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM1 f1 div ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "div" }, { "id": "s", "net": "ts" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM2 f2 ref ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ts" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=500n ng=4 m=1", "source": "XMC1 m1 vbc f1 vss sg13_lv_nmos w=20u l=500n ng=4 m=1", "pins": [ { "id": "d", "net": "m1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=500n ng=4 m=1", "source": "XMC2 x vbc f2 vss sg13_lv_nmos w=20u l=500n ng=4 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM3 m1 m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "m1" }, { "id": "g", "net": "m1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", 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"Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.435u l=29.435u m=23", "source": "XCc out f2 cap_cmim w=29.435u l=29.435u m=23", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "f2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCx", "displayName": "Cx", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.435u l=29.435u m=23", "source": "XCx x vss cap_cmim w=29.435u l=29.435u m=23", "pins": [ { "id": "p", "net": "x" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR1 sense div vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "div" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR2 div vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "div" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=17.447u", "source": "XRb out vss vss rppd w=0.5u l=17.447u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMBP", "pin": "d" }, { "device": "XMBP", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMBF", "pin": "g" }, { "device": "XMBQ", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMBP", "pin": "s" }, { "device": "XMBP", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMBF", "pin": "s" }, { "device": "XMBF", "pin": "b" }, { "device": "XMBQ", "pin": "s" }, { "device": "XMBQ", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "ts", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "pg", "ground": false, "terminals": [ { "device": "XMBF", "pin": "d" }, { "device": "XMF", "pin": "s" }, { "device": "XMF", "pin": "b" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XMBQ", "pin": "d" }, { "device": "XRq", "pin": "p" }, { "device": "XMC1", "pin": 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[] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XMN1", "pin": "d" }, { "device": "XM1", "pin": "d" }, { "device": "XMC1", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XM2", "pin": "d" }, { "device": "XMC2", "pin": "s" }, { "device": "XCc", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "div", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XR1", "pin": "n" }, { "device": "XR2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "m1", "ground": false, "terminals": [ { "device": "XMC1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XMF", "pin": "g" }, { "device": "XCx", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCc", "pin": "p" }, { "device": "XRb", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XR1", "pin": "p" } ], "ports": [ "sense" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldocapless" } }, { "id": "graph-7", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m", "source": "Vref ref 0 dc 400m", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib ib 0 dc 5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldocapless", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldocapless", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldocapless" }, { "id": "Vinj", "displayName": "Vinj", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Vinj sense out dc 0 ac 1", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "100p", "source": "Cl out 0 100p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "dc 5m", "source": "Vload il 0 dc 5m", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vinj", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vinj", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldocapless", "name": "ldocapless", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMBP", "displayName": "MBP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMBP ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=6", "source": "XMT ts ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=6", "pins": [ { "id": "d", "net": "ts" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBF", "displayName": "MBF", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMBF pg ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "pg" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBQ", "displayName": "MBQ", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMBQ vbc ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRq", "displayName": "Rq", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=9.166u", "source": "XRq vbc vbn vss rhigh w=0.5u l=9.166u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMBN", "displayName": "MBN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMBN vbn vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN1", "displayName": "MN1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=8", "source": "XMN1 f1 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=8", "source": "XMN2 f2 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM1 f1 div ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "div" }, { "id": "s", "net": "ts" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM2 f2 ref ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ts" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=500n ng=4 m=1", "source": "XMC1 m1 vbc f1 vss sg13_lv_nmos w=20u l=500n ng=4 m=1", "pins": [ { "id": "d", "net": "m1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=500n ng=4 m=1", "source": "XMC2 x vbc f2 vss sg13_lv_nmos w=20u l=500n ng=4 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM3 m1 m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "m1" }, { "id": "g", "net": "m1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM4 x m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "m1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMF", "displayName": "MF", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2m l=400n ng=400 m=1", "source": "XMF vss x pg pg sg13_lv_pmos w=2m l=400n ng=400 m=1", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "x" }, { "id": "s", "net": "pg" }, { "id": "b", "net": "pg" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3m l=180n ng=600 m=1", "source": "XMP out pg vdd vdd sg13_lv_pmos w=3m l=180n ng=600 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "pg" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.435u l=29.435u m=23", "source": "XCc out f2 cap_cmim w=29.435u l=29.435u m=23", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "f2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCx", "displayName": "Cx", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.435u l=29.435u m=23", "source": "XCx x vss cap_cmim w=29.435u l=29.435u m=23", "pins": [ { "id": "p", "net": "x" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR1 sense div vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "div" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR2 div vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "div" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=17.447u", "source": "XRb out vss vss rppd w=0.5u l=17.447u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMBP", "pin": "d" }, { "device": "XMBP", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMBF", "pin": "g" }, { "device": "XMBQ", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMBP", "pin": "s" }, { "device": "XMBP", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMBF", "pin": "s" }, { "device": "XMBF", "pin": "b" }, { "device": "XMBQ", "pin": "s" }, { "device": "XMBQ", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "ts", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "pg", "ground": false, "terminals": [ { "device": "XMBF", "pin": "d" }, { "device": "XMF", "pin": "s" }, { "device": "XMF", "pin": "b" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XMBQ", "pin": "d" }, { "device": "XRq", "pin": "p" }, { "device": "XMC1", "pin": "g" }, { "device": "XMC2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRq", "pin": "n" }, { "device": "XMBN", "pin": "d" }, { "device": "XMBN", "pin": "g" }, { "device": "XMN1", "pin": "g" }, { "device": "XMN2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRq", "pin": "substrate" }, { "device": "XMBN", "pin": "s" }, { "device": "XMBN", "pin": "b" }, { "device": "XMN1", "pin": "s" }, { "device": "XMN1", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XMC1", "pin": "b" }, { "device": "XMC2", "pin": "b" }, { "device": "XMF", "pin": "d" }, { "device": "XCx", "pin": "n" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR2", "pin": "n" }, { "device": "XR2", "pin": "substrate" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XMN1", "pin": "d" }, { "device": "XM1", "pin": "d" }, { "device": "XMC1", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XM2", "pin": "d" }, { "device": "XMC2", "pin": "s" }, { "device": "XCc", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "div", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XR1", "pin": "n" }, { "device": "XR2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "m1", "ground": false, "terminals": [ { "device": "XMC1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XMF", "pin": "g" }, { "device": "XCx", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCc", "pin": "p" }, { "device": "XRb", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XR1", "pin": "p" } ], "ports": [ "sense" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldocapless" } }, { "id": "graph-8", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m", "source": "Vref ref 0 dc 400m", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib ib 0 dc 5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldocapless", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldocapless", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldocapless" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "100p", "source": "Cl out 0 100p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "pwl(0 0 8u 0 8.4u 20u 20u 20u 20.4u 5u 28u 5u 28.4u 25u 40u 25u 40.4u 50u 48u 50u 48.4u 70u 60u 70u 60.4u 500u 68u 500u 68.4u 550u 80u 550u 80.4u 5m 88u 5m 88.4u 5.5m 100u 5.5m)", "source": "Vload il 0 pwl(0 0 8u 0 8.4u 20u 20u 20u 20.4u 5u 28u 5u 28.4u 25u 40u 25u 40.4u 50u 48u 50u 48.4u 70u 60u 70u 60.4u 500u 68u 500u 68.4u 550u 80u 550u 80.4u 5m 88u 5m 88.4u 5.5m 100u 5.5m)", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldocapless", "name": "ldocapless", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMBP", "displayName": "MBP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMBP ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=6", "source": "XMT ts ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=6", "pins": [ { "id": "d", "net": "ts" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBF", "displayName": "MBF", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMBF pg ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "pg" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBQ", "displayName": "MBQ", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMBQ vbc ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRq", "displayName": "Rq", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=9.166u", "source": "XRq vbc vbn vss rhigh w=0.5u l=9.166u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMBN", "displayName": "MBN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMBN vbn vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN1", "displayName": "MN1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=8", "source": "XMN1 f1 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=8", "source": "XMN2 f2 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM1 f1 div ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "div" }, { "id": "s", "net": "ts" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM2 f2 ref ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ts" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=500n ng=4 m=1", "source": "XMC1 m1 vbc f1 vss sg13_lv_nmos w=20u l=500n ng=4 m=1", "pins": [ { "id": "d", "net": "m1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=500n ng=4 m=1", "source": "XMC2 x vbc f2 vss sg13_lv_nmos w=20u l=500n ng=4 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM3 m1 m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "m1" }, { "id": "g", "net": "m1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM4 x m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "m1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMF", "displayName": "MF", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2m l=400n ng=400 m=1", "source": "XMF vss x pg pg sg13_lv_pmos w=2m l=400n ng=400 m=1", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "x" }, { "id": "s", "net": "pg" }, { "id": "b", "net": "pg" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3m l=180n ng=600 m=1", "source": "XMP out pg vdd vdd sg13_lv_pmos w=3m l=180n ng=600 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "pg" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.435u l=29.435u m=23", "source": "XCc out f2 cap_cmim w=29.435u l=29.435u m=23", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "f2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCx", "displayName": "Cx", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.435u l=29.435u m=23", "source": "XCx x vss cap_cmim w=29.435u l=29.435u m=23", "pins": [ { "id": "p", "net": "x" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR1 sense div vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "div" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR2 div vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "div" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=17.447u", "source": "XRb out vss vss rppd w=0.5u l=17.447u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMBP", "pin": "d" }, { "device": "XMBP", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMBF", "pin": "g" }, { "device": "XMBQ", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMBP", "pin": "s" }, { "device": "XMBP", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMBF", "pin": "s" }, { "device": "XMBF", "pin": "b" }, { "device": "XMBQ", "pin": "s" }, { "device": "XMBQ", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "ts", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "pg", "ground": false, "terminals": [ { "device": "XMBF", "pin": "d" }, { "device": "XMF", "pin": "s" }, { "device": "XMF", "pin": "b" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XMBQ", "pin": "d" }, { "device": "XRq", "pin": "p" }, { "device": "XMC1", "pin": "g" }, { "device": "XMC2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRq", "pin": "n" }, { "device": "XMBN", "pin": "d" }, { "device": "XMBN", "pin": "g" }, { "device": "XMN1", "pin": "g" }, { "device": "XMN2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRq", "pin": "substrate" }, { "device": "XMBN", "pin": "s" }, { "device": "XMBN", "pin": "b" }, { "device": "XMN1", "pin": "s" }, { "device": "XMN1", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XMC1", "pin": "b" }, { "device": "XMC2", "pin": "b" }, { "device": "XMF", "pin": "d" }, { "device": "XCx", "pin": "n" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR2", "pin": "n" }, { "device": "XR2", "pin": "substrate" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XMN1", "pin": "d" }, { "device": "XM1", "pin": "d" }, { "device": "XMC1", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XM2", "pin": "d" }, { "device": "XMC2", "pin": "s" }, { "device": "XCc", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "div", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XR1", "pin": "n" }, { "device": "XR2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "m1", "ground": false, "terminals": [ { "device": "XMC1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XMF", "pin": "g" }, { "device": "XCx", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCc", "pin": "p" }, { "device": "XRb", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XR1", "pin": "p" } ], "ports": [ "sense" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldocapless" } }, { "id": "graph-9", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD} ac 1", "source": "Vdd vdd 0 dc {VDD} ac 1", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m", "source": "Vref ref 0 dc 400m", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib ib 0 dc 5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldocapless", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldocapless", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldocapless" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "100p", "source": "Cl out 0 100p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "dc 5m", "source": "Vload il 0 dc 5m", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldocapless", "name": "ldocapless", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMBP", "displayName": "MBP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMBP ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=6", "source": "XMT ts ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=6", "pins": [ { "id": "d", "net": "ts" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBF", "displayName": "MBF", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMBF pg ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "pg" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBQ", "displayName": "MBQ", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMBQ vbc ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRq", "displayName": "Rq", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=9.166u", "source": "XRq vbc vbn vss rhigh w=0.5u l=9.166u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMBN", "displayName": "MBN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMBN vbn vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN1", "displayName": "MN1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=8", "source": "XMN1 f1 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=8", "source": "XMN2 f2 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM1 f1 div ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "div" }, { "id": "s", "net": "ts" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM2 f2 ref ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ts" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=500n ng=4 m=1", "source": "XMC1 m1 vbc f1 vss sg13_lv_nmos w=20u l=500n ng=4 m=1", "pins": [ { "id": "d", "net": "m1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=500n ng=4 m=1", "source": "XMC2 x vbc f2 vss sg13_lv_nmos w=20u l=500n ng=4 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM3 m1 m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "m1" }, { "id": "g", "net": "m1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM4 x m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "m1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMF", "displayName": "MF", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2m l=400n ng=400 m=1", "source": "XMF vss x pg pg sg13_lv_pmos w=2m l=400n ng=400 m=1", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "x" }, { "id": "s", "net": "pg" }, { "id": "b", "net": "pg" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3m l=180n ng=600 m=1", "source": "XMP out pg vdd vdd sg13_lv_pmos w=3m l=180n ng=600 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "pg" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.435u l=29.435u m=23", "source": "XCc out f2 cap_cmim w=29.435u l=29.435u m=23", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "f2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCx", "displayName": "Cx", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.435u l=29.435u m=23", "source": "XCx x vss cap_cmim w=29.435u l=29.435u m=23", "pins": [ { "id": "p", "net": "x" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR1 sense div vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "div" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR2 div vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "div" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=17.447u", "source": "XRb out vss vss rppd w=0.5u l=17.447u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMBP", "pin": "d" }, { "device": "XMBP", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMBF", "pin": "g" }, { "device": "XMBQ", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMBP", "pin": "s" }, { "device": "XMBP", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMBF", "pin": "s" }, { "device": "XMBF", "pin": "b" }, { "device": "XMBQ", "pin": "s" }, { "device": "XMBQ", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "ts", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "pg", "ground": false, "terminals": [ { "device": "XMBF", "pin": "d" }, { "device": "XMF", "pin": "s" }, { "device": "XMF", "pin": "b" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XMBQ", "pin": "d" }, { "device": "XRq", "pin": "p" }, { "device": "XMC1", "pin": "g" }, { "device": "XMC2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRq", "pin": "n" }, { "device": "XMBN", "pin": "d" }, { "device": "XMBN", "pin": "g" }, { "device": "XMN1", "pin": "g" }, { "device": "XMN2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRq", "pin": "substrate" }, { "device": "XMBN", "pin": "s" }, { "device": "XMBN", "pin": "b" }, { "device": "XMN1", "pin": "s" }, { "device": "XMN1", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XMC1", "pin": "b" }, { "device": "XMC2", "pin": "b" }, { "device": "XMF", "pin": "d" }, { "device": "XCx", "pin": "n" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR2", "pin": "n" }, { "device": "XR2", "pin": "substrate" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XMN1", "pin": "d" }, { "device": "XM1", "pin": "d" }, { "device": "XMC1", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XM2", "pin": "d" }, { "device": "XMC2", "pin": "s" }, { "device": "XCc", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "div", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XR1", "pin": "n" }, { "device": "XR2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "m1", "ground": false, "terminals": [ { "device": "XMC1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XMF", "pin": "g" }, { "device": "XCx", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCc", "pin": "p" }, { "device": "XRb", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XR1", "pin": "p" } ], "ports": [ "sense" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldocapless" } }, { "id": "graph-10", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m", "source": "Vref ref 0 dc 400m", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib ib 0 dc 5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldocapless", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldocapless", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldocapless" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "100p", "source": "Cl out 0 100p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "pulse(0 5m 4u 1u 1u 17u 80u)", "source": "Vload il 0 pulse(0 5m 4u 1u 1u 17u 80u)", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldocapless", "name": "ldocapless", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMBP", "displayName": "MBP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMBP ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=6", "source": "XMT ts ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=6", "pins": [ { "id": "d", "net": "ts" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBF", "displayName": "MBF", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XMBF pg ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "pg" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBQ", "displayName": "MBQ", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMBQ vbc ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRq", "displayName": "Rq", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=9.166u", "source": "XRq vbc vbn vss rhigh w=0.5u l=9.166u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMBN", "displayName": "MBN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMBN vbn vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN1", "displayName": "MN1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=8", "source": "XMN1 f1 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=8", "source": "XMN2 f2 vbn vss vss sg13_lv_nmos w=4u l=4u ng=1 m=8", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM1 f1 div ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "div" }, { "id": "s", "net": "ts" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=80u l=1u ng=16 m=1", "source": "XM2 f2 ref ts vdd sg13_lv_pmos w=80u l=1u ng=16 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "ts" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC1", "displayName": "MC1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=500n ng=4 m=1", "source": "XMC1 m1 vbc f1 vss sg13_lv_nmos w=20u l=500n ng=4 m=1", "pins": [ { "id": "d", "net": "m1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMC2", "displayName": "MC2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=500n ng=4 m=1", "source": "XMC2 x vbc f2 vss sg13_lv_nmos w=20u l=500n ng=4 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM3 m1 m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "m1" }, { "id": "g", "net": "m1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM4 x m1 vdd vdd sg13_lv_pmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "m1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMF", "displayName": "MF", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2m l=400n ng=400 m=1", "source": "XMF vss x pg pg sg13_lv_pmos w=2m l=400n ng=400 m=1", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "x" }, { "id": "s", "net": "pg" }, { "id": "b", "net": "pg" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3m l=180n ng=600 m=1", "source": "XMP out pg vdd vdd sg13_lv_pmos w=3m l=180n ng=600 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "pg" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.435u l=29.435u m=23", "source": "XCc out f2 cap_cmim w=29.435u l=29.435u m=23", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "f2" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCx", "displayName": "Cx", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.435u l=29.435u m=23", "source": "XCx x vss cap_cmim w=29.435u l=29.435u m=23", "pins": [ { "id": "p", "net": "x" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR1 sense div vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "div" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR2 div vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "div" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=17.447u", "source": "XRb out vss vss rppd w=0.5u l=17.447u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMBP", "pin": "d" }, { "device": "XMBP", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMBF", "pin": "g" }, { "device": "XMBQ", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMBP", "pin": "s" }, { "device": "XMBP", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMBF", "pin": "s" }, { "device": "XMBF", "pin": "b" }, { "device": "XMBQ", "pin": "s" }, { "device": "XMBQ", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "ts", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "pg", "ground": false, "terminals": [ { "device": "XMBF", "pin": "d" }, { "device": "XMF", "pin": "s" }, { "device": "XMF", "pin": "b" }, { "device": "XMP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XMBQ", "pin": "d" }, { "device": "XRq", "pin": "p" }, { "device": "XMC1", "pin": "g" }, { "device": "XMC2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRq", "pin": "n" }, { "device": "XMBN", "pin": "d" }, { "device": "XMBN", "pin": "g" }, { "device": "XMN1", "pin": "g" }, { "device": "XMN2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRq", "pin": "substrate" }, { "device": "XMBN", "pin": "s" }, { "device": "XMBN", "pin": "b" }, { "device": "XMN1", "pin": "s" }, { "device": "XMN1", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XMC1", "pin": "b" }, { "device": "XMC2", "pin": "b" }, { "device": "XMF", "pin": "d" }, { "device": "XCx", "pin": "n" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR2", "pin": "n" }, { "device": "XR2", "pin": "substrate" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XMN1", "pin": "d" }, { "device": "XM1", "pin": "d" }, { "device": "XMC1", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XM2", "pin": "d" }, { "device": "XMC2", "pin": "s" }, { "device": "XCc", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "div", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XR1", "pin": "n" }, { "device": "XR2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "m1", "ground": false, "terminals": [ { "device": "XMC1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMC2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XMF", "pin": "g" }, { "device": "XCx", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCc", "pin": "p" }, { "device": "XRb", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XR1", "pin": "p" } ], "ports": [ "sense" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldocapless" } }, { "id": "graph-11", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "pulse(1.08 1.32 4u 1u 1u 17u 80u)", "source": "Vdd vdd 0 pulse(1.08 1.32 4u 1u 1u 17u 80u)", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m", "source": "Vref ref 0 dc 400m", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib ib 0 dc 5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldocapless", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldocapless", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldocapless" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "100p", "source": "Cl out 0 100p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "dc 5m", "source": "Vload il 0 dc 5m", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { 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