{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ldo-error-amp-3v3", "name": "LDO error amplifier, 3.3 V, level-shifted output", "group": "Op amps and OTAs", "subgroup": "Two-stage op amps", "title": "LDO error amplifier, 3.3 V", "summary": "Compares a regulator's reference with its sensed output and drives a PMOS pass gate. Two gain stages and a level shifter provide gain and gate drive from a 3.3 V supply. Matched current sinks reduce built-in offset; compensation trades speed for stability.", "reference": { "kind": "paper", "authors": "Texas Instruments", "title": "TPS7A21 500-mA, Low-Noise, Low-IQ, High-PSRR LDO", "year": 2022, "where": "Texas Instruments datasheet SBVS398A, Rev. A (original Dec. 2021)", "publisher": "Texas Instruments", "takes": "The application: the error amplifier of a low-dropout regulator of that kind, run from the regulator's input and driving its PMOS pass device, with a level-shifted common-source output stage. The 3.3 V devices - chosen because the amplifier lives on a 3.3 V input rail and must swing the pass gate across it - the offset-cancelling twin of the level shifter, the sizing and the spec targets are this library's." }, "resources": { "record": "/circuits/ldo-error-amp-3v3.json", "page": "/index.html#ldo-error-amp-3v3", "achieved": "/achieved/ldo-error-amp-3v3.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_hv_tt.spice", "url": "/sg13g2_hv_tt.spice", "sha256": "e9b858ad4f7bba550467f1eddb6ca496bcc5f4644474f41240d63927934928ad" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "inp", "kind": "input" }, { "name": "inn", "kind": "input" }, { "name": "out", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the reference current, fed into this pin" } ], "devices": [ { "name": "MB", "type": "nmos", "nodes": "ib ib vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "bias reference, diode-connected (3.3 V NMOS)", "fingers": 6, "copies": 1 }, { "name": "MT", "type": "nmos", "nodes": "tail ib vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "tail current source, two copies of MB", "fingers": 6, "copies": 2 }, { "name": "M1", "type": "nmos", "nodes": "d1 inn tail vss", "sizedBy": [ "W1", "L1" ], "role": "input pair, inverting input, on the mirror's diode side", "fingers": 40, "copies": 1 }, { "name": "M2", "type": "nmos", "nodes": "d2 inp tail vss", "sizedBy": [ "W1", "L1" ], "role": "input pair, non-inverting input", "fingers": 40, "copies": 1 }, { "name": "M3", "type": "pmos", "nodes": "d1 d1 vdd vdd", "sizedBy": [ "Wm", "Lm" ], "role": "mirror load, diode-connected (3.3 V PMOS)", "fingers": 16, "copies": 1 }, { "name": "M4", "type": "pmos", "nodes": "d2 d1 vdd vdd", "sizedBy": [ "Wm", "Lm" ], "role": "mirror load, first-stage output", "fingers": 16, "copies": 1 }, { "name": "MLS", "type": "pmos", "nodes": "ls ls d2 d2", "sizedBy": [ "Wls", "Lls" ], "role": "level shifter: a PMOS diode standing on d2, its n-well on d2", "fingers": 1, "copies": 1 }, { "name": "MLN", "type": "nmos", "nodes": "ls ib vss vss", "sizedBy": [ "Wt", "Lt" ], "role": "the level shifter's current: MB's current density on a larger area", "fingers": 10, "copies": 1 }, { "name": "MLD", "type": "nmos", "nodes": "d1 ib vss vss", "sizedBy": [ "Wt", "Lt" ], "role": "MLN's twin on the diode side: balances the pair", "fingers": 10, "copies": 1 }, { "name": "MO", "type": "pmos", "nodes": "out ls vdd vdd", "sizedBy": [ "Wo", "Lo" ], "role": "output stage, common source, driven from ls", "fingers": 6, "copies": 1 }, { "name": "MS", "type": "nmos", "nodes": "out ib vss vss", "sizedBy": [ "Wn", "Ln", "N" ], "role": "output sink, N copies of MB", "fingers": 6, "copies": 20 }, { "name": "Cc", "type": "capacitor", "nodes": "d2 cz", "sizedBy": [ "Cc" ], "role": "Miller compensation" }, { "name": "Rz", "type": "resistor", "nodes": "cz out", "sizedBy": [ "Rz" ], "role": "nulling resistor" } ], "intent": [ { "rule": "supply", "of": [ "vdd" ], "constraint": "3.3 V devices at V_DD = 3.3 V", "why": "An error amplifier runs from the regulator's input and drives the pass device's gate across it. On chip that input is the 3.3 V rail, beyond what the 1.2 V core devices take, and the level shifter needs its volts: at 1.2 V there is no room to drop a gate a whole V_SG." }, { "rule": "match", "of": [ "M1", "M2" ], "why": "The input pair: its threshold mismatch goes straight to the input, and the regulator multiplies it by its feedback ratio. 200 × 5 µm each, 0.22 mV σ of threshold per device; the long channel also keeps the pair's current nearly independent of where d2 sits, so the offset stays small over temperature." }, { "rule": "match", "of": [ "M3", "M4" ], "why": "The mirror load: a mismatch copies the wrong current to d2. Its share of the offset is its threshold mismatch times g_m3/g_m1, so the mirror runs in stronger inversion than the pair - g_m/I_D 5.7 against 17.5, 72 × 5.5 µm - and passes on only two thirds of its mismatch." }, { "rule": "offset-budget", "of": [ "M1", "M2", "M3", "M4", "MLN", "MLD" ], "constraint": "σ_os² = 2σ²_VT1 + 2(g_m3/g_m1)² σ²_VT3 + 2(I_LS (g_m/I_D)_LN/g_m1)² σ²_VTLN", "why": "3.3 V devices match about half as well as the core ones for the same area - about 7 mV·µm of threshold for the NMOS, 4.5 mV·µm for the PMOS. At 40 × 2 µm the pair alone gave 1.1 mV σ of the whole 1.34 mV, and a quarter of the draws missed ±2 mV. Each group is sized for its share - the pair 55 %, the mirror 25 %, the twin 20 % - for 0.42 mV σ of threshold mismatch; the draws show 0.46 mV." }, { "rule": "unit-copies", "of": [ "MB", "MT", "MS", "MLN", "MLD" ], "constraint": "MT = 2, MS = N copies of MB; MLN = MLD at MB's W/L, four times its area", "why": "The tail and the output sink are copies of the one reference device. The level shifter's sink and its twin keep MB's W/L, so they carry its current, on four times its area: only their difference reaches the offset, and it halves." }, { "rule": "balance", "of": [ "MLD", "MLN", "M3", "M4" ], "constraint": "I_MLD = I_MLN", "why": "MLS draws its current out of d2, so without a twin the pair would carry I_LS more on M1's side at balance: 64 mV of built-in offset. MLD draws the same current from d1, the mirror's diode side, and the two sides carry equal currents again." }, { "rule": "level-shift", "of": [ "MLS", "MO" ], "constraint": "V_SG,MO = (V_DD − v_d2) + V_SG,MLS", "why": "The output device's gate sits a whole V_SG below d2, so MO runs at about 1.8 V of V_SG: 22 µm carries 200 µA and can pull the pass gate up with much more. MLS stands in its own n-well, tied to d2, so body effect adds nothing to the shift: with the well on vdd it added about 0.3 V, MO ran at 2.1 V, and its larger V_DSAT cost the top of the output range 0.17 V at the slow, hot corner. The price of the drive is g_m per µA, 1.7 V⁻¹, which puts the output pole low." }, { "rule": "zero", "of": [ "Rz", "Cc", "MO" ], "constraint": "R_z ≈ 2/g_mO", "why": "Cc feeds d2 forward to the output: a right-half-plane zero at g_mO/C_c. R_z of 6 kΩ against 1/g_mO of 2.9 kΩ moves it into the left half-plane just above the crossover, where it gives back the phase the larger mirror's pole takes: at 5 kΩ the fast corner kept only 72°." } ], "specs": [ { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.0003 A", "min": null, "max": 0.0003, "why": "20 µA in the pair, 10 µA each in the level shifter and its twin, 200 µA in the output stage and the 10 µA reference itself: 252 µA, all copies of the reference, which is held at every corner." }, { "key": "vos", "label": "Systematic offset", "unit": "V", "direction": "target", "constraint": ">= -0.002 V, <= 0.002 V", "min": -0.002, "max": 0.002, "why": "The level shifter's 10 µA comes out of d2 and on its own would unbalance the pair by I_LS/g_m1, 64 mV; MLD draws the same from d1, and what is left is within 0.4 mV at every corner. Mismatch adds 0.46 mV σ over forty draws - the pair, the mirror and the twin are sized for the 3.3 V devices' matching - and every draw of seeds 1 to 40 stays within 0.9 mV." }, { "key": "dc_gain_db", "label": "DC open-loop gain", "unit": "dB", "direction": "max", "constraint": ">= 70 dB", "min": 70, "max": null, "why": "Two stages of 3.3 V devices with long channels: 94 dB at 27 °C, 91 dB slow, hot and 10 % low." }, { "key": "ugf_hz", "label": "Unity-gain frequency", "unit": "Hz", "direction": "max", "constraint": ">= 1200000 Hz", "min": 1200000, "max": null, "why": "g_m1/(2π C_c): 1.9 MHz at 27 °C, 1.36 MHz at the slow, hot corner." }, { "key": "pm_deg", "label": "Phase margin", "unit": "deg", "direction": "max", "constraint": ">= 70 deg", "min": 70, "max": null, "why": "The output pole g_mO/C_L sits nearly three times above the crossover, and R_z, twice 1/g_mO, puts the Miller zero in the left half-plane just above it: 80° to 92° over the corners." }, { "key": "t_settle", "label": "Settling time, 1 %", "unit": "s", "direction": "min", "constraint": "<= 7e-7 s", "min": null, "max": 7e-7, "why": "A 0.2 V step, rising: 0.42 µs at 27 °C, 0.53 µs slow, hot and 10 % low." }, { "key": "t_settle_fall", "label": "Settling time, 1 %, falling", "unit": "s", "direction": "min", "constraint": "<= 7e-7 s", "min": null, "max": 7e-7, "why": "The falling edge, pulled down by MS's fixed 200 µA against the pass gate's 10 pF: as fast as the rising one." }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 55 dB", "min": 55, "max": null, "why": "Every current is a copy of the held reference, and the level shifter and the output device sit between d2 and V_DD: 62 dB or more at every corner." }, { "key": "cmrr_db", "label": "Common-mode rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 65 dB", "min": 65, "max": null, "why": "The pair's long channels and the tail's output resistance: 80 dB or more at every corner." }, { "key": "icmr_lo", "label": "Lowest input common mode", "unit": "V", "direction": "min", "constraint": "<= 1 V", "min": null, "max": 1, "why": "The tail needs V_GS1 + V_DSAT,T under the input: about 0.86 V, which a 1.2 V bandgap reference clears." }, { "key": "icmr_hi", "label": "Highest input common mode", "unit": "V", "direction": "max", "constraint": ">= 2.5 V", "min": 2.5, "max": null, "why": "The pair keeps saturated until its drains, a mirror V_SG under V_DD, come within a threshold of the input: far above any reference it will be given." }, { "key": "swing_lo", "label": "Lowest output", "unit": "V", "direction": "min", "constraint": "<= 0.6 V", "min": null, "max": 0.6, "why": "MS leaves saturation at its V_DSAT: the output reaches 0.5 V, where the pass device is fully on." }, { "key": "swing_hi", "label": "Highest output", "unit": "V", "direction": "max", "constraint": ">= 1.5 V", "min": 1.5, "max": null, "why": "MO, driven at 1.8 V of V_SG, has a V_DSAT near 0.7 V and loses output resistance before it: the gain is 6 dB below its 94 dB peak at 2.2 V and still 63 dB at 2.64 V, where a pass device's gate turns it off. 1.72 V slow, hot and 10 % low." } ], "explanation": { "idea": "Compares a regulator's reference with its sensed output and drives a PMOS pass gate. Two gain stages and a level shifter provide gain and gate drive from a 3.3 V supply. Matched current sinks reduce built-in offset; compensation trades speed for stability.", "detail": "The error amplifier of a low-dropout regulator that runs from a 3.3 V input rail: it compares the reference with the fed-back fraction of the output and drives the gate of the PMOS pass device, so its gain sets how closely the output holds its value and its offset sets how exactly. It is built from SG13G2's 3.3 V devices because it lives on that rail and must swing the pass gate across it. Two stages - an NMOS pair on a PMOS mirror, then a common-source PMOS - with a diode-connected PMOS between them that shifts the output device's gate a whole V_SG down, so a small output device runs at a large gate drive. The level shifter's current comes out of the first stage's output, and a twin of it drawn from the mirror's other side keeps the pair balanced. The 3.3 V devices match about half as well as the core ones, so the pair, mirror and twin need enough matching area.", "lesson": { "relation": 1, "symbols": "f_u is unity-gain frequency in hertz; g_m1 is input-device transconductance; C_c is the Miller compensation capacitance.", "assumptions": "The Miller dominant-pole approximation with adequate second-stage gain and other poles above crossover. The level shifter and parasitic capacitances affect the measured result.", "exercise": { "param": "Cc", "value": 2e-11, "analysis": "open_loop", "expect": "A larger compensation capacitor should reduce unity-gain frequency. Check phase margin too: compensation must be assessed with the actual load." }, "limits": "This is an amplifier, not a complete regulator. It needs a 3.3 V supply, external bias current and a compatible pass-gate load; the bench uses 10 pF." }, "path": [ { "part": "Input pair", "devices": "M1, M2, MT", "does": "MT's 20 µA divides between M1 and M2 by inp − inn. A rise on inp pulls d2 down through M2; the output stage inverts it back, so out follows inp." }, { "part": "Mirror load", "devices": "M3, M4, MLD", "does": "M3 turns the current on d1 - M1's and MLD's - into a gate voltage, and M4 copies it onto d2, where M2 and the level shifter draw theirs." }, { "part": "Level shifter", "devices": "MLS, MLN", "does": "Diode-connected MLS stands on d2, in its own n-well, and carries MLN's fixed 10 µA, so ls follows d2 1.03 V lower, with a gain close to one." }, { "part": "Output stage", "devices": "MO, MS", "does": "Common-source MO, its gate on ls, amplifies against the sink MS and inverts onto out; its 1.8 V of V_SG lets a 22 µm device carry 200 µA." }, { "part": "Compensation", "devices": "Cc, Rz", "does": "Cc in series with Rz, from d2 to out, is a Miller capacitor across the level shifter and the output stage; Rz moves its feed-forward zero into the left half-plane, just above the crossover." } ], "bias": "The testbench feeds the 10 µA reference into the diode MB. MT, two copies, is the tail and MS, twenty copies, sinks the output stage's 200 µA; MLN and MLD keep MB's W/L on four times its area, so each carries its 10 µA - 252 µA in all. With MLD taking from d1 what MLS takes from d2, each mirror device carries 20 µA and each input device 10 µA. The pair (200 × 5 µm) runs near weak inversion, g_m/I_D 17.5; the mirror (72 × 5.5 µm) in stronger inversion, 5.7, at 0.99 V of V_SG.", "relations": [ { "what": "DC gain", "expr": "A_0 ≈ g_m2 (r_o2 ∥ r_o4) · g_mO (r_oO ∥ r_oS)", "note": "The level shifter passes d2 to ls with a gain close to one, so it drops out. 3.3 V devices with long channels give about 94 dB." }, { "what": "Unity-gain frequency", "expr": "f_u ≈ g_m1/(2π C_c)", "note": "About 0.17 mS into 15 pF: 1.9 MHz." }, { "what": "Output pole", "expr": "f_p2 ≈ g_mO/(2π C_L)", "note": "C_L is the pass device's gate, 10 pF here. MO driven hard makes only 1.7 S/A, so the pole sits near 5.4 MHz: it takes 200 µA to keep it nearly three times above the crossover." }, { "what": "Built-in offset, cancelled", "expr": "V_os ≈ (I_MLN − I_MLD)/g_m1", "note": "Without MLD this is I_MLN/g_m1, 64 mV; with it only the two sinks' small difference is left, within 0.4 mV at every corner." }, { "what": "Offset from mismatch", "expr": "σ_os² = 2σ²_VT1 + 2(g_m3/g_m1)² σ²_VT3 + 2(I_LS (g_m/I_D)_LN/g_m1)² σ²_VTLN", "note": "With σ_VT = A_VT/√(W·L): the pair 0.31 mV, the mirror 0.21 mV - its mismatch scaled by g_m3/g_m1, 0.66 - and the twin 0.19 mV, 0.42 mV together. Forty draws show 0.46 mV σ." }, { "what": "Output device's drive", "expr": "V_SG,MO = (V_DD − v_d2) + V_SG,MLS", "note": "d2 rests about 0.77 V under V_DD, where MO carries MS's current, and MLS adds 1.03 V: 1.8 V of V_SG. As ls falls MO can source far more into the pass gate." } ], "tradeoffs": [ "Area for offset: the pair gives most of it, so it is the largest device (1000 µm² each). At 40 × 2 µm the offset was 1.34 mV σ and a quarter of the draws missed ±2 mV; the price of 200 × 5 µm is input capacitance, which the real reference and feedback divider must drive.", "The mirror in stronger inversion reduces its input-referred mismatch through the factor g_m3/g_m1, but lowers the pair's drains and the top of the input range, and its larger gates put a pole near 7 MHz on d1: Cc grew from 12 to 15 pF and R_z to 6 kΩ to keep 80° of margin at the fast corner.", "A stronger level shift (narrower MLS, or its well on vdd) drives MO harder: a smaller MO and more pull-up, but less g_m per µA, a lower output pole, and a larger V_DSAT that lowers the top of the output range - by 0.17 V at the slow, hot corner with the well on vdd.", "More output current (N) raises g_mO and the output pole, allowing a smaller Cc and more bandwidth, and slews the pass gate faster downwards, at the cost of supply current - already 200 of the 252 µA." ] }, "sizing": [ { "key": "Ib", "label": "Reference current", "unit": "A", "value": 0.00001, "min": 0.000001, "max": 0.0001, "kind": "si" }, { "key": "Wn", "label": "W NMOS unit (MB, MT, MS)", "unit": "m", "value": 0.000024, "min": 5e-7, "max": 0.00005, "kind": "si" }, { "key": "Ln", "label": "L NMOS unit", "unit": "m", "value": 0.000006, "min": 4.5e-7, "max": 0.00001, "kind": "si" }, { "key": "N", "label": "Output sink, in Ib", "unit": "", "value": 20, "min": 2, "max": 60, "kind": "int" }, { "key": "W1", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.0002, "min": 0.000001, "max": 0.0004, "kind": "si" }, { "key": "L1", "label": "L input pair", "unit": "m", "value": 0.000005, "min": 4.5e-7, "max": 0.00001, "kind": "si" }, { "key": "Wm", "label": "W PMOS mirror (M3, M4)", "unit": "m", "value": 0.000072, "min": 0.000001, "max": 0.0001, "kind": "si" }, { "key": "Lm", "label": "L PMOS mirror", "unit": "m", "value": 0.0000055, "min": 4.5e-7, "max": 0.00001, "kind": "si" }, { "key": "Wt", "label": "W level-shift sinks (MLN, MLD)", "unit": "m", "value": 0.000048, "min": 5e-7, "max": 0.0002, "kind": "si" }, { "key": "Lt", "label": "L level-shift sinks", "unit": "m", "value": 0.000012, "min": 4.5e-7, "max": 0.00002, "kind": "si" }, { "key": "Wls", "label": "W level-shift diode (MLS)", "unit": "m", "value": 0.0000045, "min": 5e-7, "max": 0.00005, "kind": "si" }, { "key": "Lls", "label": "L level-shift diode", "unit": "m", "value": 0.000001, "min": 4.5e-7, "max": 0.00001, "kind": "si" }, { "key": "Wo", "label": "W output device (MO)", "unit": "m", "value": 0.000022, "min": 5e-7, "max": 0.0002, "kind": "si" }, { "key": "Lo", "label": "L output device", "unit": "m", "value": 0.000002, "min": 4.5e-7, "max": 0.00001, "kind": "si" }, { "key": "Cc", "label": "Miller capacitor", "unit": "F", "value": 1.5e-11, "min": 1e-12, "max": 6e-11, "kind": "si" }, { "key": "Rz", "label": "Nulling resistor", "unit": "Ω", "value": 6000, "min": 100, "max": 100000, "kind": "si" }, { "key": "CL", "label": "Load capacitance (the pass device's gate)", "unit": "F", "value": 1e-11, "min": 1e-12, "max": 1e-10, "kind": "si" }, { "key": "VCM", "label": "Input common mode (the reference level)", "unit": "V", "value": 1.2, "min": 0.8, "max": 2.4, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.", "measures": [], "metricKeys": [ "i_supply", "vout_dc", "vos" ], "acceptance": [ "i_supply", "vos" ], "acceptanceRules": [ { "key": "i_supply", "unit": "A", "min": null, "max": 0.0003, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "vos", "unit": "V", "min": -0.002, "max": 0.002, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* LDO error amplifier, 3.3 V, level-shifted output - operating point as a unity-gain buffer\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD}\nIb vdd ib 10u\n.subckt ldoea inp inn out vdd vss ib\n* bias: the reference into an NMOS diode, and copies of it\nXMB ib ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=1\nXMT tail ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=2\n* first stage: an NMOS pair on a PMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1\nXM2 d2 inp tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1\nXM3 d1 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1\nXM4 d2 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1\n* level shifter: a PMOS diode on d2, its n-well on d2, carries MLN's current,\n* so ls sits a V_SG below d2; MLD draws the same current from d1, so the pair\n* stays balanced\nXMLS ls ls d2 d2 sg13_hv_pmos w=4.5u l=1u ng=1 m=1\nXMLN ls ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1\nXMLD d1 ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1\n* output stage: a common-source PMOS driven hard from ls, against an NMOS sink\nXMO out ls vdd vdd sg13_hv_pmos w=22u l=2u ng=6 m=1\nXMS out ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=20\n* Miller compensation across the level shifter and the output stage\nXCc d2 cz cap_cmim w=28.814u l=28.814u m=12\nXRz cz out vss rppd w=0.5u l=11.54u\n.ends\nXdut inp inn out vdd 0 ib ldoea\nCl out 0 10p\nVin inp 0 dc 1.2\n* the output drives the inverting input: a unity-gain buffer\nVfb inn out 0\n.op\n.end" }, { "id": "open_loop", "label": "Open-loop gain", "note": "Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.", "measures": [], "metricKeys": [ "dc_gain_db", "ugf_hz", "pm_deg", "gm_db" ], "acceptance": [ "dc_gain_db", "ugf_hz", "pm_deg" ], "acceptanceRules": [ { "key": "dc_gain_db", "unit": "dB", "min": 70, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "ugf_hz", "unit": "Hz", "min": 1200000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "pm_deg", "unit": "deg", "min": 70, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* LDO error amplifier, 3.3 V, level-shifted output - open-loop gain and phase\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD}\nIb vdd ib 10u\n.subckt ldoea inp inn out vdd vss ib\n* bias: the reference into an NMOS diode, and copies of it\nXMB ib ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=1\nXMT tail ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=2\n* first stage: an NMOS pair on a PMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1\nXM2 d2 inp tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1\nXM3 d1 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1\nXM4 d2 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1\n* level shifter: a PMOS diode on d2, its n-well on d2, carries MLN's current,\n* so ls sits a V_SG below d2; MLD draws the same current from d1, so the pair\n* stays balanced\nXMLS ls ls d2 d2 sg13_hv_pmos w=4.5u l=1u ng=1 m=1\nXMLN ls ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1\nXMLD d1 ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1\n* output stage: a common-source PMOS driven hard from ls, against an NMOS sink\nXMO out ls vdd vdd sg13_hv_pmos w=22u l=2u ng=6 m=1\nXMS out ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=20\n* Miller compensation across the level shifter and the output stage\nXCc d2 cz cap_cmim w=28.814u l=28.814u m=12\nXRz cz out vss rppd w=0.5u l=11.54u\n.ends\nXdut inp inn out vdd 0 ib ldoea\nCl out 0 10p\nVin inp 0 dc 1.2 ac 1\n* the loop closed at DC and open at every frequency the sweep visits\nLfb out inn 1t\nCfb inn 0 1t\n.ac dec 25 0.1 10g\n.end" }, { "id": "step", "label": "Step response", "note": "A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.", "measures": [], "metricKeys": [ "sr", "t_settle", "overshoot_pct", "sr_fall", "t_settle_fall" ], "acceptance": [ "t_settle", "t_settle_fall" ], "acceptanceRules": [ { "key": "t_settle", "unit": "s", "min": null, "max": 7e-7, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "t_settle_fall", "unit": "s", "min": null, "max": 7e-7, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* LDO error amplifier, 3.3 V, level-shifted output - step response of the unity-gain buffer\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD}\nIb vdd ib 10u\n.subckt ldoea inp inn out vdd vss ib\n* bias: the reference into an NMOS diode, and copies of it\nXMB ib ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=1\nXMT tail ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=2\n* first stage: an NMOS pair on a PMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1\nXM2 d2 inp tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1\nXM3 d1 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1\nXM4 d2 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1\n* level shifter: a PMOS diode on d2, its n-well on d2, carries MLN's current,\n* so ls sits a V_SG below d2; MLD draws the same current from d1, so the pair\n* stays balanced\nXMLS ls ls d2 d2 sg13_hv_pmos w=4.5u l=1u ng=1 m=1\nXMLN ls ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1\nXMLD d1 ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1\n* output stage: a common-source PMOS driven hard from ls, against an NMOS sink\nXMO out ls vdd vdd sg13_hv_pmos w=22u l=2u ng=6 m=1\nXMS out ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=20\n* Miller compensation across the level shifter and the output stage\nXCc d2 cz cap_cmim w=28.814u l=28.814u m=12\nXRz cz out vss rppd w=0.5u l=11.54u\n.ends\nXdut inp inn out vdd 0 ib ldoea\nCl out 0 10p\nVin inp 0 pulse(1.1 1.3 1u 1n 1n 5u 20u)\nVfb inn out 0\n.tran 2.5n 10u\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.", "measures": [], "metricKeys": [ "psrr_db" ], "acceptance": [ "psrr_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 55, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* LDO error amplifier, 3.3 V, level-shifted output - supply rejection of the unity-gain buffer\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD} ac 1\nIb vdd ib 10u\n.subckt ldoea inp inn out vdd vss ib\n* bias: the reference into an NMOS diode, and copies of it\nXMB ib ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=1\nXMT tail ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=2\n* first stage: an NMOS pair on a PMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1\nXM2 d2 inp tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1\nXM3 d1 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1\nXM4 d2 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1\n* level shifter: a PMOS diode on d2, its n-well on d2, carries MLN's current,\n* so ls sits a V_SG below d2; MLD draws the same current from d1, so the pair\n* stays balanced\nXMLS ls ls d2 d2 sg13_hv_pmos w=4.5u l=1u ng=1 m=1\nXMLN ls ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1\nXMLD d1 ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1\n* output stage: a common-source PMOS driven hard from ls, against an NMOS sink\nXMO out ls vdd vdd sg13_hv_pmos w=22u l=2u ng=6 m=1\nXMS out ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=20\n* Miller compensation across the level shifter and the output stage\nXCc d2 cz cap_cmim w=28.814u l=28.814u m=12\nXRz cz out vss rppd w=0.5u l=11.54u\n.ends\nXdut inp inn out vdd 0 ib ldoea\nCl out 0 10p\nVin inp 0 dc 1.2\nVfb inn out 0\n.ac dec 25 1 100meg\n.end" }, { "id": "cmrr", "label": "Common-mode rejection", "note": "Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.", "measures": [], "metricKeys": [ "cmrr_db" ], "acceptance": [ "cmrr_db" ], "acceptanceRules": [ { "key": "cmrr_db", "unit": "dB", "min": 65, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* LDO error amplifier, 3.3 V, level-shifted output - common-mode rejection\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD}\nIb vdd ib 10u\n.subckt ldoea inp inn out vdd vss ib\n* bias: the reference into an NMOS diode, and copies of it\nXMB ib ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=1\nXMT tail ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=2\n* first stage: an NMOS pair on a PMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1\nXM2 d2 inp tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1\nXM3 d1 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1\nXM4 d2 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1\n* level shifter: a PMOS diode on d2, its n-well on d2, carries MLN's current,\n* so ls sits a V_SG below d2; MLD draws the same current from d1, so the pair\n* stays balanced\nXMLS ls ls d2 d2 sg13_hv_pmos w=4.5u l=1u ng=1 m=1\nXMLN ls ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1\nXMLD d1 ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1\n* output stage: a common-source PMOS driven hard from ls, against an NMOS sink\nXMO out ls vdd vdd sg13_hv_pmos w=22u l=2u ng=6 m=1\nXMS out ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=20\n* Miller compensation across the level shifter and the output stage\nXCc d2 cz cap_cmim w=28.814u l=28.814u m=12\nXRz cz out vss rppd w=0.5u l=11.54u\n.ends\nXdut inp inn out vdd 0 ib ldoea\nCl out 0 10p\nVsrc src 0 dc 1.2\n* va on the non-inverting input, vb in the feedback path: both inputs move with the signal\nVa inp src dc 0 ac 1\nVb inn out dc 0 ac 1\n.ac dec 25 1 100meg\n.end" }, { "id": "noise", "label": "Noise", "note": "Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.", "measures": [], "metricKeys": [ "vn_1k", "vn_int" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* LDO error amplifier, 3.3 V, level-shifted output - input-referred noise\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD}\nIb vdd ib 10u\n.subckt ldoea inp inn out vdd vss ib\n* bias: the reference into an NMOS diode, and copies of it\nXMB ib ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=1\nXMT tail ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=2\n* first stage: an NMOS pair on a PMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1\nXM2 d2 inp tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1\nXM3 d1 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1\nXM4 d2 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1\n* level shifter: a PMOS diode on d2, its n-well on d2, carries MLN's current,\n* so ls sits a V_SG below d2; MLD draws the same current from d1, so the pair\n* stays balanced\nXMLS ls ls d2 d2 sg13_hv_pmos w=4.5u l=1u ng=1 m=1\nXMLN ls ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1\nXMLD d1 ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1\n* output stage: a common-source PMOS driven hard from ls, against an NMOS sink\nXMO out ls vdd vdd sg13_hv_pmos w=22u l=2u ng=6 m=1\nXMS out ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=20\n* Miller compensation across the level shifter and the output stage\nXCc d2 cz cap_cmim w=28.814u l=28.814u m=12\nXRz cz out vss rppd w=0.5u l=11.54u\n.ends\nXdut inp inn out vdd 0 ib ldoea\nCl out 0 10p\nVin inp 0 dc 1.2 ac 1\nVfb inn out 0\n.control\nnoise v(out) Vin dec 20 1 1meg\nsetplot noise1\n* 20 points a decade from 1 Hz: point 60 is 1 kHz\nlet vn_1k = inoise_spectrum[60]\nprint vn_1k\nsetplot noise2\nprint inoise_total\n.endc\n.op\n.end" }, { "id": "icmr", "label": "Input common-mode range", "note": "Both inputs swept together while the output is held at one level. The range is where open-loop gain falls by no more than 6 dB and unity-gain frequency by no more than 5 % from their values at the design common mode; increases are allowed.", "measures": [], "metricKeys": [ "icmr_lo", "icmr_hi" ], "acceptance": [ "icmr_lo", "icmr_hi" ], "acceptanceRules": [ { "key": "icmr_lo", "unit": "V", "min": null, "max": 1, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "icmr_hi", "unit": "V", "min": 2.5, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* LDO error amplifier, 3.3 V, level-shifted output - input common-mode range, the output held at one level\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD}\nIb vdd ib 10u\n.subckt ldoea inp inn out vdd vss ib\n* bias: the reference into an NMOS diode, and copies of it\nXMB ib ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=1\nXMT tail ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=2\n* first stage: an NMOS pair on a PMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1\nXM2 d2 inp tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1\nXM3 d1 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1\nXM4 d2 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1\n* level shifter: a PMOS diode on d2, its n-well on d2, carries MLN's current,\n* so ls sits a V_SG below d2; MLD draws the same current from d1, so the pair\n* stays balanced\nXMLS ls ls d2 d2 sg13_hv_pmos w=4.5u l=1u ng=1 m=1\nXMLN ls ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1\nXMLD d1 ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1\n* output stage: a common-source PMOS driven hard from ls, against an NMOS sink\nXMO out ls vdd vdd sg13_hv_pmos w=22u l=2u ng=6 m=1\nXMS out ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=20\n* Miller compensation across the level shifter and the output stage\nXCc d2 cz cap_cmim w=28.814u l=28.814u m=12\nXRz cz out vss rppd w=0.5u l=11.54u\n.ends\nXdut inp inn out vdd 0 ib ldoea\nCl out 0 10p\nVin inp 0 dc 1.2 ac 1\nVpark park 0 dc 1.2\n* inn is inp shifted by how far out is from park: the loop holds out at park\n* while both inputs follow inp, and it is closed at DC only, as in the\n* open-loop bench, so each ac sweep sees the open loop\nEfb fb inp out park 1\nLfb fb inn 1t\nCfb inn 0 1t\n.control\n* point 0 is the design common mode, the reference; then every level\nac dec 20 0.1 10g\nmeas ac a0_0 find vdb(out) at=0.1\nmeas ac fu_0 when vdb(out)=0 fall=1\nalter vin dc = 0\nac dec 20 0.1 10g\nmeas ac a0_1 find vdb(out) at=0.1\nmeas ac fu_1 when vdb(out)=0 fall=1\nalter vin dc = 82.5m\nac dec 20 0.1 10g\nmeas ac a0_2 find vdb(out) at=0.1\nmeas ac fu_2 when vdb(out)=0 fall=1\nalter vin dc = 165m\nac dec 20 0.1 10g\nmeas ac a0_3 find vdb(out) at=0.1\nmeas ac fu_3 when vdb(out)=0 fall=1\nalter vin dc = 247.5m\nac dec 20 0.1 10g\nmeas ac a0_4 find vdb(out) at=0.1\nmeas ac fu_4 when vdb(out)=0 fall=1\nalter vin dc = 330m\nac dec 20 0.1 10g\nmeas ac a0_5 find vdb(out) at=0.1\nmeas ac fu_5 when vdb(out)=0 fall=1\nalter vin dc = 412.5m\nac dec 20 0.1 10g\nmeas ac a0_6 find vdb(out) at=0.1\nmeas ac fu_6 when vdb(out)=0 fall=1\nalter vin dc = 495m\nac dec 20 0.1 10g\nmeas ac a0_7 find vdb(out) at=0.1\nmeas ac fu_7 when vdb(out)=0 fall=1\nalter vin dc = 577.5m\nac dec 20 0.1 10g\nmeas ac a0_8 find vdb(out) at=0.1\nmeas ac fu_8 when vdb(out)=0 fall=1\nalter vin dc = 660m\nac dec 20 0.1 10g\nmeas ac a0_9 find vdb(out) at=0.1\nmeas ac fu_9 when vdb(out)=0 fall=1\nalter vin dc = 742.5m\nac dec 20 0.1 10g\nmeas ac a0_10 find vdb(out) at=0.1\nmeas ac fu_10 when vdb(out)=0 fall=1\nalter vin dc = 825m\nac dec 20 0.1 10g\nmeas ac a0_11 find vdb(out) at=0.1\nmeas ac fu_11 when vdb(out)=0 fall=1\nalter vin dc = 907.5m\nac dec 20 0.1 10g\nmeas ac a0_12 find vdb(out) at=0.1\nmeas ac fu_12 when vdb(out)=0 fall=1\nalter vin dc = 990m\nac dec 20 0.1 10g\nmeas ac a0_13 find vdb(out) at=0.1\nmeas ac fu_13 when vdb(out)=0 fall=1\nalter vin dc = 1.0725\nac dec 20 0.1 10g\nmeas ac a0_14 find vdb(out) at=0.1\nmeas ac fu_14 when vdb(out)=0 fall=1\nalter vin dc = 1.155\nac dec 20 0.1 10g\nmeas ac a0_15 find vdb(out) at=0.1\nmeas ac fu_15 when vdb(out)=0 fall=1\nalter vin dc = 1.2375\nac dec 20 0.1 10g\nmeas ac a0_16 find vdb(out) at=0.1\nmeas ac fu_16 when vdb(out)=0 fall=1\nalter vin dc = 1.32\nac dec 20 0.1 10g\nmeas ac a0_17 find vdb(out) at=0.1\nmeas ac fu_17 when vdb(out)=0 fall=1\nalter vin dc = 1.4025\nac dec 20 0.1 10g\nmeas ac a0_18 find vdb(out) at=0.1\nmeas ac fu_18 when vdb(out)=0 fall=1\nalter vin dc = 1.485\nac dec 20 0.1 10g\nmeas ac a0_19 find vdb(out) at=0.1\nmeas ac fu_19 when vdb(out)=0 fall=1\nalter vin dc = 1.5675\nac dec 20 0.1 10g\nmeas ac a0_20 find vdb(out) at=0.1\nmeas ac fu_20 when vdb(out)=0 fall=1\nalter vin dc = 1.65\nac dec 20 0.1 10g\nmeas ac a0_21 find vdb(out) at=0.1\nmeas ac fu_21 when vdb(out)=0 fall=1\nalter vin dc = 1.7325\nac dec 20 0.1 10g\nmeas ac a0_22 find vdb(out) at=0.1\nmeas ac fu_22 when vdb(out)=0 fall=1\nalter vin dc = 1.815\nac dec 20 0.1 10g\nmeas ac a0_23 find vdb(out) at=0.1\nmeas ac fu_23 when vdb(out)=0 fall=1\nalter vin dc = 1.8975\nac dec 20 0.1 10g\nmeas ac a0_24 find vdb(out) at=0.1\nmeas ac fu_24 when vdb(out)=0 fall=1\nalter vin dc = 1.98\nac dec 20 0.1 10g\nmeas ac a0_25 find vdb(out) at=0.1\nmeas ac fu_25 when vdb(out)=0 fall=1\nalter vin dc = 2.0625\nac dec 20 0.1 10g\nmeas ac a0_26 find vdb(out) at=0.1\nmeas ac fu_26 when vdb(out)=0 fall=1\nalter vin dc = 2.145\nac dec 20 0.1 10g\nmeas ac a0_27 find vdb(out) at=0.1\nmeas ac fu_27 when vdb(out)=0 fall=1\nalter vin dc = 2.2275\nac dec 20 0.1 10g\nmeas ac a0_28 find vdb(out) at=0.1\nmeas ac fu_28 when vdb(out)=0 fall=1\nalter vin dc = 2.31\nac dec 20 0.1 10g\nmeas ac a0_29 find vdb(out) at=0.1\nmeas ac fu_29 when vdb(out)=0 fall=1\nalter vin dc = 2.3925\nac dec 20 0.1 10g\nmeas ac a0_30 find vdb(out) at=0.1\nmeas ac fu_30 when vdb(out)=0 fall=1\nalter vin dc = 2.475\nac dec 20 0.1 10g\nmeas ac a0_31 find vdb(out) at=0.1\nmeas ac fu_31 when vdb(out)=0 fall=1\nalter vin dc = 2.5575\nac dec 20 0.1 10g\nmeas ac a0_32 find vdb(out) at=0.1\nmeas ac fu_32 when vdb(out)=0 fall=1\nalter vin dc = 2.64\nac dec 20 0.1 10g\nmeas ac a0_33 find vdb(out) at=0.1\nmeas ac fu_33 when vdb(out)=0 fall=1\nalter vin dc = 2.7225\nac dec 20 0.1 10g\nmeas ac a0_34 find vdb(out) at=0.1\nmeas ac fu_34 when vdb(out)=0 fall=1\nalter vin dc = 2.805\nac dec 20 0.1 10g\nmeas ac a0_35 find vdb(out) at=0.1\nmeas ac fu_35 when vdb(out)=0 fall=1\nalter vin dc = 2.8875\nac dec 20 0.1 10g\nmeas ac a0_36 find vdb(out) at=0.1\nmeas ac fu_36 when vdb(out)=0 fall=1\nalter vin dc = 2.97\nac dec 20 0.1 10g\nmeas ac a0_37 find vdb(out) at=0.1\nmeas ac fu_37 when vdb(out)=0 fall=1\nalter vin dc = 3.0525\nac dec 20 0.1 10g\nmeas ac a0_38 find vdb(out) at=0.1\nmeas ac fu_38 when vdb(out)=0 fall=1\nalter vin dc = 3.135\nac dec 20 0.1 10g\nmeas ac a0_39 find vdb(out) at=0.1\nmeas ac fu_39 when vdb(out)=0 fall=1\nalter vin dc = 3.2175\nac dec 20 0.1 10g\nmeas ac a0_40 find vdb(out) at=0.1\nmeas ac fu_40 when vdb(out)=0 fall=1\nalter vin dc = 3.3\nac dec 20 0.1 10g\nmeas ac a0_41 find vdb(out) at=0.1\nmeas ac fu_41 when vdb(out)=0 fall=1\nalter vin dc = 3.3825\nac dec 20 0.1 10g\nmeas ac a0_42 find vdb(out) at=0.1\nmeas ac fu_42 when vdb(out)=0 fall=1\nalter vin dc = 3.465\nac dec 20 0.1 10g\nmeas ac a0_43 find vdb(out) at=0.1\nmeas ac fu_43 when vdb(out)=0 fall=1\nalter vin dc = 3.5475\nac dec 20 0.1 10g\nmeas ac a0_44 find vdb(out) at=0.1\nmeas ac fu_44 when vdb(out)=0 fall=1\nalter vin dc = 3.63\nac dec 20 0.1 10g\nmeas ac a0_45 find vdb(out) at=0.1\nmeas ac fu_45 when vdb(out)=0 fall=1\n.endc\n.dc Vin 0 3.63 82.5m\n.end" }, { "id": "swing", "label": "Output swing", "note": "The amplifier as an inverting gain of one - its inverting input at the midpoint of the output and a signal, through two ideal controlled sources that load nothing - with the signal swept so the output crosses from rail to rail, and at each level the open-loop gain: the swing is where the gain stays within 6 dB of its value with the output at the input common mode.", "measures": [], "metricKeys": [ "swing_lo", "swing_hi" ], "acceptance": [ "swing_lo", "swing_hi" ], "acceptanceRules": [ { "key": "swing_lo", "unit": "V", "min": null, "max": 0.6, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "swing_hi", "unit": "V", "min": 1.5, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* LDO error amplifier, 3.3 V, level-shifted output - output swing, as an inverting amplifier of gain one\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD}\nIb vdd ib 10u\n.subckt ldoea inp inn out vdd vss ib\n* bias: the reference into an NMOS diode, and copies of it\nXMB ib ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=1\nXMT tail ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=2\n* first stage: an NMOS pair on a PMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1\nXM2 d2 inp tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1\nXM3 d1 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1\nXM4 d2 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1\n* level shifter: a PMOS diode on d2, its n-well on d2, carries MLN's current,\n* so ls sits a V_SG below d2; MLD draws the same current from d1, so the pair\n* stays balanced\nXMLS ls ls d2 d2 sg13_hv_pmos w=4.5u l=1u ng=1 m=1\nXMLN ls ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1\nXMLD d1 ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1\n* output stage: a common-source PMOS driven hard from ls, against an NMOS sink\nXMO out ls vdd vdd sg13_hv_pmos w=22u l=2u ng=6 m=1\nXMS out ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=20\n* Miller compensation across the level shifter and the output stage\nXCc d2 cz cap_cmim w=28.814u l=28.814u m=12\nXRz cz out vss rppd w=0.5u l=11.54u\n.ends\nXdut inp inn out vdd 0 ib ldoea\nCl out 0 10p\nVcm inp 0 dc 1.2 ac 1\nVsig sig 0 dc 1.2\n* inn is the midpoint of out and sig: v(out) = 2 V_CM - v(sig). Closed at DC\n* only, so each ac sweep reads the open-loop gain at that output level\nE1 fbn mid out 0 0.5\nE2 mid 0 sig 0 0.5\nLfb fbn inn 1t\nCfb inn 0 1t\n.control\n* point 0 has the output at the input common mode, the reference\nac dec 1 0.1 1\nmeas ac a0_0 find vdb(out) at=0.1\nalter vsig dc = 2.4\nac dec 1 0.1 1\nmeas ac a0_1 find vdb(out) at=0.1\nalter vsig dc = 2.3175\nac dec 1 0.1 1\nmeas ac a0_2 find vdb(out) at=0.1\nalter vsig dc = 2.235\nac dec 1 0.1 1\nmeas ac a0_3 find vdb(out) at=0.1\nalter vsig dc = 2.1525\nac dec 1 0.1 1\nmeas ac a0_4 find vdb(out) at=0.1\nalter vsig dc = 2.07\nac dec 1 0.1 1\nmeas ac a0_5 find vdb(out) at=0.1\nalter vsig dc = 1.9875\nac dec 1 0.1 1\nmeas ac a0_6 find vdb(out) at=0.1\nalter vsig dc = 1.905\nac dec 1 0.1 1\nmeas ac a0_7 find vdb(out) at=0.1\nalter vsig dc = 1.8225\nac dec 1 0.1 1\nmeas ac a0_8 find vdb(out) at=0.1\nalter vsig dc = 1.74\nac dec 1 0.1 1\nmeas ac a0_9 find vdb(out) at=0.1\nalter vsig dc = 1.6575\nac dec 1 0.1 1\nmeas ac a0_10 find vdb(out) at=0.1\nalter vsig dc = 1.575\nac dec 1 0.1 1\nmeas ac a0_11 find vdb(out) at=0.1\nalter vsig dc = 1.4925\nac dec 1 0.1 1\nmeas ac a0_12 find vdb(out) at=0.1\nalter vsig dc = 1.41\nac dec 1 0.1 1\nmeas ac a0_13 find vdb(out) at=0.1\nalter vsig dc = 1.3275\nac dec 1 0.1 1\nmeas ac a0_14 find vdb(out) at=0.1\nalter vsig dc = 1.245\nac dec 1 0.1 1\nmeas ac a0_15 find vdb(out) at=0.1\nalter vsig dc = 1.1625\nac dec 1 0.1 1\nmeas ac a0_16 find vdb(out) at=0.1\nalter vsig dc = 1.08\nac dec 1 0.1 1\nmeas ac a0_17 find vdb(out) at=0.1\nalter vsig dc = 997.5m\nac dec 1 0.1 1\nmeas ac a0_18 find vdb(out) at=0.1\nalter vsig dc = 915m\nac dec 1 0.1 1\nmeas ac a0_19 find vdb(out) at=0.1\nalter vsig dc = 832.5m\nac dec 1 0.1 1\nmeas ac a0_20 find vdb(out) at=0.1\nalter vsig dc = 750m\nac dec 1 0.1 1\nmeas ac a0_21 find vdb(out) at=0.1\nalter vsig dc = 667.5m\nac dec 1 0.1 1\nmeas ac a0_22 find vdb(out) at=0.1\nalter vsig dc = 585m\nac dec 1 0.1 1\nmeas ac a0_23 find vdb(out) at=0.1\nalter vsig dc = 502.5m\nac dec 1 0.1 1\nmeas ac a0_24 find vdb(out) at=0.1\nalter vsig dc = 420m\nac dec 1 0.1 1\nmeas ac a0_25 find vdb(out) at=0.1\nalter vsig dc = 337.5m\nac dec 1 0.1 1\nmeas ac a0_26 find vdb(out) at=0.1\nalter vsig dc = 255m\nac dec 1 0.1 1\nmeas ac a0_27 find vdb(out) at=0.1\nalter vsig dc = 172.5m\nac dec 1 0.1 1\nmeas ac a0_28 find vdb(out) at=0.1\nalter vsig dc = 90m\nac dec 1 0.1 1\nmeas ac a0_29 find vdb(out) at=0.1\nalter vsig dc = 7.5m\nac dec 1 0.1 1\nmeas ac a0_30 find vdb(out) at=0.1\nalter vsig dc = -75m\nac dec 1 0.1 1\nmeas ac a0_31 find vdb(out) at=0.1\nalter vsig dc = -157.5m\nac dec 1 0.1 1\nmeas ac a0_32 find vdb(out) at=0.1\nalter vsig dc = -240m\nac dec 1 0.1 1\nmeas ac a0_33 find vdb(out) at=0.1\nalter vsig dc = -322.5m\nac dec 1 0.1 1\nmeas ac a0_34 find vdb(out) at=0.1\nalter vsig dc = -405m\nac dec 1 0.1 1\nmeas ac a0_35 find vdb(out) at=0.1\nalter vsig dc = -487.5m\nac dec 1 0.1 1\nmeas ac a0_36 find vdb(out) at=0.1\nalter vsig dc = -570m\nac dec 1 0.1 1\nmeas ac a0_37 find vdb(out) at=0.1\nalter vsig dc = -652.5m\nac dec 1 0.1 1\nmeas ac a0_38 find vdb(out) at=0.1\nalter vsig dc = -735m\nac dec 1 0.1 1\nmeas ac a0_39 find vdb(out) at=0.1\nalter vsig dc = -817.5m\nac dec 1 0.1 1\nmeas ac a0_40 find vdb(out) at=0.1\nalter vsig dc = -900m\nac dec 1 0.1 1\nmeas ac a0_41 find vdb(out) at=0.1\n.endc\n.dc Vsig -900m 2.4 82.5m\n.end" } ], "measurements": { "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.0003 } }, "vos": { "label": "Systematic offset", "unit": "V", "spec": { "min": -0.002, "max": 0.002 } }, "dc_gain_db": { "label": "DC open-loop gain", "unit": "dB", "spec": { "min": 70, "max": null } }, "ugf_hz": { "label": "Unity-gain frequency", "unit": "Hz", "spec": { "min": 1200000, "max": null } }, "pm_deg": { "label": "Phase margin", "unit": "deg", "spec": { "min": 70, "max": null } }, "t_settle": { "label": "Settling time, 1 %", "unit": "s", "spec": { "min": null, "max": 7e-7 } }, "t_settle_fall": { "label": "Settling time, 1 %, falling", "unit": "s", "spec": { "min": null, "max": 7e-7 } }, "psrr_db": { "label": "Supply rejection at 1 kHz", "unit": "dB", "spec": { "min": 55, "max": null } }, "cmrr_db": { "label": "Common-mode rejection at 1 kHz", "unit": "dB", "spec": { "min": 65, "max": null } }, "icmr_lo": { "label": "Lowest input common mode", "unit": "V", "spec": { "min": null, "max": 1 } }, "icmr_hi": { "label": "Highest input common mode", "unit": "V", "spec": { "min": 2.5, "max": null } }, "swing_lo": { "label": "Lowest output", "unit": "V", "spec": { "min": null, "max": 0.6 } }, "swing_hi": { "label": "Highest output", "unit": "V", "spec": { "min": 1.5, "max": null } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "cf2f6475cf00d4560414a31730b0cb28f0c5a00b2b3a36e8bd144ed55308ddfc" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ldo-error-amp-3v3.js", "sha256": "1d0fef55d60f1ad62a41b830a463b3db000b26290d9dfb0c2a8705dff1f3e874" }, "simulationFingerprints": { "op": "79df24ec8952ff3184e22832b27b92046ac51da2e65fa0da5d590a6bf91b4337", "open_loop": "24f13782f45a4185987d1f07c6d10a7077a90d6ea39b9176dbe0bd9c6ae273d3", "step": "5cd65a673b9269745fec4ebd6b361e1346f4b8eba5c994c344c4d0361e15682b", "psrr": "5f3b880e703e4219ce8b1892e3437fe4e1c20cb4f089f2b8244dda7ec046c134", "cmrr": "ed45ae89a32c6ec751c96ab6d0a3d8ae74a1a0fac0d7174932bfb04d29c57f84", "noise": "f9c994b13314eb12f92807f35dad480897616fda394befee2b420796a499ab76", "icmr": "d200526f32fe7ffd23867da49b4273977a531a8be00ba24dce1d657291ab09bf", "swing": "04bb4b350ddea0324aae33eb9d6f6559d398c1a42b56de8f02551de4f2c0e265" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "073d6847c74215c6d1a7d2fbbc1b64363b3a20fd53d5c5ab486454967e2dfa08", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ldo-error-amp-3v3", "parameters": { "Ib": 0.00001, "Wn": 0.000024, "Ln": 0.000006, "N": 20, "W1": 0.0002, "L1": 0.000005, "Wm": 0.000072, "Lm": 0.0000055, "Wt": 0.000048, "Lt": 0.000012, "Wls": 0.0000045, "Lls": 0.000001, "Wo": 0.000022, "Lo": 0.000002, "Cc": 1.5e-11, "Rz": 6000, "CL": 1e-11, "VCM": 1.2 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ldo-error-amp-3v3/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=3.3" ], "scopes": [ { "id": "dut", "name": "ldoea", "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=2", 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"d2" }, { "id": "b", "net": "d2" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLN", "displayName": "MLN", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=48u l=12u ng=10 m=1", "source": "XMLN ls ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1", "pins": [ { "id": "d", "net": "ls" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLD", "displayName": "MLD", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=48u l=12u ng=10 m=1", "source": "XMLD d1 ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO", "displayName": "MO", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=22u l=2u ng=6 m=1", "source": "XMO out ls vdd vdd sg13_hv_pmos w=22u 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"voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XMLD", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XMLS", "pin": "s" }, { "device": "XMLS", "pin": "b" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMO", "pin": "s" }, { "device": "XMO", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "ls", "ground": false, "terminals": [ { "device": "XMLS", "pin": "d" }, { "device": "XMLS", "pin": "g" }, { "device": "XMLN", "pin": "d" }, { "device": "XMO", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMO", "pin": "d" }, { "device": "XMS", "pin": "d" }, { "device": "XRz", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "cz", "ground": false, "terminals": [ { "device": "XCc", "pin": "n" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=3.3" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=3.3" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib vdd ib 10u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldoea", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ldoea", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldoea" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.2", "source": "Vin inp 0 dc 1.2", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ldoea", "name": "ldoea", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=2", "source": "XMT tail ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=200u l=5u ng=40 m=1", "source": "XM1 d1 inn tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=200u l=5u ng=40 m=1", "source": "XM2 d2 inp tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=72u l=5.5u ng=16 m=1", "source": "XM3 d1 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=72u l=5.5u ng=16 m=1", "source": "XM4 d2 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLS", "displayName": "MLS", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=4.5u l=1u ng=1 m=1", "source": "XMLS ls ls d2 d2 sg13_hv_pmos w=4.5u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "ls" }, { "id": "g", "net": "ls" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "d2" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLN", "displayName": "MLN", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=48u l=12u ng=10 m=1", "source": "XMLN ls ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1", "pins": [ { "id": "d", "net": "ls" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLD", "displayName": "MLD", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=48u l=12u ng=10 m=1", "source": "XMLD d1 ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO", "displayName": "MO", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=22u l=2u ng=6 m=1", "source": "XMO out ls vdd vdd sg13_hv_pmos w=22u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ls" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS", "displayName": "MS", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=20", "source": "XMS out ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=20", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=12", "source": "XCc d2 cz cap_cmim w=28.814u l=28.814u m=12", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "cz" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRz cz out vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", 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"id": "g", "net": "ls" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "d2" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLN", "displayName": "MLN", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=48u l=12u ng=10 m=1", "source": "XMLN ls ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1", "pins": [ { "id": "d", "net": "ls" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLD", "displayName": "MLD", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=48u l=12u ng=10 m=1", "source": "XMLD d1 ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO", "displayName": "MO", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=22u l=2u ng=6 m=1", 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PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=3.3" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=3.3" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib vdd ib 10u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldoea", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ldoea", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldoea" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "pulse(1.1 1.3 1u 1n 1n 5u 20u)", "source": "Vin inp 0 pulse(1.1 1.3 1u 1n 1n 5u 20u)", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ldoea", "name": "ldoea", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=2", "source": "XMT tail ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=200u l=5u ng=40 m=1", "source": "XM1 d1 inn tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=200u l=5u ng=40 m=1", "source": "XM2 d2 inp tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=72u l=5.5u ng=16 m=1", "source": "XM3 d1 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=72u l=5.5u ng=16 m=1", "source": "XM4 d2 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLS", "displayName": "MLS", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=4.5u l=1u ng=1 m=1", "source": "XMLS ls ls d2 d2 sg13_hv_pmos w=4.5u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "ls" }, { "id": "g", "net": "ls" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "d2" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLN", "displayName": "MLN", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=48u l=12u ng=10 m=1", "source": "XMLN ls ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1", "pins": [ { "id": "d", "net": "ls" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLD", "displayName": "MLD", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=48u l=12u ng=10 m=1", "source": "XMLD d1 ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO", "displayName": "MO", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=22u l=2u ng=6 m=1", "source": "XMO out ls vdd vdd sg13_hv_pmos w=22u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ls" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS", "displayName": "MS", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=20", "source": "XMS out ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=20", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=12", "source": "XCc d2 cz cap_cmim w=28.814u l=28.814u m=12", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "cz" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRz cz out vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMLN", "pin": "g" }, { "device": "XMLD", "pin": "g" }, { "device": "XMS", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XMLN", "pin": "s" }, { "device": "XMLN", "pin": "b" }, { "device": "XMLD", "pin": "s" }, { "device": "XMLD", "pin": "b" }, { "device": "XMS", "pin": "s" }, { "device": "XMS", "pin": "b" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XMLD", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XMLS", "pin": "s" }, { "device": "XMLS", "pin": "b" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMO", "pin": "s" }, { "device": "XMO", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "ls", "ground": false, "terminals": [ { "device": "XMLS", "pin": "d" }, { "device": "XMLS", "pin": "g" }, { "device": "XMLN", "pin": "d" }, { "device": "XMO", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMO", "pin": "d" }, { "device": "XMS", "pin": "d" }, { "device": "XRz", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "cz", "ground": false, "terminals": [ { "device": "XCc", "pin": "n" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldoea" } }, { "id": "graph-6", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=3.3" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=3.3" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD} ac 1", "source": "Vdd vdd 0 dc {VDD} ac 1", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib vdd ib 10u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldoea", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ldoea", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldoea" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.2", "source": "Vin inp 0 dc 1.2", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ldoea", "name": "ldoea", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=2", "source": "XMT tail ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=200u l=5u ng=40 m=1", "source": "XM1 d1 inn tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=200u l=5u ng=40 m=1", "source": "XM2 d2 inp tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=72u l=5.5u ng=16 m=1", "source": "XM3 d1 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=72u l=5.5u ng=16 m=1", "source": "XM4 d2 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLS", "displayName": "MLS", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=4.5u l=1u ng=1 m=1", "source": "XMLS ls ls d2 d2 sg13_hv_pmos w=4.5u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "ls" }, { "id": "g", "net": "ls" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "d2" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLN", "displayName": "MLN", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=48u l=12u ng=10 m=1", "source": "XMLN ls ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1", "pins": [ { "id": "d", "net": "ls" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLD", "displayName": "MLD", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=48u l=12u ng=10 m=1", "source": "XMLD d1 ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO", "displayName": "MO", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=22u l=2u ng=6 m=1", "source": "XMO out ls vdd vdd sg13_hv_pmos w=22u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ls" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS", "displayName": "MS", "spiceType": "X", "model": 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"voltageReferences": [] }, { "id": "ls", "ground": false, "terminals": [ { "device": "XMLS", "pin": "d" }, { "device": "XMLS", "pin": "g" }, { "device": "XMLN", "pin": "d" }, { "device": "XMO", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMO", "pin": "d" }, { "device": "XMS", "pin": "d" }, { "device": "XRz", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "cz", "ground": false, "terminals": [ { "device": "XCc", "pin": "n" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldoea" } }, { "id": "graph-7", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. 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{ "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldoea" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vsrc", "displayName": "Vsrc", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.2", "source": "Vsrc src 0 dc 1.2", "pins": [ { "id": "p", "net": "src" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Va", "displayName": "Va", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Va inp src dc 0 ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "src" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vb", "displayName": "Vb", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Vb 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[], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "src", "ground": false, "terminals": [ { "device": "Vsrc", "pin": "p" }, { "device": "Va", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ldoea", "name": "ldoea", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, 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"displayName": "MO", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=22u l=2u ng=6 m=1", "source": "XMO out ls vdd vdd sg13_hv_pmos w=22u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ls" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS", "displayName": "MS", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=20", "source": "XMS out ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=20", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=12", "source": "XCc d2 cz cap_cmim w=28.814u l=28.814u m=12", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "cz" } ], "pinMeaning": "IHP MIM model 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"voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldoea" } }, { "id": "graph-8", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=3.3" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=3.3" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib vdd ib 10u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldoea", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ldoea", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldoea" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.2 ac 1", "source": "Vin inp 0 dc 1.2 ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ldoea", "name": "ldoea", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=2", "source": "XMT tail ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=200u l=5u ng=40 m=1", "source": "XM1 d1 inn tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=200u l=5u ng=40 m=1", "source": "XM2 d2 inp tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=72u l=5.5u ng=16 m=1", "source": "XM3 d1 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=72u l=5.5u ng=16 m=1", "source": "XM4 d2 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLS", "displayName": "MLS", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=4.5u l=1u ng=1 m=1", "source": "XMLS ls ls d2 d2 sg13_hv_pmos w=4.5u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "ls" }, { "id": "g", "net": "ls" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "d2" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLN", "displayName": "MLN", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=48u l=12u ng=10 m=1", "source": "XMLN ls ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1", "pins": [ { "id": "d", "net": "ls" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLD", "displayName": "MLD", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=48u l=12u ng=10 m=1", "source": "XMLD d1 ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO", "displayName": "MO", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=22u l=2u ng=6 m=1", "source": "XMO out ls vdd vdd sg13_hv_pmos w=22u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ls" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS", "displayName": "MS", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=20", "source": "XMS out ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=20", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=12", "source": "XCc d2 cz cap_cmim w=28.814u l=28.814u m=12", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "cz" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRz cz out vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMLN", "pin": "g" }, { "device": "XMLD", "pin": "g" }, { "device": "XMS", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XMLN", "pin": "s" }, { "device": "XMLN", "pin": "b" }, { "device": "XMLD", "pin": "s" }, { "device": "XMLD", "pin": "b" }, { "device": "XMS", "pin": "s" }, { "device": "XMS", "pin": "b" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XMLD", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XMLS", "pin": "s" }, { "device": "XMLS", "pin": "b" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMO", "pin": "s" }, { "device": "XMO", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "ls", "ground": false, "terminals": [ { "device": "XMLS", "pin": "d" }, { "device": "XMLS", "pin": "g" }, { "device": "XMLN", "pin": "d" }, { "device": "XMO", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMO", "pin": "d" }, { "device": "XMS", "pin": "d" }, { "device": "XRz", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "cz", "ground": false, "terminals": [ { "device": "XCc", "pin": "n" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldoea" } }, { "id": "graph-9", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=3.3" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=3.3" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib vdd ib 10u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldoea", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ldoea", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldoea" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.2 ac 1", "source": "Vin inp 0 dc 1.2 ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vpark", "displayName": "Vpark", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.2", "source": "Vpark park 0 dc 1.2", "pins": [ { "id": "p", "net": "park" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efb", "displayName": "Efb", "spiceType": "E", "model": null, "parametersOrValue": "1", "source": "Efb fb inp out park 1", "pins": [ { "id": "p", "net": "fb" }, { "id": "n", "net": "inp" }, { "id": "cp", "net": "out" }, { "id": "cn", "net": "park" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfb", "displayName": "Lfb", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfb fb inn 1t", "pins": [ { "id": "p", "net": "fb" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cfb", "displayName": "Cfb", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cfb inn 0 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" }, { "device": "Vpark", "pin": "n" }, { "device": "Cfb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" }, { "device": "Efb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Lfb", "pin": "n" }, { "device": "Cfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Efb", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "park", "ground": false, "terminals": [ { "device": "Vpark", "pin": "p" }, { "device": "Efb", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "fb", "ground": false, "terminals": [ { "device": "Efb", "pin": "p" }, { "device": "Lfb", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ldoea", "name": "ldoea", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=2", "source": "XMT tail ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=200u l=5u ng=40 m=1", "source": "XM1 d1 inn tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=200u l=5u ng=40 m=1", "source": "XM2 d2 inp tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=72u l=5.5u ng=16 m=1", "source": "XM3 d1 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=72u l=5.5u ng=16 m=1", "source": "XM4 d2 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLS", "displayName": "MLS", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=4.5u l=1u ng=1 m=1", "source": "XMLS ls ls d2 d2 sg13_hv_pmos w=4.5u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "ls" }, { "id": "g", "net": "ls" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "d2" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLN", "displayName": "MLN", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=48u l=12u ng=10 m=1", "source": "XMLN ls ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1", "pins": [ { "id": "d", "net": "ls" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLD", "displayName": "MLD", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=48u l=12u ng=10 m=1", "source": "XMLD d1 ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO", "displayName": "MO", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=22u l=2u ng=6 m=1", "source": "XMO out ls vdd vdd sg13_hv_pmos w=22u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ls" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS", "displayName": "MS", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=20", "source": "XMS out ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=20", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=12", "source": "XCc d2 cz cap_cmim w=28.814u l=28.814u m=12", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "cz" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRz cz out vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMLN", "pin": "g" }, { "device": "XMLD", "pin": "g" }, { "device": "XMS", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XMLN", "pin": "s" }, { "device": "XMLN", "pin": "b" }, { "device": "XMLD", "pin": "s" }, { "device": "XMLD", "pin": "b" }, { "device": "XMS", "pin": "s" }, { "device": "XMS", "pin": "b" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XMLD", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XMLS", "pin": "s" }, { "device": "XMLS", "pin": "b" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMO", "pin": "s" }, { "device": "XMO", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "ls", "ground": false, "terminals": [ { "device": "XMLS", "pin": "d" }, { "device": "XMLS", "pin": "g" }, { "device": "XMLN", "pin": "d" }, { "device": "XMO", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMO", "pin": "d" }, { "device": "XMS", "pin": "d" }, { "device": "XRz", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "cz", "ground": false, "terminals": [ { "device": "XCc", "pin": "n" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldoea" } }, { "id": "graph-10", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=3.3" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=3.3" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib vdd ib 10u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldoea", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ldoea", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldoea" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vcm", "displayName": "Vcm", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.2 ac 1", "source": "Vcm inp 0 dc 1.2 ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vsig", "displayName": "Vsig", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.2", "source": "Vsig sig 0 dc 1.2", "pins": [ { "id": "p", "net": "sig" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "E1", "displayName": "E1", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "E1 fbn mid out 0 0.5", "pins": [ { "id": "p", "net": "fbn" }, { "id": "n", "net": "mid" }, { "id": "cp", "net": "out" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "E2", "displayName": "E2", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "E2 mid 0 sig 0 0.5", "pins": [ { "id": "p", "net": "mid" }, { "id": "n", "net": "0" }, { "id": "cp", "net": "sig" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfb", "displayName": "Lfb", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfb fbn inn 1t", "pins": [ { "id": "p", "net": "fbn" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cfb", "displayName": "Cfb", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cfb inn 0 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vcm", "pin": "n" }, { "device": "Vsig", "pin": "n" }, { "device": "E1", "pin": "cn" }, { "device": "E2", "pin": "n" }, { "device": "E2", "pin": "cn" }, { "device": "Cfb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vcm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Lfb", "pin": "n" }, { "device": "Cfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "E1", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "sig", "ground": false, "terminals": [ { "device": "Vsig", "pin": "p" }, { "device": "E2", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "fbn", "ground": false, "terminals": [ { "device": "E1", "pin": "p" }, { "device": "Lfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "mid", "ground": false, "terminals": [ { "device": "E1", "pin": "n" }, { "device": "E2", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ldoea", "name": "ldoea", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=2", "source": "XMT tail ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=200u l=5u ng=40 m=1", "source": "XM1 d1 inn tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=200u l=5u ng=40 m=1", "source": "XM2 d2 inp tail vss sg13_hv_nmos w=200u l=5u ng=40 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=72u l=5.5u ng=16 m=1", "source": "XM3 d1 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=72u l=5.5u ng=16 m=1", "source": "XM4 d2 d1 vdd vdd sg13_hv_pmos w=72u l=5.5u ng=16 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLS", "displayName": "MLS", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=4.5u l=1u ng=1 m=1", "source": "XMLS ls ls d2 d2 sg13_hv_pmos w=4.5u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "ls" }, { "id": "g", "net": "ls" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "d2" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLN", "displayName": "MLN", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=48u l=12u ng=10 m=1", "source": "XMLN ls ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1", "pins": [ { "id": "d", "net": "ls" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMLD", "displayName": "MLD", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=48u l=12u ng=10 m=1", "source": "XMLD d1 ib vss vss sg13_hv_nmos w=48u l=12u ng=10 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMO", "displayName": "MO", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=22u l=2u ng=6 m=1", "source": "XMO out ls vdd vdd sg13_hv_pmos w=22u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ls" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS", "displayName": "MS", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=24u l=6u ng=6 m=20", "source": "XMS out ib vss vss sg13_hv_nmos w=24u l=6u ng=6 m=20", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=12", "source": "XCc d2 cz cap_cmim w=28.814u l=28.814u m=12", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "cz" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRz cz out vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMLN", "pin": "g" }, { "device": "XMLD", "pin": "g" }, { "device": "XMS", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", 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