{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ldo-fc-hv", "name": "Folded-cascode LDO, 2.8 V from 3.3 V", "group": "Voltage regulators", "subgroup": "LDOs", "title": "Folded-cascode LDO, 2.8 V from 3.3 V", "summary": "Regulates a 3.3 V input down to about 2.8 V. A folded-cascode amplifier compares the output directly with a reference and drives a PMOS pass transistor. Its input range supports this high output voltage; small remaining headroom limits full-load regulation.", "reference": { "kind": "paper", "authors": "Z. Li, A. Chan Carusone", "title": "Design and Optimization of Low-Dropout Voltage Regulator Using Relational Graph Neural Network and Reinforcement Learning in Open-Source SKY130 Process", "year": 2023, "where": "2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 1-9", "doi": "10.1109/ICCAD57390.2023.10323720", "takes": "The topology: a folded-cascode error amplifier with an NMOS input pair and PMOS cascodes, unity feedback, a PMOS pass device compensated by a Miller capacitor with a series resistor, and a bleed. Its bias is referenced to one current, the cascodes' gate made inside; the sizing, the 2.8 V output and the specs are this library's, on SG13G2's 3.3 V devices." }, "resources": { "record": "/circuits/ldo-fc-hv.json", "page": "/index.html#ldo-fc-hv", "achieved": "/achieved/ldo-fc-hv.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_hv_tt.spice", "url": "/sg13g2_hv_tt.spice", "sha256": "e9b858ad4f7bba550467f1eddb6ca496bcc5f4644474f41240d63927934928ad" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "ref", "kind": "input", "note": "the reference voltage, which the output copies" }, { "name": "sense", "kind": "input", "note": "the output as the regulator reads it" }, { "name": "out", "kind": "output" }, { "name": "vdd", "kind": "supply", "note": "the unregulated 3.3 V input" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the bias current, driven into this pin" } ], "devices": [ { "name": "MB", "type": "nmos", "model": "sg13_hv_nmos", "nodes": "ib ib vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "bias reference, diode-connected", "fingers": 2, "copies": 1 }, { "name": "MT", "type": "nmos", "model": "sg13_hv_nmos", "nodes": "tail ib vss vss", "sizedBy": [ "Wn", "Ln", "N" ], "role": "tail, N copies of MB", "fingers": 2, "copies": 8 }, { "name": "M9", "type": "nmos", "model": "sg13_hv_nmos", "nodes": "mir ib vss vss", "sizedBy": [ "Wn", "Ln", "K" ], "role": "sink under the diode-side cascode, K copies of MB", "fingers": 2, "copies": 4 }, { "name": "M10", "type": "nmos", "model": "sg13_hv_nmos", "nodes": "gate ib vss vss", "sizedBy": [ "Wn", "Ln", "K" ], "role": "sink under the output cascode, K copies of MB", "fingers": 2, "copies": 4 }, { "name": "MB2", "type": "nmos", "model": "sg13_hv_nmos", "nodes": "vbc ib vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "a copy of Ib for the cascode bias", "fingers": 2, "copies": 1 }, { "name": "MBC", "type": "pmos", "model": "sg13_hv_pmos", "nodes": "vbc vbc vdd vdd", "sizedBy": [ "Wc", "Lc" ], "role": "cascode bias, diode-connected", "fingers": 1, "copies": 1 }, { "name": "M1", "type": "nmos", "model": "sg13_hv_nmos", "nodes": "f1 sense tail vss", "sizedBy": [ "W1", "L1" ], "role": "input pair, the output", "fingers": 8, "copies": 1 }, { "name": "M2", "type": "nmos", "model": "sg13_hv_nmos", "nodes": "f2 ref tail vss", "sizedBy": [ "W1", "L1" ], "role": "input pair, the reference", "fingers": 8, "copies": 1 }, { "name": "M5", "type": "pmos", "model": "sg13_hv_pmos", "nodes": "f1 mir vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "top mirror, diode side through M7", "fingers": 40, "copies": 1 }, { "name": "M6", "type": "pmos", "model": "sg13_hv_pmos", "nodes": "f2 mir vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "top mirror, output side", "fingers": 40, "copies": 1 }, { "name": "M7", "type": "pmos", "model": "sg13_hv_pmos", "nodes": "mir vbc f1 vdd", "sizedBy": [ "Wk", "Lk" ], "role": "cascode, diode side", "fingers": 20, "copies": 1 }, { "name": "M8", "type": "pmos", "model": "sg13_hv_pmos", "nodes": "gate vbc f2 vdd", "sizedBy": [ "Wk", "Lk" ], "role": "cascode, output side", "fingers": 20, "copies": 1 }, { "name": "MP", "type": "pmos", "model": "sg13_hv_pmos", "nodes": "out gate vdd vdd", "sizedBy": [ "Wpass", "Lpass" ], "role": "pass device", "fingers": 240, "copies": 1 }, { "name": "Rb", "type": "resistor", "nodes": "out vss", "sizedBy": [ "Rb" ], "role": "bleed: the least MP always carries" }, { "name": "Rz", "type": "resistor", "nodes": "gate cz", "sizedBy": [ "Rz" ], "role": "zero resistor, in series with Cc" }, { "name": "Cc", "type": "capacitor", "nodes": "cz out", "sizedBy": [ "Cc" ], "role": "Miller capacitor across the pass device" } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "The input pair: any difference between them is an offset, and with unity feedback it is the output's error one for one." }, { "rule": "match", "of": [ "M5", "M6" ], "why": "The top mirror turns M1's current round onto the output side; a mismatch is offset." }, { "rule": "match", "of": [ "M9", "M10" ], "why": "The sinks under the two folded branches: a difference between them is a difference the mirror cannot tell from signal." }, { "rule": "unit-copies", "of": [ "MB", "MT", "M9", "M10", "MB2" ], "constraint": "MT = N, M9 = M10 = K copies of MB", "why": "The tail and sinks copy an externally supplied Ib. Their nominal ratios track across corners; finite output resistance and mismatch still cause variation." }, { "rule": "rating", "of": [ "MP", "M1", "M2", "M5", "M6", "M7", "M8" ], "constraint": "3.3 V devices throughout", "why": "The input is the 3.3 V I/O supply; every node can reach it." }, { "rule": "input-range", "of": [ "M1", "M2", "M5", "M6" ], "constraint": "input common mode at 2.8 V, with M1 and M2 saturated at a 2.97 V input", "why": "The pair's drains fold into M5 and M6 just under the supply, so the pair keeps more than 0.8 V across it with its gates at the output. A five-transistor amplifier's pair would have only its load's V_SG of room and fall into triode." }, { "rule": "output-stack", "of": [ "M6", "M8", "MBC", "MP" ], "constraint": "V_DSAT,M6 + V_DSAT,M8 below V_SG,MP at no load, about 0.6 V", "why": "With no load the gate sits one small V_SG under the supply, and the output branch has two devices between them. Both run in weak inversion, and MBC sets the cascodes' gate so M5, M6 keep about 0.25 V: set higher, M5 and M6 fall into triode; lower, M7 and M8 do." }, { "rule": "zero", "of": [ "Rz", "MP", "M2" ], "constraint": "1/g_m,MP at no load < Rz < 1/g_m2", "why": "The zero Cc makes is in the left half-plane at every load, and the loop gain above it stays under 0 dB." } ], "specs": [ { "key": "vout", "label": "Output voltage", "unit": "V", "direction": "target", "constraint": ">= 2.75 V, <= 2.85 V", "min": 2.75, "max": 2.85, "why": "The 2.8 V reference, copied: the amplifier's offset and finite gain are the only error." }, { "key": "i_q", "label": "Quiescent current", "unit": "A", "direction": "min", "constraint": "<= 0.00035 A", "min": null, "max": 0.00035, "why": "The folded cascode's tail and sinks, the top mirror that carries both, and the 140 µA bleed." }, { "key": "load_reg", "label": "Load regulation", "unit": "V/A", "direction": "min", "constraint": "<= 1.5 V/A", "min": null, "max": 1.5, "why": "At most 15 mV from no load to 10 mA." }, { "key": "line_reg", "label": "Line regulation", "unit": "%/V", "direction": "min", "constraint": "<= 0.2 %/V", "min": null, "max": 0.2, "why": "At most 3.7 mV across the rated 2.97 to 3.63 V input - including its bottom, where only 0.17 V is left across the pass device." }, { "key": "dropout", "label": "Dropout at full load", "unit": "V", "direction": "min", "constraint": "<= 0.15 V", "min": null, "max": 0.15, "why": "Below the 0.17 V between the output and the lowest rated input, so the regulator still regulates there at 10 mA." }, { "key": "loop_gain_db", "label": "DC loop gain at full load", "unit": "dB", "direction": "max", "constraint": ">= 25 dB", "min": 25, "max": null, "why": "Lowest at full load and the lowest input, where the pass device runs in triode with 0.17 V across it." }, { "key": "loop_ugf_hz", "label": "Loop crossover at full load", "unit": "Hz", "direction": "max", "constraint": ">= 200000 Hz", "min": 200000, "max": null, "why": "Set by g_m2 over Cc; lowest at the slow, hot, low-input corner." }, { "key": "loop_pm_deg", "label": "Loop phase margin, worst load", "unit": "deg", "direction": "max", "constraint": ">= 60 deg", "min": 60, "max": null, "why": "At every load; the output pole is lowest at no load." }, { "key": "ring_pct", "label": "Ringing after a kick, worst load", "unit": "%", "direction": "min", "constraint": "<= 5 %", "min": null, "max": 5, "why": "No load of the range may leave the output ringing after a small step." }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 25 dB", "min": 25, "max": null, "why": "At 1 kHz; lowest at the bottom of the input range, with the pass device in triode." }, { "key": "undershoot", "label": "Undershoot on the load step", "unit": "V", "direction": "min", "constraint": "<= 0.16 V", "min": null, "max": 0.16, "why": "For a 0 to 10 mA step in 1 µs on 100 pF." }, { "key": "overshoot", "label": "Overshoot on the load release", "unit": "V", "direction": "min", "constraint": "<= 0.22 V", "min": null, "max": 0.22, "why": "For the release in 1 µs." }, { "key": "t_recover", "label": "Settling after the load step", "unit": "s", "direction": "min", "constraint": "<= 0.000003 s", "min": null, "max": 0.000003, "why": "Back within 1 % after the step." }, { "key": "t_release", "label": "Settling after the load release", "unit": "s", "direction": "min", "constraint": "<= 0.000003 s", "min": null, "max": 0.000003, "why": "Back within 1 % after the release, at no load." }, { "key": "line_step", "label": "Output step for an input step", "unit": "V", "direction": "min", "constraint": "<= 0.18 V", "min": null, "max": 0.18, "why": "For the input stepped across its whole rated range in 1 µs at full load: the gate must follow the input through a high-resistance node." }, { "key": "vn_out", "label": "Output noise, 10 Hz to 100 kHz", "unit": "V", "direction": "min", "constraint": "<= 0.000045 V", "min": null, "max": 0.000045, "why": "10 Hz to 100 kHz, rms: the input pair, and the folded branches' current sources, whose noise a folded cascode adds." } ], "explanation": { "idea": "Regulates a 3.3 V input down to about 2.8 V. A folded-cascode amplifier compares the output directly with a reference and drives a PMOS pass transistor. Its input range supports this high output voltage; small remaining headroom limits full-load regulation.", "detail": "A 2.8 V supply from the 3.3 V I/O supply, with only 0.17 V of headroom at the lowest input. The output copies a 2.8 V reference through unity feedback, so the error amplifier's input sits at 2.8 V: too close to the supply for a five-transistor amplifier's input pair, which needs room under its load. The folded input pair connects to current sources near the supply, leaving more drain headroom at this input level. Every transistor is a 3.3 V one.", "lesson": { "relation": 0, "symbols": "V_CM,max is the highest input common-mode voltage; V_DD is the supply; V_DSAT,M5 and V_DSAT1 are device saturation-voltage estimates; V_GS1 is the input device's gate-source voltage.", "assumptions": "A headroom estimate for the folded input branch at its intended bias. It is not a permission to exceed device terminal-voltage ratings.", "exercise": { "param": "IL", "value": 0.005, "analysis": "load_step", "expect": "Halving the full-load step should reduce the output excursions. The pass transistor needs a smaller current change, while the compensation and bias stay unchanged." }, "limits": "The default is 2.8 V output from 2.97–3.63 V input using 3.3 V devices. Supply external reference and bias, connect sense to out, and check headroom at full load." }, "path": [ { "part": "Input pair", "devices": "M1, M2, MT", "does": "M1 senses the output, M2 the reference, both near 2.8 V; their drains fold into f1 and f2, just under the supply." }, { "part": "Folded cascode", "devices": "M5, M6, M7, M8, M9, M10", "does": "M5, M6 on top are a mirror gated from mir, the drain of the cascode M7; M8 carries the output side down to gate against the sink M10. A rise in the output lifts gate." }, { "part": "Cascode bias", "devices": "MB2, MBC", "does": "MBC, a narrow PMOS diode fed by a copy of Ib, sets vbc so that M5, M6 keep about 0.25 V and M7, M8 stay saturated." }, { "part": "Pass device and compensation", "devices": "MP, Rz, Cc, Rb", "does": "A 3.3 V PMOS from the input; Cc with Rz across it splits the poles, and Rb is the bleed." } ], "bias": "Ib, 5 µA from outside, into MB; the tail MT is 8 copies of it, the sinks M9 and M10 4 each. The reference is an input, 2.8 V; the input is 3.3 V (2.97 to 3.63 V).", "relations": [ { "what": "Input range", "expr": "V_CM,max ≈ V_DD − V_DSAT,M5 + V_GS1 − V_DSAT1", "note": "Above the supply for this design: the input-stage estimate reaches above the intended common mode, but terminal-voltage ratings still apply." }, { "what": "Output swing at no load", "expr": "V_DD − V_gate ≥ V_DSAT,M6 + V_DSAT,M8", "note": "With no load gate sits only about 0.6 V below the supply; M6 and M8 run in weak inversion so both fit." }, { "what": "Loop gain", "expr": "T ≈ g_m2 · R_gate · g_m,MP · R_o", "note": "R_gate: the cascoded output resistance; at the lowest input MP runs in triode and T falls to about 31 dB." }, { "what": "Noise", "expr": "v_n,in² ≈ v_n,M1² · (1 + g_m,M5/g_m1 + g_m,M9/g_m1)", "note": "The folded branches' current sources add their noise: extra current-source noise must be budgeted; the comparison with another amplifier depends on sizing and current allocation." } ], "tradeoffs": [ "Wc, Lc (MBC): too wide and vbc sits too high, leaving M5, M6 in triode; too narrow and M7, M8 run out of room.", "K against N: more sink current speeds the output and the line step, but its noise and the mirror's grow against the pair's transconductance.", "Wp, Wk: wider M5-M8 run in weak inversion with small saturation voltages, which the 0.6 V at no load needs; wider still adds capacitance and noise.", "Rb: the bleed sets MP's g_m at no load, and so the output pole." ] }, "sizing": [ { "key": "Ib", "label": "Bias current", "unit": "A", "value": 0.000005, "min": 0.000001, "max": 0.00005, "kind": "si" }, { "key": "N", "label": "Tail current, in Ib", "unit": "", "value": 8, "min": 1, "max": 40, "kind": "int" }, { "key": "K", "label": "Sink current (M9, M10), in Ib", "unit": "", "value": 4, "min": 1, "max": 40, "kind": "int" }, { "key": "Wn", "label": "W NMOS bias unit", "unit": "m", "value": 0.000008, "min": 5e-7, "max": 0.00004, "kind": "si" }, { "key": "Ln", "label": "L NMOS bias unit", "unit": "m", "value": 0.000001, "min": 4.5e-7, "max": 0.000004, "kind": "si" }, { "key": "Wc", "label": "W cascode-bias diode MBC", "unit": "m", "value": 0.000002, "min": 5e-7, "max": 0.00004, "kind": "si" }, { "key": "Lc", "label": "L cascode-bias diode MBC", "unit": "m", "value": 0.000001, "min": 4.5e-7, "max": 0.00002, "kind": "si" }, { "key": "W1", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.00004, "min": 0.000001, "max": 0.0002, "kind": "si" }, { "key": "L1", "label": "L input pair", "unit": "m", "value": 0.000002, "min": 4.5e-7, "max": 0.000008, "kind": "si" }, { "key": "Wp", "label": "W top mirror (M5, M6)", "unit": "m", "value": 0.0002, "min": 0.000001, "max": 0.0004, "kind": "si" }, { "key": "Lp", "label": "L top mirror", "unit": "m", "value": 0.000001, "min": 4.5e-7, "max": 0.000008, "kind": "si" }, { "key": "Wk", "label": "W cascodes (M7, M8)", "unit": "m", "value": 0.0001, "min": 0.000001, "max": 0.0004, "kind": "si" }, { "key": "Lk", "label": "L cascodes", "unit": "m", "value": 0.000001, "min": 4.5e-7, "max": 0.000008, "kind": "si" }, { "key": "Wpass", "label": "W pass device", "unit": "m", "value": 0.0012, "min": 0.00002, "max": 0.006, "kind": "si" }, { "key": "Lpass", "label": "L pass device", "unit": "m", "value": 4.5e-7, "min": 4.5e-7, "max": 0.000002, "kind": "si" }, { "key": "Rb", "label": "Bleed resistor", "unit": "Ω", "value": 20000, "min": 1000, "max": 200000, "kind": "si" }, { "key": "Rz", "label": "Zero resistor", "unit": "Ω", "value": 1500, "min": 200, "max": 20000, "kind": "si" }, { "key": "Cc", "label": "Miller capacitor", "unit": "F", "value": 2e-11, "min": 1e-12, "max": 2e-10, "kind": "si" }, { "key": "Vref", "label": "Reference", "unit": "V", "value": 2.8, "min": 1.2, "max": 2.85, "kind": "si" }, { "key": "IL", "label": "Full load", "unit": "A", "value": 0.01, "min": 0.001, "max": 0.03, "kind": "si" }, { "key": "CL", "label": "Load capacitance", "unit": "F", "value": 1e-10, "min": 1e-11, "max": 1e-9, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The regulator at its nominal input and its lightest load: the output it holds and the current it draws to hold it.", "measures": [], "metricKeys": [ "vout", "i_q" ], "acceptance": [ "vout", "i_q" ], "acceptanceRules": [ { "key": "vout", "unit": "V", "min": 2.75, "max": 2.85, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "i_q", "unit": "A", "min": null, "max": 0.00035, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Folded-cascode LDO, 2.8 V from 3.3 V - operating point at the lightest load\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 2.8\nIb vdd ib dc 5u\n.subckt ldofchv ref sense out vdd vss ib\n* bias: the tail and the two sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMT tail ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\nXM9 mir ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXM10 gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\n* the cascodes' gate: a PMOS diode one V_SG below the supply, fed by a copy of Ib\nXMB2 vbc ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMBC vbc vbc vdd vdd sg13_hv_pmos w=2u l=1u ng=1 m=1\n* input pair: the output on M1, the reference on M2\nXM1 f1 sense tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\nXM2 f2 ref tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\n* the folded cascode: the mirror M5, M6 on top, gated from mir; the cascodes M7, M8\nXM5 f1 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM6 f2 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM7 mir vbc f1 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\nXM8 gate vbc f2 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\n* the pass device and its bleed\nXMP out gate vdd vdd sg13_hv_pmos w=1.2m l=450n ng=240 m=1\nXRb out vss vss rhigh w=0.5u l=6.078u\n* Miller compensation across the pass device, the zero resistor in series\nXRz gate cz vss rppd w=0.5u l=2.678u\nXCc cz out cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldofchv\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 0\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.op\n.end" }, { "id": "load_reg", "label": "Load regulation", "note": "The load is swept from lightest to full at nominal input. Regulation is the magnitude of the endpoint output change per ampere; a large output rise fails just as a large fall does.", "measures": [], "metricKeys": [ "load_reg" ], "acceptance": [ "load_reg" ], "acceptanceRules": [ { "key": "load_reg", "unit": "V/A", "min": null, "max": 1.5, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Folded-cascode LDO, 2.8 V from 3.3 V - output against load current\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 2.8\nIb vdd ib dc 5u\n.subckt ldofchv ref sense out vdd vss ib\n* bias: the tail and the two sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMT tail ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\nXM9 mir ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXM10 gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\n* the cascodes' gate: a PMOS diode one V_SG below the supply, fed by a copy of Ib\nXMB2 vbc ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMBC vbc vbc vdd vdd sg13_hv_pmos w=2u l=1u ng=1 m=1\n* input pair: the output on M1, the reference on M2\nXM1 f1 sense tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\nXM2 f2 ref tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\n* the folded cascode: the mirror M5, M6 on top, gated from mir; the cascodes M7, M8\nXM5 f1 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM6 f2 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM7 mir vbc f1 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\nXM8 gate vbc f2 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\n* the pass device and its bleed\nXMP out gate vdd vdd sg13_hv_pmos w=1.2m l=450n ng=240 m=1\nXRb out vss vss rhigh w=0.5u l=6.078u\n* Miller compensation across the pass device, the zero resistor in series\nXRz gate cz vss rppd w=0.5u l=2.678u\nXCc cz out cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldofchv\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 0\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.dc Vload 0 10m 100u\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc v_light FIND v(out) AT=0\n.meas dc v_full FIND v(out) AT=10m\n.end" }, { "id": "line_reg", "label": "Line regulation", "note": "The input swept across its rated range, at the lightest and at the full load: how much of the input's change reaches the output.", "measures": [], "metricKeys": [ "line_reg" ], "acceptance": [ "line_reg" ], "acceptanceRules": [ { "key": "line_reg", "unit": "%/V", "min": null, "max": 0.2, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Folded-cascode LDO, 2.8 V from 3.3 V - output against input voltage\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n* the input swept across its rated range, 2.97V to 3.63V\nVdd vdd 0 dc 3.3\nVref ref 0 dc 2.8\nIb vdd ib dc 5u\n.subckt ldofchv ref sense out vdd vss ib\n* bias: the tail and the two sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMT tail ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\nXM9 mir ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXM10 gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\n* the cascodes' gate: a PMOS diode one V_SG below the supply, fed by a copy of Ib\nXMB2 vbc ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMBC vbc vbc vdd vdd sg13_hv_pmos w=2u l=1u ng=1 m=1\n* input pair: the output on M1, the reference on M2\nXM1 f1 sense tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\nXM2 f2 ref tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\n* the folded cascode: the mirror M5, M6 on top, gated from mir; the cascodes M7, M8\nXM5 f1 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM6 f2 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM7 mir vbc f1 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\nXM8 gate vbc f2 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\n* the pass device and its bleed\nXMP out gate vdd vdd sg13_hv_pmos w=1.2m l=450n ng=240 m=1\nXRb out vss vss rhigh w=0.5u l=6.078u\n* Miller compensation across the pass device, the zero resistor in series\nXRz gate cz vss rppd w=0.5u l=2.678u\nXCc cz out cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldofchv\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 0\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n* the input swept at each of two loads: the lightest, then the full load\n.dc Vdd 2.97 3.63 13.75m Vload 0 10m 10m\n.end" }, { "id": "dropout", "label": "Dropout", "note": "The input lowered at full load until the output has fallen 2 % below the level it holds at the nominal input: the input-to-output voltage left there is the dropout.", "measures": [], "metricKeys": [ "dropout" ], "acceptance": [ "dropout" ], "acceptanceRules": [ { "key": "dropout", "unit": "V", "min": null, "max": 0.15, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Folded-cascode LDO, 2.8 V from 3.3 V - dropout at full load\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n* the input swept down to below the output: 2.5V to 3.63V\nVdd vdd 0 dc 3.3\nVref ref 0 dc 2.8\nIb vdd ib dc 5u\n.subckt ldofchv ref sense out vdd vss ib\n* bias: the tail and the two sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMT tail ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\nXM9 mir ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXM10 gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\n* the cascodes' gate: a PMOS diode one V_SG below the supply, fed by a copy of Ib\nXMB2 vbc ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMBC vbc vbc vdd vdd sg13_hv_pmos w=2u l=1u ng=1 m=1\n* input pair: the output on M1, the reference on M2\nXM1 f1 sense tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\nXM2 f2 ref tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\n* the folded cascode: the mirror M5, M6 on top, gated from mir; the cascodes M7, M8\nXM5 f1 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM6 f2 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM7 mir vbc f1 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\nXM8 gate vbc f2 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\n* the pass device and its bleed\nXMP out gate vdd vdd sg13_hv_pmos w=1.2m l=450n ng=240 m=1\nXRb out vss vss rhigh w=0.5u l=6.078u\n* Miller compensation across the pass device, the zero resistor in series\nXRz gate cz vss rppd w=0.5u l=2.678u\nXCc cz out cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldofchv\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 10m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.dc Vdd 2.5 3.63 5.65m\n.end" }, { "id": "loop", "label": "Loop gain", "note": "The loop gain at loads across the whole range, from the lightest to the full load: the loop is cut at the sense line and measured by Middlebrook's double injection - a voltage in series there, then a current into out - which gives it exactly, with every loading in place. The phase and gain margins are the worst over the loads.", "measures": [], "metricKeys": [ "loop_gain_db", "loop_ugf_hz", "loop_pm_deg", "loop_gm_db" ], "acceptance": [ "loop_gain_db", "loop_ugf_hz", "loop_pm_deg" ], "acceptanceRules": [ { "key": "loop_gain_db", "unit": "dB", "min": 25, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "loop_ugf_hz", "unit": "Hz", "min": 200000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "loop_pm_deg", "unit": "deg", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Folded-cascode LDO, 2.8 V from 3.3 V - loop gain at 10mA, voltage injection\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 2.8\nIb vdd ib dc 5u\n.subckt ldofchv ref sense out vdd vss ib\n* bias: the tail and the two sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMT tail ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\nXM9 mir ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXM10 gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\n* the cascodes' gate: a PMOS diode one V_SG below the supply, fed by a copy of Ib\nXMB2 vbc ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMBC vbc vbc vdd vdd sg13_hv_pmos w=2u l=1u ng=1 m=1\n* input pair: the output on M1, the reference on M2\nXM1 f1 sense tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\nXM2 f2 ref tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\n* the folded cascode: the mirror M5, M6 on top, gated from mir; the cascodes M7, M8\nXM5 f1 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM6 f2 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM7 mir vbc f1 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\nXM8 gate vbc f2 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\n* the pass device and its bleed\nXMP out gate vdd vdd sg13_hv_pmos w=1.2m l=450n ng=240 m=1\nXRb out vss vss rhigh w=0.5u l=6.078u\n* Miller compensation across the pass device, the zero resistor in series\nXRz gate cz vss rppd w=0.5u l=2.678u\nXCc cz out cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldofchv\n* the sense line cut by a 1 V ac source in series: T_v = -v(out)/v(sense)\nVinj sense out dc 0 ac 1\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 10m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.ac dec 20 0.1 1g\n.end" }, { "id": "ring", "label": "Ringing across the loads", "note": "The loads the loop bench visits, in a staircase from the lightest to the full load; at each, once the output has settled, a small step - a tenth more load. How far the output overshoots its new level on the way back, and what is left moving at the end of each step, show whether the regulator is damped at that load: a loop inside it that the sense line does not pass through, and so the loop gain cannot see, shows here.", "measures": [], "metricKeys": [ "ring_pct" ], "acceptance": [ "ring_pct" ], "acceptanceRules": [ { "key": "ring_pct", "unit": "%", "min": null, "max": 5, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Folded-cascode LDO, 2.8 V from 3.3 V - a small load step at each load\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 2.8\nIb vdd ib dc 5u\n.subckt ldofchv ref sense out vdd vss ib\n* bias: the tail and the two sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMT tail ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\nXM9 mir ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXM10 gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\n* the cascodes' gate: a PMOS diode one V_SG below the supply, fed by a copy of Ib\nXMB2 vbc ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMBC vbc vbc vdd vdd sg13_hv_pmos w=2u l=1u ng=1 m=1\n* input pair: the output on M1, the reference on M2\nXM1 f1 sense tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\nXM2 f2 ref tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\n* the folded cascode: the mirror M5, M6 on top, gated from mir; the cascodes M7, M8\nXM5 f1 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM6 f2 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM7 mir vbc f1 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\nXM8 gate vbc f2 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\n* the pass device and its bleed\nXMP out gate vdd vdd sg13_hv_pmos w=1.2m l=450n ng=240 m=1\nXRb out vss vss rhigh w=0.5u l=6.078u\n* Miller compensation across the pass device, the zero resistor in series\nXRz gate cz vss rppd w=0.5u l=2.678u\nXCc cz out cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldofchv\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 pwl(0 0 8u 0 8.4u 40u 20u 40u 20.4u 10u 28u 10u 28.4u 50u 40u 50u 40.4u 100u 48u 100u 48.4u 140u 60u 140u 60.4u 1m 68u 1m 68.4u 1.1m 80u 1.1m 80.4u 10m 88u 10m 88.4u 11m 100u 11m)\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.tran 10n 100u\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on the input, at the lightest and at the full load: how much of it reaches the output.", "measures": [], "metricKeys": [ "psrr_db", "psrr_hf_db" ], "acceptance": [ "psrr_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 25, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Folded-cascode LDO, 2.8 V from 3.3 V - supply rejection at 10mA\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD} ac 1\nVref ref 0 dc 2.8\nIb vdd ib dc 5u\n.subckt ldofchv ref sense out vdd vss ib\n* bias: the tail and the two sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMT tail ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\nXM9 mir ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXM10 gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\n* the cascodes' gate: a PMOS diode one V_SG below the supply, fed by a copy of Ib\nXMB2 vbc ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMBC vbc vbc vdd vdd sg13_hv_pmos w=2u l=1u ng=1 m=1\n* input pair: the output on M1, the reference on M2\nXM1 f1 sense tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\nXM2 f2 ref tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\n* the folded cascode: the mirror M5, M6 on top, gated from mir; the cascodes M7, M8\nXM5 f1 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM6 f2 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM7 mir vbc f1 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\nXM8 gate vbc f2 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\n* the pass device and its bleed\nXMP out gate vdd vdd sg13_hv_pmos w=1.2m l=450n ng=240 m=1\nXRb out vss vss rhigh w=0.5u l=6.078u\n* Miller compensation across the pass device, the zero resistor in series\nXRz gate cz vss rppd w=0.5u l=2.678u\nXCc cz out cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldofchv\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 10m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.ac dec 20 1 100meg\n.end" }, { "id": "load_step", "label": "Load step", "note": "The load stepped from the lightest to the full load and back, each edge 1.00 µs: how far the output dips and peaks, and how long it takes to settle within 1 % after each edge. A loop that rings or oscillates at either load shows here, whatever the loop gain says.", "measures": [], "metricKeys": [ "undershoot", "overshoot", "t_recover", "t_release" ], "acceptance": [ "undershoot", "overshoot", "t_recover", "t_release" ], "acceptanceRules": [ { "key": "undershoot", "unit": "V", "min": null, "max": 0.16, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "overshoot", "unit": "V", "min": null, "max": 0.22, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "t_recover", "unit": "s", "min": null, "max": 0.000003, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "t_release", "unit": "s", "min": null, "max": 0.000003, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Folded-cascode LDO, 2.8 V from 3.3 V - load step\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 2.8\nIb vdd ib dc 5u\n.subckt ldofchv ref sense out vdd vss ib\n* bias: the tail and the two sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMT tail ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\nXM9 mir ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXM10 gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\n* the cascodes' gate: a PMOS diode one V_SG below the supply, fed by a copy of Ib\nXMB2 vbc ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMBC vbc vbc vdd vdd sg13_hv_pmos w=2u l=1u ng=1 m=1\n* input pair: the output on M1, the reference on M2\nXM1 f1 sense tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\nXM2 f2 ref tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\n* the folded cascode: the mirror M5, M6 on top, gated from mir; the cascodes M7, M8\nXM5 f1 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM6 f2 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM7 mir vbc f1 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\nXM8 gate vbc f2 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\n* the pass device and its bleed\nXMP out gate vdd vdd sg13_hv_pmos w=1.2m l=450n ng=240 m=1\nXRb out vss vss rhigh w=0.5u l=6.078u\n* Miller compensation across the pass device, the zero resistor in series\nXRz gate cz vss rppd w=0.5u l=2.678u\nXCc cz out cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldofchv\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 pulse(0 10m 4u 1u 1u 17u 80u)\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.tran 8n 40u\n.end" }, { "id": "line_step", "label": "Line step", "note": "The input stepped across its rated range, 2.97 V to 3.63 V, and back, each edge 1.00 µs, at full load: how far the output moves.", "measures": [], "metricKeys": [ "line_step" ], "acceptance": [ "line_step" ], "acceptanceRules": [ { "key": "line_step", "unit": "V", "min": null, "max": 0.18, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Folded-cascode LDO, 2.8 V from 3.3 V - line step at full load\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n* the input steps across its rated range and back\nVdd vdd 0 pulse(2.97 3.63 4u 1u 1u 17u 80u)\nVref ref 0 dc 2.8\nIb vdd ib dc 5u\n.subckt ldofchv ref sense out vdd vss ib\n* bias: the tail and the two sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMT tail ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\nXM9 mir ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXM10 gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\n* the cascodes' gate: a PMOS diode one V_SG below the supply, fed by a copy of Ib\nXMB2 vbc ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMBC vbc vbc vdd vdd sg13_hv_pmos w=2u l=1u ng=1 m=1\n* input pair: the output on M1, the reference on M2\nXM1 f1 sense tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\nXM2 f2 ref tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\n* the folded cascode: the mirror M5, M6 on top, gated from mir; the cascodes M7, M8\nXM5 f1 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM6 f2 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM7 mir vbc f1 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\nXM8 gate vbc f2 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\n* the pass device and its bleed\nXMP out gate vdd vdd sg13_hv_pmos w=1.2m l=450n ng=240 m=1\nXRb out vss vss rhigh w=0.5u l=6.078u\n* Miller compensation across the pass device, the zero resistor in series\nXRz gate cz vss rppd w=0.5u l=2.678u\nXCc cz out cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldofchv\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 10m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.tran 8n 40u\n.end" }, { "id": "noise", "label": "Output noise", "note": "The noise at the output at full load: its density at 1 kHz and its total from 10 Hz to 100 kHz. The reference is an ideal, noiseless source, so this is the regulator's own noise.", "measures": [], "metricKeys": [ "vn_out", "vn_out_1k" ], "acceptance": [ "vn_out" ], "acceptanceRules": [ { "key": "vn_out", "unit": "V", "min": null, "max": 0.000045, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Folded-cascode LDO, 2.8 V from 3.3 V - output noise at full load\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=3.3\n* ac 1 only because ngspice's noise analysis names an input; the output noise does not depend on it\nVdd vdd 0 dc {VDD} ac 1\nVref ref 0 dc 2.8\nIb vdd ib dc 5u\n.subckt ldofchv ref sense out vdd vss ib\n* bias: the tail and the two sinks, copies of the reference Ib\nXMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMT tail ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8\nXM9 mir ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\nXM10 gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4\n* the cascodes' gate: a PMOS diode one V_SG below the supply, fed by a copy of Ib\nXMB2 vbc ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1\nXMBC vbc vbc vdd vdd sg13_hv_pmos w=2u l=1u ng=1 m=1\n* input pair: the output on M1, the reference on M2\nXM1 f1 sense tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\nXM2 f2 ref tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1\n* the folded cascode: the mirror M5, M6 on top, gated from mir; the cascodes M7, M8\nXM5 f1 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM6 f2 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1\nXM7 mir vbc f1 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\nXM8 gate vbc f2 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1\n* the pass device and its bleed\nXMP out gate vdd vdd sg13_hv_pmos w=1.2m l=450n ng=240 m=1\nXRb out vss vss rhigh w=0.5u l=6.078u\n* Miller compensation across the pass device, the zero resistor in series\nXRz gate cz vss rppd w=0.5u l=2.678u\nXCc cz out cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldofchv\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 10m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.control\nnoise v(out) Vdd dec 20 10 100k\nsetplot noise1\n* 20 points a decade from 10 Hz: point 40 is 1 kHz\nlet vn_1k = onoise_spectrum[40]\nprint vn_1k\nsetplot noise2\nprint onoise_total\n.endc\n.op\n.end" } ], "measurements": { "vout": { "label": "Output voltage", "unit": "V", "spec": { "min": 2.75, "max": 2.85 } }, "i_q": { "label": "Quiescent current", "unit": "A", "spec": { "min": null, "max": 0.00035 } }, "load_reg": { "label": "Load regulation", "unit": "V/A", "spec": { "min": null, "max": 1.5 } }, "line_reg": { "label": "Line regulation", "unit": "%/V", "spec": { "min": null, "max": 0.2 } }, "dropout": { "label": "Dropout at full load", "unit": "V", "spec": { "min": null, "max": 0.15 } }, "loop_gain_db": { "label": "DC loop gain at full load", "unit": "dB", "spec": { "min": 25, "max": null } }, "loop_ugf_hz": { "label": "Loop crossover at full load", "unit": "Hz", "spec": { "min": 200000, "max": null } }, "loop_pm_deg": { "label": "Loop phase margin, worst load", "unit": "deg", "spec": { "min": 60, "max": null } }, "ring_pct": { "label": "Ringing after a kick, worst load", "unit": "%", "spec": { "min": null, "max": 5 } }, "psrr_db": { "label": "Supply rejection at 1 kHz", "unit": "dB", "spec": { "min": 25, "max": null } }, "undershoot": { "label": "Undershoot on the load step", "unit": "V", "spec": { "min": null, "max": 0.16 } }, "overshoot": { "label": "Overshoot on the load release", "unit": "V", "spec": { "min": null, "max": 0.22 } }, "t_recover": { "label": "Settling after the load step", "unit": "s", "spec": { "min": null, "max": 0.000003 } }, "t_release": { "label": "Settling after the load release", "unit": "s", "spec": { "min": null, "max": 0.000003 } }, "line_step": { "label": "Output step for an input step", "unit": "V", "spec": { "min": null, "max": 0.18 } }, "vn_out": { "label": "Output noise, 10 Hz to 100 kHz", "unit": "V", "spec": { "min": null, "max": 0.000045 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "54ccfb0d540cf8f6235870db7c3cffcd439a2b988add12b357d70bf8e821c4a4" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ldo-fc-hv.js", "sha256": "f0a577429579dbb4b7b3c2bfdc0d99d140b97c914b7e971dd505aa04823222eb" }, "simulationFingerprints": { "op": "ece11c799761a20489d6e71950e6c726c9fbd105b6f018b6eda39ed842ef4a60", "load_reg": "978601b6be94c208cb39c3e1254ab085e2e3553bc5b57a084cbac14284300d04", "line_reg": "16812ceabce98fef8ff8abde1cfb1dbd3536ec92fde20a0a2d86fbb7bd861636", "dropout": "2aff789d94dc32e15a56df56bb094b94cb569cab8b5d618024c4c9880b97495d", "loop": "84fd512c52dd874c328717a34d26893cef8e06910041e5c96703be0741ea182e", "ring": "9fb259de96406e4498fddfa39f0438371549d344876155c58ec1e8a969da750a", "psrr": "c2710680779311b14a8d8e249835851fb788a9a422c85fb7cf8838825993d730", "load_step": "462fb0426c9c66f771b52a2d25a5a0bdd441dd46ba85fe18ef8af6527e02ce98", "line_step": "fb04068398c3b7148b63d4d79c9253c8103dab775e478cdd068b94b8a287ecec", "noise": "f3592cad1c90232e1028a2f0530182d84806493de287810f14218fe180231464" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "f5bc1cc2e8d907d2318d245d99650ce31991e5fe923c48fd72651d729eaa9608", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ldo-fc-hv", "parameters": { "Ib": 0.000005, "N": 8, "K": 4, "Wn": 0.000008, "Ln": 0.000001, "Wc": 0.000002, "Lc": 0.000001, "W1": 0.00004, "L1": 0.000002, "Wp": 0.0002, "Lp": 0.000001, "Wk": 0.0001, "Lk": 0.000001, "Wpass": 0.0012, "Lpass": 4.5e-7, "Rb": 20000, "Rz": 1500, "Cc": 2e-11, "Vref": 2.8, "IL": 0.01, "CL": 1e-10 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ldo-fc-hv/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=3.3" ], "scopes": [ { "id": "dut", "name": "ldofchv", "ports": [ { "name": "ref", "net": "ref", "kind": "input" }, { "name": "sense", "net": "sense", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=8", "source": "XMT tail ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XM9 mir ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "mir" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XM10 gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB2 vbc ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBC", "displayName": "MBC", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMBC vbc vbc vdd vdd sg13_hv_pmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM1 f1 sense tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM2 f2 ref tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=200u l=1u ng=40 m=1", "source": "XM5 f1 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "mir" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=200u l=1u ng=40 m=1", "source": "XM6 f2 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "mir" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=100u l=1u ng=20 m=1", "source": "XM7 mir vbc f1 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1", "pins": [ { "id": "d", "net": "mir" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=100u l=1u ng=20 m=1", "source": "XM8 gate vbc f2 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=1.2m l=450n ng=240 m=1", "source": "XMP out gate vdd vdd sg13_hv_pmos w=1.2m l=450n ng=240 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRb out vss vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=2.678u", "source": "XRz gate cz vss rppd w=0.5u l=2.678u", "pins": [ { "id": "p", "net": "gate" }, { "id": "n", "net": "cz" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.761u l=29.761u m=15", "source": "XCc cz out cap_cmim w=29.761u l=29.761u m=15", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" }, { "device": "XMB2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "mir", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XM10", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XMBC", "pin": "d" }, { "device": "XMBC", "pin": "g" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMBC", "pin": "s" }, { "device": "XMBC", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XRb", "pin": "p" }, { "device": "XCc", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "cz", "ground": false, "terminals": [ { "device": "XRz", "pin": "n" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=3.3" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=3.3" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 2.8", "source": "Vref ref 0 dc 2.8", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib vdd ib dc 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldofchv", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldofchv", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldofchv" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "100p", "source": "Cl out 0 100p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vload il 0 dc 0", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldofchv", "name": "ldofchv", "ports": [ { "name": "ref", "net": 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"sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XM9 mir ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "mir" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XM10 gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB2 vbc ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBC", "displayName": "MBC", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMBC vbc vbc vdd vdd sg13_hv_pmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM1 f1 sense tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM2 f2 ref tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=200u l=1u ng=40 m=1", "source": "XM5 f1 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "mir" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=200u l=1u ng=40 m=1", "source": "XM6 f2 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "mir" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=100u l=1u ng=20 m=1", "source": "XM7 mir vbc f1 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1", "pins": [ { "id": "d", "net": "mir" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=100u l=1u ng=20 m=1", "source": "XM8 gate vbc f2 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=1.2m l=450n ng=240 m=1", "source": "XMP out gate vdd vdd sg13_hv_pmos w=1.2m l=450n ng=240 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRb out vss vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=2.678u", "source": "XRz gate cz vss rppd w=0.5u l=2.678u", "pins": [ { "id": "p", "net": "gate" }, { "id": "n", "net": "cz" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.761u l=29.761u m=15", "source": "XCc cz out cap_cmim w=29.761u l=29.761u m=15", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" }, { "device": "XMB2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "mir", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XM10", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XMBC", "pin": "d" }, { "device": "XMBC", "pin": "g" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMBC", "pin": "s" }, { "device": "XMBC", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XRb", "pin": "p" }, { "device": "XCc", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "cz", "ground": false, "terminals": [ { "device": "XRz", "pin": "n" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldofchv" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Bias reference", "devices": [ { "scope": "dut", "device": "XMB" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "Tail", "devices": [ { "scope": "dut", "device": "XMT" } ], "inferredStages": [ 1 ] }, { "id": "block-3", "label": "Sink under the diode-side cascode", "devices": [ { "scope": "dut", "device": "XM9" } ], "inferredStages": [ 2 ] }, { "id": "block-4", "label": "Sink under the output cascode", "devices": [ { "scope": "dut", "device": "XM10" } ], "inferredStages": [ 2 ] }, { "id": "block-5", "label": "A copy of Ib for the cascode bias", "devices": [ { "scope": "dut", "device": "XMB2" } ], "inferredStages": [ "bias" ] }, { "id": "block-6", "label": "Cascode bias", "devices": [ { "scope": "dut", "device": "XMBC" } ], "inferredStages": [ "bias" ] }, { "id": "block-7", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 1 ] }, { "id": "block-8", "label": "Top mirror", "devices": [ { "scope": "dut", "device": "XM5" }, { "scope": "dut", "device": "XM6" } ], "inferredStages": [ 1 ] }, { "id": "block-9", "label": "Cascode", "devices": [ { "scope": "dut", "device": "XM7" }, { "scope": "dut", "device": "XM8" } ], "inferredStages": [ 2 ] }, { "id": "block-10", "label": "Pass device", "devices": [ { "scope": "dut", "device": "XMP" } ], "inferredStages": [ 3 ] }, { "id": "block-11", "label": "Bleed: the least MP always carries", "devices": [ { "scope": "dut", "device": "XRb" } ], "inferredStages": [ 3 ] }, { "id": "block-12", "label": "Zero resistor", "devices": [ { "scope": "dut", "device": "XRz" } ], "inferredStages": [ "comp" ] }, { "id": "block-13", "label": "Miller capacitor across the pass device", "devices": [ { "scope": "dut", "device": "XCc" } ], "inferredStages": [ "comp" ] } ], "edges": [ { "id": "net-1", "net": "ib", "nodes": [ "block-1", "block-2", "block-3", "block-4", "block-5" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "tail", "nodes": [ "block-2", "block-7" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "mir", "nodes": [ "block-3", "block-8", "block-9" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "gate", "nodes": [ "block-4", "block-9", "block-10", "block-12" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "vbc", "nodes": [ "block-5", "block-6", "block-9" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "f1", "nodes": [ "block-7", "block-8", "block-9" ], "direction": "undirected-shared-net" }, { "id": "net-7", "net": "f2", "nodes": [ "block-7", "block-8", "block-9" ], "direction": "undirected-shared-net" }, { "id": "net-8", "net": "out", "nodes": [ "block-10", "block-11", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-9", "net": "cz", "nodes": [ "block-12", "block-13" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "ref", "net": "ref", "kind": "input" }, { "name": "sense", "net": "sense", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [], "scopes": [ { "id": "dut", "name": "ldofchv", "ports": [ { "name": "ref", "net": "ref", "kind": "input" }, { "name": "sense", "net": "sense", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=8", "source": "XMT tail ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XM9 mir ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "mir" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XM10 gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB2 vbc ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBC", "displayName": "MBC", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMBC vbc vbc vdd vdd sg13_hv_pmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM1 f1 sense tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM2 f2 ref tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=200u l=1u ng=40 m=1", "source": "XM5 f1 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "mir" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=200u l=1u ng=40 m=1", "source": "XM6 f2 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "mir" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=100u l=1u ng=20 m=1", "source": "XM7 mir vbc f1 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1", "pins": [ { "id": "d", "net": "mir" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=100u l=1u ng=20 m=1", "source": "XM8 gate vbc f2 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=1.2m l=450n ng=240 m=1", "source": "XMP out gate vdd vdd sg13_hv_pmos w=1.2m l=450n ng=240 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRb out vss vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=2.678u", "source": "XRz gate cz vss rppd w=0.5u l=2.678u", "pins": [ { "id": "p", "net": "gate" }, { "id": "n", "net": "cz" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.761u l=29.761u m=15", "source": "XCc cz out cap_cmim w=29.761u l=29.761u m=15", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" }, { "device": "XMB2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "mir", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XM10", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XMBC", "pin": "d" }, { "device": "XMBC", "pin": "g" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMBC", "pin": "s" }, { "device": "XMBC", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XRb", "pin": "p" }, { "device": "XCc", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "cz", "ground": false, "terminals": [ { "device": "XRz", "pin": "n" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ] }, { "id": "graph-5", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc 3.3", "source": "Vdd vdd 0 dc 3.3", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 2.8", "source": "Vref ref 0 dc 2.8", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib vdd ib dc 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldofchv", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldofchv", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldofchv" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "100p", "source": "Cl out 0 100p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vload il 0 dc 0", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldofchv", "name": "ldofchv", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=8", "source": "XMT tail ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XM9 mir ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "mir" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XM10 gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB2 vbc ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBC", "displayName": "MBC", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMBC vbc vbc vdd vdd sg13_hv_pmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM1 f1 sense tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM2 f2 ref tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=200u l=1u ng=40 m=1", "source": "XM5 f1 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "mir" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=200u l=1u ng=40 m=1", "source": "XM6 f2 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "mir" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=100u l=1u ng=20 m=1", "source": "XM7 mir vbc f1 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1", "pins": [ { "id": "d", "net": "mir" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=100u l=1u ng=20 m=1", "source": "XM8 gate vbc f2 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=1.2m l=450n ng=240 m=1", "source": "XMP out gate vdd vdd sg13_hv_pmos w=1.2m l=450n ng=240 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRb out vss vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=2.678u", "source": "XRz gate cz vss rppd w=0.5u l=2.678u", "pins": [ { "id": "p", "net": "gate" }, { "id": "n", "net": "cz" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.761u l=29.761u m=15", "source": "XCc cz out cap_cmim w=29.761u l=29.761u m=15", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" }, { "device": "XMB2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "mir", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XM10", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XMBC", "pin": "d" }, { "device": "XMBC", "pin": "g" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMBC", "pin": "s" }, { "device": "XMBC", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XRb", "pin": "p" }, { "device": "XCc", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "cz", "ground": false, "terminals": [ { "device": "XRz", "pin": "n" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldofchv" } }, { "id": "graph-6", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc 3.3", "source": "Vdd vdd 0 dc 3.3", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 2.8", "source": "Vref ref 0 dc 2.8", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib vdd ib dc 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldofchv", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldofchv", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldofchv" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "100p", "source": "Cl out 0 100p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "dc 10m", "source": "Vload il 0 dc 10m", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldofchv", "name": "ldofchv", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=8", "source": "XMT tail ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XM9 mir ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "mir" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XM10 gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB2 vbc ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBC", "displayName": "MBC", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMBC vbc vbc vdd vdd sg13_hv_pmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM1 f1 sense tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM2 f2 ref tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=200u l=1u ng=40 m=1", "source": "XM5 f1 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "mir" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=200u l=1u ng=40 m=1", "source": "XM6 f2 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "mir" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=100u l=1u ng=20 m=1", "source": "XM7 mir vbc f1 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1", "pins": [ { "id": "d", "net": "mir" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=100u l=1u ng=20 m=1", "source": "XM8 gate vbc f2 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=1.2m l=450n ng=240 m=1", "source": "XMP out gate vdd vdd sg13_hv_pmos w=1.2m l=450n ng=240 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRb out vss vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=2.678u", "source": "XRz gate cz vss rppd w=0.5u l=2.678u", "pins": [ { "id": "p", "net": "gate" }, { "id": "n", "net": "cz" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.761u l=29.761u m=15", "source": "XCc cz out cap_cmim w=29.761u l=29.761u m=15", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" }, { "device": "XMB2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "mir", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XM10", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XMBC", "pin": "d" }, { "device": "XMBC", "pin": "g" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMBC", "pin": "s" }, { "device": "XMBC", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": 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This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=3.3" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=3.3" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 2.8", "source": "Vref ref 0 dc 2.8", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib vdd ib dc 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldofchv", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldofchv", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldofchv" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "100p", "source": "Cl out 0 100p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "pwl(0 0 8u 0 8.4u 40u 20u 40u 20.4u 10u 28u 10u 28.4u 50u 40u 50u 40.4u 100u 48u 100u 48.4u 140u 60u 140u 60.4u 1m 68u 1m 68.4u 1.1m 80u 1.1m 80.4u 10m 88u 10m 88.4u 11m 100u 11m)", "source": "Vload il 0 pwl(0 0 8u 0 8.4u 40u 20u 40u 20.4u 10u 28u 10u 28.4u 50u 40u 50u 40.4u 100u 48u 100u 48.4u 140u 60u 140u 60.4u 1m 68u 1m 68.4u 1.1m 80u 1.1m 80.4u 10m 88u 10m 88.4u 11m 100u 11m)", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldofchv", "name": "ldofchv", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=8", "source": "XMT tail ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XM9 mir ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "mir" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XM10 gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB2 vbc ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBC", "displayName": "MBC", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMBC vbc vbc vdd vdd sg13_hv_pmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM1 f1 sense tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM2 f2 ref tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=200u l=1u ng=40 m=1", "source": "XM5 f1 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "mir" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=200u l=1u ng=40 m=1", "source": "XM6 f2 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "mir" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=100u l=1u ng=20 m=1", "source": "XM7 mir vbc f1 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1", "pins": [ { "id": "d", "net": "mir" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=100u l=1u ng=20 m=1", "source": "XM8 gate vbc f2 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=1.2m l=450n ng=240 m=1", "source": "XMP out gate vdd vdd sg13_hv_pmos w=1.2m l=450n ng=240 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRb out vss vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=2.678u", "source": "XRz gate cz vss rppd w=0.5u l=2.678u", "pins": [ { "id": "p", "net": "gate" }, { "id": "n", "net": "cz" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.761u l=29.761u m=15", "source": "XCc cz out cap_cmim w=29.761u l=29.761u m=15", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" }, { "device": "XMB2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "mir", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XM10", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XMBC", "pin": "d" }, { "device": "XMBC", "pin": "g" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMBC", "pin": "s" }, { "device": "XMBC", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XRb", "pin": "p" }, { "device": "XCc", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "cz", "ground": false, "terminals": [ { "device": "XRz", "pin": "n" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldofchv" } }, { "id": "graph-9", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=3.3" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=3.3" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD} ac 1", "source": "Vdd vdd 0 dc {VDD} ac 1", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 2.8", "source": "Vref ref 0 dc 2.8", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib vdd ib dc 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldofchv", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldofchv", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldofchv" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "100p", "source": "Cl out 0 100p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "dc 10m", "source": "Vload il 0 dc 10m", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldofchv", "name": "ldofchv", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=8", "source": "XMT tail ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XM9 mir ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "mir" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XM10 gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB2 vbc ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBC", "displayName": "MBC", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMBC vbc vbc vdd vdd sg13_hv_pmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM1 f1 sense tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM2 f2 ref tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=200u l=1u ng=40 m=1", "source": "XM5 f1 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "mir" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=200u l=1u ng=40 m=1", "source": "XM6 f2 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "mir" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=100u 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bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRb out vss vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=2.678u", "source": "XRz gate cz vss rppd w=0.5u l=2.678u", "pins": [ { "id": "p", "net": "gate" }, { "id": "n", "net": "cz" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.761u l=29.761u m=15", "source": "XCc cz out cap_cmim w=29.761u l=29.761u m=15", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, 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"XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "mir", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XM10", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XMBC", "pin": "d" }, { "device": "XMBC", "pin": "g" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMBC", "pin": "s" }, { "device": "XMBC", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XRb", "pin": "p" }, { "device": "XCc", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "cz", "ground": false, "terminals": [ { "device": "XRz", "pin": "n" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldofchv" } }, { "id": "graph-10", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=3.3" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=3.3" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 2.8", "source": "Vref ref 0 dc 2.8", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib vdd ib dc 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldofchv", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldofchv", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldofchv" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "100p", "source": "Cl out 0 100p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "pulse(0 10m 4u 1u 1u 17u 80u)", "source": "Vload il 0 pulse(0 10m 4u 1u 1u 17u 80u)", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldofchv", "name": "ldofchv", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=8", "source": "XMT tail ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XM9 mir ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "mir" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XM10 gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB2 vbc ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBC", "displayName": "MBC", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMBC vbc vbc vdd vdd sg13_hv_pmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM1 f1 sense tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM2 f2 ref tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=200u l=1u ng=40 m=1", "source": "XM5 f1 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "mir" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=200u l=1u ng=40 m=1", "source": "XM6 f2 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "mir" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=100u l=1u ng=20 m=1", "source": "XM7 mir vbc f1 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1", "pins": [ { "id": "d", "net": "mir" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=100u l=1u ng=20 m=1", "source": "XM8 gate vbc f2 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=1.2m l=450n ng=240 m=1", "source": "XMP out gate vdd vdd sg13_hv_pmos w=1.2m l=450n ng=240 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRb out vss vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=2.678u", "source": "XRz gate cz vss rppd w=0.5u l=2.678u", "pins": [ { "id": "p", "net": "gate" }, { "id": "n", "net": "cz" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.761u l=29.761u m=15", "source": "XCc cz out cap_cmim w=29.761u l=29.761u m=15", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" }, { "device": "XMB2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XRb", "pin": "n" }, { "device": "XRb", "pin": "substrate" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "mir", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XM10", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XMBC", "pin": "d" }, { "device": "XMBC", "pin": "g" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMBC", "pin": "s" }, { "device": "XMBC", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XRb", "pin": "p" }, { "device": "XCc", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "cz", "ground": false, "terminals": [ { "device": "XRz", "pin": "n" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldofchv" } }, { "id": "graph-11", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "pulse(2.97 3.63 4u 1u 1u 17u 80u)", "source": "Vdd vdd 0 pulse(2.97 3.63 4u 1u 1u 17u 80u)", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 2.8", "source": "Vref ref 0 dc 2.8", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 5u", "source": "Ib vdd ib dc 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldofchv", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldofchv", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldofchv" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "100p", "source": "Cl out 0 100p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "dc 10m", "source": "Vload il 0 dc 10m", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldofchv", "name": "ldofchv", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB ib ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=8", "source": "XMT tail ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=8", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XM9 mir ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "mir" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=4", "source": "XM10 gate ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=4", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=8u l=1u ng=2 m=1", "source": "XMB2 vbc ib vss vss sg13_hv_nmos w=8u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMBC", "displayName": "MBC", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=2u l=1u ng=1 m=1", "source": "XMBC vbc vbc vdd vdd sg13_hv_pmos w=2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM1 f1 sense tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=40u l=2u ng=8 m=1", "source": "XM2 f2 ref tail vss sg13_hv_nmos w=40u l=2u ng=8 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=200u l=1u ng=40 m=1", "source": "XM5 f1 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "mir" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=200u l=1u ng=40 m=1", "source": "XM6 f2 mir vdd vdd sg13_hv_pmos w=200u l=1u ng=40 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "mir" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=100u l=1u ng=20 m=1", "source": "XM7 mir vbc f1 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1", "pins": [ { "id": "d", "net": "mir" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=100u l=1u ng=20 m=1", "source": "XM8 gate vbc f2 vdd sg13_hv_pmos w=100u l=1u ng=20 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=1.2m l=450n ng=240 m=1", "source": "XMP out gate vdd vdd sg13_hv_pmos w=1.2m l=450n ng=240 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, 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