{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ldo-miller-cff", "name": "PMOS LDO, Miller and feed-forward compensated", "group": "Voltage regulators", "subgroup": "LDOs", "title": "PMOS LDO, Miller and feed-forward compensated", "summary": "Regulates 1.2 V down to about 0.9 V with a small output capacitor. A capacitor across the PMOS pass device separates the loop's poles; another across the feedback divider adds phase lead. This saves a large output capacitor but offers limited extra phase margin.", "reference": { "kind": "book", "authors": "G. A. Rincon-Mora", "title": "Analog IC Design with Low-Dropout Regulators", "edition": "2nd", "publisher": "McGraw-Hill", "year": 2014, "where": "the PMOS-pass LDO, its feedback divider and its frequency compensation", "takes": "The topology: a five-transistor error amplifier, a PMOS pass device, a Miller capacitor across it and a feed-forward capacitor across the divider's upper resistor. The sizing and specs are this library's, for SG13G2 at 1.2 V.", "also": [ { "authors": "B. Razavi", "title": "Design of Analog CMOS Integrated Circuits", "edition": "2nd ed.", "publisher": "McGraw-Hill", "year": 2016, "where": "Sec. 10.5, compensating two-stage op amps: pole splitting by a Miller capacitor, and the right-half-plane zero it brings" } ] }, "resources": { "record": "/circuits/ldo-miller-cff.json", "page": "/index.html#ldo-miller-cff", "achieved": "/achieved/ldo-miller-cff.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "ref", "kind": "input", "note": "the reference voltage" }, { "name": "sense", "kind": "input", "note": "the output as the regulator reads it; the divider hangs from it" }, { "name": "out", "kind": "output" }, { "name": "vdd", "kind": "supply", "note": "the unregulated input" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the bias current, driven into this pin" } ], "devices": [ { "name": "MB", "type": "nmos", "nodes": "ib ib vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "bias reference, diode-connected", "fingers": 1, "copies": 1 }, { "name": "MT", "type": "nmos", "nodes": "tail ib vss vss", "sizedBy": [ "Wn", "Ln", "N" ], "role": "error amplifier tail, N copies of MB", "fingers": 1, "copies": 4 }, { "name": "M1", "type": "nmos", "nodes": "d1 div tail vss", "sizedBy": [ "W1", "L1" ], "role": "input pair, the divided output", "fingers": 8, "copies": 1 }, { "name": "M2", "type": "nmos", "nodes": "gate ref tail vss", "sizedBy": [ "W1", "L1" ], "role": "input pair, the reference", "fingers": 8, "copies": 1 }, { "name": "M3", "type": "pmos", "nodes": "d1 d1 vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "mirror load, diode-connected", "fingers": 40, "copies": 1 }, { "name": "M4", "type": "pmos", "nodes": "gate d1 vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "mirror load, drives the pass gate", "fingers": 40, "copies": 1 }, { "name": "MP", "type": "pmos", "nodes": "out gate vdd vdd", "sizedBy": [ "Wpass", "Lpass" ], "role": "pass device", "fingers": 240, "copies": 1 }, { "name": "R1", "type": "resistor", "nodes": "sense div", "sizedBy": [ "Ru" ], "role": "divider, the unit above div" }, { "name": "R2", "type": "resistor", "nodes": "div dv", "sizedBy": [ "Ru" ], "role": "divider, first unit below div" }, { "name": "R3", "type": "resistor", "nodes": "dv vss", "sizedBy": [ "Ru" ], "role": "divider, second unit below div" }, { "name": "Cc", "type": "capacitor", "nodes": "gate out", "sizedBy": [ "Cc" ], "role": "Miller capacitor across the pass device" }, { "name": "Cf", "type": "capacitor", "nodes": "sense div", "sizedBy": [ "Cf" ], "role": "feed-forward capacitor across R1" } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "The input pair: any difference between them is an offset at div, and the divider multiplies it by 1.5 onto the output." }, { "rule": "match", "of": [ "M3", "M4" ], "why": "The mirror load: a mismatch copies the wrong current onto gate and appears as offset." }, { "rule": "unit-copies", "of": [ "MB", "MT" ], "constraint": "MT = N copies of MB", "why": "The tail current is set by repeating the bias device, never by drawing a wider one: copies share nominal geometry-dependent behavior, while random mismatch remains." }, { "rule": "unit-copies", "of": [ "R1", "R2", "R3" ], "constraint": "three copies of one resistor: V_out = 1.5 V_ref", "why": "Only the ratio sets the output, so the divider is one resistor repeated. Two different values - worse, two different materials, as p+ and high-resistance poly are on either side of 20 kΩ - drift apart with temperature and corner and move the output with them." }, { "rule": "bleed", "of": [ "R1", "R2", "R3", "MP" ], "constraint": "V_out/(3 Ru) above MP's leakage at 125 °C, fast corner", "why": "With no load the divider is all MP drives. Hot and fast, MP leaks tens of µA even with its gate within 0.1 V of the supply; a divider drawing less lets that leakage lift the unloaded output." }, { "rule": "weak-inversion", "of": [ "M3", "M4" ], "constraint": "V_DSAT of M4 near 0.1 V", "why": "At no load the loop must hold gate within about 0.1 V of V_DD to shut MP off. M4 has to stay saturated there, or the amplifier loses its gain exactly where MP's leakage has to be held - so the mirror runs wide and long, in weak inversion." }, { "rule": "headroom", "of": [ "MP", "M2" ], "constraint": "5 mA with 0.18 V across MP at a 1.08 V input", "why": "The five-transistor amplifier cannot pull gate below the tail node plus M2's saturation voltage, about 0.4 V, so MP's width is chosen for full load with only 0.68 V of V_SG, at the slow corner." }, { "rule": "pole-splitting", "of": [ "Cc", "MP" ], "constraint": "g_m,MP/C_L at no load above twice β g_m2/Cc", "why": "Cc makes gate the dominant pole and the crossover β g_m2/Cc; the output pole, g_m,MP over the load capacitance, must stay above it, and it is lowest at no load - which is what sizes Cc." }, { "rule": "lead", "of": [ "Cf", "R1", "R2", "R3" ], "constraint": "zero 1/(2π R1 Cf) near the no-load crossover; lead at most asin(1/5) = 11.5°", "why": "Cf lifts the feedback factor from 2/3 at low frequency to 1 above its pole: a zero-pole pair 1.5:1 apart, whose lead - never more than 11.5° for this divider - is placed at the crossover where the margin is least, at no load. Much larger, the pair slides below the crossover and gives nothing." } ], "specs": [ { "key": "vout", "label": "Output voltage", "unit": "V", "direction": "target", "constraint": ">= 0.88 V, <= 0.92 V", "min": 0.88, "max": 0.92, "why": "0.9 V, 1.5 times the 0.6 V reference, within ±20 mV: the error amplifier's finite gain and its offset, at every corner and load." }, { "key": "i_q", "label": "Quiescent current", "unit": "A", "direction": "min", "constraint": "<= 0.0001 A", "min": null, "max": 0.0001, "why": "Bias, tail and the 30 µA the divider must draw to keep MP's hot leakage from lifting the unloaded output: 2 % of the full load." }, { "key": "load_reg", "label": "Load regulation", "unit": "V/A", "direction": "min", "constraint": "<= 4 V/A", "min": null, "max": 4, "why": "At most 20 mV from no load to 5 mA. A single gain stage cannot do much better: most of the fall comes at light load, where MP's transconductance is small." }, { "key": "line_reg", "label": "Line regulation", "unit": "%/V", "direction": "min", "constraint": "<= 2 %/V", "min": null, "max": 2, "why": "At most 4.3 mV across the rated 1.08 to 1.32 V input, at the worse of no load and full load." }, { "key": "dropout", "label": "Dropout at full load", "unit": "V", "direction": "min", "constraint": "<= 0.15 V", "min": null, "max": 0.15, "why": "Below the 0.18 V between the output and the lowest rated input, 1.08 V, so the regulator still regulates there at full load." }, { "key": "loop_gain_db", "label": "DC loop gain at full load", "unit": "dB", "direction": "max", "constraint": ">= 35 dB", "min": 35, "max": null, "why": "The loop gain that divides the output resistance and the supply's feedthrough; lowest at full load and low input, where MP is closest to triode." }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 20 dB", "min": 20, "max": null, "why": "At 1 kHz, where the loop gain rejects the ripple; lowest at full load and the lowest input." }, { "key": "vn_out", "label": "Output noise, 10 Hz to 100 kHz", "unit": "V", "direction": "min", "constraint": "<= 0.00004 V", "min": null, "max": 0.00004, "why": "10 Hz to 100 kHz, rms: the input pair's noise, multiplied by 1.5 through the divider." }, { "key": "loop_ugf_hz", "label": "Loop crossover at full load", "unit": "Hz", "direction": "max", "constraint": ">= 200000 Hz", "min": 200000, "max": null, "why": "Set by the error amplifier's transconductance over Cc, a little higher where Cf's lead lifts the loop gain." }, { "key": "loop_pm_deg", "label": "Loop phase margin, worst load", "unit": "deg", "direction": "max", "constraint": ">= 50 deg", "min": 50, "max": null, "why": "At every load, the worst at no load: there the output pole is lowest and the right-half-plane zero g_m,MP/Cc nearest the crossover, and Cf's lead is what holds the margin." }, { "key": "ring_pct", "label": "Ringing after a kick, worst load", "unit": "%", "direction": "min", "constraint": "<= 5 %", "min": null, "max": 5, "why": "No load of the range may leave the output ringing after a small step - the test for a loop the margin cannot see." }, { "key": "undershoot", "label": "Undershoot on the load step", "unit": "V", "direction": "min", "constraint": "<= 0.18 V", "min": null, "max": 0.18, "why": "For a 0 to 5 mA step in 1 µs on 100 pF, the loop alone holding the output." }, { "key": "overshoot", "label": "Overshoot on the load release", "unit": "V", "direction": "min", "constraint": "<= 0.22 V", "min": null, "max": 0.22, "why": "For the release: the amplifier slews the gate back up against Cc with its tail current." }, { "key": "t_recover", "label": "Settling after the load step", "unit": "s", "direction": "min", "constraint": "<= 0.000004 s", "min": null, "max": 0.000004, "why": "Back within 1 % of the output after the step." }, { "key": "t_release", "label": "Settling after the load release", "unit": "s", "direction": "min", "constraint": "<= 0.000005 s", "min": null, "max": 0.000005, "why": "Back within 1 % after the release, at no load, where the margin is least." }, { "key": "line_step", "label": "Output step for an input step", "unit": "V", "direction": "min", "constraint": "<= 0.12 V", "min": null, "max": 0.12, "why": "For the input stepped across its whole rated range in 1 µs at full load, with no large capacitor to absorb it." } ], "explanation": { "idea": "Regulates 1.2 V down to about 0.9 V with a small output capacitor. A capacitor across the PMOS pass device separates the loop's poles; another across the feedback divider adds phase lead. This saves a large output capacitor but offers limited extra phase margin.", "detail": "A PMOS-pass LDO compensated from inside for a 100 pF load, with no zero resistor. Cc straight from the pass device's gate to its drain splits the poles, and leaves a right-half-plane zero at g_m,MP/Cc that takes phase near the crossover at light load. Cf across the divider's upper resistor gives phase back from the feedback side: above 1/(2π R1 Cf) the divider passes more of the output to div, a zero-pole pair that leads the phase. The rest is the basic LDO's core: 0.9 V from 1.2 V at up to 5 mA.", "lesson": { "relation": 0, "symbols": "β(s) is the feedback divider's frequency-dependent gain; s is complex frequency in radians per second; R1 is one divider unit; Cf is the feed-forward capacitor; ∥ means a parallel resistance.", "assumptions": "Three equal divider resistors, negligible input loading and ideal capacitor behavior. This relation describes the divider, not every pole and zero in the regulator.", "exercise": { "param": "Cf", "value": 4e-11, "analysis": "loop", "expect": "Doubling Cf moves the divider's zero and pole to half their frequencies. The phase lead moves lower; phase margin need not improve if it no longer aligns with crossover." }, "limits": "Cf supplies limited phase lead and does not remove the pass stage's right-half-plane zero. The default load is 100 pF; reference, bias and sense connection are external." }, "path": [ { "part": "Feedback divider", "devices": "R1, R2, R3", "does": "Three copies of one resistor, one above div and two below: div is two thirds of the output, and the loop holds it at V_ref. Their 30 µA are also the least MP ever carries." }, { "part": "Feed-forward capacitor", "devices": "Cf, R1", "does": "Cf bypasses R1: the feedback factor rises from 2/3 towards 1 between its zero and its pole, and the loop gains up to 11.5° of phase there." }, { "part": "Error amplifier", "devices": "M1, M2, M3, M4, MT", "does": "M1 takes div and M2 the reference, on the tail MT; the mirror M3, M4 turns M1's current round onto gate, so a rise in div lifts gate." }, { "part": "Pass device", "devices": "MP", "does": "A common-source PMOS from the input to the output: a higher gate means less current, so the output falls back." }, { "part": "Miller compensation", "devices": "Cc, MP", "does": "Cc across MP makes gate the dominant pole and sets the crossover; with nothing in series it also feeds gate forward to the output, a right-half-plane zero." } ], "bias": "Ib, 10 µA from outside, flows into the diode MB; the tail MT is N copies of it, 40 µA. The reference is an input, 0.6 V, and the supply is 1.2 V (1.08 to 1.32 V).", "relations": [ { "what": "Feedback factor", "expr": "β(s) = (2/3) · (1 + s · R1 · Cf)/(1 + s · (R1 ∥ 2R1) · Cf)", "note": "A zero at 1/(2π · R1 · Cf) and a pole 1.5 times higher: the most lead such a pair gives is asin(1/5) = 11.5°." }, { "what": "Crossover", "expr": "f_c ≈ β · g_m2/(2π · Cc)", "note": "Slightly higher where Cf has lifted β." }, { "what": "Right-half-plane zero", "expr": "f_z = g_m,MP/(2π · Cc)", "note": "Lowest at no load, where it costs the most phase: the margin is least there." } ], "tradeoffs": [ "Cf: placed so its pair sits at the no-load crossover it adds its full lead; much larger and the pair slides below the crossover and gives nothing back.", "Cc: larger lowers the crossover and the right-half-plane zero together - their ratio is approximately g_m,MP/(β g_m2) - so it buys margin mainly through the output pole.", "Compared with a zero resistor, Cf cannot move the zero at all; it can only lead the phase a little, which gives about 64° versus 93° worst-load phase margin for the two default designs at the nominal condition." ] }, "sizing": [ { "key": "Ib", "label": "Bias current", "unit": "A", "value": 0.00001, "min": 0.000001, "max": 0.00005, "kind": "si" }, { "key": "N", "label": "Tail current, in Ib", "unit": "", "value": 4, "min": 1, "max": 16, "kind": "int" }, { "key": "Wn", "label": "W NMOS bias unit (MB, MT)", "unit": "m", "value": 0.000004, "min": 5e-7, "max": 0.00002, "kind": "si" }, { "key": "Ln", "label": "L NMOS bias unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "W1", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.00004, "min": 0.000001, "max": 0.0001, "kind": "si" }, { "key": "L1", "label": "L input pair", "unit": "m", "value": 0.000004, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Wp", "label": "W mirror (M3, M4)", "unit": "m", "value": 0.0002, "min": 0.000001, "max": 0.0004, "kind": "si" }, { "key": "Lp", "label": "L mirror", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wpass", "label": "W pass device", "unit": "m", "value": 0.0012, "min": 0.00005, "max": 0.005, "kind": "si" }, { "key": "Lpass", "label": "L pass device", "unit": "m", "value": 2e-7, "min": 1.3e-7, "max": 0.000001, "kind": "si" }, { "key": "Ru", "label": "Divider unit resistor", "unit": "Ω", "value": 10000, "min": 2000, "max": 200000, "kind": "si" }, { "key": "Vref", "label": "Reference", "unit": "V", "value": 0.6, "min": 0.45, "max": 0.75, "kind": "si" }, { "key": "IL", "label": "Full load", "unit": "A", "value": 0.005, "min": 0.0005, "max": 0.02, "kind": "si" }, { "key": "Cc", "label": "Miller capacitor", "unit": "F", "value": 5e-11, "min": 1e-12, "max": 2e-10, "kind": "si" }, { "key": "Cf", "label": "Feed-forward capacitor", "unit": "F", "value": 2e-11, "min": 1e-13, "max": 1e-10, "kind": "si" }, { "key": "CL", "label": "Load capacitance", "unit": "F", "value": 1e-10, "min": 1e-11, "max": 1e-9, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The regulator at its nominal input and its lightest load: the output it holds and the current it draws to hold it.", "measures": [], "metricKeys": [ "vout", "i_q" ], "acceptance": [ "vout", "i_q" ], "acceptanceRules": [ { "key": "vout", "unit": "V", "min": 0.88, "max": 0.92, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "i_q", "unit": "A", "min": null, "max": 0.0001, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* PMOS LDO, Miller and feed-forward compensated - operating point at the lightest load\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldomff ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4\n* error amplifier: div on the diode side, so a rise in div lifts gate\nXM1 d1 div tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate ref tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\n* the divider: three copies of one resistor, one above div and two below\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div dv vss rppd w=0.5u l=19.417u\nXR3 dv vss vss rppd w=0.5u l=19.417u\n* Miller compensation across the pass device\nXCc gate out cap_cmim w=29.962u l=29.962u m=37\n* the feed-forward capacitor across the top of the divider\nXCf sense div cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldomff\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 0\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.op\n.end" }, { "id": "load_reg", "label": "Load regulation", "note": "The load is swept from lightest to full at nominal input. Regulation is the magnitude of the endpoint output change per ampere; a large output rise fails just as a large fall does.", "measures": [], "metricKeys": [ "load_reg" ], "acceptance": [ "load_reg" ], "acceptanceRules": [ { "key": "load_reg", "unit": "V/A", "min": null, "max": 4, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* PMOS LDO, Miller and feed-forward compensated - output against load current\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldomff ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4\n* error amplifier: div on the diode side, so a rise in div lifts gate\nXM1 d1 div tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate ref tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\n* the divider: three copies of one resistor, one above div and two below\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div dv vss rppd w=0.5u l=19.417u\nXR3 dv vss vss rppd w=0.5u l=19.417u\n* Miller compensation across the pass device\nXCc gate out cap_cmim w=29.962u l=29.962u m=37\n* the feed-forward capacitor across the top of the divider\nXCf sense div cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldomff\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 0\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.dc Vload 0 5m 50u\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc v_light FIND v(out) AT=0\n.meas dc v_full FIND v(out) AT=5m\n.end" }, { "id": "line_reg", "label": "Line regulation", "note": "The input swept across its rated range, at the lightest and at the full load: how much of the input's change reaches the output.", "measures": [], "metricKeys": [ "line_reg" ], "acceptance": [ "line_reg" ], "acceptanceRules": [ { "key": "line_reg", "unit": "%/V", "min": null, "max": 2, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* PMOS LDO, Miller and feed-forward compensated - output against input voltage\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n* the input swept across its rated range, 1.08V to 1.32V\nVdd vdd 0 dc 1.2\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldomff ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4\n* error amplifier: div on the diode side, so a rise in div lifts gate\nXM1 d1 div tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate ref tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\n* the divider: three copies of one resistor, one above div and two below\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div dv vss rppd w=0.5u l=19.417u\nXR3 dv vss vss rppd w=0.5u l=19.417u\n* Miller compensation across the pass device\nXCc gate out cap_cmim w=29.962u l=29.962u m=37\n* the feed-forward capacitor across the top of the divider\nXCf sense div cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldomff\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 0\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n* the input swept at each of two loads: the lightest, then the full load\n.dc Vdd 1.08 1.32 5m Vload 0 5m 5m\n.end" }, { "id": "dropout", "label": "Dropout", "note": "The input lowered at full load until the output has fallen 2 % below the level it holds at the nominal input: the input-to-output voltage left there is the dropout.", "measures": [], "metricKeys": [ "dropout" ], "acceptance": [ "dropout" ], "acceptanceRules": [ { "key": "dropout", "unit": "V", "min": null, "max": 0.15, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* PMOS LDO, Miller and feed-forward compensated - dropout at full load\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n* the input swept down to below the output: 600mV to 1.32V\nVdd vdd 0 dc 1.2\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldomff ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4\n* error amplifier: div on the diode side, so a rise in div lifts gate\nXM1 d1 div tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate ref tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\n* the divider: three copies of one resistor, one above div and two below\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div dv vss rppd w=0.5u l=19.417u\nXR3 dv vss vss rppd w=0.5u l=19.417u\n* Miller compensation across the pass device\nXCc gate out cap_cmim w=29.962u l=29.962u m=37\n* the feed-forward capacitor across the top of the divider\nXCf sense div cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldomff\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 5m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.dc Vdd 600m 1.32 3.6m\n.end" }, { "id": "loop", "label": "Loop gain", "note": "The loop gain at loads across the whole range, from the lightest to the full load: the loop is cut at the sense line and measured by Middlebrook's double injection - a voltage in series there, then a current into out - which gives it exactly, with every loading in place. The phase and gain margins are the worst over the loads.", "measures": [], "metricKeys": [ "loop_gain_db", "loop_ugf_hz", "loop_pm_deg", "loop_gm_db" ], "acceptance": [ "loop_gain_db", "loop_ugf_hz", "loop_pm_deg" ], "acceptanceRules": [ { "key": "loop_gain_db", "unit": "dB", "min": 35, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "loop_ugf_hz", "unit": "Hz", "min": 200000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "loop_pm_deg", "unit": "deg", "min": 50, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* PMOS LDO, Miller and feed-forward compensated - loop gain at 5mA, voltage injection\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldomff ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4\n* error amplifier: div on the diode side, so a rise in div lifts gate\nXM1 d1 div tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate ref tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\n* the divider: three copies of one resistor, one above div and two below\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div dv vss rppd w=0.5u l=19.417u\nXR3 dv vss vss rppd w=0.5u l=19.417u\n* Miller compensation across the pass device\nXCc gate out cap_cmim w=29.962u l=29.962u m=37\n* the feed-forward capacitor across the top of the divider\nXCf sense div cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldomff\n* the sense line cut by a 1 V ac source in series: T_v = -v(out)/v(sense)\nVinj sense out dc 0 ac 1\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 5m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.ac dec 20 0.1 1g\n.end" }, { "id": "ring", "label": "Ringing across the loads", "note": "The loads the loop bench visits, in a staircase from the lightest to the full load; at each, once the output has settled, a small step - a tenth more load. How far the output overshoots its new level on the way back, and what is left moving at the end of each step, show whether the regulator is damped at that load: a loop inside it that the sense line does not pass through, and so the loop gain cannot see, shows here.", "measures": [], "metricKeys": [ "ring_pct" ], "acceptance": [ "ring_pct" ], "acceptanceRules": [ { "key": "ring_pct", "unit": "%", "min": null, "max": 5, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* PMOS LDO, Miller and feed-forward compensated - a small load step at each load\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldomff ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4\n* error amplifier: div on the diode side, so a rise in div lifts gate\nXM1 d1 div tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate ref tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\n* the divider: three copies of one resistor, one above div and two below\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div dv vss rppd w=0.5u l=19.417u\nXR3 dv vss vss rppd w=0.5u l=19.417u\n* Miller compensation across the pass device\nXCc gate out cap_cmim w=29.962u l=29.962u m=37\n* the feed-forward capacitor across the top of the divider\nXCf sense div cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldomff\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 pwl(0 0 8u 0 8.4u 20u 20u 20u 20.4u 5u 28u 5u 28.4u 25u 40u 25u 40.4u 50u 48u 50u 48.4u 70u 60u 70u 60.4u 500u 68u 500u 68.4u 550u 80u 550u 80.4u 5m 88u 5m 88.4u 5.5m 100u 5.5m)\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.tran 10n 100u\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on the input, at the lightest and at the full load: how much of it reaches the output.", "measures": [], "metricKeys": [ "psrr_db", "psrr_hf_db" ], "acceptance": [ "psrr_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 20, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* PMOS LDO, Miller and feed-forward compensated - supply rejection at 5mA\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD} ac 1\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldomff ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4\n* error amplifier: div on the diode side, so a rise in div lifts gate\nXM1 d1 div tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate ref tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\n* the divider: three copies of one resistor, one above div and two below\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div dv vss rppd w=0.5u l=19.417u\nXR3 dv vss vss rppd w=0.5u l=19.417u\n* Miller compensation across the pass device\nXCc gate out cap_cmim w=29.962u l=29.962u m=37\n* the feed-forward capacitor across the top of the divider\nXCf sense div cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldomff\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 5m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.ac dec 20 1 100meg\n.end" }, { "id": "load_step", "label": "Load step", "note": "The load stepped from the lightest to the full load and back, each edge 1.00 µs: how far the output dips and peaks, and how long it takes to settle within 1 % after each edge. A loop that rings or oscillates at either load shows here, whatever the loop gain says.", "measures": [], "metricKeys": [ "undershoot", "overshoot", "t_recover", "t_release" ], "acceptance": [ "undershoot", "overshoot", "t_recover", "t_release" ], "acceptanceRules": [ { "key": "undershoot", "unit": "V", "min": null, "max": 0.18, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "overshoot", "unit": "V", "min": null, "max": 0.22, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "t_recover", "unit": "s", "min": null, "max": 0.000004, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "t_release", "unit": "s", "min": null, "max": 0.000005, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* PMOS LDO, Miller and feed-forward compensated - load step\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldomff ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4\n* error amplifier: div on the diode side, so a rise in div lifts gate\nXM1 d1 div tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate ref tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\n* the divider: three copies of one resistor, one above div and two below\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div dv vss rppd w=0.5u l=19.417u\nXR3 dv vss vss rppd w=0.5u l=19.417u\n* Miller compensation across the pass device\nXCc gate out cap_cmim w=29.962u l=29.962u m=37\n* the feed-forward capacitor across the top of the divider\nXCf sense div cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldomff\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 pulse(0 5m 4u 1u 1u 17u 80u)\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.tran 8n 40u\n.end" }, { "id": "line_step", "label": "Line step", "note": "The input stepped across its rated range, 1.08 V to 1.32 V, and back, each edge 1.00 µs, at full load: how far the output moves.", "measures": [], "metricKeys": [ "line_step" ], "acceptance": [ "line_step" ], "acceptanceRules": [ { "key": "line_step", "unit": "V", "min": null, "max": 0.12, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* PMOS LDO, Miller and feed-forward compensated - line step at full load\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n* the input steps across its rated range and back\nVdd vdd 0 pulse(1.08 1.32 4u 1u 1u 17u 80u)\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldomff ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4\n* error amplifier: div on the diode side, so a rise in div lifts gate\nXM1 d1 div tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate ref tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\n* the divider: three copies of one resistor, one above div and two below\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div dv vss rppd w=0.5u l=19.417u\nXR3 dv vss vss rppd w=0.5u l=19.417u\n* Miller compensation across the pass device\nXCc gate out cap_cmim w=29.962u l=29.962u m=37\n* the feed-forward capacitor across the top of the divider\nXCf sense div cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldomff\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 5m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.tran 8n 40u\n.end" }, { "id": "noise", "label": "Output noise", "note": "The noise at the output at full load: its density at 1 kHz and its total from 10 Hz to 100 kHz. The reference is an ideal, noiseless source, so this is the regulator's own noise.", "measures": [], "metricKeys": [ "vn_out", "vn_out_1k" ], "acceptance": [ "vn_out" ], "acceptanceRules": [ { "key": "vn_out", "unit": "V", "min": null, "max": 0.00004, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* PMOS LDO, Miller and feed-forward compensated - output noise at full load\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\n* ac 1 only because ngspice's noise analysis names an input; the output noise does not depend on it\nVdd vdd 0 dc {VDD} ac 1\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldomff ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4\n* error amplifier: div on the diode side, so a rise in div lifts gate\nXM1 d1 div tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate ref tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\n* the divider: three copies of one resistor, one above div and two below\nXR1 sense div vss rppd w=0.5u l=19.417u\nXR2 div dv vss rppd w=0.5u l=19.417u\nXR3 dv vss vss rppd w=0.5u l=19.417u\n* Miller compensation across the pass device\nXCc gate out cap_cmim w=29.962u l=29.962u m=37\n* the feed-forward capacitor across the top of the divider\nXCf sense div cap_cmim w=29.761u l=29.761u m=15\n.ends\nXdut ref sense out vdd 0 ib ldomff\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 5m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.control\nnoise v(out) Vdd dec 20 10 100k\nsetplot noise1\n* 20 points a decade from 10 Hz: point 40 is 1 kHz\nlet vn_1k = onoise_spectrum[40]\nprint vn_1k\nsetplot noise2\nprint onoise_total\n.endc\n.op\n.end" } ], "measurements": { "vout": { "label": "Output voltage", "unit": "V", "spec": { "min": 0.88, "max": 0.92 } }, "i_q": { "label": "Quiescent current", "unit": "A", "spec": { "min": null, "max": 0.0001 } }, "load_reg": { "label": "Load regulation", "unit": "V/A", "spec": { "min": null, "max": 4 } }, "line_reg": { "label": "Line regulation", "unit": "%/V", "spec": { "min": null, "max": 2 } }, "dropout": { "label": "Dropout at full load", "unit": "V", "spec": { "min": null, "max": 0.15 } }, "loop_gain_db": { "label": "DC loop gain at full load", "unit": "dB", "spec": { "min": 35, "max": null } }, "psrr_db": { "label": "Supply rejection at 1 kHz", "unit": "dB", "spec": { "min": 20, "max": null } }, "vn_out": { "label": "Output noise, 10 Hz to 100 kHz", "unit": "V", "spec": { "min": null, "max": 0.00004 } }, "loop_ugf_hz": { "label": "Loop crossover at full load", "unit": "Hz", "spec": { "min": 200000, "max": null } }, "loop_pm_deg": { "label": "Loop phase margin, worst load", "unit": "deg", "spec": { "min": 50, "max": null } }, "ring_pct": { "label": "Ringing after a kick, worst load", "unit": "%", "spec": { "min": null, "max": 5 } }, "undershoot": { "label": "Undershoot on the load step", "unit": "V", "spec": { "min": null, "max": 0.18 } }, "overshoot": { "label": "Overshoot on the load release", "unit": "V", "spec": { "min": null, "max": 0.22 } }, "t_recover": { "label": "Settling after the load step", "unit": "s", "spec": { "min": null, "max": 0.000004 } }, "t_release": { "label": "Settling after the load release", "unit": "s", "spec": { "min": null, "max": 0.000005 } }, "line_step": { "label": "Output step for an input step", "unit": "V", "spec": { "min": null, "max": 0.12 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "df0d3e1651bca3ea16db37d05184b515d422963be384d0dd78ac2d52f74ce540" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ldo-miller-cff.js", "sha256": "a4c2c7cd88ab71b3e5ea8f34ed43c866d96f7ba0fcc548635fbb0f754e6f1594" }, "simulationFingerprints": { "op": "8cb365d2fdbad0e2ac7516b99dfd155680500601442d8af4416935b50ef083ea", "load_reg": "82aeb715c87671b2e3d05ae95b624e733f2735d951b8e254ca165fa47ed5b93e", "line_reg": "b1b5a230fa349d06c5333197c3aeefe02f5f06c00e77b172c6a27da1c5450d2c", "dropout": "82ed49323057b305dbd5eb4cf99f16631c44ce47cc12348254d78fffff9fef73", "loop": "47d6473a54c2c6ad1b9bb40019601533681d7631a98003b89c0baa894f3f437d", "ring": "05bae41e2aa1af97fe53a7acb5fd1d6a02ab0ba1cc226cd03afd36f284a9978e", "psrr": "f7c4583d33616ad38256e564e31c0e2a0491770365dc40f1b15a82291ccae8a9", "load_step": "4005c4b76ccc80172f562992639201d98d4eb3fad4219eb429844cf8edb751b2", "line_step": "4298942ba12a28edda36df460965316ebdf30d9c506fde048f700539246e8eeb", "noise": "49c4c5cf59716522c0e184d1dc395328a8b627f3dfa42029c8d838ad83c51dd9" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "5914348124b942fdd8d45224dceecffcad348d944f21999972d0c539cfc40c35", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ldo-miller-cff", "parameters": { "Ib": 0.00001, "N": 4, "Wn": 0.000004, "Ln": 0.000001, "W1": 0.00004, "L1": 0.000004, "Wp": 0.0002, "Lp": 0.000002, "Wpass": 0.0012, "Lpass": 2e-7, "Ru": 10000, "Vref": 0.6, "IL": 0.005, "Cc": 5e-11, "Cf": 2e-11, "CL": 1e-10 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ldo-miller-cff/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "ldomff", "ports": [ { "name": "ref", "net": "ref", "kind": "input" }, { "name": "sense", "net": "sense", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=4", "source": "XMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XM1 d1 div tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "div" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XM2 gate ref tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=200u l=2u ng=40 m=1", "source": "XM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=200u l=2u ng=40 m=1", "source": "XM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.2m l=200n ng=240 m=1", "source": "XMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR1 sense div vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "div" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR2 div dv vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "div" }, { "id": "n", "net": "dv" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR3", "displayName": "R3", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR3 dv vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "dv" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=37", "source": "XCc gate out cap_cmim w=29.962u l=29.962u m=37", "pins": [ { "id": "p", "net": "gate" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.761u l=29.761u m=15", "source": "XCf sense div cap_cmim w=29.761u l=29.761u m=15", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "div" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR2", "pin": "substrate" }, { "device": "XR3", "pin": "n" }, { "device": "XR3", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "div", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XR1", "pin": "n" }, { "device": "XR2", "pin": "p" }, { "device": "XCf", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCc", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XR1", "pin": "p" }, { "device": "XCf", "pin": "p" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "dv", "ground": false, "terminals": [ { "device": "XR2", "pin": "n" }, { "device": "XR3", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vref ref 0 dc 600m", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 10u", "source": "Ib vdd ib dc 10u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldomff", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldomff", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldomff" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "100p", "source": "Cl out 0 100p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vload il 0 dc 0", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldomff", "name": "ldomff", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=4", "source": "XMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XM1 d1 div tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "div" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XM2 gate ref tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=200u l=2u ng=40 m=1", "source": "XM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=200u l=2u ng=40 m=1", "source": "XM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.2m l=200n ng=240 m=1", "source": "XMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR1 sense div vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "div" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR2 div dv vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "div" }, { "id": "n", "net": "dv" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR3", "displayName": "R3", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR3 dv vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "dv" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=37", "source": "XCc gate out cap_cmim w=29.962u l=29.962u m=37", "pins": [ { "id": "p", "net": "gate" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.761u l=29.761u m=15", "source": "XCf sense div cap_cmim w=29.761u l=29.761u m=15", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "div" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR2", "pin": "substrate" }, { "device": "XR3", "pin": "n" }, { "device": "XR3", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "div", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XR1", "pin": "n" }, { "device": "XR2", "pin": "p" }, { "device": "XCf", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCc", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XR1", "pin": "p" }, { "device": "XCf", "pin": "p" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "dv", "ground": false, "terminals": [ { "device": "XR2", "pin": "n" }, { "device": "XR3", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldomff" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Bias reference", "devices": [ { "scope": "dut", "device": "XMB" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "Error amplifier tail", "devices": [ { "scope": "dut", "device": "XMT" } ], "inferredStages": [ 1 ] }, { "id": "block-3", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 2, 1 ] }, { "id": "block-4", "label": "Mirror load", "devices": [ { "scope": "dut", "device": "XM3" }, { "scope": "dut", "device": "XM4" } ], "inferredStages": [ 2, 1 ] }, { "id": "block-5", "label": "Pass device", "devices": [ { "scope": "dut", "device": "XMP" } ], "inferredStages": [ 2 ] }, { "id": "block-6", "label": "Divider", "devices": [ { "scope": "dut", "device": "XR1" }, { "scope": "dut", "device": "XR2" }, { "scope": "dut", "device": "XR3" } ], "inferredStages": [ 1 ] }, { "id": "block-7", "label": "Miller capacitor across the pass device", "devices": [ { "scope": "dut", "device": "XCc" } ], "inferredStages": [ "comp" ] }, { "id": "block-8", "label": "Feed-forward capacitor across R1", "devices": [ { "scope": "dut", "device": "XCf" } ], "inferredStages": [ 1 ] } ], "edges": [ { "id": "net-1", "net": "ib", "nodes": [ "block-1", "block-2" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "tail", "nodes": [ "block-2", "block-3" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "d1", "nodes": [ "block-3", "block-4" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "div", "nodes": [ "block-3", "block-6", "block-8" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "gate", "nodes": [ "block-3", "block-4", "block-5", "block-7" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "out", "nodes": [ "block-5", "block-7" ], "direction": "undirected-shared-net" }, { "id": "net-7", "net": "sense", "nodes": [ "block-6", "block-8" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "ref", "net": "ref", "kind": "input" }, { "name": "sense", "net": "sense", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [], "scopes": [ { "id": "dut", "name": "ldomff", "ports": [ { "name": "ref", "net": "ref", "kind": "input" }, { "name": "sense", "net": "sense", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=4", "source": "XMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XM1 d1 div tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "div" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XM2 gate ref tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=200u l=2u ng=40 m=1", "source": "XM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=200u l=2u ng=40 m=1", "source": "XM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.2m l=200n ng=240 m=1", "source": "XMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR1 sense div vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "div" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR2 div dv vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "div" }, { "id": "n", "net": "dv" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR3", "displayName": "R3", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR3 dv vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "dv" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=37", "source": "XCc gate out cap_cmim w=29.962u l=29.962u m=37", "pins": [ { "id": "p", "net": "gate" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.761u l=29.761u m=15", "source": "XCf sense div cap_cmim w=29.761u l=29.761u m=15", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "div" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR2", "pin": "substrate" }, { "device": "XR3", "pin": "n" }, { "device": "XR3", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "div", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XR1", "pin": "n" }, { "device": "XR2", "pin": "p" }, { "device": "XCf", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCc", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XR1", "pin": "p" }, { "device": "XCf", "pin": "p" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "dv", "ground": false, "terminals": [ { "device": "XR2", "pin": "n" }, { "device": "XR3", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ] }, { "id": "graph-5", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.2", "source": "Vdd vdd 0 dc 1.2", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vref ref 0 dc 600m", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 10u", "source": "Ib vdd ib dc 10u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldomff", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldomff", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldomff" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "100p", "source": "Cl out 0 100p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vload il 0 dc 0", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldomff", "name": "ldomff", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=4", "source": "XMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XM1 d1 div tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "div" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XM2 gate ref tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=200u l=2u ng=40 m=1", "source": "XM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=200u l=2u ng=40 m=1", "source": "XM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.2m l=200n ng=240 m=1", "source": "XMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR1 sense div vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "div" }, { "id": "substrate", "net": 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"ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=4", "source": "XMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XM1 d1 div tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "div" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XM2 gate ref tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=200u l=2u ng=40 m=1", "source": "XM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=200u l=2u ng=40 m=1", "source": "XM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.2m l=200n ng=240 m=1", "source": "XMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR1 sense div vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "div" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR2 div dv vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "div" }, { "id": "n", "net": "dv" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR3", "displayName": "R3", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR3 dv vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "dv" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.962u l=29.962u m=37", "source": "XCc gate out cap_cmim w=29.962u l=29.962u m=37", "pins": [ { "id": "p", "net": "gate" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.761u l=29.761u m=15", "source": "XCf sense div cap_cmim w=29.761u l=29.761u m=15", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "div" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XR1", "pin": "substrate" }, { "device": "XR2", "pin": "substrate" }, { "device": "XR3", "pin": "n" }, { "device": "XR3", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "div", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XR1", "pin": "n" }, { "device": "XR2", "pin": "p" }, { "device": "XCf", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "gate", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "ref" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XCc", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "XR1", "pin": "p" }, { "device": "XCf", "pin": "p" } ], "ports": [ "sense" ], "voltageReferences": [] }, { "id": "dv", "ground": false, "terminals": [ { "device": "XR2", "pin": "n" }, { "device": "XR3", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ldomff" } }, { "id": "graph-8", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vref ref 0 dc 600m", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 10u", "source": "Ib vdd ib dc 10u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldomff", "parametersOrValue": "", "source": "Xdut ref sense out vdd 0 ib ldomff", "pins": [ { "id": "ref", "net": "ref" }, { "id": "sense", "net": "sense" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldomff" }, { "id": "Vsense", "displayName": "Vsense", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vsense sense out 0", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "100p", "source": "Cl out 0 100p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vload", "displayName": "Vload", "spiceType": "V", "model": null, "parametersOrValue": "pwl(0 0 8u 0 8.4u 20u 20u 20u 20.4u 5u 28u 5u 28.4u 25u 40u 25u 40.4u 50u 48u 50u 48.4u 70u 60u 70u 60.4u 500u 68u 500u 68.4u 550u 80u 550u 80.4u 5m 88u 5m 88.4u 5.5m 100u 5.5m)", "source": "Vload il 0 pwl(0 0 8u 0 8.4u 20u 20u 20u 20.4u 5u 28u 5u 28.4u 25u 40u 25u 40.4u 50u 48u 50u 48.4u 70u 60u 70u 60.4u 500u 68u 500u 68.4u 550u 80u 550u 80.4u 5m 88u 5m 88.4u 5.5m 100u 5.5m)", "pins": [ { "id": "p", "net": "il" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Bload", "displayName": "Bload", "spiceType": "B", "model": null, "parametersOrValue": "i=v(il)*min(1, max(v(out), 0)/0.05)", "source": "Bload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order", "expressionDependencies": { "voltageNets": [ "il", "out" ], "currentDevices": [] } } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vload", "pin": "n" }, { "device": "Bload", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldomff", "name": "ldomff", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": "sense" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=4", "source": "XMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XM1 d1 div tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "div" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XM2 gate ref tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "ref" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=200u l=2u ng=40 m=1", "source": "XM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=200u l=2u ng=40 m=1", "source": "XM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.2m l=200n ng=240 m=1", "source": "XMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR1 sense div vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "sense" }, { "id": "n", "net": "div" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR2", "displayName": "R2", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR2 div dv vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "div" }, { "id": "n", "net": "dv" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XR3", "displayName": "R3", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=19.417u", "source": "XR3 dv vss vss rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "dv" }, { "id": "n", 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