{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ldo-ref-amp", "name": "LDO reference amplifier, self-biased", "group": "Op amps and OTAs", "subgroup": "Two-stage op amps", "title": "LDO reference amplifier, self-biased", "summary": "Buffers a voltage reference so it can drive a regulator's error amplifier. A two-stage amplifier uses feedback to copy the input while drawing its bias from two supply-connected diodes. No bias-current input is needed, but its current and bandwidth vary with supply and process.", "reference": { "kind": "paper", "authors": "Texas Instruments", "title": "TPS7A21 500-mA, Low-Noise, Low-IQ, High-PSRR LDO", "year": 2022, "where": "Texas Instruments datasheet SBVS398A, Rev. A (original Dec. 2021)", "publisher": "Texas Instruments", "takes": "The application: the reference amplifier of a low-dropout regulator of that kind, which carries the reference voltage to the error amplifier, so its offset, noise and supply rejection reach the regulated output. The circuit - a self-biased two-stage Miller op amp - its sizing for the library's 0.76 V bandgap and 1.2 V supply, and its spec targets are this library's." }, "resources": { "record": "/circuits/ldo-ref-amp.json", "page": "/index.html#ldo-ref-amp", "achieved": "/achieved/ldo-ref-amp.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "inp", "kind": "input" }, { "name": "inn", "kind": "input" }, { "name": "out", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" } ], "devices": [ { "name": "MP", "type": "pmos", "nodes": "nx nx vdd vdd", "sizedBy": [ "Wbp", "Lbp" ], "role": "bias: PMOS diode, the upper half of the stack across the supply", "fingers": 1, "copies": 1 }, { "name": "MN", "type": "nmos", "nodes": "nx nx vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "bias: NMOS diode, the lower half; the unit the tail and the sink copy", "fingers": 1, "copies": 1 }, { "name": "MT", "type": "nmos", "nodes": "tail nx vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "tail current source, two copies of MN", "fingers": 1, "copies": 2 }, { "name": "M1", "type": "nmos", "nodes": "d1 inn tail vss", "sizedBy": [ "W1", "L1" ], "role": "input pair, inverting input, on the mirror's diode side", "fingers": 4, "copies": 1 }, { "name": "M2", "type": "nmos", "nodes": "d2 inp tail vss", "sizedBy": [ "W1", "L1" ], "role": "input pair, non-inverting input", "fingers": 4, "copies": 1 }, { "name": "M3", "type": "pmos", "nodes": "d1 d1 vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "mirror load, diode-connected", "fingers": 6, "copies": 1 }, { "name": "M4", "type": "pmos", "nodes": "d2 d1 vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "mirror load, first-stage output", "fingers": 6, "copies": 1 }, { "name": "M5", "type": "pmos", "nodes": "out d2 vdd vdd", "sizedBy": [ "Wp", "Lp", "S" ], "role": "second stage, common source; S copies of the mirror unit", "fingers": 6, "copies": 4 }, { "name": "M6", "type": "nmos", "nodes": "out nx vss vss", "sizedBy": [ "Wn", "Ln", "S" ], "role": "second-stage sink, S copies of MN", "fingers": 1, "copies": 4 }, { "name": "Cc", "type": "capacitor", "nodes": "d2 cz", "sizedBy": [ "Cc" ], "role": "Miller compensation" }, { "name": "Rz", "type": "resistor", "nodes": "cz out", "sizedBy": [ "Rz" ], "role": "nulling resistor" } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "The input pair: any difference is input offset, and in a reference amplifier offset is an error in the regulated voltage. 20 × 2 µm each: about 1 mV σ with the mirror." }, { "rule": "match", "of": [ "M3", "M4" ], "why": "The mirror load: a mismatch copies the wrong current to d2 and appears as offset." }, { "rule": "self-bias", "of": [ "MP", "MN" ], "constraint": "V_SG,MP + V_GS,MN = V_DD", "why": "The two diodes in series across the supply fix the reference current with no bias pin. MP is long and strongly inverted, so it takes most of V_DD and most of its variation, and MN, near weak inversion, sits at a steady V_GS; even so the current spans about 3:1 over the corners, and every figure is set to hold at both ends." }, { "rule": "unit-copies", "of": [ "MN", "MT", "M6" ], "constraint": "MT = 2 copies of MN, M6 = S copies", "why": "The tail and the output sink are copies of the one reference device, so all the currents rise and fall together with the self-set reference, and the phase margin - a ratio of g_m - holds while the bandwidth moves." }, { "rule": "ratio", "of": [ "M5", "M4", "M6", "MT" ], "constraint": "M5 = S copies of the M3/M4 unit", "why": "Each mirror device carries one MN current, M6 sinks S of them, so S copies of the mirror unit carry M6's current at the mirror's density: d2 rests at d1's voltage and the systematic offset is about 0.1 mV." }, { "rule": "input-range", "of": [ "M3", "M4", "M1", "M2" ], "constraint": "V_DD − V_SG3 ≥ V_CM − V_GS1 + V_DSAT1 with V_DD 10 % low", "why": "The pair's drains hang a mirror V_SG below the supply, and at the 0.76 V reference the pair must stay saturated even at 1.08 V. A strongly inverted mirror, at 0.56 V of V_SG, stops the range at 0.75 V there - short of the reference; weakly inverted, at 0.39 V, it reaches 0.87 V." }, { "rule": "zero", "of": [ "Rz", "Cc", "M5" ], "constraint": "R_z just above 1/g_m5 where the current is lowest", "why": "Rz above 1/g_m5 puts the Miller zero in the left half-plane. 1/g_m5 is 3 kΩ at 27 °C and near 5 kΩ at the slow, hot, low corner; 6 kΩ keeps the zero on the left there, above the crossover. At 15 kΩ the zero fell below the crossover at 27 °C and flattened the gain around it." } ], "specs": [ { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.00006 A", "min": null, "max": 0.00006, "why": "Seven times the self-set reference current: 28 µA at 27 °C, but the two diodes across the supply set it from V_DD and the thresholds, so it spans 17 to 51 µA over the corners." }, { "key": "dc_gain_db", "label": "DC open-loop gain", "unit": "dB", "direction": "max", "constraint": ">= 60 dB", "min": 60, "max": null, "why": "Two stages, each limited by its NMOS r_o: 65 dB at 27 °C, 61 dB slow, hot and 10 % low, where every current is lowest." }, { "key": "ugf_hz", "label": "Unity-gain frequency", "unit": "Hz", "direction": "max", "constraint": ">= 1500000 Hz", "min": 1500000, "max": null, "why": "g_m1/(2π C_c) follows the self-set current: 4.6 MHz at 27 °C, 2.0 MHz slow, hot and low." }, { "key": "pm_deg", "label": "Phase margin", "unit": "deg", "direction": "max", "constraint": ">= 65 deg", "min": 65, "max": null, "why": "Every current, and so every g_m, scales with the one reference, so the ratio of output pole to crossover holds: 73° to 82° over the corners." }, { "key": "t_settle", "label": "Settling time, 1 %", "unit": "s", "direction": "min", "constraint": "<= 5e-7 s", "min": null, "max": 5e-7, "why": "A 0.1 V step into the buffer: 146 ns at 27 °C, 272 ns where the current is lowest." }, { "key": "t_settle_fall", "label": "Settling time, 1 %, falling", "unit": "s", "direction": "min", "constraint": "<= 5e-7 s", "min": null, "max": 5e-7, "why": "The falling edge, which the PMOS output stage pulls down only with M6's fixed current: 126 ns at 27 °C, 216 ns at the slow corner." }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 60 dB", "min": 60, "max": null, "why": "The reference current moves with V_DD, but every current moves with it: M5 still matches M4's density, so a ripple barely unbalances the stages. Above 65 dB at every corner and in every draw of seeds 1 to 40." }, { "key": "cmrr_db", "label": "Common-mode rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 60 dB", "min": 60, "max": null, "why": "The tail's output resistance and the pair's match: above 66 dB at every corner." }, { "key": "vn_1k", "label": "Input noise at 1 kHz", "unit": "V/√Hz", "direction": "min", "constraint": "<= 2.5e-7 V/√Hz", "min": null, "max": 2.5e-7, "why": "The reference's own noise passes straight to the regulated output, so the pair (20 × 2 µm) and the mirror (30 × 1.5 µm) are large for their flicker noise: 167 nV/√Hz at 27 °C, 213 nV/√Hz hot." }, { "key": "icmr_lo", "label": "Lowest input common mode", "unit": "V", "direction": "min", "constraint": "<= 0.6 V", "min": null, "max": 0.6, "why": "The tail needs V_GS1 + V_DSAT,T under the input: 0.45 V at 27 °C, 0.50 V at the slow corners." }, { "key": "icmr_hi", "label": "Highest input common mode", "unit": "V", "direction": "max", "constraint": ">= 0.8 V", "min": 0.8, "max": null, "why": "The bandgap's 0.756 V must be inside with room at every corner: the weakly inverted mirror, 0.39 V of V_SG, keeps the pair saturated to 1.01 V, and to 0.87 V with the supply 10 % low." }, { "key": "swing_lo", "label": "Lowest output", "unit": "V", "direction": "min", "constraint": "<= 0.3 V", "min": null, "max": 0.3, "why": "M6 leaves saturation at its V_DSAT, 0.19 V; 0.24 V hot." }, { "key": "swing_hi", "label": "Highest output", "unit": "V", "direction": "max", "constraint": ">= 0.85 V", "min": 0.85, "max": null, "why": "M5 leaves saturation a V_DSAT below the supply: 1.05 V, 0.92 V with the supply 10 % low." } ], "explanation": { "idea": "Buffers a voltage reference so it can drive a regulator's error amplifier. A two-stage amplifier uses feedback to copy the input while drawing its bias from two supply-connected diodes. No bias-current input is needed, but its current and bandwidth vary with supply and process.", "detail": "The amplifier that, in a low-dropout regulator, carries the reference voltage from the bandgap to the error amplifier as a unity-gain buffer - so its offset and noise contribute to output error through the regulator's reference-to-output gain. It is a two-stage Miller op amp: an NMOS pair on a PMOS mirror, then a common-source PMOS, the two gains multiplying, with Cc and its nulling resistor splitting the poles. It has no bias pin: a PMOS and an NMOS diode in series across the supply set its current. That current moves with V_DD and the corners, but every current in the amplifier is a copy of it, so the stages stay balanced and the phase margin holds.", "lesson": { "relation": 2, "symbols": "f_u is unity-gain frequency in hertz; g_m1 is input-device transconductance; C_c is the Miller compensation capacitance.", "assumptions": "Small-signal operation around the default bias, with a dominant Miller pole and adequate output-stage gain. Supply-dependent bias changes g_m1.", "exercise": { "param": "Cc", "value": 4e-12, "analysis": "open_loop", "expect": "Increasing Cc should lower unity-gain frequency. Compare the margin and bandwidth together rather than judging the amplifier by gain alone." }, "limits": "Intended as a unity-gain buffer around a 0.76 V reference from a 1.2 V supply. Its self-set current varies with supply and process, and the input and output are not rail-to-rail." }, "path": [ { "part": "Self-bias", "devices": "MP, MN", "does": "Two diodes in series across the supply: their gate-source voltages add up to V_DD, which fixes the current through both, and MN's gate voltage nx carries it to the copies." }, { "part": "Input pair", "devices": "M1, M2, MT", "does": "MT, two copies of MN, feeds the pair; a rise on inp steers current into M2 and pulls d2 down." }, { "part": "Mirror load", "devices": "M3, M4", "does": "M3 turns M1's current into a gate voltage on d1 and M4 copies it onto d2, where both halves of the signal current meet." }, { "part": "Second stage", "devices": "M5, M6", "does": "Common-source M5, gate on d2, amplifies against M6, S copies of MN, and inverts onto out, so out follows inp." }, { "part": "Compensation", "devices": "Cc, Rz", "does": "Cc from d2 to out, multiplied by the second stage's gain, makes d2 the dominant pole; Rz, just above 1/g_m5, keeps the zero Cc makes in the left half-plane." } ], "bias": "MP, long and strongly inverted, takes 0.85 V of the supply and MN 0.35 V, which sets 3.8 µA at 27 °C - 2.2 µA slow, hot and 10 % low, 6.9 µA fast, cold and 10 % high. MT, two copies of MN, feeds the pair about 4 µA a side; M6, four copies, sinks 17 µA, and M5, four copies of the mirror unit, sources it at the mirror's current density, so d2 rests at d1's voltage. 28 µA in all.", "relations": [ { "what": "Reference current", "expr": "V_SG,MP(I_ref) + V_GS,MN(I_ref) = V_DD", "note": "Two diodes across the supply fix I_ref, so it rises with V_DD and moves with both thresholds: about 3:1 over the corners." }, { "what": "DC gain", "expr": "A_0 ≈ g_m2 (r_o2 ∥ r_o4) · g_m5 (r_o5 ∥ r_o6)", "note": "In both stages the NMOS r_o is the shorter: about 65 dB." }, { "what": "Unity-gain frequency", "expr": "f_u ≈ g_m1/(2π C_c)", "note": "94 µS into 3 pF, about 4.6 MHz; it follows the self-set current, from 2.0 to 12 MHz over the corners." }, { "what": "Compensation zero", "expr": "f_z = 1/[2π C_c (R_z − 1/g_m5)]", "note": "R_z is 6 kΩ against 1/g_m5 of 3 kΩ at 27 °C and about 5 kΩ where the current is lowest: the zero stays in the left half-plane, above the crossover." }, { "what": "Highest input", "expr": "V_CM,max = V_DD − V_SG3 − V_DSAT1 + V_GS1", "note": "The weakly inverted mirror's small V_SG keeps the 0.76 V reference inside the range even with the supply 10 % low: 0.87 V there." }, { "what": "Reduced systematic offset", "expr": "(W/L)_5/(W/L)_3 = I_M6/I_M3 = S", "note": "Repeated units set nominal current density; finite output resistance and mismatch leave residual offset." } ], "tradeoffs": [ "A wider MP raises the reference current and every current with it: more bandwidth and less noise, at a supply current that already spans 3:1 over the corners.", "A larger mirror unit (Wp, Lp) lowers its flicker noise - 219 nV/√Hz at 20 × 1 µm, 167 nV/√Hz at 30 × 1.5 µm - but M5, S copies of it, loads d2 with its gate and pulls the output pole in: at 40 × 2 µm the margin fell to 62° at the fast corner.", "A mirror in stronger inversion lowers its noise contribution further but raises V_SG3, and with it the top of the input range falls below the 0.76 V reference at the low supply.", "Cc: larger lowers the bandwidth and the slew rate and adds phase margin; the current it is charged with moves 3:1 with the corners, so settling does too." ] }, "sizing": [ { "key": "Wbp", "label": "W bias PMOS diode (MP)", "unit": "m", "value": 0.0000028, "min": 1.5e-7, "max": 0.00002, "kind": "si" }, { "key": "Lbp", "label": "L bias PMOS diode", "unit": "m", "value": 0.000008, "min": 1.3e-7, "max": 0.00002, "kind": "si" }, { "key": "Wn", "label": "W NMOS unit (MN, MT, M6)", "unit": "m", "value": 0.000004, "min": 1.5e-7, "max": 0.00005, "kind": "si" }, { "key": "Ln", "label": "L NMOS unit", "unit": "m", "value": 0.000004, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "S", "label": "Second-stage current, in MN's current", "unit": "", "value": 4, "min": 1, "max": 16, "kind": "int" }, { "key": "W1", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.00002, "min": 5e-7, "max": 0.0001, "kind": "si" }, { "key": "L1", "label": "L input pair", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Wp", "label": "W PMOS mirror unit (M3, M4, M5)", "unit": "m", "value": 0.00003, "min": 5e-7, "max": 0.0001, "kind": "si" }, { "key": "Lp", "label": "L PMOS mirror unit", "unit": "m", "value": 0.0000015, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Cc", "label": "Miller capacitor", "unit": "F", "value": 3e-12, "min": 2e-13, "max": 2e-11, "kind": "si" }, { "key": "Rz", "label": "Nulling resistor", "unit": "Ω", "value": 6000, "min": 100, "max": 500000, "kind": "si" }, { "key": "CL", "label": "Load capacitance", "unit": "F", "value": 2e-12, "min": 1e-13, "max": 2e-11, "kind": "si" }, { "key": "VCM", "label": "Input common mode (the reference level)", "unit": "V", "value": 0.75, "min": 0.3, "max": 1, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.", "measures": [], "metricKeys": [ "i_supply", "vout_dc", "vos" ], "acceptance": [ "i_supply" ], "acceptanceRules": [ { "key": "i_supply", "unit": "A", "min": null, "max": 0.00006, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* LDO reference amplifier, self-biased - operating point as a unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n.subckt ldoref inp inn out vdd vss\n* bias: a PMOS and an NMOS diode in series across the supply\nXMP nx nx vdd vdd sg13_lv_pmos w=2.8u l=8u ng=1 m=1\nXMN nx nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1\nXMT tail nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=2\n* first stage: an NMOS pair on a PMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1\nXM2 d2 inp tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1\nXM4 d2 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1\n* second stage: a common-source PMOS against an NMOS sink; out rises with inp\nXM5 out d2 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=4\nXM6 out nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=4\n* Miller compensation with its nulling resistor\nXCc d2 cz cap_cmim w=25.767u l=25.767u m=3\nXRz cz out vss rppd w=0.5u l=11.54u\n.ends\nXdut inp inn out vdd 0 ldoref\nCl out 0 2p\nVin inp 0 dc 750m\n* the output drives the inverting input: a unity-gain buffer\nVfb inn out 0\n.op\n.end" }, { "id": "open_loop", "label": "Open-loop gain", "note": "Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.", "measures": [], "metricKeys": [ "dc_gain_db", "ugf_hz", "pm_deg", "gm_db" ], "acceptance": [ "dc_gain_db", "ugf_hz", "pm_deg" ], "acceptanceRules": [ { "key": "dc_gain_db", "unit": "dB", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "ugf_hz", "unit": "Hz", "min": 1500000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "pm_deg", "unit": "deg", "min": 65, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* LDO reference amplifier, self-biased - open-loop gain and phase\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n.subckt ldoref inp inn out vdd vss\n* bias: a PMOS and an NMOS diode in series across the supply\nXMP nx nx vdd vdd sg13_lv_pmos w=2.8u l=8u ng=1 m=1\nXMN nx nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1\nXMT tail nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=2\n* first stage: an NMOS pair on a PMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1\nXM2 d2 inp tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1\nXM4 d2 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1\n* second stage: a common-source PMOS against an NMOS sink; out rises with inp\nXM5 out d2 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=4\nXM6 out nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=4\n* Miller compensation with its nulling resistor\nXCc d2 cz cap_cmim w=25.767u l=25.767u m=3\nXRz cz out vss rppd w=0.5u l=11.54u\n.ends\nXdut inp inn out vdd 0 ldoref\nCl out 0 2p\nVin inp 0 dc 750m ac 1\n* the loop closed at DC and open at every frequency the sweep visits\nLfb out inn 1t\nCfb inn 0 1t\n.ac dec 25 0.1 10g\n.end" }, { "id": "step", "label": "Step response", "note": "A 100mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.", "measures": [], "metricKeys": [ "sr", "t_settle", "overshoot_pct", "sr_fall", "t_settle_fall" ], "acceptance": [ "t_settle", "t_settle_fall" ], "acceptanceRules": [ { "key": "t_settle", "unit": "s", "min": null, "max": 5e-7, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "t_settle_fall", "unit": "s", "min": null, "max": 5e-7, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* LDO reference amplifier, self-biased - step response of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n.subckt ldoref inp inn out vdd vss\n* bias: a PMOS and an NMOS diode in series across the supply\nXMP nx nx vdd vdd sg13_lv_pmos w=2.8u l=8u ng=1 m=1\nXMN nx nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1\nXMT tail nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=2\n* first stage: an NMOS pair on a PMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1\nXM2 d2 inp tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1\nXM4 d2 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1\n* second stage: a common-source PMOS against an NMOS sink; out rises with inp\nXM5 out d2 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=4\nXM6 out nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=4\n* Miller compensation with its nulling resistor\nXCc d2 cz cap_cmim w=25.767u l=25.767u m=3\nXRz cz out vss rppd w=0.5u l=11.54u\n.ends\nXdut inp inn out vdd 0 ldoref\nCl out 0 2p\nVin inp 0 pulse(700m 800m 200n 1n 1n 1u 4u)\nVfb inn out 0\n.tran 500p 2u\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.", "measures": [], "metricKeys": [ "psrr_db" ], "acceptance": [ "psrr_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* LDO reference amplifier, self-biased - supply rejection of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD} ac 1\n.subckt ldoref inp inn out vdd vss\n* bias: a PMOS and an NMOS diode in series across the supply\nXMP nx nx vdd vdd sg13_lv_pmos w=2.8u l=8u ng=1 m=1\nXMN nx nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1\nXMT tail nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=2\n* first stage: an NMOS pair on a PMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1\nXM2 d2 inp tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1\nXM4 d2 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1\n* second stage: a common-source PMOS against an NMOS sink; out rises with inp\nXM5 out d2 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=4\nXM6 out nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=4\n* Miller compensation with its nulling resistor\nXCc d2 cz cap_cmim w=25.767u l=25.767u m=3\nXRz cz out vss rppd w=0.5u l=11.54u\n.ends\nXdut inp inn out vdd 0 ldoref\nCl out 0 2p\nVin inp 0 dc 750m\nVfb inn out 0\n.ac dec 25 1 100meg\n.end" }, { "id": "cmrr", "label": "Common-mode rejection", "note": "Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.", "measures": [], "metricKeys": [ "cmrr_db" ], "acceptance": [ "cmrr_db" ], "acceptanceRules": [ { "key": "cmrr_db", "unit": "dB", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* LDO reference amplifier, self-biased - common-mode rejection\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n.subckt ldoref inp inn out vdd vss\n* bias: a PMOS and an NMOS diode in series across the supply\nXMP nx nx vdd vdd sg13_lv_pmos w=2.8u l=8u ng=1 m=1\nXMN nx nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1\nXMT tail nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=2\n* first stage: an NMOS pair on a PMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1\nXM2 d2 inp tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1\nXM4 d2 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1\n* second stage: a common-source PMOS against an NMOS sink; out rises with inp\nXM5 out d2 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=4\nXM6 out nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=4\n* Miller compensation with its nulling resistor\nXCc d2 cz cap_cmim w=25.767u l=25.767u m=3\nXRz cz out vss rppd w=0.5u l=11.54u\n.ends\nXdut inp inn out vdd 0 ldoref\nCl out 0 2p\nVsrc src 0 dc 750m\n* va on the non-inverting input, vb in the feedback path: both inputs move with the signal\nVa inp src dc 0 ac 1\nVb inn out dc 0 ac 1\n.ac dec 25 1 100meg\n.end" }, { "id": "noise", "label": "Noise", "note": "Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.", "measures": [], "metricKeys": [ "vn_1k", "vn_int" ], "acceptance": [ "vn_1k" ], "acceptanceRules": [ { "key": "vn_1k", "unit": "V/√Hz", "min": null, "max": 2.5e-7, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* LDO reference amplifier, self-biased - input-referred noise\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n.subckt ldoref inp inn out vdd vss\n* bias: a PMOS and an NMOS diode in series across the supply\nXMP nx nx vdd vdd sg13_lv_pmos w=2.8u l=8u ng=1 m=1\nXMN nx nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1\nXMT tail nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=2\n* first stage: an NMOS pair on a PMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1\nXM2 d2 inp tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1\nXM4 d2 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1\n* second stage: a common-source PMOS against an NMOS sink; out rises with inp\nXM5 out d2 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=4\nXM6 out nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=4\n* Miller compensation with its nulling resistor\nXCc d2 cz cap_cmim w=25.767u l=25.767u m=3\nXRz cz out vss rppd w=0.5u l=11.54u\n.ends\nXdut inp inn out vdd 0 ldoref\nCl out 0 2p\nVin inp 0 dc 750m ac 1\nVfb inn out 0\n.control\nnoise v(out) Vin dec 20 1 1meg\nsetplot noise1\n* 20 points a decade from 1 Hz: point 60 is 1 kHz\nlet vn_1k = inoise_spectrum[60]\nprint vn_1k\nsetplot noise2\nprint inoise_total\n.endc\n.op\n.end" }, { "id": "icmr", "label": "Input common-mode range", "note": "Both inputs swept together while the output is held at one level. The range is where open-loop gain falls by no more than 6 dB and unity-gain frequency by no more than 5 % from their values at the design common mode; increases are allowed.", "measures": [], "metricKeys": [ "icmr_lo", "icmr_hi" ], "acceptance": [ "icmr_lo", "icmr_hi" ], "acceptanceRules": [ { "key": "icmr_lo", "unit": "V", "min": null, "max": 0.6, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "icmr_hi", "unit": "V", "min": 0.8, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* LDO reference amplifier, self-biased - input common-mode range, the output held at one level\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n.subckt ldoref inp inn out vdd vss\n* bias: a PMOS and an NMOS diode in series across the supply\nXMP nx nx vdd vdd sg13_lv_pmos w=2.8u l=8u ng=1 m=1\nXMN nx nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1\nXMT tail nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=2\n* first stage: an NMOS pair on a PMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1\nXM2 d2 inp tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1\nXM4 d2 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1\n* second stage: a common-source PMOS against an NMOS sink; out rises with inp\nXM5 out d2 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=4\nXM6 out nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=4\n* Miller compensation with its nulling resistor\nXCc d2 cz cap_cmim w=25.767u l=25.767u m=3\nXRz cz out vss rppd w=0.5u l=11.54u\n.ends\nXdut inp inn out vdd 0 ldoref\nCl out 0 2p\nVin inp 0 dc 750m ac 1\nVpark park 0 dc 750m\n* inn is inp shifted by how far out is from park: the loop holds out at park\n* while both inputs follow inp, and it is closed at DC only, as in the\n* open-loop bench, so each ac sweep sees the open loop\nEfb fb inp out park 1\nLfb fb inn 1t\nCfb inn 0 1t\n.control\n* point 0 is the design common mode, the reference; then every level\nac dec 20 0.1 10g\nmeas ac a0_0 find vdb(out) at=0.1\nmeas ac fu_0 when vdb(out)=0 fall=1\nalter vin dc = 0\nac dec 20 0.1 10g\nmeas ac a0_1 find vdb(out) at=0.1\nmeas ac fu_1 when vdb(out)=0 fall=1\nalter vin dc = 30m\nac dec 20 0.1 10g\nmeas ac a0_2 find vdb(out) at=0.1\nmeas ac fu_2 when vdb(out)=0 fall=1\nalter vin dc = 60m\nac dec 20 0.1 10g\nmeas ac a0_3 find vdb(out) at=0.1\nmeas ac fu_3 when vdb(out)=0 fall=1\nalter vin dc = 90m\nac dec 20 0.1 10g\nmeas ac a0_4 find vdb(out) at=0.1\nmeas ac fu_4 when vdb(out)=0 fall=1\nalter vin dc = 120m\nac dec 20 0.1 10g\nmeas ac a0_5 find vdb(out) at=0.1\nmeas ac fu_5 when vdb(out)=0 fall=1\nalter vin dc = 150m\nac dec 20 0.1 10g\nmeas ac a0_6 find vdb(out) at=0.1\nmeas ac fu_6 when vdb(out)=0 fall=1\nalter vin dc = 180m\nac dec 20 0.1 10g\nmeas ac a0_7 find vdb(out) at=0.1\nmeas ac fu_7 when vdb(out)=0 fall=1\nalter vin dc = 210m\nac dec 20 0.1 10g\nmeas ac a0_8 find vdb(out) at=0.1\nmeas ac fu_8 when vdb(out)=0 fall=1\nalter vin dc = 240m\nac dec 20 0.1 10g\nmeas ac a0_9 find vdb(out) at=0.1\nmeas ac fu_9 when vdb(out)=0 fall=1\nalter vin dc = 270m\nac dec 20 0.1 10g\nmeas ac a0_10 find vdb(out) at=0.1\nmeas ac fu_10 when vdb(out)=0 fall=1\nalter vin dc = 300m\nac dec 20 0.1 10g\nmeas ac a0_11 find vdb(out) at=0.1\nmeas ac fu_11 when vdb(out)=0 fall=1\nalter vin dc = 330m\nac dec 20 0.1 10g\nmeas ac a0_12 find vdb(out) at=0.1\nmeas ac fu_12 when vdb(out)=0 fall=1\nalter vin dc = 360m\nac dec 20 0.1 10g\nmeas ac a0_13 find vdb(out) at=0.1\nmeas ac fu_13 when vdb(out)=0 fall=1\nalter vin dc = 390m\nac dec 20 0.1 10g\nmeas ac a0_14 find vdb(out) at=0.1\nmeas ac fu_14 when vdb(out)=0 fall=1\nalter vin dc = 420m\nac dec 20 0.1 10g\nmeas ac a0_15 find vdb(out) at=0.1\nmeas ac fu_15 when vdb(out)=0 fall=1\nalter vin dc = 450m\nac dec 20 0.1 10g\nmeas ac a0_16 find vdb(out) at=0.1\nmeas ac fu_16 when vdb(out)=0 fall=1\nalter vin dc = 480m\nac dec 20 0.1 10g\nmeas ac a0_17 find vdb(out) at=0.1\nmeas ac fu_17 when vdb(out)=0 fall=1\nalter vin dc = 510m\nac dec 20 0.1 10g\nmeas ac a0_18 find vdb(out) at=0.1\nmeas ac fu_18 when vdb(out)=0 fall=1\nalter vin dc = 540m\nac dec 20 0.1 10g\nmeas ac a0_19 find vdb(out) at=0.1\nmeas ac fu_19 when vdb(out)=0 fall=1\nalter vin dc = 570m\nac dec 20 0.1 10g\nmeas ac a0_20 find vdb(out) at=0.1\nmeas ac fu_20 when vdb(out)=0 fall=1\nalter vin dc = 600m\nac dec 20 0.1 10g\nmeas ac a0_21 find vdb(out) at=0.1\nmeas ac fu_21 when vdb(out)=0 fall=1\nalter vin dc = 630m\nac dec 20 0.1 10g\nmeas ac a0_22 find vdb(out) at=0.1\nmeas ac fu_22 when vdb(out)=0 fall=1\nalter vin dc = 660m\nac dec 20 0.1 10g\nmeas ac a0_23 find vdb(out) at=0.1\nmeas ac fu_23 when vdb(out)=0 fall=1\nalter vin dc = 690m\nac dec 20 0.1 10g\nmeas ac a0_24 find vdb(out) at=0.1\nmeas ac fu_24 when vdb(out)=0 fall=1\nalter vin dc = 720m\nac dec 20 0.1 10g\nmeas ac a0_25 find vdb(out) at=0.1\nmeas ac fu_25 when vdb(out)=0 fall=1\nalter vin dc = 750m\nac dec 20 0.1 10g\nmeas ac a0_26 find vdb(out) at=0.1\nmeas ac fu_26 when vdb(out)=0 fall=1\nalter vin dc = 780m\nac dec 20 0.1 10g\nmeas ac a0_27 find vdb(out) at=0.1\nmeas ac fu_27 when vdb(out)=0 fall=1\nalter vin dc = 810m\nac dec 20 0.1 10g\nmeas ac a0_28 find vdb(out) at=0.1\nmeas ac fu_28 when vdb(out)=0 fall=1\nalter vin dc = 840m\nac dec 20 0.1 10g\nmeas ac a0_29 find vdb(out) at=0.1\nmeas ac fu_29 when vdb(out)=0 fall=1\nalter vin dc = 870m\nac dec 20 0.1 10g\nmeas ac a0_30 find vdb(out) at=0.1\nmeas ac fu_30 when vdb(out)=0 fall=1\nalter vin dc = 900m\nac dec 20 0.1 10g\nmeas ac a0_31 find vdb(out) at=0.1\nmeas ac fu_31 when vdb(out)=0 fall=1\nalter vin dc = 930m\nac dec 20 0.1 10g\nmeas ac a0_32 find vdb(out) at=0.1\nmeas ac fu_32 when vdb(out)=0 fall=1\nalter vin dc = 960m\nac dec 20 0.1 10g\nmeas ac a0_33 find vdb(out) at=0.1\nmeas ac fu_33 when vdb(out)=0 fall=1\nalter vin dc = 990m\nac dec 20 0.1 10g\nmeas ac a0_34 find vdb(out) at=0.1\nmeas ac fu_34 when vdb(out)=0 fall=1\nalter vin dc = 1.02\nac dec 20 0.1 10g\nmeas ac a0_35 find vdb(out) at=0.1\nmeas ac fu_35 when vdb(out)=0 fall=1\nalter vin dc = 1.05\nac dec 20 0.1 10g\nmeas ac a0_36 find vdb(out) at=0.1\nmeas ac fu_36 when vdb(out)=0 fall=1\nalter vin dc = 1.08\nac dec 20 0.1 10g\nmeas ac a0_37 find vdb(out) at=0.1\nmeas ac fu_37 when vdb(out)=0 fall=1\nalter vin dc = 1.11\nac dec 20 0.1 10g\nmeas ac a0_38 find vdb(out) at=0.1\nmeas ac fu_38 when vdb(out)=0 fall=1\nalter vin dc = 1.14\nac dec 20 0.1 10g\nmeas ac a0_39 find vdb(out) at=0.1\nmeas ac fu_39 when vdb(out)=0 fall=1\nalter vin dc = 1.17\nac dec 20 0.1 10g\nmeas ac a0_40 find vdb(out) at=0.1\nmeas ac fu_40 when vdb(out)=0 fall=1\nalter vin dc = 1.2\nac dec 20 0.1 10g\nmeas ac a0_41 find vdb(out) at=0.1\nmeas ac fu_41 when vdb(out)=0 fall=1\nalter vin dc = 1.23\nac dec 20 0.1 10g\nmeas ac a0_42 find vdb(out) at=0.1\nmeas ac fu_42 when vdb(out)=0 fall=1\nalter vin dc = 1.26\nac dec 20 0.1 10g\nmeas ac a0_43 find vdb(out) at=0.1\nmeas ac fu_43 when vdb(out)=0 fall=1\nalter vin dc = 1.29\nac dec 20 0.1 10g\nmeas ac a0_44 find vdb(out) at=0.1\nmeas ac fu_44 when vdb(out)=0 fall=1\nalter vin dc = 1.32\nac dec 20 0.1 10g\nmeas ac a0_45 find vdb(out) at=0.1\nmeas ac fu_45 when vdb(out)=0 fall=1\n.endc\n.dc Vin 0 1.32 30m\n.end" }, { "id": "swing", "label": "Output swing", "note": "The amplifier as an inverting gain of one - its inverting input at the midpoint of the output and a signal, through two ideal controlled sources that load nothing - with the signal swept so the output crosses from rail to rail, and at each level the open-loop gain: the swing is where the gain stays within 6 dB of its value with the output at the input common mode.", "measures": [], "metricKeys": [ "swing_lo", "swing_hi" ], "acceptance": [ "swing_lo", "swing_hi" ], "acceptanceRules": [ { "key": "swing_lo", "unit": "V", "min": null, "max": 0.3, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "swing_hi", "unit": "V", "min": 0.85, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* LDO reference amplifier, self-biased - output swing, as an inverting amplifier of gain one\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n.subckt ldoref inp inn out vdd vss\n* bias: a PMOS and an NMOS diode in series across the supply\nXMP nx nx vdd vdd sg13_lv_pmos w=2.8u l=8u ng=1 m=1\nXMN nx nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1\nXMT tail nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=2\n* first stage: an NMOS pair on a PMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1\nXM2 d2 inp tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1\nXM4 d2 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1\n* second stage: a common-source PMOS against an NMOS sink; out rises with inp\nXM5 out d2 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=4\nXM6 out nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=4\n* Miller compensation with its nulling resistor\nXCc d2 cz cap_cmim w=25.767u l=25.767u m=3\nXRz cz out vss rppd w=0.5u l=11.54u\n.ends\nXdut inp inn out vdd 0 ldoref\nCl out 0 2p\nVcm inp 0 dc 750m ac 1\nVsig sig 0 dc 750m\n* inn is the midpoint of out and sig: v(out) = 2 V_CM - v(sig). Closed at DC\n* only, so each ac sweep reads the open-loop gain at that output level\nE1 fbn mid out 0 0.5\nE2 mid 0 sig 0 0.5\nLfb fbn inn 1t\nCfb inn 0 1t\n.control\n* point 0 has the output at the input common mode, the reference\nac dec 1 0.1 1\nmeas ac a0_0 find vdb(out) at=0.1\nalter vsig dc = 1.5\nac dec 1 0.1 1\nmeas ac a0_1 find vdb(out) at=0.1\nalter vsig dc = 1.47\nac dec 1 0.1 1\nmeas ac a0_2 find vdb(out) at=0.1\nalter vsig dc = 1.44\nac dec 1 0.1 1\nmeas ac a0_3 find vdb(out) at=0.1\nalter vsig dc = 1.41\nac dec 1 0.1 1\nmeas ac a0_4 find vdb(out) at=0.1\nalter vsig dc = 1.38\nac dec 1 0.1 1\nmeas ac a0_5 find vdb(out) at=0.1\nalter vsig dc = 1.35\nac dec 1 0.1 1\nmeas ac a0_6 find vdb(out) at=0.1\nalter vsig dc = 1.32\nac dec 1 0.1 1\nmeas ac a0_7 find vdb(out) at=0.1\nalter vsig dc = 1.29\nac dec 1 0.1 1\nmeas ac a0_8 find vdb(out) at=0.1\nalter vsig dc = 1.26\nac dec 1 0.1 1\nmeas ac a0_9 find vdb(out) at=0.1\nalter vsig dc = 1.23\nac dec 1 0.1 1\nmeas ac a0_10 find vdb(out) at=0.1\nalter vsig dc = 1.2\nac dec 1 0.1 1\nmeas ac a0_11 find vdb(out) at=0.1\nalter vsig dc = 1.17\nac dec 1 0.1 1\nmeas ac a0_12 find vdb(out) at=0.1\nalter vsig dc = 1.14\nac dec 1 0.1 1\nmeas ac a0_13 find vdb(out) at=0.1\nalter vsig dc = 1.11\nac dec 1 0.1 1\nmeas ac a0_14 find vdb(out) at=0.1\nalter vsig dc = 1.08\nac dec 1 0.1 1\nmeas ac a0_15 find vdb(out) at=0.1\nalter vsig dc = 1.05\nac dec 1 0.1 1\nmeas ac a0_16 find vdb(out) at=0.1\nalter vsig dc = 1.02\nac dec 1 0.1 1\nmeas ac a0_17 find vdb(out) at=0.1\nalter vsig dc = 990m\nac dec 1 0.1 1\nmeas ac a0_18 find vdb(out) at=0.1\nalter vsig dc = 960m\nac dec 1 0.1 1\nmeas ac a0_19 find vdb(out) at=0.1\nalter vsig dc = 930m\nac dec 1 0.1 1\nmeas ac a0_20 find vdb(out) at=0.1\nalter vsig dc = 900m\nac dec 1 0.1 1\nmeas ac a0_21 find vdb(out) at=0.1\nalter vsig dc = 870m\nac dec 1 0.1 1\nmeas ac a0_22 find vdb(out) at=0.1\nalter vsig dc = 840m\nac dec 1 0.1 1\nmeas ac a0_23 find vdb(out) at=0.1\nalter vsig dc = 810m\nac dec 1 0.1 1\nmeas ac a0_24 find vdb(out) at=0.1\nalter vsig dc = 780m\nac dec 1 0.1 1\nmeas ac a0_25 find vdb(out) at=0.1\nalter vsig dc = 750m\nac dec 1 0.1 1\nmeas ac a0_26 find vdb(out) at=0.1\nalter vsig dc = 720m\nac dec 1 0.1 1\nmeas ac a0_27 find vdb(out) at=0.1\nalter vsig dc = 690m\nac dec 1 0.1 1\nmeas ac a0_28 find vdb(out) at=0.1\nalter vsig dc = 660m\nac dec 1 0.1 1\nmeas ac a0_29 find vdb(out) at=0.1\nalter vsig dc = 630m\nac dec 1 0.1 1\nmeas ac a0_30 find vdb(out) at=0.1\nalter vsig dc = 600m\nac dec 1 0.1 1\nmeas ac a0_31 find vdb(out) at=0.1\nalter vsig dc = 570m\nac dec 1 0.1 1\nmeas ac a0_32 find vdb(out) at=0.1\nalter vsig dc = 540m\nac dec 1 0.1 1\nmeas ac a0_33 find vdb(out) at=0.1\nalter vsig dc = 510m\nac dec 1 0.1 1\nmeas ac a0_34 find vdb(out) at=0.1\nalter vsig dc = 480m\nac dec 1 0.1 1\nmeas ac a0_35 find vdb(out) at=0.1\nalter vsig dc = 450m\nac dec 1 0.1 1\nmeas ac a0_36 find vdb(out) at=0.1\nalter vsig dc = 420m\nac dec 1 0.1 1\nmeas ac a0_37 find vdb(out) at=0.1\nalter vsig dc = 390m\nac dec 1 0.1 1\nmeas ac a0_38 find vdb(out) at=0.1\nalter vsig dc = 360m\nac dec 1 0.1 1\nmeas ac a0_39 find vdb(out) at=0.1\nalter vsig dc = 330m\nac dec 1 0.1 1\nmeas ac a0_40 find vdb(out) at=0.1\nalter vsig dc = 300m\nac dec 1 0.1 1\nmeas ac a0_41 find vdb(out) at=0.1\n.endc\n.dc Vsig 300m 1.5 30m\n.end" } ], "measurements": { "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.00006 } }, "dc_gain_db": { "label": "DC open-loop gain", "unit": "dB", "spec": { "min": 60, "max": null } }, "ugf_hz": { "label": "Unity-gain frequency", "unit": "Hz", "spec": { "min": 1500000, "max": null } }, "pm_deg": { "label": "Phase margin", "unit": "deg", "spec": { "min": 65, "max": null } }, "t_settle": { "label": "Settling time, 1 %", "unit": "s", "spec": { "min": null, "max": 5e-7 } }, "t_settle_fall": { "label": "Settling time, 1 %, falling", "unit": "s", "spec": { "min": null, "max": 5e-7 } }, "psrr_db": { "label": "Supply rejection at 1 kHz", "unit": "dB", "spec": { "min": 60, "max": null } }, "cmrr_db": { "label": "Common-mode rejection at 1 kHz", "unit": "dB", "spec": { "min": 60, "max": null } }, "vn_1k": { "label": "Input noise at 1 kHz", "unit": "V/√Hz", "spec": { "min": null, "max": 2.5e-7 } }, "icmr_lo": { "label": "Lowest input common mode", "unit": "V", "spec": { "min": null, "max": 0.6 } }, "icmr_hi": { "label": "Highest input common mode", "unit": "V", "spec": { "min": 0.8, "max": null } }, "swing_lo": { "label": "Lowest output", "unit": "V", "spec": { "min": null, "max": 0.3 } }, "swing_hi": { "label": "Highest output", "unit": "V", "spec": { "min": 0.85, "max": null } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "60fb4eff26ee0cd4aaddfa9fd3312d907a89b442b821d213f7f03b043efce84f" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ldo-ref-amp.js", "sha256": "25b06df6f773b86af4cb0096940421b26d6c31b9abc078555edbf9617fdb1a5a" }, "simulationFingerprints": { "op": "1b573e16fe0daae687cebd0756fcca70f07ca5034a00f29d57cecf77ecba76a6", "open_loop": "ee48f1afd7141cc0afc1fd7b3a7d258822f811092dca67bd1c917ced4175dfa9", "step": "bbd3bf20abbbcd99b3e71cd49d5388fb62a735500e79ce2e605d8ca76d188ea4", "psrr": "138f8edfecc9e91ae20dd3f1c54ffa81dfd7afd85d97e130a219028aeede4d2f", "cmrr": "ca26c8671d78e1fd7410bae2fda2c9b73e090be512dea35ce02330c292904e1f", "noise": "e9e220fb0663435a80d4afc3d27cf6b50317ddb775101c459a4d85b7f6913ed8", "icmr": "f9f9b3ade05a153a5cc8ba614ab51dde904091f55e23c6894514c4b776d23418", "swing": "f926d37c29246ecc1ae0fc2970482147d0ee7239a6547e54224226d6268e088d" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "adeb080cec3dbcd3d3c417ed520538b939448883a4c1ca3cdac979b89aea19af", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ldo-ref-amp", "parameters": { "Wbp": 0.0000028, "Lbp": 0.000008, "Wn": 0.000004, "Ln": 0.000004, "S": 4, "W1": 0.00002, "L1": 0.000002, "Wp": 0.00003, "Lp": 0.0000015, "Cc": 3e-12, "Rz": 6000, "CL": 2e-12, "VCM": 0.75 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ldo-ref-amp/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "ldoref", "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" } ], "definitions": [], "devices": [ { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.8u l=8u ng=1 m=1", "source": "XMP nx nx vdd vdd sg13_lv_pmos w=2.8u l=8u ng=1 m=1", "pins": [ { "id": "d", "net": "nx" }, { "id": "g", "net": "nx" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN", "displayName": "MN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMN nx nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "nx" }, { "id": "g", "net": "nx" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=2", "source": "XMT tail nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "nx" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM1 d1 inn tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM2 d2 inp tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=30u l=1.5u ng=6 m=1", "source": "XM3 d1 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=30u l=1.5u ng=6 m=1", "source": "XM4 d2 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=30u l=1.5u ng=6 m=4", "source": "XM5 out d2 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=4", "source": "XM6 out nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "nx" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCc d2 cz cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "cz" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRz cz out vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "nx", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XMN", "pin": "d" }, { "device": "XMN", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMN", "pin": "s" }, { "device": "XMN", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "d2", "ground": false, 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This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldoref", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ldoref", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldoref" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cl out 0 2p", "pins": [ { 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"inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ldoref", "name": "ldoref", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" } ], "definitions": [], "devices": [ { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.8u l=8u ng=1 m=1", "source": "XMP nx nx vdd vdd sg13_lv_pmos w=2.8u l=8u ng=1 m=1", "pins": [ { "id": "d", "net": "nx" }, { "id": "g", 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"X", "model": "sg13_lv_pmos", "parametersOrValue": "w=30u l=1.5u ng=6 m=1", "source": "XM4 d2 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=30u l=1.5u ng=6 m=4", "source": "XM5 out d2 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=4", "source": "XM6 out nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "nx" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], 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Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Bias: PMOS diode", "devices": [ { "scope": "dut", "device": "XMP" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "Bias: NMOS diode", "devices": [ { "scope": "dut", "device": "XMN" } ], "inferredStages": [ "bias" ] }, { "id": "block-3", "label": "Tail current source", "devices": [ { "scope": "dut", "device": "XMT" } ], "inferredStages": [ 1 ] }, { "id": "block-4", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 1 ] }, { "id": "block-5", "label": "Mirror load", "devices": [ { "scope": "dut", "device": "XM3" }, { "scope": "dut", "device": "XM4" } ], "inferredStages": [ 1 ] }, { "id": "block-6", "label": "Second stage", "devices": [ { "scope": "dut", "device": "XM5" } ], "inferredStages": [ 2 ] }, { "id": "block-7", "label": "Second-stage sink", "devices": [ { "scope": "dut", "device": "XM6" } ], "inferredStages": [ 2 ] }, { "id": "block-8", "label": "Miller compensation", "devices": [ { "scope": "dut", "device": "XCc" } ], "inferredStages": [ "comp" ] }, { "id": "block-9", "label": "Nulling resistor", "devices": [ { "scope": "dut", "device": "XRz" } ], "inferredStages": [ "comp" ] } ], "edges": [ { "id": "net-1", "net": "nx", "nodes": [ "block-1", "block-2", "block-3", "block-7" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "tail", "nodes": [ "block-3", "block-4" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "d1", "nodes": [ "block-4", "block-5" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "d2", "nodes": [ "block-4", "block-5", "block-6", "block-8" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "out", "nodes": [ "block-6", "block-7", "block-9" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "cz", "nodes": [ "block-8", "block-9" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. 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}, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ldoref", "name": "ldoref", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" } ], "definitions": [], "devices": [ { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.8u l=8u ng=1 m=1", "source": "XMP nx nx vdd vdd sg13_lv_pmos w=2.8u l=8u ng=1 m=1", "pins": [ { "id": "d", "net": "nx" }, { "id": "g", "net": "nx" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN", "displayName": "MN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMN nx nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "nx" }, { "id": "g", "net": "nx" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=2", "source": "XMT tail nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "nx" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM1 d1 inn tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM2 d2 inp tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=30u l=1.5u ng=6 m=1", "source": "XM3 d1 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=30u l=1.5u ng=6 m=1", "source": "XM4 d2 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=30u l=1.5u ng=6 m=4", "source": "XM5 out d2 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=4", "source": "XM6 out nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "nx" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCc d2 cz cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "cz" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRz cz out vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "nx", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XMN", "pin": "d" }, { "device": "XMN", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMN", "pin": "s" }, { "device": "XMN", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XRz", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "cz", "ground": false, "terminals": [ { "device": "XCc", "pin": "n" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], 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PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ldoref", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ldoref", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ldoref" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cl out 0 2p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vsrc", "displayName": "Vsrc", "spiceType": "V", "model": null, "parametersOrValue": "dc 750m", "source": "Vsrc src 0 dc 750m", "pins": [ { "id": "p", "net": "src" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Va", "displayName": "Va", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Va inp src dc 0 ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "src" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vb", "displayName": "Vb", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Vb inn out dc 0 ac 1", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vsrc", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Va", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "src", "ground": false, "terminals": [ { "device": "Vsrc", "pin": "p" }, { "device": "Va", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ldoref", "name": "ldoref", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" } ], "definitions": [], "devices": [ { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.8u l=8u ng=1 m=1", "source": "XMP nx nx vdd vdd sg13_lv_pmos w=2.8u l=8u ng=1 m=1", "pins": [ { "id": "d", "net": "nx" }, { "id": "g", "net": "nx" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN", "displayName": "MN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=1", "source": "XMN nx nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "nx" }, { "id": "g", "net": "nx" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=2", "source": "XMT tail nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "nx" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM1 d1 inn tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM2 d2 inp tail vss sg13_lv_nmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=30u l=1.5u ng=6 m=1", "source": "XM3 d1 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=30u l=1.5u ng=6 m=1", "source": "XM4 d2 d1 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=30u l=1.5u ng=6 m=4", "source": "XM5 out d2 vdd vdd sg13_lv_pmos w=30u l=1.5u ng=6 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=4u ng=1 m=4", "source": "XM6 out nx vss vss sg13_lv_nmos w=4u l=4u ng=1 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "nx" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCc d2 cz cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "cz" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=11.54u", "source": "XRz cz out vss rppd w=0.5u l=11.54u", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "nx", "ground": false, "terminals": [ { "device": "XMP", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XMN", "pin": "d" }, { "device": "XMN", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMN", "pin": "s" }, { "device": "XMN", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], 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PDK/model internals are referenced, not expanded. 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