{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ldo-unity-5t", "name": "Unity-feedback PMOS LDO", "group": "Voltage regulators", "subgroup": "LDOs", "title": "Unity-feedback PMOS LDO", "summary": "Regulates 1.2 V down to about 0.6 V without a feedback divider. A five-transistor amplifier directly compares output and reference, then drives a PMOS pass transistor. Unity feedback avoids divider noise, but the amplifier's voltage range limits output voltage and dropout.", "reference": { "kind": "book", "authors": "G. A. Rincon-Mora", "title": "Analog IC Design with Low-Dropout Regulators", "edition": "2nd", "publisher": "McGraw-Hill", "year": 2014, "where": "the PMOS-pass LDO, its error amplifier and its frequency compensation", "takes": "The topology: a five-transistor error amplifier fed back from the output directly, a PMOS pass device, a Miller capacitor from the output to the pass gate, and a bleed and a capacitor on the output. The sizing and specs are this library's, for SG13G2 at 1.2 V." }, "resources": { "record": "/circuits/ldo-unity-5t.json", "page": "/index.html#ldo-unity-5t", "achieved": "/achieved/ldo-unity-5t.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "ref", "kind": "input", "note": "the reference voltage, which the output copies" }, { "name": "sense", "kind": "input", "note": "the output as the regulator reads it" }, { "name": "out", "kind": "output" }, { "name": "vdd", "kind": "supply", "note": "the unregulated input" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the bias current, driven into this pin" } ], "devices": [ { "name": "MB", "type": "nmos", "nodes": "ib ib vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "bias reference, diode-connected", "fingers": 1, "copies": 1 }, { "name": "MT", "type": "nmos", "nodes": "tail ib vss vss", "sizedBy": [ "Wn", "Ln", "N" ], "role": "error amplifier tail, N copies of MB", "fingers": 1, "copies": 2 }, { "name": "Rr", "type": "resistor", "nodes": "ref refi", "sizedBy": [ "Rr" ], "role": "the reference's source resistance" }, { "name": "M1", "type": "nmos", "nodes": "d1 sense tail vss", "sizedBy": [ "W1", "L1" ], "role": "input pair, the output", "fingers": 8, "copies": 1 }, { "name": "M2", "type": "nmos", "nodes": "gate refi tail vss", "sizedBy": [ "W1", "L1" ], "role": "input pair, the reference", "fingers": 8, "copies": 1 }, { "name": "M3", "type": "pmos", "nodes": "d1 d1 vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "mirror load, diode-connected", "fingers": 40, "copies": 1 }, { "name": "M4", "type": "pmos", "nodes": "gate d1 vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "mirror load, drives the pass gate", "fingers": 40, "copies": 1 }, { "name": "MP", "type": "pmos", "nodes": "out gate vdd vdd", "sizedBy": [ "Wpass", "Lpass" ], "role": "pass device", "fingers": 240, "copies": 1 }, { "name": "Rb", "type": "resistor", "nodes": "out vss", "sizedBy": [ "Rb" ], "role": "bleed: the least MP always carries" }, { "name": "Co", "type": "capacitor", "nodes": "out vss", "sizedBy": [ "Co" ], "role": "on-chip output capacitor" }, { "name": "Cc", "type": "capacitor", "nodes": "out gate", "sizedBy": [ "Cc" ], "role": "Miller capacitor" } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "The input pair: any difference between them is an offset, and with unity feedback it is the output's error one for one." }, { "rule": "match", "of": [ "M3", "M4" ], "why": "The mirror load: a mismatch copies the wrong current onto gate and appears as offset." }, { "rule": "unit-copies", "of": [ "MB", "MT" ], "constraint": "MT = N copies of MB", "why": "The tail current is set by repeating the bias device, never by drawing a wider one: copies share nominal geometry-dependent behavior, while random mismatch remains." }, { "rule": "common-mode", "of": [ "M1", "M2", "M3", "MT" ], "constraint": "V_ref - V_GS1 below V_DD - V_SG3 - 0.15 V at 1.08 V", "why": "The amplifier's input is the output. Its tail node rides one V_GS below it, and M1's drain sits one V_SG below the supply: between them M1 needs room to stay saturated at the lowest input. A 0.7 V output leaves too little, and a wider pair - less V_GS, a higher tail - makes it worse. So the output is 0.6 V." }, { "rule": "headroom", "of": [ "MP", "M2", "MT" ], "constraint": "5 mA with the gate no lower than about 0.45 V", "why": "With the tail near 0.35 V, M2 cannot pull gate much below 0.45 V: at a 1.08 V input MP gets 0.63 V of V_SG at most, and its width is chosen for full load with that." }, { "rule": "bleed", "of": [ "Rb", "MP" ], "constraint": "V_out/Rb above MP's leakage at 125 °C, fast corner", "why": "With no load Rb is all MP drives; drawing less than MP leaks hot, it would let the unloaded output rise. Its 50 µA also sets MP's transconductance at no load, which places the output pole." }, { "rule": "zero", "of": [ "Cc", "MP", "M2" ], "constraint": "g_m,MP at no load several times g_m2", "why": "Cc feeds the gate forward to the output: a right-half-plane zero at g_m,MP/Cc, while the crossover is g_m2/Cc - so their ratio is g_m,MP/g_m2 whatever Cc is. At no load g_m,MP is only the bleed's; a larger bleed and a smaller tail current are what keep that zero clear of the crossover." }, { "rule": "reference-noise", "of": [ "Rr", "M2" ], "constraint": "Rr at most a few tens of kΩ", "why": "At DC, M2 draws little gate current, so a moderate Rr causes little voltage drop. Rr adds thermal noise and, with input capacitance, limits the reference bandwidth." } ], "specs": [ { "key": "vout", "label": "Output voltage", "unit": "V", "direction": "target", "constraint": ">= 0.58 V, <= 0.62 V", "min": 0.58, "max": 0.62, "why": "The 0.6 V reference, copied: the amplifier's offset and finite gain are the only error, at every corner and load." }, { "key": "i_q", "label": "Quiescent current", "unit": "A", "direction": "min", "constraint": "<= 0.0001 A", "min": null, "max": 0.0001, "why": "Bias, tail and the 50 µA bleed that keeps MP's hot leakage from lifting the unloaded output." }, { "key": "load_reg", "label": "Load regulation", "unit": "V/A", "direction": "min", "constraint": "<= 4 V/A", "min": null, "max": 4, "why": "At most 20 mV from no load to 5 mA; the full loop gain applies, with no divider to divide it." }, { "key": "line_reg", "label": "Line regulation", "unit": "%/V", "direction": "min", "constraint": "<= 3 %/V", "min": null, "max": 3, "why": "At most 4.3 mV across the rated 1.08 to 1.32 V input, at the worse of no load and full load." }, { "key": "dropout", "label": "Dropout at full load", "unit": "V", "direction": "min", "constraint": "<= 0.45 V", "min": null, "max": 0.45, "why": "Below the 0.48 V between the output and the lowest rated input. It is large for an LDO because the amplifier's input sits at the output: its tail node rides 0.35 V up, and the gate cannot be pulled below about 0.45 V." }, { "key": "loop_gain_db", "label": "DC loop gain at full load", "unit": "dB", "direction": "max", "constraint": ">= 45 dB", "min": 45, "max": null, "why": "With unity feedback the error amplifier's whole gain is in the loop." }, { "key": "loop_ugf_hz", "label": "Loop crossover at full load", "unit": "Hz", "direction": "max", "constraint": ">= 150000 Hz", "min": 150000, "max": null, "why": "g_m2 over Cc: the whole feedback factor is one, so Cc has to be larger than in a divided loop for the same crossover." }, { "key": "loop_pm_deg", "label": "Loop phase margin, worst load", "unit": "deg", "direction": "max", "constraint": ">= 55 deg", "min": 55, "max": null, "why": "At every load, the worst at no load: the output pole g_m,MP/(Co + C_L) is lowest there, and the right-half-plane zero g_m,MP/Cc only a few times above the crossover." }, { "key": "ring_pct", "label": "Ringing after a kick, worst load", "unit": "%", "direction": "min", "constraint": "<= 5 %", "min": null, "max": 5, "why": "No load of the range may leave the output ringing after a small step - the test for a loop the margin cannot see." }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 20 dB", "min": 20, "max": null, "why": "At 1 kHz; lowest at full load and the lowest input, where the gate has least room below MP's source." }, { "key": "undershoot", "label": "Undershoot on the load step", "unit": "V", "direction": "min", "constraint": "<= 0.2 V", "min": null, "max": 0.2, "why": "For a 0 to 5 mA step in 1 µs on 150 pF - the regulator's own 50 pF and a 100 pF load." }, { "key": "overshoot", "label": "Overshoot on the load release", "unit": "V", "direction": "min", "constraint": "<= 0.25 V", "min": null, "max": 0.25, "why": "For the release, while the amplifier slews the gate back up against Cc." }, { "key": "t_recover", "label": "Settling after the load step", "unit": "s", "direction": "min", "constraint": "<= 0.000005 s", "min": null, "max": 0.000005, "why": "Back within 1 % of the output after the step." }, { "key": "t_release", "label": "Settling after the load release", "unit": "s", "direction": "min", "constraint": "<= 0.000005 s", "min": null, "max": 0.000005, "why": "Back within 1 % after the release, at no load, where the margin is least." }, { "key": "line_step", "label": "Output step for an input step", "unit": "V", "direction": "min", "constraint": "<= 0.15 V", "min": null, "max": 0.15, "why": "For the input stepped across its whole rated range in 1 µs at full load." }, { "key": "vn_out", "label": "Output noise, 10 Hz to 100 kHz", "unit": "V", "direction": "min", "constraint": "<= 0.00003 V", "min": null, "max": 0.00003, "why": "10 Hz to 100 kHz, rms: the input pair's noise and Rr's, reaching the output one for one - no divider multiplies them." } ], "explanation": { "idea": "Regulates 1.2 V down to about 0.6 V without a feedback divider. A five-transistor amplifier directly compares output and reference, then drives a PMOS pass transistor. Unity feedback avoids divider noise, but the amplifier's voltage range limits output voltage and dropout.", "detail": "A PMOS-pass LDO with no divider: the output goes straight back to M1 in the five-transistor error amplifier, so the loop holds it at the reference, 0.6 V from a 1.2 V input at up to 5 mA. The whole loop gain regulates and no divider multiplies the amplifier's noise. The price is that the amplifier's input sits at the output: its tail node rides one V_GS below it, which caps how high the output can be and how far down the amplifier can pull the pass device's gate.", "lesson": { "relation": 3, "symbols": "V_DO is dropout voltage; V_in,min is the input where the bench's output has fallen 2% below its nominal-input value; V_out,98 is the output at that same point.", "assumptions": "Full-load DC sweep with the same reference and bias settings. This is the bench's measured 2% criterion, not a universal industry dropout threshold.", "exercise": { "param": "Vref", "value": 0.55, "analysis": "op", "expect": "The output should follow the lower reference toward 0.55 V. This experiment leaves the fixed 0.6 V default-design target; the pass-gate headroom must still be checked." }, "limits": "The amplifier is not rail-to-rail and limits gate drive. Supply reference and bias, connect sense to out, and do not assume the voltage setpoint alone guarantees regulation." }, "path": [ { "part": "Reference input", "devices": "Rr", "does": "The reference reaches M2 through Rr, the resistance of whatever drives it; M2 draws little DC gate current, so a moderate Rr produces little DC drop; Rr and input capacitance also limit bandwidth." }, { "part": "Error amplifier", "devices": "M1, M2, M3, M4, MT", "does": "M1 senses the output itself, M2 the reference; the mirror M3, M4 turns M1's current onto gate, so a rise in the output lifts gate." }, { "part": "Pass device", "devices": "MP", "does": "Common-source PMOS: a higher gate means less current and the output falls back to the reference." }, { "part": "Compensation and output", "devices": "Cc, Co, Rb", "does": "Cc from the output back to gate splits the poles; Co is the capacitor the regulator carries on its own output, and Rb the bleed that keeps MP conducting - and sets its g_m - with no load." } ], "bias": "Ib, 10 µA from outside, flows into the diode MB; the tail MT is two copies of it, 20 µA. The reference is an input, 0.6 V, and the supply is 1.2 V (1.08 to 1.32 V).", "relations": [ { "what": "Output voltage", "expr": "V_out ≈ V_ref", "note": "Unity feedback; the offset of M1, M2 is the output's error one for one." }, { "what": "Common mode", "expr": "V_ref − V_GS1 < V_DD − V_SG3 − V_DSAT1", "note": "M1 must stay saturated between its tail and its diode-connected load: at 1.08 V this caps the output near 0.6 V." }, { "what": "Right-half-plane zero", "expr": "f_z / f_c = g_m,MP/g_m2", "note": "Cc sets both, so only a larger bleed or a smaller tail moves the zero away from the crossover." }, { "what": "Dropout", "expr": "V_DO = V_in,min − V_out,98", "note": "Measured at full load when the output is 2% below its nominal-input level. The amplifier cannot pull the gate below about 0.45 V, contributing to the measured 0.31 V dropout." } ], "tradeoffs": [ "Vref: a higher output squeezes M1 between its tail and its load and raises the dropout; at 0.7 V the slow, hot corner runs out of headroom.", "W1 (M1, M2): a wider pair has less V_GS, which lifts the tail node and squeezes M1 further - the opposite of what it does elsewhere.", "Rb: less bleed current saves power but lowers g_m,MP at no load, bringing the output pole and the right-half-plane zero towards the crossover.", "Rr: its thermal noise reaches the output one for one; a few tens of kΩ at most." ] }, "sizing": [ { "key": "Ib", "label": "Bias current", "unit": "A", "value": 0.00001, "min": 0.000001, "max": 0.00005, "kind": "si" }, { "key": "N", "label": "Tail current, in Ib", "unit": "", "value": 2, "min": 1, "max": 16, "kind": "int" }, { "key": "Wn", "label": "W NMOS bias unit (MB, MT)", "unit": "m", "value": 0.000004, "min": 5e-7, "max": 0.00002, "kind": "si" }, { "key": "Ln", "label": "L NMOS bias unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Rr", "label": "Reference source resistance", "unit": "Ω", "value": 20000, "min": 500, "max": 500000, "kind": "si" }, { "key": "W1", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.00004, "min": 0.000001, "max": 0.0002, "kind": "si" }, { "key": "L1", "label": "L input pair", "unit": "m", "value": 0.000004, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Wp", "label": "W mirror (M3, M4)", "unit": "m", "value": 0.0002, "min": 0.000001, "max": 0.0004, "kind": "si" }, { "key": "Lp", "label": "L mirror", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wpass", "label": "W pass device", "unit": "m", "value": 0.0012, "min": 0.00005, "max": 0.005, "kind": "si" }, { "key": "Lpass", "label": "L pass device", "unit": "m", "value": 2e-7, "min": 1.3e-7, "max": 0.000001, "kind": "si" }, { "key": "Rb", "label": "Bleed resistor", "unit": "Ω", "value": 12000, "min": 2000, "max": 200000, "kind": "si" }, { "key": "Co", "label": "On-chip output capacitor", "unit": "F", "value": 5e-11, "min": 1e-12, "max": 5e-10, "kind": "si" }, { "key": "Cc", "label": "Miller capacitor", "unit": "F", "value": 8e-11, "min": 1e-12, "max": 3e-10, "kind": "si" }, { "key": "Vref", "label": "Reference", "unit": "V", "value": 0.6, "min": 0.45, "max": 0.7, "kind": "si" }, { "key": "IL", "label": "Full load", "unit": "A", "value": 0.005, "min": 0.0005, "max": 0.02, "kind": "si" }, { "key": "CL", "label": "Load capacitance", "unit": "F", "value": 1e-10, "min": 1e-11, "max": 1e-9, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The regulator at its nominal input and its lightest load: the output it holds and the current it draws to hold it.", "measures": [], "metricKeys": [ "vout", "i_q" ], "acceptance": [ "vout", "i_q" ], "acceptanceRules": [ { "key": "vout", "unit": "V", "min": 0.58, "max": 0.62, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "i_q", "unit": "A", "min": null, "max": 0.0001, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Unity-feedback PMOS LDO - operating point at the lightest load\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldounity ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2\n* the reference arrives through Rr, the resistance of whatever drives it\nXRr ref refi vss rhigh w=0.5u l=6.078u\n* error amplifier: the output itself on the diode side, so a rise lifts gate\nXM1 d1 sense tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate refi tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device, its bleed and the capacitor on the output\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\nXRb out vss vss rppd w=0.5u l=23.355u\nXCo out vss cap_cmim w=29.962u l=29.962u m=37\n* Miller compensation: from the output back to gate\nXCc out gate cap_cmim w=29.761u l=29.761u m=60\n.ends\nXdut ref sense out vdd 0 ib ldounity\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 0\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.op\n.end" }, { "id": "load_reg", "label": "Load regulation", "note": "The load is swept from lightest to full at nominal input. Regulation is the magnitude of the endpoint output change per ampere; a large output rise fails just as a large fall does.", "measures": [], "metricKeys": [ "load_reg" ], "acceptance": [ "load_reg" ], "acceptanceRules": [ { "key": "load_reg", "unit": "V/A", "min": null, "max": 4, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Unity-feedback PMOS LDO - output against load current\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldounity ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2\n* the reference arrives through Rr, the resistance of whatever drives it\nXRr ref refi vss rhigh w=0.5u l=6.078u\n* error amplifier: the output itself on the diode side, so a rise lifts gate\nXM1 d1 sense tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate refi tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device, its bleed and the capacitor on the output\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\nXRb out vss vss rppd w=0.5u l=23.355u\nXCo out vss cap_cmim w=29.962u l=29.962u m=37\n* Miller compensation: from the output back to gate\nXCc out gate cap_cmim w=29.761u l=29.761u m=60\n.ends\nXdut ref sense out vdd 0 ib ldounity\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 0\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.dc Vload 0 5m 50u\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc v_light FIND v(out) AT=0\n.meas dc v_full FIND v(out) AT=5m\n.end" }, { "id": "line_reg", "label": "Line regulation", "note": "The input swept across its rated range, at the lightest and at the full load: how much of the input's change reaches the output.", "measures": [], "metricKeys": [ "line_reg" ], "acceptance": [ "line_reg" ], "acceptanceRules": [ { "key": "line_reg", "unit": "%/V", "min": null, "max": 3, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Unity-feedback PMOS LDO - output against input voltage\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n* the input swept across its rated range, 1.08V to 1.32V\nVdd vdd 0 dc 1.2\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldounity ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2\n* the reference arrives through Rr, the resistance of whatever drives it\nXRr ref refi vss rhigh w=0.5u l=6.078u\n* error amplifier: the output itself on the diode side, so a rise lifts gate\nXM1 d1 sense tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate refi tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device, its bleed and the capacitor on the output\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\nXRb out vss vss rppd w=0.5u l=23.355u\nXCo out vss cap_cmim w=29.962u l=29.962u m=37\n* Miller compensation: from the output back to gate\nXCc out gate cap_cmim w=29.761u l=29.761u m=60\n.ends\nXdut ref sense out vdd 0 ib ldounity\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 0\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n* the input swept at each of two loads: the lightest, then the full load\n.dc Vdd 1.08 1.32 5m Vload 0 5m 5m\n.end" }, { "id": "dropout", "label": "Dropout", "note": "The input lowered at full load until the output has fallen 2 % below the level it holds at the nominal input: the input-to-output voltage left there is the dropout.", "measures": [], "metricKeys": [ "dropout" ], "acceptance": [ "dropout" ], "acceptanceRules": [ { "key": "dropout", "unit": "V", "min": null, "max": 0.45, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Unity-feedback PMOS LDO - dropout at full load\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n* the input swept down to below the output: 300mV to 1.32V\nVdd vdd 0 dc 1.2\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldounity ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2\n* the reference arrives through Rr, the resistance of whatever drives it\nXRr ref refi vss rhigh w=0.5u l=6.078u\n* error amplifier: the output itself on the diode side, so a rise lifts gate\nXM1 d1 sense tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate refi tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device, its bleed and the capacitor on the output\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\nXRb out vss vss rppd w=0.5u l=23.355u\nXCo out vss cap_cmim w=29.962u l=29.962u m=37\n* Miller compensation: from the output back to gate\nXCc out gate cap_cmim w=29.761u l=29.761u m=60\n.ends\nXdut ref sense out vdd 0 ib ldounity\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 5m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.dc Vdd 300m 1.32 5.1m\n.end" }, { "id": "loop", "label": "Loop gain", "note": "The loop gain at loads across the whole range, from the lightest to the full load: the loop is cut at the sense line and measured by Middlebrook's double injection - a voltage in series there, then a current into out - which gives it exactly, with every loading in place. The phase and gain margins are the worst over the loads.", "measures": [], "metricKeys": [ "loop_gain_db", "loop_ugf_hz", "loop_pm_deg", "loop_gm_db" ], "acceptance": [ "loop_gain_db", "loop_ugf_hz", "loop_pm_deg" ], "acceptanceRules": [ { "key": "loop_gain_db", "unit": "dB", "min": 45, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "loop_ugf_hz", "unit": "Hz", "min": 150000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "loop_pm_deg", "unit": "deg", "min": 55, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Unity-feedback PMOS LDO - loop gain at 5mA, voltage injection\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldounity ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2\n* the reference arrives through Rr, the resistance of whatever drives it\nXRr ref refi vss rhigh w=0.5u l=6.078u\n* error amplifier: the output itself on the diode side, so a rise lifts gate\nXM1 d1 sense tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate refi tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device, its bleed and the capacitor on the output\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\nXRb out vss vss rppd w=0.5u l=23.355u\nXCo out vss cap_cmim w=29.962u l=29.962u m=37\n* Miller compensation: from the output back to gate\nXCc out gate cap_cmim w=29.761u l=29.761u m=60\n.ends\nXdut ref sense out vdd 0 ib ldounity\n* the sense line cut by a 1 V ac source in series: T_v = -v(out)/v(sense)\nVinj sense out dc 0 ac 1\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 5m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.ac dec 20 0.1 1g\n.end" }, { "id": "ring", "label": "Ringing across the loads", "note": "The loads the loop bench visits, in a staircase from the lightest to the full load; at each, once the output has settled, a small step - a tenth more load. How far the output overshoots its new level on the way back, and what is left moving at the end of each step, show whether the regulator is damped at that load: a loop inside it that the sense line does not pass through, and so the loop gain cannot see, shows here.", "measures": [], "metricKeys": [ "ring_pct" ], "acceptance": [ "ring_pct" ], "acceptanceRules": [ { "key": "ring_pct", "unit": "%", "min": null, "max": 5, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Unity-feedback PMOS LDO - a small load step at each load\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldounity ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2\n* the reference arrives through Rr, the resistance of whatever drives it\nXRr ref refi vss rhigh w=0.5u l=6.078u\n* error amplifier: the output itself on the diode side, so a rise lifts gate\nXM1 d1 sense tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate refi tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device, its bleed and the capacitor on the output\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\nXRb out vss vss rppd w=0.5u l=23.355u\nXCo out vss cap_cmim w=29.962u l=29.962u m=37\n* Miller compensation: from the output back to gate\nXCc out gate cap_cmim w=29.761u l=29.761u m=60\n.ends\nXdut ref sense out vdd 0 ib ldounity\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 pwl(0 0 8u 0 8.4u 20u 20u 20u 20.4u 5u 28u 5u 28.4u 25u 40u 25u 40.4u 50u 48u 50u 48.4u 70u 60u 70u 60.4u 500u 68u 500u 68.4u 550u 80u 550u 80.4u 5m 88u 5m 88.4u 5.5m 100u 5.5m)\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.tran 10n 100u\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on the input, at the lightest and at the full load: how much of it reaches the output.", "measures": [], "metricKeys": [ "psrr_db", "psrr_hf_db" ], "acceptance": [ "psrr_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 20, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Unity-feedback PMOS LDO - supply rejection at 5mA\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD} ac 1\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldounity ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2\n* the reference arrives through Rr, the resistance of whatever drives it\nXRr ref refi vss rhigh w=0.5u l=6.078u\n* error amplifier: the output itself on the diode side, so a rise lifts gate\nXM1 d1 sense tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate refi tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device, its bleed and the capacitor on the output\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\nXRb out vss vss rppd w=0.5u l=23.355u\nXCo out vss cap_cmim w=29.962u l=29.962u m=37\n* Miller compensation: from the output back to gate\nXCc out gate cap_cmim w=29.761u l=29.761u m=60\n.ends\nXdut ref sense out vdd 0 ib ldounity\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 5m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.ac dec 20 1 100meg\n.end" }, { "id": "load_step", "label": "Load step", "note": "The load stepped from the lightest to the full load and back, each edge 1.00 µs: how far the output dips and peaks, and how long it takes to settle within 1 % after each edge. A loop that rings or oscillates at either load shows here, whatever the loop gain says.", "measures": [], "metricKeys": [ "undershoot", "overshoot", "t_recover", "t_release" ], "acceptance": [ "undershoot", "overshoot", "t_recover", "t_release" ], "acceptanceRules": [ { "key": "undershoot", "unit": "V", "min": null, "max": 0.2, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "overshoot", "unit": "V", "min": null, "max": 0.25, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "t_recover", "unit": "s", "min": null, "max": 0.000005, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "t_release", "unit": "s", "min": null, "max": 0.000005, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Unity-feedback PMOS LDO - load step\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldounity ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2\n* the reference arrives through Rr, the resistance of whatever drives it\nXRr ref refi vss rhigh w=0.5u l=6.078u\n* error amplifier: the output itself on the diode side, so a rise lifts gate\nXM1 d1 sense tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate refi tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device, its bleed and the capacitor on the output\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\nXRb out vss vss rppd w=0.5u l=23.355u\nXCo out vss cap_cmim w=29.962u l=29.962u m=37\n* Miller compensation: from the output back to gate\nXCc out gate cap_cmim w=29.761u l=29.761u m=60\n.ends\nXdut ref sense out vdd 0 ib ldounity\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 pulse(0 5m 4u 1u 1u 17u 80u)\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.tran 8n 40u\n.end" }, { "id": "line_step", "label": "Line step", "note": "The input stepped across its rated range, 1.08 V to 1.32 V, and back, each edge 1.00 µs, at full load: how far the output moves.", "measures": [], "metricKeys": [ "line_step" ], "acceptance": [ "line_step" ], "acceptanceRules": [ { "key": "line_step", "unit": "V", "min": null, "max": 0.15, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Unity-feedback PMOS LDO - line step at full load\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n* the input steps across its rated range and back\nVdd vdd 0 pulse(1.08 1.32 4u 1u 1u 17u 80u)\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldounity ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2\n* the reference arrives through Rr, the resistance of whatever drives it\nXRr ref refi vss rhigh w=0.5u l=6.078u\n* error amplifier: the output itself on the diode side, so a rise lifts gate\nXM1 d1 sense tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate refi tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device, its bleed and the capacitor on the output\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\nXRb out vss vss rppd w=0.5u l=23.355u\nXCo out vss cap_cmim w=29.962u l=29.962u m=37\n* Miller compensation: from the output back to gate\nXCc out gate cap_cmim w=29.761u l=29.761u m=60\n.ends\nXdut ref sense out vdd 0 ib ldounity\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 5m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.tran 8n 40u\n.end" }, { "id": "noise", "label": "Output noise", "note": "The noise at the output at full load: its density at 1 kHz and its total from 10 Hz to 100 kHz. The reference is an ideal, noiseless source, so this is the regulator's own noise.", "measures": [], "metricKeys": [ "vn_out", "vn_out_1k" ], "acceptance": [ "vn_out" ], "acceptanceRules": [ { "key": "vn_out", "unit": "V", "min": null, "max": 0.00003, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Unity-feedback PMOS LDO - output noise at full load\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\n* ac 1 only because ngspice's noise analysis names an input; the output noise does not depend on it\nVdd vdd 0 dc {VDD} ac 1\nVref ref 0 dc 600m\nIb vdd ib dc 10u\n.subckt ldounity ref sense out vdd vss ib\n* bias: the tail current, N copies of the reference Ib\nXMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1\nXMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2\n* the reference arrives through Rr, the resistance of whatever drives it\nXRr ref refi vss rhigh w=0.5u l=6.078u\n* error amplifier: the output itself on the diode side, so a rise lifts gate\nXM1 d1 sense tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM2 gate refi tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1\nXM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\nXM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1\n* the pass device, its bleed and the capacitor on the output\nXMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1\nXRb out vss vss rppd w=0.5u l=23.355u\nXCo out vss cap_cmim w=29.962u l=29.962u m=37\n* Miller compensation: from the output back to gate\nXCc out gate cap_cmim w=29.761u l=29.761u m=60\n.ends\nXdut ref sense out vdd 0 ib ldounity\n* the sense line: the regulator reads its output here\nVsense sense out 0\nCl out 0 100p\n* the load: v(il) amperes drawn from out, falling to none as out falls below 50 mV\nVload il 0 dc 5m\nBload out 0 i=v(il)*min(1, max(v(out), 0)/0.05)\n.control\nnoise v(out) Vdd dec 20 10 100k\nsetplot noise1\n* 20 points a decade from 10 Hz: point 40 is 1 kHz\nlet vn_1k = onoise_spectrum[40]\nprint vn_1k\nsetplot noise2\nprint onoise_total\n.endc\n.op\n.end" } ], "measurements": { "vout": { "label": "Output voltage", "unit": "V", "spec": { "min": 0.58, "max": 0.62 } }, "i_q": { "label": "Quiescent current", "unit": "A", "spec": { "min": null, "max": 0.0001 } }, "load_reg": { "label": "Load regulation", "unit": "V/A", "spec": { "min": null, "max": 4 } }, "line_reg": { "label": "Line regulation", "unit": "%/V", "spec": { "min": null, "max": 3 } }, "dropout": { "label": "Dropout at full load", "unit": "V", "spec": { "min": null, "max": 0.45 } }, "loop_gain_db": { "label": "DC loop gain at full load", "unit": "dB", "spec": { "min": 45, "max": null } }, "loop_ugf_hz": { "label": "Loop crossover at full load", "unit": "Hz", "spec": { "min": 150000, "max": null } }, "loop_pm_deg": { "label": "Loop phase margin, worst load", "unit": "deg", "spec": { "min": 55, "max": null } }, "ring_pct": { "label": "Ringing after a kick, worst load", "unit": "%", "spec": { "min": null, "max": 5 } }, "psrr_db": { "label": "Supply rejection at 1 kHz", "unit": "dB", "spec": { "min": 20, "max": null } }, "undershoot": { "label": "Undershoot on the load step", "unit": "V", "spec": { "min": null, "max": 0.2 } }, "overshoot": { "label": "Overshoot on the load release", "unit": "V", "spec": { "min": null, "max": 0.25 } }, "t_recover": { "label": "Settling after the load step", "unit": "s", "spec": { "min": null, "max": 0.000005 } }, "t_release": { "label": "Settling after the load release", "unit": "s", "spec": { "min": null, "max": 0.000005 } }, "line_step": { "label": "Output step for an input step", "unit": "V", "spec": { "min": null, "max": 0.15 } }, "vn_out": { "label": "Output noise, 10 Hz to 100 kHz", "unit": "V", "spec": { "min": null, "max": 0.00003 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "0d15a1c92b3991eefbd956b16a31211be8638d115765451bf48791733edd3ff4" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ldo-unity-5t.js", "sha256": "d99cc339ee1326a07c47bb80ec0918af2877080c011dfdaa4e25d9213e6d37f5" }, "simulationFingerprints": { "op": "0241f8acfe7e3df72edbd893855e238f3593cce0f6d619c6184a5f0450e98a8e", "load_reg": "4f08cfb1985466d8799e3666b7824b37379e2331caed43ffeb6a816c9d41bdbc", "line_reg": "661e2f8c85ba60f9b0512e69f284828797b840e389fc72353f1bbcf7d6b9ab09", "dropout": "5d2fac59a9e020a0bb9da251e3d2aa6ea1530e787492d0b7509acfdcb27df0a1", "loop": "f77bec81e53e1228a41bba10b6f8958f6e4081f0b25b22cf53bf243af285b32d", "ring": "63672ce818b2b05b4541fe7be9285ba4b87ecae1ee08e395d7df7547395adfc4", "psrr": "bac3abb063c8498128ab4cc8748901e12fcbb04dfe56b1ef7bdad3d6730b73d2", "load_step": "f038c5d6ec732a7093478366d4e97ad96f47dfd337c3c07e07d58fd329e46e2b", "line_step": "6c266c8a6851dd85f5c39777377c08040246d31e4881679ee431896aa52ce7df", "noise": "00c4fcbb440f10ba7eccc4b79ae32d150d6f73834ab05e73b75531151ffc3144" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "9ea4b903694a20adfd94ee1150402311e884437402c1521c0d660c0d36bf4ae0", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ldo-unity-5t", "parameters": { "Ib": 0.00001, "N": 2, "Wn": 0.000004, "Ln": 0.000001, "Rr": 20000, "W1": 0.00004, "L1": 0.000004, "Wp": 0.0002, "Lp": 0.000002, "Wpass": 0.0012, "Lpass": 2e-7, "Rb": 12000, "Co": 5e-11, "Cc": 8e-11, "Vref": 0.6, "IL": 0.005, "CL": 1e-10 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ldo-unity-5t/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "ldounity", "ports": [ { "name": "ref", "net": "ref", "kind": "input" }, { "name": "sense", "net": "sense", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMT tail ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRr", "displayName": "Rr", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRr ref refi vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "refi" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XM1 d1 sense tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "sense" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=40u l=4u ng=8 m=1", "source": "XM2 gate refi tail vss sg13_lv_nmos w=40u l=4u ng=8 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "refi" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=200u l=2u ng=40 m=1", "source": "XM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=200u l=2u ng=40 m=1", "source": "XM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], 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PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [], "scopes": [ { "id": "dut", "name": "ldounity", "ports": [ { "name": "ref", "net": "ref", "kind": "input" }, { "name": "sense", "net": "sense", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=4u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=1u ng=1 m=2", "source": "XMT tail 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PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc 1.2", "source": "Vdd vdd 0 dc 1.2", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m", "source": "Vref ref 0 dc 600m", "pins": [ { "id": "p", "net": "ref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 10u", "source": "Ib vdd ib dc 10u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", 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"voltageReferences": [] }, { "id": "ref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xdut", "pin": "ref" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "sense", "ground": false, "terminals": [ { "device": "Xdut", "pin": "sense" }, { "device": "Vsense", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vsense", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Bload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] }, { "id": "il", "ground": false, "terminals": [ { "device": "Vload", "pin": "p" } ], "ports": [], "voltageReferences": [ "Bload" ] } ] }, { "id": "subckt/ldounity", "name": "ldounity", "ports": [ { "name": "ref", "net": "ref" }, { "name": "sense", "net": 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"M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=200u l=2u ng=40 m=1", "source": "XM3 d1 d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=200u l=2u ng=40 m=1", "source": "XM4 gate d1 vdd vdd sg13_lv_pmos w=200u l=2u ng=40 m=1", "pins": [ { "id": "d", "net": "gate" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.2m l=200n ng=240 m=1", "source": "XMP out gate vdd vdd sg13_lv_pmos w=1.2m l=200n ng=240 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "gate" }, { "id": "s", "net": "vdd" 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