{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ota-2stage-micro", "name": "Micropower two-stage op amp, nulling-resistor Miller", "group": "Op amps and OTAs", "subgroup": "Two-stage op amps", "title": "Micropower two-stage op amp", "summary": "This two-stage amplifier is designed for a very small current budget. Its input transistors use weak inversion to obtain useful gain from little current. A compensation capacitor keeps feedback stable, but the small available current limits bandwidth and large-signal speed.", "reference": { "kind": "paper", "authors": "J. Li, H. Zhi, R. Lyu, W. Li, Z. Bi, K. Zhu, Y. Zeng, W. Shan, C. Yan, F. Yang, Y. Li, X. Zeng", "title": "AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis", "year": 2024, "where": "Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD '24), article 59, pp. 1-9", "doi": "10.1145/3676536.3697117", "takes": "The topology - a PMOS pair on an NMOS mirror, a common-source NMOS second stage, one Miller capacitor with a nulling resistor - and its micropower setting, a 100 nA reference. The weak-inversion sizing, the load, the compensation values and the spec targets are this library's.", "also": [ { "authors": "K. N. Leung and P. K. T. Mok", "title": "Analysis of Multistage Amplifier-Frequency Compensation", "year": 2001, "where": "IEEE Transactions on Circuits and Systems I, vol. 48, no. 9, pp. 1041-1056 - single Miller compensation with a nulling resistor (SMCNR)" } ] }, "resources": { "record": "/circuits/ota-2stage-micro.json", "page": "/index.html#ota-2stage-micro", "achieved": "/achieved/ota-2stage-micro.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "inp", "kind": "input" }, { "name": "inn", "kind": "input" }, { "name": "out", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the 100 nA reference, drawn out of this pin" } ], "devices": [ { "name": "MB", "type": "pmos", "nodes": "ib ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "bias reference, diode-connected", "fingers": 1, "copies": 1 }, { "name": "MT", "type": "pmos", "nodes": "tail ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "tail current source, two copies of MB", "fingers": 1, "copies": 2 }, { "name": "M1", "type": "pmos", "nodes": "d1 inn tail vdd", "sizedBy": [ "W1", "L1" ], "role": "input pair, inverting input", "fingers": 2, "copies": 1 }, { "name": "M2", "type": "pmos", "nodes": "d2 inp tail vdd", "sizedBy": [ "W1", "L1" ], "role": "input pair, non-inverting input", "fingers": 2, "copies": 1 }, { "name": "M3", "type": "nmos", "nodes": "d1 d1 vss vss", "sizedBy": [ "Wm", "Lm" ], "role": "mirror load, diode-connected", "fingers": 1, "copies": 1 }, { "name": "M4", "type": "nmos", "nodes": "d2 d1 vss vss", "sizedBy": [ "Wm", "Lm" ], "role": "mirror load, first-stage output", "fingers": 1, "copies": 1 }, { "name": "M5", "type": "nmos", "nodes": "out d2 vss vss", "sizedBy": [ "Wn", "Ln", "N" ], "role": "second stage, common source; N units at the mirror's W/L", "fingers": 1, "copies": 10 }, { "name": "M6", "type": "pmos", "nodes": "out ib vdd vdd", "sizedBy": [ "Wp", "Lp", "N" ], "role": "second-stage current source; N copies of MB", "fingers": 1, "copies": 10 }, { "name": "Cc", "type": "capacitor", "nodes": "d2 cz", "sizedBy": [ "Cc" ], "role": "Miller compensation" }, { "name": "Rz", "type": "resistor", "nodes": "cz out", "sizedBy": [ "Rz" ], "role": "nulling resistor" } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "The input pair: any difference is input offset. 10 µm × 4 µm each, and at 100 nA a side deep in weak inversion." }, { "rule": "match", "of": [ "M3", "M4" ], "why": "The mirror load: near weak inversion its g_m is close to the pair's, so its threshold mismatch reaches the input almost whole - most of the offset, and of the supply ripple a mismatch lets through. 1 × 8 µm each, four times the second-stage unit's area at its W/L: 1.4 mV σ of offset against 2.5 mV with 0.5 × 4 µm, and the worst supply rejection of 200 draws 79 dB against 74 dB." }, { "rule": "unit-copies", "of": [ "MB", "MT", "M6" ], "constraint": "MT = 2 copies of MB, M6 = N copies", "why": "The currents use repeated units of MB to preserve their nominal geometry-dependent ratio. Random threshold mismatch still matters strongly in weak inversion, and unequal drain voltages add systematic error." }, { "rule": "ratio", "of": [ "M5", "M4", "M6", "MT" ], "constraint": "M5 = N units with M4's W/L", "why": "M4 carries Ib with the pair balanced and M6 sources N Ib, so N units at M4's current density - its W/L, half its length - carry M6's current: d2 then sits at d1's voltage and there is no systematic offset. With 2N units d2 falls about 30 mV to sink the same current, and the offset grows tenfold. The units are kept small because their gates load d2." }, { "rule": "weak-inversion", "of": [ "M1", "M2", "M5" ], "constraint": "g_m ≈ I_D/(n U_T)", "why": "At these currents g_m is set by the current, not the size: the reference current sets the unity-gain frequency and the output pole, and since both g_m scale with 1/U_T their ratio, and the phase margin, hold over temperature." }, { "rule": "zero", "of": [ "Rz", "Cc", "M5" ], "constraint": "R_z > 1/g_m5, the zero above the crossover", "why": "Cc feeds d2 forward to the output: a right-half-plane zero at g_m5/C_c. R_z of 150 kΩ against 1/g_m5 of about 52 kΩ moves it into the left half-plane near 1 MHz, four times the crossover, where it gives phase back. Much larger brings the zero down onto the crossover, and R_z with the gate capacitance of M5 makes a pole of its own." } ], "specs": [ { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.0000015 A", "min": null, "max": 0.0000015, "why": "13 copies of the 100 nA reference: 0.1 µA in MB, 0.2 µA in the pair and 1 µA in the second stage. The reference is held at every corner." }, { "key": "dc_gain_db", "label": "DC open-loop gain", "unit": "dB", "direction": "max", "constraint": ">= 60 dB", "min": 60, "max": null, "why": "Two stages, each limited by its NMOS r_o: 69 dB at 27 °C, 64 dB hot, where the NMOS g_m/g_ds falls." }, { "key": "ugf_hz", "label": "Unity-gain frequency", "unit": "Hz", "direction": "max", "constraint": ">= 150000 Hz", "min": 150000, "max": null, "why": "g_m1/(2π C_c) with the pair in weak inversion: 250 kHz at 27 °C, falling as U_T rises to about 175 kHz hot and slow." }, { "key": "pm_deg", "label": "Phase margin", "unit": "deg", "direction": "max", "constraint": ">= 60 deg", "min": 60, "max": null, "why": "The output pole g_m5/C_L sits 2.5 times above the crossover and the nulling resistor's zero four times above it; both g_m scale with 1/U_T, so the margin holds over temperature: 69° to 85°." }, { "key": "t_settle", "label": "Settling time, 1 %", "unit": "s", "direction": "min", "constraint": "<= 0.000006 s", "min": null, "max": 0.000006, "why": "A 0.2 V step slews at I_tail/C_c, about 0.1 V/µs, then settles: 3.3 µs at 27 °C, 4.5 µs hot." }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 75 dB", "min": 75, "max": null, "why": "Every current is a copy of the reference, so a ripple on V_DD moves no bias: above 84 dB at every corner. A mismatch between the mirror's halves lets the ripple through, so the mirror is drawn large: the worst of 200 draws is 79 dB, against 74 dB with half-size units." }, { "key": "cmrr_db", "label": "Common-mode rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 75 dB", "min": 75, "max": null, "why": "The long tail and the matched mirror: above 87 dB at every corner and in every draw of seeds 1 to 40." }, { "key": "icmr_lo", "label": "Lowest input common mode", "unit": "V", "direction": "min", "constraint": "<= 0.1 V", "min": null, "max": 0.1, "why": "A PMOS pair on a weakly inverted NMOS mirror: the input works down to ground." }, { "key": "icmr_hi", "label": "Highest input common mode", "unit": "V", "direction": "max", "constraint": ">= 0.55 V", "min": 0.55, "max": null, "why": "The tail needs V_SG1 + V_DSAT,T below the supply: 0.63 V with the supply 10 % low." }, { "key": "swing_lo", "label": "Lowest output", "unit": "V", "direction": "min", "constraint": "<= 0.2 V", "min": null, "max": 0.2, "why": "M5 leaves saturation at about 0.14 V, 0.17 V hot." }, { "key": "swing_hi", "label": "Highest output", "unit": "V", "direction": "max", "constraint": ">= 0.85 V", "min": 0.85, "max": null, "why": "M6 leaves saturation a V_DSAT below the supply: 0.89 V with the supply 10 % low." } ], "explanation": { "idea": "This two-stage amplifier is designed for a very small current budget. Its input transistors use weak inversion to obtain useful gain from little current. A compensation capacitor keeps feedback stable, but the small available current limits bandwidth and large-signal speed.", "detail": "A two-stage op amp for a power budget of about a microamp: a PMOS pair on an NMOS mirror, then a common-source NMOS stage, all run from a 100 nA reference. At these currents the signal devices sit near weak inversion, where g_m approaches I_D/(n·U_T) at fixed current. Bias current therefore strongly controls the bandwidth, but device size still affects inversion level, capacitance, output resistance and mismatch. One Miller capacitor across the second stage makes d2 the dominant pole; its nulling resistor, well above 1/g_m5, turns the Miller zero into phase lead above the crossover.", "lesson": { "relation": 1, "symbols": "f_u is unity-gain frequency in Hz; g_m1 is input-device transconductance in S; C_c is compensation capacitance in F; I_tail is total input-pair bias current in A; n is the dimensionless weak-inversion slope factor. U_T = kT/q is thermal voltage in V: k is Boltzmann's constant, T is absolute temperature in kelvin, and q is elementary charge.", "assumptions": "Small signals with balanced, saturated input devices in weak inversion, each carrying half of I_tail, and a Miller-dominated response with other poles above crossover. Size still changes inversion level, parasitics, output resistance and mismatch.", "exercise": { "param": "Cc", "value": 3.2e-12, "analysis": "open_loop", "expect": "Increasing the compensation capacitance should lower the unity-gain frequency. Compare the phase margin as well; a slower crossover does not by itself prove every internal loop is stable." }, "limits": "Supply a suitable bias current and respect the input common-mode range, output swing and specified load. Qualification applies to the default design and declared conditions, not every editable setting." }, "path": [ { "part": "Input pair", "devices": "M1, M2, MT", "does": "MT's 200 nA divides between M1 and M2 as inp and inn differ; a rise on inp starves M2 and pulls d2 down." }, { "part": "Mirror load", "devices": "M3, M4", "does": "M3 turns M1's current into a gate voltage on d1 and M4 copies it onto d2, where both halves of the signal current meet." }, { "part": "Second stage", "devices": "M5, M6", "does": "M5, N units at the mirror's current density, amplifies d2 against M6, N copies of the bias unit, and inverts it onto out, so out follows inp." }, { "part": "Compensation", "devices": "Cc, Rz", "does": "Cc from d2 to out, multiplied by the second stage's gain, sets the dominant pole at d2; Rz in series moves the zero Cc makes into the left half-plane, above the crossover." } ], "bias": "The testbench draws 100 nA out of the diode MB. MT, two copies of it, gives the pair 200 nA, and M6, N = 10 copies, gives the second stage 1 µA: 1.3 µA in all. M5 is N units with the mirror's W/L, so with the pair balanced it sinks M6's 1 µA at the same current density as M4 carries 100 nA: d2 rests at d1's 0.25 V and the output carries almost no systematic offset. The mirror is drawn at four times a unit's area, 1 × 8 µm, for matching.", "relations": [ { "what": "Transconductance", "expr": "g_m ≈ I_D/(n·U_T)", "note": "The weak-inversion limit these devices approach: the pair reaches g_m/I_D of 28, M5 about 19; U_T = kT/q is 26 mV at room temperature." }, { "what": "Unity-gain frequency", "expr": "f_u ≈ g_m1/(2π C_c) ≈ I_tail/(4π n U_T C_c)", "note": "About 2.8 µS into 1.6 pF: 250 kHz. It approximately follows bias current while the input pair stays in weak inversion; sizing still affects inversion level and parasitic capacitance." }, { "what": "Output pole", "expr": "f_p2 ≈ g_m5/(2π C_L)", "note": "1 µA in M5 into 5 pF puts it near 620 kHz, 2.5 times the crossover. In the weak-inversion approximation both transconductances vary roughly as 1/U_T, helping their ratio track temperature. The model-based corner results check the remaining variation." }, { "what": "Compensation zero", "expr": "f_z = 1/[2π C_c (R_z − 1/g_m5)]", "note": "R_z is 150 kΩ against 1/g_m5 near 52 kΩ: the zero is in the left half-plane near 1 MHz and adds about 14° at the crossover." }, { "what": "DC gain", "expr": "A_0 ≈ g_m2 (r_o2 ∥ r_o4) · g_m5 (r_o5 ∥ r_o6)", "note": "In both stages the NMOS r_o is the short one - M4 has only its 0.25 V V_GS across it - so the gain is about 69 dB, 64 dB hot." }, { "what": "Nominal current balance", "expr": "(W/L)_5/(W/L)_4 = N = (W/L)_6/(W/L)_B", "note": "M4 carries Ib and M6 sources N·Ib, so M5 is N units with M4's W/L." } ], "tradeoffs": [ "Cc: larger lowers the unity-gain frequency and the slew rate, I_tail/C_c, and adds phase margin; smaller widens the bandwidth until the output pole, fixed by M5's 1 µA, catches up with it.", "N: more second-stage current raises g_m5 and pushes the output pole out, so a smaller Cc and a wider bandwidth become stable, at the cost of the supply current it multiplies.", "Rz: near 1/g_m5 the zero goes to infinity and gives nothing; much larger brings it down to the crossover, and Rz with M5's gate capacitance on d2 adds a pole of its own.", "A larger mirror (Wm, Lm) at the same W/L matches better - the offset falls from 2.5 to 1.4 mV σ and the worst supply rejection of 200 draws rises from 74 to 79 dB at 1 × 8 µm - but its gates load d1, the mirror's own pole, and the margin at the hot corner falls from 71° to 69°.", "Longer second-stage units (Ln) raise the gain only slowly - M4, not M5, has too little drain voltage - and their gate capacitance on d2 costs phase margin." ] }, "sizing": [ { "key": "Ib", "label": "Reference current", "unit": "A", "value": 1e-7, "min": 2e-8, "max": 0.000001, "kind": "si" }, { "key": "W1", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.00001, "min": 5e-7, "max": 0.00005, "kind": "si" }, { "key": "L1", "label": "L input pair", "unit": "m", "value": 0.000004, "min": 1.3e-7, "max": 0.00001, "kind": "si" }, { "key": "Wm", "label": "W NMOS mirror (M3, M4)", "unit": "m", "value": 0.000001, "min": 1.5e-7, "max": 0.00001, "kind": "si" }, { "key": "Lm", "label": "L NMOS mirror", "unit": "m", "value": 0.000008, "min": 1.3e-7, "max": 0.00002, "kind": "si" }, { "key": "Wn", "label": "W second-stage unit (M5)", "unit": "m", "value": 5e-7, "min": 1.5e-7, "max": 0.00001, "kind": "si" }, { "key": "Ln", "label": "L second-stage unit", "unit": "m", "value": 0.000004, "min": 1.3e-7, "max": 0.00001, "kind": "si" }, { "key": "Wp", "label": "W PMOS unit (MB, MT, M6)", "unit": "m", "value": 0.000001, "min": 1.5e-7, "max": 0.00001, "kind": "si" }, { "key": "Lp", "label": "L PMOS unit", "unit": "m", "value": 0.000008, "min": 1.3e-7, "max": 0.00001, "kind": "si" }, { "key": "N", "label": "Second-stage current, in Ib", "unit": "", "value": 10, "min": 2, "max": 40, "kind": "int" }, { "key": "Cc", "label": "Miller capacitor", "unit": "F", "value": 1.6e-12, "min": 2e-13, "max": 1e-11, "kind": "si" }, { "key": "Rz", "label": "Nulling resistor", "unit": "Ω", "value": 150000, "min": 1000, "max": 1000000, "kind": "si" }, { "key": "CL", "label": "Load capacitance", "unit": "F", "value": 5e-12, "min": 5e-13, "max": 5e-11, "kind": "si" }, { "key": "VCM", "label": "Input common mode", "unit": "V", "value": 0.4, "min": 0, "max": 0.6, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.", "measures": [], "metricKeys": [ "i_supply", "vout_dc", "vos" ], "acceptance": [ "i_supply" ], "acceptanceRules": [ { "key": "i_supply", "unit": "A", "min": null, "max": 0.0000015, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Micropower two-stage op amp - operating point as a unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 100n\n.subckt ota2u inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, copied twice\nXMB ib ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=2\n* first stage: a PMOS pair into an NMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1\nXM2 d2 inp tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=1u l=8u ng=1 m=1\nXM4 d2 d1 vss vss sg13_lv_nmos w=1u l=8u ng=1 m=1\n* second stage: common-source NMOS against a PMOS source; out rises with inp\nXM5 out d2 vss vss sg13_lv_nmos w=500n l=4u ng=1 m=10\nXM6 out ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=10\n* single Miller capacitor with its nulling resistor\nXCc d2 cz cap_cmim w=23.041u l=23.041u m=2\nXRz cz out vss rhigh w=0.5u l=46.225u\n.ends\nXdut inp inn out vdd 0 ib ota2u\nCl out 0 5p\nVin inp 0 dc 400m\n* the output drives the inverting input: a unity-gain buffer\nVfb inn out 0\n.op\n.end" }, { "id": "open_loop", "label": "Open-loop gain", "note": "Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.", "measures": [], "metricKeys": [ "dc_gain_db", "ugf_hz", "pm_deg", "gm_db" ], "acceptance": [ "dc_gain_db", "ugf_hz", "pm_deg" ], "acceptanceRules": [ { "key": "dc_gain_db", "unit": "dB", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "ugf_hz", "unit": "Hz", "min": 150000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "pm_deg", "unit": "deg", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Micropower two-stage op amp - open-loop gain and phase\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 100n\n.subckt ota2u inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, copied twice\nXMB ib ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=2\n* first stage: a PMOS pair into an NMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1\nXM2 d2 inp tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=1u l=8u ng=1 m=1\nXM4 d2 d1 vss vss sg13_lv_nmos w=1u l=8u ng=1 m=1\n* second stage: common-source NMOS against a PMOS source; out rises with inp\nXM5 out d2 vss vss sg13_lv_nmos w=500n l=4u ng=1 m=10\nXM6 out ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=10\n* single Miller capacitor with its nulling resistor\nXCc d2 cz cap_cmim w=23.041u l=23.041u m=2\nXRz cz out vss rhigh w=0.5u l=46.225u\n.ends\nXdut inp inn out vdd 0 ib ota2u\nCl out 0 5p\nVin inp 0 dc 400m ac 1\n* the loop closed at DC and open at every frequency the sweep visits\nLfb out inn 1t\nCfb inn 0 1t\n.ac dec 25 0.1 10g\n.end" }, { "id": "step", "label": "Step response", "note": "A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.", "measures": [], "metricKeys": [ "sr", "t_settle", "overshoot_pct" ], "acceptance": [ "t_settle" ], "acceptanceRules": [ { "key": "t_settle", "unit": "s", "min": null, "max": 0.000006, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Micropower two-stage op amp - step response of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 100n\n.subckt ota2u inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, copied twice\nXMB ib ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=2\n* first stage: a PMOS pair into an NMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1\nXM2 d2 inp tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=1u l=8u ng=1 m=1\nXM4 d2 d1 vss vss sg13_lv_nmos w=1u l=8u ng=1 m=1\n* second stage: common-source NMOS against a PMOS source; out rises with inp\nXM5 out d2 vss vss sg13_lv_nmos w=500n l=4u ng=1 m=10\nXM6 out ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=10\n* single Miller capacitor with its nulling resistor\nXCc d2 cz cap_cmim w=23.041u l=23.041u m=2\nXRz cz out vss rhigh w=0.5u l=46.225u\n.ends\nXdut inp inn out vdd 0 ib ota2u\nCl out 0 5p\nVin inp 0 pulse(300m 500m 4u 1n 1n 20u 80u)\nVfb inn out 0\n.tran 10n 40u\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.", "measures": [], "metricKeys": [ "psrr_db" ], "acceptance": [ "psrr_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 75, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Micropower two-stage op amp - supply rejection of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD} ac 1\nIb ib 0 100n\n.subckt ota2u inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, copied twice\nXMB ib ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=2\n* first stage: a PMOS pair into an NMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1\nXM2 d2 inp tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=1u l=8u ng=1 m=1\nXM4 d2 d1 vss vss sg13_lv_nmos w=1u l=8u ng=1 m=1\n* second stage: common-source NMOS against a PMOS source; out rises with inp\nXM5 out d2 vss vss sg13_lv_nmos w=500n l=4u ng=1 m=10\nXM6 out ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=10\n* single Miller capacitor with its nulling resistor\nXCc d2 cz cap_cmim w=23.041u l=23.041u m=2\nXRz cz out vss rhigh w=0.5u l=46.225u\n.ends\nXdut inp inn out vdd 0 ib ota2u\nCl out 0 5p\nVin inp 0 dc 400m\nVfb inn out 0\n.ac dec 25 1 100meg\n.end" }, { "id": "cmrr", "label": "Common-mode rejection", "note": "Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.", "measures": [], "metricKeys": [ "cmrr_db" ], "acceptance": [ "cmrr_db" ], "acceptanceRules": [ { "key": "cmrr_db", "unit": "dB", "min": 75, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Micropower two-stage op amp - common-mode rejection\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 100n\n.subckt ota2u inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, copied twice\nXMB ib ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=2\n* first stage: a PMOS pair into an NMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1\nXM2 d2 inp tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=1u l=8u ng=1 m=1\nXM4 d2 d1 vss vss sg13_lv_nmos w=1u l=8u ng=1 m=1\n* second stage: common-source NMOS against a PMOS source; out rises with inp\nXM5 out d2 vss vss sg13_lv_nmos w=500n l=4u ng=1 m=10\nXM6 out ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=10\n* single Miller capacitor with its nulling resistor\nXCc d2 cz cap_cmim w=23.041u l=23.041u m=2\nXRz cz out vss rhigh w=0.5u l=46.225u\n.ends\nXdut inp inn out vdd 0 ib ota2u\nCl out 0 5p\nVsrc src 0 dc 400m\n* va on the non-inverting input, vb in the feedback path: both inputs move with the signal\nVa inp src dc 0 ac 1\nVb inn out dc 0 ac 1\n.ac dec 25 1 100meg\n.end" }, { "id": "noise", "label": "Noise", "note": "Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.", "measures": [], "metricKeys": [ "vn_1k", "vn_int" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Micropower two-stage op amp - input-referred noise\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 100n\n.subckt ota2u inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, copied twice\nXMB ib ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=2\n* first stage: a PMOS pair into an NMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1\nXM2 d2 inp tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=1u l=8u ng=1 m=1\nXM4 d2 d1 vss vss sg13_lv_nmos w=1u l=8u ng=1 m=1\n* second stage: common-source NMOS against a PMOS source; out rises with inp\nXM5 out d2 vss vss sg13_lv_nmos w=500n l=4u ng=1 m=10\nXM6 out ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=10\n* single Miller capacitor with its nulling resistor\nXCc d2 cz cap_cmim w=23.041u l=23.041u m=2\nXRz cz out vss rhigh w=0.5u l=46.225u\n.ends\nXdut inp inn out vdd 0 ib ota2u\nCl out 0 5p\nVin inp 0 dc 400m ac 1\nVfb inn out 0\n.control\nnoise v(out) Vin dec 20 1 1meg\nsetplot noise1\n* 20 points a decade from 1 Hz: point 60 is 1 kHz\nlet vn_1k = inoise_spectrum[60]\nprint vn_1k\nsetplot noise2\nprint inoise_total\n.endc\n.op\n.end" }, { "id": "icmr", "label": "Input common-mode range", "note": "Both inputs swept together while the output is held at one level. The range is where open-loop gain falls by no more than 6 dB and unity-gain frequency by no more than 5 % from their values at the design common mode; increases are allowed.", "measures": [], "metricKeys": [ "icmr_lo", "icmr_hi" ], "acceptance": [ "icmr_lo", "icmr_hi" ], "acceptanceRules": [ { "key": "icmr_lo", "unit": "V", "min": null, "max": 0.1, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "icmr_hi", "unit": "V", "min": 0.55, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Micropower two-stage op amp - input common-mode range, the output held at one level\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 100n\n.subckt ota2u inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, copied twice\nXMB ib ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=2\n* first stage: a PMOS pair into an NMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1\nXM2 d2 inp tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=1u l=8u ng=1 m=1\nXM4 d2 d1 vss vss sg13_lv_nmos w=1u l=8u ng=1 m=1\n* second stage: common-source NMOS against a PMOS source; out rises with inp\nXM5 out d2 vss vss sg13_lv_nmos w=500n l=4u ng=1 m=10\nXM6 out ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=10\n* single Miller capacitor with its nulling resistor\nXCc d2 cz cap_cmim w=23.041u l=23.041u m=2\nXRz cz out vss rhigh w=0.5u l=46.225u\n.ends\nXdut inp inn out vdd 0 ib ota2u\nCl out 0 5p\nVin inp 0 dc 400m ac 1\nVpark park 0 dc 400m\n* inn is inp shifted by how far out is from park: the loop holds out at park\n* while both inputs follow inp, and it is closed at DC only, as in the\n* open-loop bench, so each ac sweep sees the open loop\nEfb fb inp out park 1\nLfb fb inn 1t\nCfb inn 0 1t\n.control\n* point 0 is the design common mode, the reference; then every level\nac dec 20 0.1 10g\nmeas ac a0_0 find vdb(out) at=0.1\nmeas ac fu_0 when vdb(out)=0 fall=1\nalter vin dc = 0\nac dec 20 0.1 10g\nmeas ac a0_1 find vdb(out) at=0.1\nmeas ac fu_1 when vdb(out)=0 fall=1\nalter vin dc = 30m\nac dec 20 0.1 10g\nmeas ac a0_2 find vdb(out) at=0.1\nmeas ac fu_2 when vdb(out)=0 fall=1\nalter vin dc = 60m\nac dec 20 0.1 10g\nmeas ac a0_3 find vdb(out) at=0.1\nmeas ac fu_3 when vdb(out)=0 fall=1\nalter vin dc = 90m\nac dec 20 0.1 10g\nmeas ac a0_4 find vdb(out) at=0.1\nmeas ac fu_4 when vdb(out)=0 fall=1\nalter vin dc = 120m\nac dec 20 0.1 10g\nmeas ac a0_5 find vdb(out) at=0.1\nmeas ac fu_5 when vdb(out)=0 fall=1\nalter vin dc = 150m\nac dec 20 0.1 10g\nmeas ac a0_6 find vdb(out) at=0.1\nmeas ac fu_6 when vdb(out)=0 fall=1\nalter vin dc = 180m\nac dec 20 0.1 10g\nmeas ac a0_7 find vdb(out) at=0.1\nmeas ac fu_7 when vdb(out)=0 fall=1\nalter vin dc = 210m\nac dec 20 0.1 10g\nmeas ac a0_8 find vdb(out) at=0.1\nmeas ac fu_8 when vdb(out)=0 fall=1\nalter vin dc = 240m\nac dec 20 0.1 10g\nmeas ac a0_9 find vdb(out) at=0.1\nmeas ac fu_9 when vdb(out)=0 fall=1\nalter vin dc = 270m\nac dec 20 0.1 10g\nmeas ac a0_10 find vdb(out) at=0.1\nmeas ac fu_10 when vdb(out)=0 fall=1\nalter vin dc = 300m\nac dec 20 0.1 10g\nmeas ac a0_11 find vdb(out) at=0.1\nmeas ac fu_11 when vdb(out)=0 fall=1\nalter vin dc = 330m\nac dec 20 0.1 10g\nmeas ac a0_12 find vdb(out) at=0.1\nmeas ac fu_12 when vdb(out)=0 fall=1\nalter vin dc = 360m\nac dec 20 0.1 10g\nmeas ac a0_13 find vdb(out) at=0.1\nmeas ac fu_13 when vdb(out)=0 fall=1\nalter vin dc = 390m\nac dec 20 0.1 10g\nmeas ac a0_14 find vdb(out) at=0.1\nmeas ac fu_14 when vdb(out)=0 fall=1\nalter vin dc = 420m\nac dec 20 0.1 10g\nmeas ac a0_15 find vdb(out) at=0.1\nmeas ac fu_15 when vdb(out)=0 fall=1\nalter vin dc = 450m\nac dec 20 0.1 10g\nmeas ac a0_16 find vdb(out) at=0.1\nmeas ac fu_16 when vdb(out)=0 fall=1\nalter vin dc = 480m\nac dec 20 0.1 10g\nmeas ac a0_17 find vdb(out) at=0.1\nmeas ac fu_17 when vdb(out)=0 fall=1\nalter vin dc = 510m\nac dec 20 0.1 10g\nmeas ac a0_18 find vdb(out) at=0.1\nmeas ac fu_18 when vdb(out)=0 fall=1\nalter vin dc = 540m\nac dec 20 0.1 10g\nmeas ac a0_19 find vdb(out) at=0.1\nmeas ac fu_19 when vdb(out)=0 fall=1\nalter vin dc = 570m\nac dec 20 0.1 10g\nmeas ac a0_20 find vdb(out) at=0.1\nmeas ac fu_20 when vdb(out)=0 fall=1\nalter vin dc = 600m\nac dec 20 0.1 10g\nmeas ac a0_21 find vdb(out) at=0.1\nmeas ac fu_21 when vdb(out)=0 fall=1\nalter vin dc = 630m\nac dec 20 0.1 10g\nmeas ac a0_22 find vdb(out) at=0.1\nmeas ac fu_22 when vdb(out)=0 fall=1\nalter vin dc = 660m\nac dec 20 0.1 10g\nmeas ac a0_23 find vdb(out) at=0.1\nmeas ac fu_23 when vdb(out)=0 fall=1\nalter vin dc = 690m\nac dec 20 0.1 10g\nmeas ac a0_24 find vdb(out) at=0.1\nmeas ac fu_24 when vdb(out)=0 fall=1\nalter vin dc = 720m\nac dec 20 0.1 10g\nmeas ac a0_25 find vdb(out) at=0.1\nmeas ac fu_25 when vdb(out)=0 fall=1\nalter vin dc = 750m\nac dec 20 0.1 10g\nmeas ac a0_26 find vdb(out) at=0.1\nmeas ac fu_26 when vdb(out)=0 fall=1\nalter vin dc = 780m\nac dec 20 0.1 10g\nmeas ac a0_27 find vdb(out) at=0.1\nmeas ac fu_27 when vdb(out)=0 fall=1\nalter vin dc = 810m\nac dec 20 0.1 10g\nmeas ac a0_28 find vdb(out) at=0.1\nmeas ac fu_28 when vdb(out)=0 fall=1\nalter vin dc = 840m\nac dec 20 0.1 10g\nmeas ac a0_29 find vdb(out) at=0.1\nmeas ac fu_29 when vdb(out)=0 fall=1\nalter vin dc = 870m\nac dec 20 0.1 10g\nmeas ac a0_30 find vdb(out) at=0.1\nmeas ac fu_30 when vdb(out)=0 fall=1\nalter vin dc = 900m\nac dec 20 0.1 10g\nmeas ac a0_31 find vdb(out) at=0.1\nmeas ac fu_31 when vdb(out)=0 fall=1\nalter vin dc = 930m\nac dec 20 0.1 10g\nmeas ac a0_32 find vdb(out) at=0.1\nmeas ac fu_32 when vdb(out)=0 fall=1\nalter vin dc = 960m\nac dec 20 0.1 10g\nmeas ac a0_33 find vdb(out) at=0.1\nmeas ac fu_33 when vdb(out)=0 fall=1\nalter vin dc = 990m\nac dec 20 0.1 10g\nmeas ac a0_34 find vdb(out) at=0.1\nmeas ac fu_34 when vdb(out)=0 fall=1\nalter vin dc = 1.02\nac dec 20 0.1 10g\nmeas ac a0_35 find vdb(out) at=0.1\nmeas ac fu_35 when vdb(out)=0 fall=1\nalter vin dc = 1.05\nac dec 20 0.1 10g\nmeas ac a0_36 find vdb(out) at=0.1\nmeas ac fu_36 when vdb(out)=0 fall=1\nalter vin dc = 1.08\nac dec 20 0.1 10g\nmeas ac a0_37 find vdb(out) at=0.1\nmeas ac fu_37 when vdb(out)=0 fall=1\nalter vin dc = 1.11\nac dec 20 0.1 10g\nmeas ac a0_38 find vdb(out) at=0.1\nmeas ac fu_38 when vdb(out)=0 fall=1\nalter vin dc = 1.14\nac dec 20 0.1 10g\nmeas ac a0_39 find vdb(out) at=0.1\nmeas ac fu_39 when vdb(out)=0 fall=1\nalter vin dc = 1.17\nac dec 20 0.1 10g\nmeas ac a0_40 find vdb(out) at=0.1\nmeas ac fu_40 when vdb(out)=0 fall=1\nalter vin dc = 1.2\nac dec 20 0.1 10g\nmeas ac a0_41 find vdb(out) at=0.1\nmeas ac fu_41 when vdb(out)=0 fall=1\nalter vin dc = 1.23\nac dec 20 0.1 10g\nmeas ac a0_42 find vdb(out) at=0.1\nmeas ac fu_42 when vdb(out)=0 fall=1\nalter vin dc = 1.26\nac dec 20 0.1 10g\nmeas ac a0_43 find vdb(out) at=0.1\nmeas ac fu_43 when vdb(out)=0 fall=1\nalter vin dc = 1.29\nac dec 20 0.1 10g\nmeas ac a0_44 find vdb(out) at=0.1\nmeas ac fu_44 when vdb(out)=0 fall=1\nalter vin dc = 1.32\nac dec 20 0.1 10g\nmeas ac a0_45 find vdb(out) at=0.1\nmeas ac fu_45 when vdb(out)=0 fall=1\n.endc\n.dc Vin 0 1.32 30m\n.end" }, { "id": "swing", "label": "Output swing", "note": "The amplifier as an inverting gain of one - its inverting input at the midpoint of the output and a signal, through two ideal controlled sources that load nothing - with the signal swept so the output crosses from rail to rail, and at each level the open-loop gain: the swing is where the gain stays within 6 dB of its value with the output at the input common mode.", "measures": [], "metricKeys": [ "swing_lo", "swing_hi" ], "acceptance": [ "swing_lo", "swing_hi" ], "acceptanceRules": [ { "key": "swing_lo", "unit": "V", "min": null, "max": 0.2, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "swing_hi", "unit": "V", "min": 0.85, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Micropower two-stage op amp - output swing, as an inverting amplifier of gain one\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 100n\n.subckt ota2u inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, copied twice\nXMB ib ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=2\n* first stage: a PMOS pair into an NMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1\nXM2 d2 inp tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=1u l=8u ng=1 m=1\nXM4 d2 d1 vss vss sg13_lv_nmos w=1u l=8u ng=1 m=1\n* second stage: common-source NMOS against a PMOS source; out rises with inp\nXM5 out d2 vss vss sg13_lv_nmos w=500n l=4u ng=1 m=10\nXM6 out ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=10\n* single Miller capacitor with its nulling resistor\nXCc d2 cz cap_cmim w=23.041u l=23.041u m=2\nXRz cz out vss rhigh w=0.5u l=46.225u\n.ends\nXdut inp inn out vdd 0 ib ota2u\nCl out 0 5p\nVcm inp 0 dc 400m ac 1\nVsig sig 0 dc 400m\n* inn is the midpoint of out and sig: v(out) = 2 V_CM - v(sig). Closed at DC\n* only, so each ac sweep reads the open-loop gain at that output level\nE1 fbn mid out 0 0.5\nE2 mid 0 sig 0 0.5\nLfb fbn inn 1t\nCfb inn 0 1t\n.control\n* point 0 has the output at the input common mode, the reference\nac dec 1 0.1 1\nmeas ac a0_0 find vdb(out) at=0.1\nalter vsig dc = 800m\nac dec 1 0.1 1\nmeas ac a0_1 find vdb(out) at=0.1\nalter vsig dc = 770m\nac dec 1 0.1 1\nmeas ac a0_2 find vdb(out) at=0.1\nalter vsig dc = 740m\nac dec 1 0.1 1\nmeas ac a0_3 find vdb(out) at=0.1\nalter vsig dc = 710m\nac dec 1 0.1 1\nmeas ac a0_4 find vdb(out) at=0.1\nalter vsig dc = 680m\nac dec 1 0.1 1\nmeas ac a0_5 find vdb(out) at=0.1\nalter vsig dc = 650m\nac dec 1 0.1 1\nmeas ac a0_6 find vdb(out) at=0.1\nalter vsig dc = 620m\nac dec 1 0.1 1\nmeas ac a0_7 find vdb(out) at=0.1\nalter vsig dc = 590m\nac dec 1 0.1 1\nmeas ac a0_8 find vdb(out) at=0.1\nalter vsig dc = 560m\nac dec 1 0.1 1\nmeas ac a0_9 find vdb(out) at=0.1\nalter vsig dc = 530m\nac dec 1 0.1 1\nmeas ac a0_10 find vdb(out) at=0.1\nalter vsig dc = 500m\nac dec 1 0.1 1\nmeas ac a0_11 find vdb(out) at=0.1\nalter vsig dc = 470m\nac dec 1 0.1 1\nmeas ac a0_12 find vdb(out) at=0.1\nalter vsig dc = 440m\nac dec 1 0.1 1\nmeas ac a0_13 find vdb(out) at=0.1\nalter vsig dc = 410m\nac dec 1 0.1 1\nmeas ac a0_14 find vdb(out) at=0.1\nalter vsig dc = 380m\nac dec 1 0.1 1\nmeas ac a0_15 find vdb(out) at=0.1\nalter vsig dc = 350m\nac dec 1 0.1 1\nmeas ac a0_16 find vdb(out) at=0.1\nalter vsig dc = 320m\nac dec 1 0.1 1\nmeas ac a0_17 find vdb(out) at=0.1\nalter vsig dc = 290m\nac dec 1 0.1 1\nmeas ac a0_18 find vdb(out) at=0.1\nalter vsig dc = 260m\nac dec 1 0.1 1\nmeas ac a0_19 find vdb(out) at=0.1\nalter vsig dc = 230m\nac dec 1 0.1 1\nmeas ac a0_20 find vdb(out) at=0.1\nalter vsig dc = 200m\nac dec 1 0.1 1\nmeas ac a0_21 find vdb(out) at=0.1\nalter vsig dc = 170m\nac dec 1 0.1 1\nmeas ac a0_22 find vdb(out) at=0.1\nalter vsig dc = 140m\nac dec 1 0.1 1\nmeas ac a0_23 find vdb(out) at=0.1\nalter vsig dc = 110m\nac dec 1 0.1 1\nmeas ac a0_24 find vdb(out) at=0.1\nalter vsig dc = 80m\nac dec 1 0.1 1\nmeas ac a0_25 find vdb(out) at=0.1\nalter vsig dc = 50m\nac dec 1 0.1 1\nmeas ac a0_26 find vdb(out) at=0.1\nalter vsig dc = 20m\nac dec 1 0.1 1\nmeas ac a0_27 find vdb(out) at=0.1\nalter vsig dc = -10m\nac dec 1 0.1 1\nmeas ac a0_28 find vdb(out) at=0.1\nalter vsig dc = -40m\nac dec 1 0.1 1\nmeas ac a0_29 find vdb(out) at=0.1\nalter vsig dc = -70m\nac dec 1 0.1 1\nmeas ac a0_30 find vdb(out) at=0.1\nalter vsig dc = -100m\nac dec 1 0.1 1\nmeas ac a0_31 find vdb(out) at=0.1\nalter vsig dc = -130m\nac dec 1 0.1 1\nmeas ac a0_32 find vdb(out) at=0.1\nalter vsig dc = -160m\nac dec 1 0.1 1\nmeas ac a0_33 find vdb(out) at=0.1\nalter vsig dc = -190m\nac dec 1 0.1 1\nmeas ac a0_34 find vdb(out) at=0.1\nalter vsig dc = -220m\nac dec 1 0.1 1\nmeas ac a0_35 find vdb(out) at=0.1\nalter vsig dc = -250m\nac dec 1 0.1 1\nmeas ac a0_36 find vdb(out) at=0.1\nalter vsig dc = -280m\nac dec 1 0.1 1\nmeas ac a0_37 find vdb(out) at=0.1\nalter vsig dc = -310m\nac dec 1 0.1 1\nmeas ac a0_38 find vdb(out) at=0.1\nalter vsig dc = -340m\nac dec 1 0.1 1\nmeas ac a0_39 find vdb(out) at=0.1\nalter vsig dc = -370m\nac dec 1 0.1 1\nmeas ac a0_40 find vdb(out) at=0.1\nalter vsig dc = -400m\nac dec 1 0.1 1\nmeas ac a0_41 find vdb(out) at=0.1\n.endc\n.dc Vsig -400m 800m 30m\n.end" } ], "measurements": { "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.0000015 } }, "dc_gain_db": { "label": "DC open-loop gain", "unit": "dB", "spec": { "min": 60, "max": null } }, "ugf_hz": { "label": "Unity-gain frequency", "unit": "Hz", "spec": { "min": 150000, "max": null } }, "pm_deg": { "label": "Phase margin", "unit": "deg", "spec": { "min": 60, "max": null } }, "t_settle": { "label": "Settling time, 1 %", "unit": "s", "spec": { "min": null, "max": 0.000006 } }, "psrr_db": { "label": "Supply rejection at 1 kHz", "unit": "dB", "spec": { "min": 75, "max": null } }, "cmrr_db": { "label": "Common-mode rejection at 1 kHz", "unit": "dB", "spec": { "min": 75, "max": null } }, "icmr_lo": { "label": "Lowest input common mode", "unit": "V", "spec": { "min": null, "max": 0.1 } }, "icmr_hi": { "label": "Highest input common mode", "unit": "V", "spec": { "min": 0.55, "max": null } }, "swing_lo": { "label": "Lowest output", "unit": "V", "spec": { "min": null, "max": 0.2 } }, "swing_hi": { "label": "Highest output", "unit": "V", "spec": { "min": 0.85, "max": null } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "fa12eef37b98e6d5f37ce2b37eb95c1bee806b52a2c9fd9bf2434ebf9dfa611f" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ota-2stage-micro.js", "sha256": "b2b165931416b903e29e984a769a03c9a9449cc714cb46784f4476187b20e5aa" }, "simulationFingerprints": { "op": "cdb5debf1bf36cd62a3b3b007962c3a978f90cab8adc80d484e597d396ac1ab8", "open_loop": "744994e3ddf5a9f448ee213db824fc246dd037164a707fc508ef02c4596abdbc", "step": "41fa77d74cd783770d413b662cab453c55c647a500386032199139911eb6bb79", "psrr": "058c7f10d40c85a007507de5f8b8d04bf38d2ff9bdb5fc10cfdfac94eed88038", "cmrr": "a0076a4f6a0cf4654d129d333e02a6df5b7bb3b653d240002cf0e8381ff156ab", "noise": "dcd88ab262515a0bf4955368bb2d893079c60acc2a1e9c924618976e1d0f9a00", "icmr": "2e60a511ee80574cd15dda8eafcf8cbbacab05039700af8e9f7ab7c294bf05c7", "swing": "6fbfe372f235863f17ec669cd63519d8965cb35563fe1b47eddac15c69d38c18" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "9087a860aca2f52de9aff74254bafab50cf41ece3c7ace45e7bbefb4cf8632e8", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ota-2stage-micro", "parameters": { "Ib": 1e-7, "W1": 0.00001, "L1": 0.000004, "Wm": 0.000001, "Lm": 0.000008, "Wn": 5e-7, "Ln": 0.000004, "Wp": 0.000001, "Lp": 0.000008, "N": 10, "Cc": 1.6e-12, "Rz": 150000, "CL": 5e-12, "VCM": 0.4 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ota-2stage-micro/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "ota2u", "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=8u ng=1 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=8u ng=1 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=4u ng=2 m=1", "source": "XM1 d1 inn tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=4u ng=2 m=1", "source": "XM2 d2 inp tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=8u ng=1 m=1", "source": "XM3 d1 d1 vss vss sg13_lv_nmos w=1u l=8u ng=1 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=8u ng=1 m=1", "source": "XM4 d2 d1 vss vss sg13_lv_nmos w=1u l=8u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=4u ng=1 m=10", "source": "XM5 out d2 vss vss sg13_lv_nmos w=500n l=4u ng=1 m=10", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=8u ng=1 m=10", "source": "XM6 out ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=10", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=23.041u l=23.041u m=2", "source": "XCc d2 cz cap_cmim w=23.041u l=23.041u m=2", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "cz" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=46.225u", "source": "XRz cz out vss rhigh w=0.5u l=46.225u", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XRz", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "cz", "ground": false, "terminals": [ { "device": "XCc", "pin": "n" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "100n", "source": "Ib ib 0 100n", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota2u", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota2u", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { 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"ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota2u", "name": "ota2u", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=8u ng=1 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=8u ng=1 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", 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"vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=8u ng=1 m=1", "source": "XM4 d2 d1 vss vss sg13_lv_nmos w=1u l=8u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=4u ng=1 m=10", "source": "XM5 out d2 vss vss sg13_lv_nmos w=500n l=4u ng=1 m=10", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=8u ng=1 m=10", "source": "XM6 out ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=10", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=23.041u l=23.041u m=2", "source": "XCc d2 cz cap_cmim w=23.041u l=23.041u m=2", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "cz" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=46.225u", "source": "XRz cz out vss rhigh w=0.5u l=46.225u", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [ "ib" ], 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}, { "device": "XM4", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XRz", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "cz", "ground": false, "terminals": [ { "device": "XCc", "pin": "n" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota2u" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Bias reference", "devices": [ { "scope": "dut", "device": "XMB" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "Tail current source", "devices": [ { "scope": "dut", "device": "XMT" } ], "inferredStages": [ 1 ] }, { "id": "block-3", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 1 ] }, { "id": "block-4", "label": "Mirror load", "devices": [ { "scope": "dut", "device": "XM3" }, { "scope": "dut", "device": "XM4" } ], "inferredStages": [ 1 ] }, { "id": "block-5", "label": "Second stage", "devices": [ { "scope": "dut", "device": "XM5" } ], "inferredStages": [ 2 ] }, { "id": "block-6", "label": "Second-stage current source; N copies of MB", "devices": [ { "scope": "dut", "device": "XM6" } ], "inferredStages": [ 2 ] }, { "id": "block-7", "label": "Miller compensation", "devices": [ { "scope": "dut", "device": "XCc" } ], "inferredStages": [ "comp" ] }, { "id": "block-8", "label": "Nulling resistor", "devices": [ { "scope": "dut", "device": "XRz" } ], "inferredStages": [ "comp" ] } ], "edges": [ { "id": "net-1", "net": "ib", "nodes": [ "block-1", "block-2", "block-6" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "tail", "nodes": [ "block-2", "block-3" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "d1", "nodes": [ "block-3", "block-4" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "d2", "nodes": [ "block-3", "block-4", "block-5", "block-7" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "out", "nodes": [ "block-5", "block-6", "block-8" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "cz", "nodes": [ "block-7", "block-8" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "100n", "source": "Ib ib 0 100n", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota2u", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota2u", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota2u" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "5p", "source": "Cl out 0 5p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m ac 1", "source": "Vin inp 0 dc 400m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfb", "displayName": "Lfb", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfb out inn 1t", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cfb", "displayName": "Cfb", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cfb inn 0 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" }, { "device": "Cfb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Lfb", "pin": "n" }, { "device": "Cfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Lfb", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota2u", "name": "ota2u", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=8u ng=1 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=8u ng=1 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=4u ng=2 m=1", "source": "XM1 d1 inn tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=4u ng=2 m=1", "source": "XM2 d2 inp tail vdd sg13_lv_pmos w=10u l=4u ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, 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], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=8u ng=1 m=10", "source": "XM6 out ib vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=10", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=23.041u l=23.041u m=2", "source": "XCc d2 cz cap_cmim w=23.041u l=23.041u m=2", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "cz" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=46.225u", "source": "XRz cz out vss rhigh w=0.5u l=46.225u", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP 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