{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ota-2stage-pmos", "name": "Two-stage Miller op amp, PMOS input", "group": "Op amps and OTAs", "subgroup": "Two-stage op amps", "title": "Two-stage Miller op amp, PMOS input", "summary": "This two-stage amplifier accepts inputs near ground through a PMOS input pair. A second stage provides more gain and drives the output. A compensation capacitor and series resistor keep feedback stable; the input range and output swing still stop at different limits.", "reference": { "kind": "book", "authors": "B. Razavi", "title": "Design of Analog CMOS Integrated Circuits", "edition": "2nd ed.", "publisher": "McGraw-Hill", "year": 2016, "where": "Sec. 9.3 (two-stage op amps) and Sec. 10.5 (compensating them)", "takes": "The topology - a PMOS pair on an NMOS mirror, an NMOS common-source second stage - and Miller compensation with a nulling resistor. The sizing is this library's, for SG13G2 at 1.2 V." }, "resources": { "record": "/circuits/ota-2stage-pmos.json", "page": "/index.html#ota-2stage-pmos", "achieved": "/achieved/ota-2stage-pmos.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "inp", "kind": "input" }, { "name": "inn", "kind": "input" }, { "name": "out", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the reference current, drawn out of this pin" } ], "devices": [ { "name": "MB", "type": "pmos", "nodes": "ib ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "bias reference, diode-connected", "fingers": 6, "copies": 1 }, { "name": "MT", "type": "pmos", "nodes": "tail ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "tail current source, two copies of MB", "fingers": 6, "copies": 2 }, { "name": "M1", "type": "pmos", "nodes": "d1 inn tail vdd", "sizedBy": [ "W1", "L1" ], "role": "input pair, inverting input", "fingers": 2, "copies": 1 }, { "name": "M2", "type": "pmos", "nodes": "d2 inp tail vdd", "sizedBy": [ "W1", "L1" ], "role": "input pair, non-inverting input", "fingers": 2, "copies": 1 }, { "name": "M3", "type": "nmos", "nodes": "d1 d1 vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "mirror load, diode-connected", "fingers": 1, "copies": 1 }, { "name": "M4", "type": "nmos", "nodes": "d2 d1 vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "mirror load, first-stage output", "fingers": 1, "copies": 1 }, { "name": "M6", "type": "nmos", "nodes": "out d2 vss vss", "sizedBy": [ "Wn", "Ln", "N" ], "role": "second stage, common source; N copies of the load unit", "fingers": 1, "copies": 10 }, { "name": "M7", "type": "pmos", "nodes": "out ib vdd vdd", "sizedBy": [ "Wp", "Lp", "N" ], "role": "second-stage current source; N copies of MB", "fingers": 6, "copies": 10 }, { "name": "Cc", "type": "capacitor", "nodes": "d2 cz", "sizedBy": [ "Cc" ], "role": "Miller compensation" }, { "name": "Rz", "type": "resistor", "nodes": "cz out", "sizedBy": [ "Rz" ], "role": "nulling resistor" } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "The input pair: any difference between them is input offset." }, { "rule": "match", "of": [ "M3", "M4" ], "why": "The mirror load: a mismatch copies the wrong current to d2 and appears as offset." }, { "rule": "unit-copies", "of": [ "MB", "MT", "M7" ], "constraint": "MT = 2 copies of MB, M7 = N copies", "why": "Repeating the same unit geometry preserves the intended nominal ratio and avoids geometry-dependent systematic shifts. Random mismatch and unequal drain voltages still cause current-copy errors." }, { "rule": "ratio", "of": [ "M6", "M4", "M7", "MT" ], "constraint": "M6 = N copies of the M3/M4 unit", "why": "With the pair balanced, each load unit carries Ib - half of MT's 2·Ib - and so does each copy of it in M6 at the same gate voltage; N copies sink the N·Ib that M7 sources. Any other count leaves the output only where a systematic offset pulls it: 2N copies left 1.9 mV of it at the input." }, { "rule": "zero", "of": [ "Rz", "M6" ], "constraint": "Rz > 1/g_m6", "why": "The Miller capacitor feeds the input of M6 forward to the output: a right-half-plane zero at g_m6/C_c. A series resistor above 1/g_m6 moves it into the left half-plane, where it adds phase instead of taking it." } ], "specs": [ { "key": "dc_gain_db", "label": "DC open-loop gain", "unit": "dB", "direction": "max", "constraint": ">= 55 dB", "min": 55, "max": null }, { "key": "ugf_hz", "label": "Unity-gain frequency", "unit": "Hz", "direction": "max", "constraint": ">= 7000000 Hz", "min": 7000000, "max": null }, { "key": "pm_deg", "label": "Phase margin", "unit": "deg", "direction": "max", "constraint": ">= 60 deg", "min": 60, "max": null }, { "key": "t_settle", "label": "Settling time, 1 %", "unit": "s", "direction": "min", "constraint": "<= 2e-7 s", "min": null, "max": 2e-7 }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 60 dB", "min": 60, "max": null }, { "key": "cmrr_db", "label": "Common-mode rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 50 dB", "min": 50, "max": null }, { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.00015 A", "min": null, "max": 0.00015 } ], "explanation": { "idea": "This two-stage amplifier accepts inputs near ground through a PMOS input pair. A second stage provides more gain and drives the output. A compensation capacitor and series resistor keep feedback stable; the input range and output swing still stop at different limits.", "detail": "A general-purpose two-stage op amp whose input pair is PMOS, so its input range extends near ground. The nominal measured lower limit is about 34 mV under the bench's gain and bandwidth criteria. The pair, on an NMOS mirror, turns the differential input into a current and a voltage at d2; a wide NMOS common-source stage against a PMOS source multiplies that gain again and drives the output across most of the supply. A Miller capacitor across the second stage makes d2 the dominant pole, and a resistor in series with it keeps the second stage's feed-forward from costing phase.", "lesson": { "relation": 1, "symbols": "f_u is unity-gain frequency in hertz; g_m1 is the input transistor's small-signal transconductance in siemens; C_c is the compensation capacitance in farads. Angular frequency ω_u = 2π f_u is in radians per second.", "assumptions": "Small signals around the default bias point, with the intended dominant pole and the other internal poles above crossover. Device and load parasitics make the relation approximate.", "exercise": { "param": "Cc", "value": 3.6e-12, "analysis": "open_loop", "expect": "Increasing the compensation capacitance should lower the unity-gain frequency. Compare the phase margin as well; a slower crossover does not by itself prove every internal loop is stable." }, "limits": "Supply a suitable bias current and respect the input common-mode range, output swing and specified load. Qualification applies to the default design and declared conditions, not every editable setting." }, "path": [ { "part": "Input pair", "devices": "M1, M2, MT", "does": "MT's tail current divides between M1 and M2 as vinp and vinn differ; a rise on inp starves M2." }, { "part": "Mirror load", "devices": "M3, M4", "does": "M3 turns M1's current into a gate voltage and M4 copies it onto d2, where both halves of the signal current meet: d2 falls as inp rises." }, { "part": "Second stage", "devices": "M6, M7", "does": "M6, N copies of the load unit, amplifies d2 against M7, N copies of the bias unit, and inverts it onto out, so out follows inp." }, { "part": "Compensation", "devices": "Cc, Rz", "does": "Cc from d2 to out, multiplied by the second stage's gain, sets the dominant pole at d2 and pushes the output pole out; Rz above 1/g_m6 moves the zero Cc makes into the left half-plane." } ], "bias": "The testbench draws the reference Ib (10 µA) out of the diode MB. MT is two copies of MB and feeds the pair with 2·Ib; M7 is N copies and feeds the second stage with N·Ib (100 µA at N = 10). With the pair balanced, M3 and M4 each carry Ib, half of the tail; M6 is N copies of that unit, so matched devices approximately balance the stage currents. Different drain voltages and random mismatch leave residual offset. The PMOS unit is wide, 24 µm, so that MT stays in saturation at the lowest supply and the hottest corner with the input common mode at 0.35 V: a starved tail is what lets the supply in.", "relations": [ { "what": "DC gain", "expr": "A_0 ≈ g_m1 (r_o2 ∥ r_o4) · g_m6 (r_o6 ∥ r_o7)", "note": "Two stages, each a transconductance into its own output resistance." }, { "what": "Unity-gain frequency", "expr": "ω_u ≈ g_m1/C_c", "note": "Set by the input pair and the Miller capacitor, not by the load." }, { "what": "Output pole", "expr": "ω_p2 ≈ g_m6/C_L", "note": "It must sit well above ω_u for a good phase margin: here about three times." }, { "what": "Compensation zero", "expr": "ω_z = 1/[C_c (1/g_m6 − R_z)]", "note": "Negative, in the left half-plane, once R_z > 1/g_m6." }, { "what": "Nominal current balance", "expr": "(W/L)_6/(W/L)_4 = 2·(W/L)_7/(W/L)_T", "note": "Met by copies: M6 = N units, M7 = N units, MT = 2 units - both sides equal N." } ], "tradeoffs": [ "Cc: larger lowers ω_u and slows the step, but adds phase margin; smaller widens the bandwidth until the output pole catches up with it.", "N: more second-stage current raises g_m6, pushing the output pole out and the slew into the load up, at the cost of supply current.", "Longer devices (L1, Ln, Lp) raise every r_o and the gain, but add capacitance at d2 and at the output, pulling the output pole in.", "Rz: too small leaves the zero in the right half-plane; much larger than 1/g_m6 brings the zero down towards ω_u, where it can lift the gain curve back up." ] }, "sizing": [ { "key": "Ib", "label": "Reference current", "unit": "A", "value": 0.00001, "min": 0.000001, "max": 0.00005, "kind": "si" }, { "key": "W1", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.00001, "min": 0.000001, "max": 0.00005, "kind": "si" }, { "key": "L1", "label": "L input pair", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wn", "label": "W NMOS unit (M3, M4, M6)", "unit": "m", "value": 0.000004, "min": 5e-7, "max": 0.00002, "kind": "si" }, { "key": "Ln", "label": "L NMOS unit", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wp", "label": "W PMOS unit (MB, MT, M7)", "unit": "m", "value": 0.000024, "min": 0.000001, "max": 0.00006, "kind": "si" }, { "key": "Lp", "label": "L PMOS unit", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "N", "label": "Second-stage current, in Ib", "unit": "", "value": 10, "min": 2, "max": 40, "kind": "int" }, { "key": "Cc", "label": "Miller capacitor", "unit": "F", "value": 1.8e-12, "min": 2e-13, "max": 2e-11, "kind": "si" }, { "key": "Rz", "label": "Nulling resistor", "unit": "Ω", "value": 2000, "min": 0, "max": 50000, "kind": "si" }, { "key": "CL", "label": "Load capacitance", "unit": "F", "value": 5e-12, "min": 5e-13, "max": 5e-11, "kind": "si" }, { "key": "VCM", "label": "Input common mode", "unit": "V", "value": 0.35, "min": 0, "max": 0.7, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.", "measures": [], "metricKeys": [ "i_supply", "vout_dc", "vos" ], "acceptance": [ "i_supply" ], "acceptanceRules": [ { "key": "i_supply", "unit": "A", "min": null, "max": 0.00015, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Two-stage Miller op amp, PMOS input - operating point as a unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt ota2p inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, copied twice\nXMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2\n* first stage: a PMOS pair into an NMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXM2 d2 inp tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1\nXM4 d2 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1\n* second stage: a common-source NMOS against a PMOS source; out rises with inp\nXM6 out d2 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=10\nXM7 out ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=10\n* Miller compensation, the nulling resistor in series\nXCc d2 cz cap_cmim w=24.442u l=24.442u m=2\nXRz cz out vss rppd w=0.5u l=3.663u\n.ends\nXdut inp inn out vdd 0 ib ota2p\nCl out 0 5p\nVin inp 0 dc 350m\n* the output drives the inverting input: a unity-gain buffer\nVfb inn out 0\n.op\n.end" }, { "id": "open_loop", "label": "Open-loop gain", "note": "Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.", "measures": [], "metricKeys": [ "dc_gain_db", "ugf_hz", "pm_deg", "gm_db" ], "acceptance": [ "dc_gain_db", "ugf_hz", "pm_deg" ], "acceptanceRules": [ { "key": "dc_gain_db", "unit": "dB", "min": 55, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "ugf_hz", "unit": "Hz", "min": 7000000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "pm_deg", "unit": "deg", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Two-stage Miller op amp, PMOS input - open-loop gain and phase\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt ota2p inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, copied twice\nXMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2\n* first stage: a PMOS pair into an NMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXM2 d2 inp tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1\nXM4 d2 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1\n* second stage: a common-source NMOS against a PMOS source; out rises with inp\nXM6 out d2 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=10\nXM7 out ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=10\n* Miller compensation, the nulling resistor in series\nXCc d2 cz cap_cmim w=24.442u l=24.442u m=2\nXRz cz out vss rppd w=0.5u l=3.663u\n.ends\nXdut inp inn out vdd 0 ib ota2p\nCl out 0 5p\nVin inp 0 dc 350m ac 1\n* the loop closed at DC and open at every frequency the sweep visits\nLfb out inn 1t\nCfb inn 0 1t\n.ac dec 25 0.1 10g\n.end" }, { "id": "step", "label": "Step response", "note": "A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.", "measures": [], "metricKeys": [ "sr", "t_settle", "overshoot_pct" ], "acceptance": [ "t_settle" ], "acceptanceRules": [ { "key": "t_settle", "unit": "s", "min": null, "max": 2e-7, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Two-stage Miller op amp, PMOS input - step response of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt ota2p inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, copied twice\nXMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2\n* first stage: a PMOS pair into an NMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXM2 d2 inp tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1\nXM4 d2 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1\n* second stage: a common-source NMOS against a PMOS source; out rises with inp\nXM6 out d2 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=10\nXM7 out ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=10\n* Miller compensation, the nulling resistor in series\nXCc d2 cz cap_cmim w=24.442u l=24.442u m=2\nXRz cz out vss rppd w=0.5u l=3.663u\n.ends\nXdut inp inn out vdd 0 ib ota2p\nCl out 0 5p\nVin inp 0 pulse(250m 450m 200n 1n 1n 1u 4u)\nVfb inn out 0\n.tran 500p 2u\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.", "measures": [], "metricKeys": [ "psrr_db" ], "acceptance": [ "psrr_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Two-stage Miller op amp, PMOS input - supply rejection of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD} ac 1\nIb ib 0 10u\n.subckt ota2p inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, copied twice\nXMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2\n* first stage: a PMOS pair into an NMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXM2 d2 inp tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1\nXM4 d2 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1\n* second stage: a common-source NMOS against a PMOS source; out rises with inp\nXM6 out d2 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=10\nXM7 out ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=10\n* Miller compensation, the nulling resistor in series\nXCc d2 cz cap_cmim w=24.442u l=24.442u m=2\nXRz cz out vss rppd w=0.5u l=3.663u\n.ends\nXdut inp inn out vdd 0 ib ota2p\nCl out 0 5p\nVin inp 0 dc 350m\nVfb inn out 0\n.ac dec 25 1 100meg\n.end" }, { "id": "cmrr", "label": "Common-mode rejection", "note": "Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.", "measures": [], "metricKeys": [ "cmrr_db" ], "acceptance": [ "cmrr_db" ], "acceptanceRules": [ { "key": "cmrr_db", "unit": "dB", "min": 50, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Two-stage Miller op amp, PMOS input - common-mode rejection\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt ota2p inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, copied twice\nXMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2\n* first stage: a PMOS pair into an NMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXM2 d2 inp tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1\nXM4 d2 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1\n* second stage: a common-source NMOS against a PMOS source; out rises with inp\nXM6 out d2 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=10\nXM7 out ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=10\n* Miller compensation, the nulling resistor in series\nXCc d2 cz cap_cmim w=24.442u l=24.442u m=2\nXRz cz out vss rppd w=0.5u l=3.663u\n.ends\nXdut inp inn out vdd 0 ib ota2p\nCl out 0 5p\nVsrc src 0 dc 350m\n* va on the non-inverting input, vb in the feedback path: both inputs move with the signal\nVa inp src dc 0 ac 1\nVb inn out dc 0 ac 1\n.ac dec 25 1 100meg\n.end" }, { "id": "noise", "label": "Noise", "note": "Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.", "measures": [], "metricKeys": [ "vn_1k", "vn_int" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Two-stage Miller op amp, PMOS input - input-referred noise\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt ota2p inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, copied twice\nXMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2\n* first stage: a PMOS pair into an NMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXM2 d2 inp tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1\nXM4 d2 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1\n* second stage: a common-source NMOS against a PMOS source; out rises with inp\nXM6 out d2 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=10\nXM7 out ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=10\n* Miller compensation, the nulling resistor in series\nXCc d2 cz cap_cmim w=24.442u l=24.442u m=2\nXRz cz out vss rppd w=0.5u l=3.663u\n.ends\nXdut inp inn out vdd 0 ib ota2p\nCl out 0 5p\nVin inp 0 dc 350m ac 1\nVfb inn out 0\n.control\nnoise v(out) Vin dec 20 1 1meg\nsetplot noise1\n* 20 points a decade from 1 Hz: point 60 is 1 kHz\nlet vn_1k = inoise_spectrum[60]\nprint vn_1k\nsetplot noise2\nprint inoise_total\n.endc\n.op\n.end" }, { "id": "icmr", "label": "Input common-mode range", "note": "Both inputs swept together while the output is held at one level. The range is where open-loop gain falls by no more than 6 dB and unity-gain frequency by no more than 5 % from their values at the design common mode; increases are allowed.", "measures": [], "metricKeys": [ "icmr_lo", "icmr_hi" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Two-stage Miller op amp, PMOS input - input common-mode range, the output held at one level\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt ota2p inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, copied twice\nXMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2\n* first stage: a PMOS pair into an NMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXM2 d2 inp tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1\nXM4 d2 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1\n* second stage: a common-source NMOS against a PMOS source; out rises with inp\nXM6 out d2 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=10\nXM7 out ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=10\n* Miller compensation, the nulling resistor in series\nXCc d2 cz cap_cmim w=24.442u l=24.442u m=2\nXRz cz out vss rppd w=0.5u l=3.663u\n.ends\nXdut inp inn out vdd 0 ib ota2p\nCl out 0 5p\nVin inp 0 dc 350m ac 1\nVpark park 0 dc 350m\n* inn is inp shifted by how far out is from park: the loop holds out at park\n* while both inputs follow inp, and it is closed at DC only, as in the\n* open-loop bench, so each ac sweep sees the open loop\nEfb fb inp out park 1\nLfb fb inn 1t\nCfb inn 0 1t\n.control\n* point 0 is the design common mode, the reference; then every level\nac dec 20 0.1 10g\nmeas ac a0_0 find vdb(out) at=0.1\nmeas ac fu_0 when vdb(out)=0 fall=1\nalter vin dc = 0\nac dec 20 0.1 10g\nmeas ac a0_1 find vdb(out) at=0.1\nmeas ac fu_1 when vdb(out)=0 fall=1\nalter vin dc = 30m\nac dec 20 0.1 10g\nmeas ac a0_2 find vdb(out) at=0.1\nmeas ac fu_2 when vdb(out)=0 fall=1\nalter vin dc = 60m\nac dec 20 0.1 10g\nmeas ac a0_3 find vdb(out) at=0.1\nmeas ac fu_3 when vdb(out)=0 fall=1\nalter vin dc = 90m\nac dec 20 0.1 10g\nmeas ac a0_4 find vdb(out) at=0.1\nmeas ac fu_4 when vdb(out)=0 fall=1\nalter vin dc = 120m\nac dec 20 0.1 10g\nmeas ac a0_5 find vdb(out) at=0.1\nmeas ac fu_5 when vdb(out)=0 fall=1\nalter vin dc = 150m\nac dec 20 0.1 10g\nmeas ac a0_6 find vdb(out) at=0.1\nmeas ac fu_6 when vdb(out)=0 fall=1\nalter vin dc = 180m\nac dec 20 0.1 10g\nmeas ac a0_7 find vdb(out) at=0.1\nmeas ac fu_7 when vdb(out)=0 fall=1\nalter vin dc = 210m\nac dec 20 0.1 10g\nmeas ac a0_8 find vdb(out) at=0.1\nmeas ac fu_8 when vdb(out)=0 fall=1\nalter vin dc = 240m\nac dec 20 0.1 10g\nmeas ac a0_9 find vdb(out) at=0.1\nmeas ac fu_9 when vdb(out)=0 fall=1\nalter vin dc = 270m\nac dec 20 0.1 10g\nmeas ac a0_10 find vdb(out) at=0.1\nmeas ac fu_10 when vdb(out)=0 fall=1\nalter vin dc = 300m\nac dec 20 0.1 10g\nmeas ac a0_11 find vdb(out) at=0.1\nmeas ac fu_11 when vdb(out)=0 fall=1\nalter vin dc = 330m\nac dec 20 0.1 10g\nmeas ac a0_12 find vdb(out) at=0.1\nmeas ac fu_12 when vdb(out)=0 fall=1\nalter vin dc = 360m\nac dec 20 0.1 10g\nmeas ac a0_13 find vdb(out) at=0.1\nmeas ac fu_13 when vdb(out)=0 fall=1\nalter vin dc = 390m\nac dec 20 0.1 10g\nmeas ac a0_14 find vdb(out) at=0.1\nmeas ac fu_14 when vdb(out)=0 fall=1\nalter vin dc = 420m\nac dec 20 0.1 10g\nmeas ac a0_15 find vdb(out) at=0.1\nmeas ac fu_15 when vdb(out)=0 fall=1\nalter vin dc = 450m\nac dec 20 0.1 10g\nmeas ac a0_16 find vdb(out) at=0.1\nmeas ac fu_16 when vdb(out)=0 fall=1\nalter vin dc = 480m\nac dec 20 0.1 10g\nmeas ac a0_17 find vdb(out) at=0.1\nmeas ac fu_17 when vdb(out)=0 fall=1\nalter vin dc = 510m\nac dec 20 0.1 10g\nmeas ac a0_18 find vdb(out) at=0.1\nmeas ac fu_18 when vdb(out)=0 fall=1\nalter vin dc = 540m\nac dec 20 0.1 10g\nmeas ac a0_19 find vdb(out) at=0.1\nmeas ac fu_19 when vdb(out)=0 fall=1\nalter vin dc = 570m\nac dec 20 0.1 10g\nmeas ac a0_20 find vdb(out) at=0.1\nmeas ac fu_20 when vdb(out)=0 fall=1\nalter vin dc = 600m\nac dec 20 0.1 10g\nmeas ac a0_21 find vdb(out) at=0.1\nmeas ac fu_21 when vdb(out)=0 fall=1\nalter vin dc = 630m\nac dec 20 0.1 10g\nmeas ac a0_22 find vdb(out) at=0.1\nmeas ac fu_22 when vdb(out)=0 fall=1\nalter vin dc = 660m\nac dec 20 0.1 10g\nmeas ac a0_23 find vdb(out) at=0.1\nmeas ac fu_23 when vdb(out)=0 fall=1\nalter vin dc = 690m\nac dec 20 0.1 10g\nmeas ac a0_24 find vdb(out) at=0.1\nmeas ac fu_24 when vdb(out)=0 fall=1\nalter vin dc = 720m\nac dec 20 0.1 10g\nmeas ac a0_25 find vdb(out) at=0.1\nmeas ac fu_25 when vdb(out)=0 fall=1\nalter vin dc = 750m\nac dec 20 0.1 10g\nmeas ac a0_26 find vdb(out) at=0.1\nmeas ac fu_26 when vdb(out)=0 fall=1\nalter vin dc = 780m\nac dec 20 0.1 10g\nmeas ac a0_27 find vdb(out) at=0.1\nmeas ac fu_27 when vdb(out)=0 fall=1\nalter vin dc = 810m\nac dec 20 0.1 10g\nmeas ac a0_28 find vdb(out) at=0.1\nmeas ac fu_28 when vdb(out)=0 fall=1\nalter vin dc = 840m\nac dec 20 0.1 10g\nmeas ac a0_29 find vdb(out) at=0.1\nmeas ac fu_29 when vdb(out)=0 fall=1\nalter vin dc = 870m\nac dec 20 0.1 10g\nmeas ac a0_30 find vdb(out) at=0.1\nmeas ac fu_30 when vdb(out)=0 fall=1\nalter vin dc = 900m\nac dec 20 0.1 10g\nmeas ac a0_31 find vdb(out) at=0.1\nmeas ac fu_31 when vdb(out)=0 fall=1\nalter vin dc = 930m\nac dec 20 0.1 10g\nmeas ac a0_32 find vdb(out) at=0.1\nmeas ac fu_32 when vdb(out)=0 fall=1\nalter vin dc = 960m\nac dec 20 0.1 10g\nmeas ac a0_33 find vdb(out) at=0.1\nmeas ac fu_33 when vdb(out)=0 fall=1\nalter vin dc = 990m\nac dec 20 0.1 10g\nmeas ac a0_34 find vdb(out) at=0.1\nmeas ac fu_34 when vdb(out)=0 fall=1\nalter vin dc = 1.02\nac dec 20 0.1 10g\nmeas ac a0_35 find vdb(out) at=0.1\nmeas ac fu_35 when vdb(out)=0 fall=1\nalter vin dc = 1.05\nac dec 20 0.1 10g\nmeas ac a0_36 find vdb(out) at=0.1\nmeas ac fu_36 when vdb(out)=0 fall=1\nalter vin dc = 1.08\nac dec 20 0.1 10g\nmeas ac a0_37 find vdb(out) at=0.1\nmeas ac fu_37 when vdb(out)=0 fall=1\nalter vin dc = 1.11\nac dec 20 0.1 10g\nmeas ac a0_38 find vdb(out) at=0.1\nmeas ac fu_38 when vdb(out)=0 fall=1\nalter vin dc = 1.14\nac dec 20 0.1 10g\nmeas ac a0_39 find vdb(out) at=0.1\nmeas ac fu_39 when vdb(out)=0 fall=1\nalter vin dc = 1.17\nac dec 20 0.1 10g\nmeas ac a0_40 find vdb(out) at=0.1\nmeas ac fu_40 when vdb(out)=0 fall=1\nalter vin dc = 1.2\nac dec 20 0.1 10g\nmeas ac a0_41 find vdb(out) at=0.1\nmeas ac fu_41 when vdb(out)=0 fall=1\nalter vin dc = 1.23\nac dec 20 0.1 10g\nmeas ac a0_42 find vdb(out) at=0.1\nmeas ac fu_42 when vdb(out)=0 fall=1\nalter vin dc = 1.26\nac dec 20 0.1 10g\nmeas ac a0_43 find vdb(out) at=0.1\nmeas ac fu_43 when vdb(out)=0 fall=1\nalter vin dc = 1.29\nac dec 20 0.1 10g\nmeas ac a0_44 find vdb(out) at=0.1\nmeas ac fu_44 when vdb(out)=0 fall=1\nalter vin dc = 1.32\nac dec 20 0.1 10g\nmeas ac a0_45 find vdb(out) at=0.1\nmeas ac fu_45 when vdb(out)=0 fall=1\n.endc\n.dc Vin 0 1.32 30m\n.end" }, { "id": "swing", "label": "Output swing", "note": "The amplifier as an inverting gain of one - its inverting input at the midpoint of the output and a signal, through two ideal controlled sources that load nothing - with the signal swept so the output crosses from rail to rail, and at each level the open-loop gain: the swing is where the gain stays within 6 dB of its value with the output at the input common mode.", "measures": [], "metricKeys": [ "swing_lo", "swing_hi" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Two-stage Miller op amp, PMOS input - output swing, as an inverting amplifier of gain one\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt ota2p inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, copied twice\nXMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2\n* first stage: a PMOS pair into an NMOS mirror; d2 falls as inp rises\nXM1 d1 inn tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXM2 d2 inp tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXM3 d1 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1\nXM4 d2 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1\n* second stage: a common-source NMOS against a PMOS source; out rises with inp\nXM6 out d2 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=10\nXM7 out ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=10\n* Miller compensation, the nulling resistor in series\nXCc d2 cz cap_cmim w=24.442u l=24.442u m=2\nXRz cz out vss rppd w=0.5u l=3.663u\n.ends\nXdut inp inn out vdd 0 ib ota2p\nCl out 0 5p\nVcm inp 0 dc 350m ac 1\nVsig sig 0 dc 350m\n* inn is the midpoint of out and sig: v(out) = 2 V_CM - v(sig). Closed at DC\n* only, so each ac sweep reads the open-loop gain at that output level\nE1 fbn mid out 0 0.5\nE2 mid 0 sig 0 0.5\nLfb fbn inn 1t\nCfb inn 0 1t\n.control\n* point 0 has the output at the input common mode, the reference\nac dec 1 0.1 1\nmeas ac a0_0 find vdb(out) at=0.1\nalter vsig dc = 700m\nac dec 1 0.1 1\nmeas ac a0_1 find vdb(out) at=0.1\nalter vsig dc = 670m\nac dec 1 0.1 1\nmeas ac a0_2 find vdb(out) at=0.1\nalter vsig dc = 640m\nac dec 1 0.1 1\nmeas ac a0_3 find vdb(out) at=0.1\nalter vsig dc = 610m\nac dec 1 0.1 1\nmeas ac a0_4 find vdb(out) at=0.1\nalter vsig dc = 580m\nac dec 1 0.1 1\nmeas ac a0_5 find vdb(out) at=0.1\nalter vsig dc = 550m\nac dec 1 0.1 1\nmeas ac a0_6 find vdb(out) at=0.1\nalter vsig dc = 520m\nac dec 1 0.1 1\nmeas ac a0_7 find vdb(out) at=0.1\nalter vsig dc = 490m\nac dec 1 0.1 1\nmeas ac a0_8 find vdb(out) at=0.1\nalter vsig dc = 460m\nac dec 1 0.1 1\nmeas ac a0_9 find vdb(out) at=0.1\nalter vsig dc = 430m\nac dec 1 0.1 1\nmeas ac a0_10 find vdb(out) at=0.1\nalter vsig dc = 400m\nac dec 1 0.1 1\nmeas ac a0_11 find vdb(out) at=0.1\nalter vsig dc = 370m\nac dec 1 0.1 1\nmeas ac a0_12 find vdb(out) at=0.1\nalter vsig dc = 340m\nac dec 1 0.1 1\nmeas ac a0_13 find vdb(out) at=0.1\nalter vsig dc = 310m\nac dec 1 0.1 1\nmeas ac a0_14 find vdb(out) at=0.1\nalter vsig dc = 280m\nac dec 1 0.1 1\nmeas ac a0_15 find vdb(out) at=0.1\nalter vsig dc = 250m\nac dec 1 0.1 1\nmeas ac a0_16 find vdb(out) at=0.1\nalter vsig dc = 220m\nac dec 1 0.1 1\nmeas ac a0_17 find vdb(out) at=0.1\nalter vsig dc = 190m\nac dec 1 0.1 1\nmeas ac a0_18 find vdb(out) at=0.1\nalter vsig dc = 160m\nac dec 1 0.1 1\nmeas ac a0_19 find vdb(out) at=0.1\nalter vsig dc = 130m\nac dec 1 0.1 1\nmeas ac a0_20 find vdb(out) at=0.1\nalter vsig dc = 100m\nac dec 1 0.1 1\nmeas ac a0_21 find vdb(out) at=0.1\nalter vsig dc = 70m\nac dec 1 0.1 1\nmeas ac a0_22 find vdb(out) at=0.1\nalter vsig dc = 40m\nac dec 1 0.1 1\nmeas ac a0_23 find vdb(out) at=0.1\nalter vsig dc = 10m\nac dec 1 0.1 1\nmeas ac a0_24 find vdb(out) at=0.1\nalter vsig dc = -20m\nac dec 1 0.1 1\nmeas ac a0_25 find vdb(out) at=0.1\nalter vsig dc = -50m\nac dec 1 0.1 1\nmeas ac a0_26 find vdb(out) at=0.1\nalter vsig dc = -80m\nac dec 1 0.1 1\nmeas ac a0_27 find vdb(out) at=0.1\nalter vsig dc = -110m\nac dec 1 0.1 1\nmeas ac a0_28 find vdb(out) at=0.1\nalter vsig dc = -140m\nac dec 1 0.1 1\nmeas ac a0_29 find vdb(out) at=0.1\nalter vsig dc = -170m\nac dec 1 0.1 1\nmeas ac a0_30 find vdb(out) at=0.1\nalter vsig dc = -200m\nac dec 1 0.1 1\nmeas ac a0_31 find vdb(out) at=0.1\nalter vsig dc = -230m\nac dec 1 0.1 1\nmeas ac a0_32 find vdb(out) at=0.1\nalter vsig dc = -260m\nac dec 1 0.1 1\nmeas ac a0_33 find vdb(out) at=0.1\nalter vsig dc = -290m\nac dec 1 0.1 1\nmeas ac a0_34 find vdb(out) at=0.1\nalter vsig dc = -320m\nac dec 1 0.1 1\nmeas ac a0_35 find vdb(out) at=0.1\nalter vsig dc = -350m\nac dec 1 0.1 1\nmeas ac a0_36 find vdb(out) at=0.1\nalter vsig dc = -380m\nac dec 1 0.1 1\nmeas ac a0_37 find vdb(out) at=0.1\nalter vsig dc = -410m\nac dec 1 0.1 1\nmeas ac a0_38 find vdb(out) at=0.1\nalter vsig dc = -440m\nac dec 1 0.1 1\nmeas ac a0_39 find vdb(out) at=0.1\nalter vsig dc = -470m\nac dec 1 0.1 1\nmeas ac a0_40 find vdb(out) at=0.1\nalter vsig dc = -500m\nac dec 1 0.1 1\nmeas ac a0_41 find vdb(out) at=0.1\n.endc\n.dc Vsig -500m 700m 30m\n.end" } ], "measurements": { "dc_gain_db": { "label": "DC open-loop gain", "unit": "dB", "spec": { "min": 55, "max": null } }, "ugf_hz": { "label": "Unity-gain frequency", "unit": "Hz", "spec": { "min": 7000000, "max": null } }, "pm_deg": { "label": "Phase margin", "unit": "deg", "spec": { "min": 60, "max": null } }, "t_settle": { "label": "Settling time, 1 %", "unit": "s", "spec": { "min": null, "max": 2e-7 } }, "psrr_db": { "label": "Supply rejection at 1 kHz", "unit": "dB", "spec": { "min": 60, "max": null } }, "cmrr_db": { "label": "Common-mode rejection at 1 kHz", "unit": "dB", "spec": { "min": 50, "max": null } }, "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.00015 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "84a4325874cb9964e44050d3ff2ab77cb03c3d2bf3ffff1a4219ee3caa0849cf" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ota-2stage-pmos.js", "sha256": "f6466b06b26d8c84eb4149d0652b74efea4f0824842cf68a64bc62c2c32913dd" }, "simulationFingerprints": { "op": "01375e69a690f1413091af14a8f3c39db97c411c96d481a37676c85be8ea10a2", "open_loop": "61a399a52b0c9a7dab3732f4e0bf8c9bd91ff99a3550fb0d5ddb8eab9620cda3", "step": "49f55e9a95a238e3e0b2461bdfa1e71407f894ef0de4c7a860b0cb5233ef13c8", "psrr": "980c36514079c008b8c7dec4c60e6e8b5fb0707f18b5d14be23a3ff0085a3379", "cmrr": "ac9138a613a1784ec0c492c8650daabc915f0886ee8c7240affba3bce1cc829c", "noise": "b7d349a75dcd74d2856d61b7922a1e97bf979739a9b2ad2c80efd23a52f17042", "icmr": "068376eab6a43eb3552c9c9a55240d486cbd7c493caffbaa63c6580fc12e8264", "swing": "5eb1939aece5fc87d57ea5a8c412bf2a51f9b98c63c601adce9bfec9b578d277" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "ee1dfc1f706b42b175a57fd770231c5f66e5822bd4b010ef4e88cd4c8d5ea509", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ota-2stage-pmos", "parameters": { "Ib": 0.00001, "W1": 0.00001, "L1": 5e-7, "Wn": 0.000004, "Ln": 0.000002, "Wp": 0.000024, "Lp": 0.000002, "N": 10, "Cc": 1.8e-12, "Rz": 2000, "CL": 5e-12, "VCM": 0.35 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ota-2stage-pmos/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "ota2p", "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=1", "source": "XM1 d1 inn tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=1", "source": "XM2 d2 inp tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XM3 d1 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XM4 d2 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=10", "source": "XM6 out d2 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=10", "source": "XM7 out ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=10", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=24.442u l=24.442u m=2", "source": "XCc d2 cz cap_cmim w=24.442u l=24.442u m=2", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "cz" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=3.663u", "source": "XRz cz out vss rppd w=0.5u l=3.663u", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM7", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "g" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XRz", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "cz", "ground": false, "terminals": [ { "device": "XCc", "pin": "n" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota2p", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota2p", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota2p" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "5p", "source": "Cl out 0 5p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 350m", "source": "Vin inp 0 dc 350m", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota2p", "name": "ota2p", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=1", "source": "XM1 d1 inn tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=1", "source": "XM2 d2 inp tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XM3 d1 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XM4 d2 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=10", "source": "XM6 out d2 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=10", "source": "XM7 out ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=10", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=24.442u l=24.442u m=2", "source": "XCc d2 cz cap_cmim w=24.442u l=24.442u m=2", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "cz" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=3.663u", "source": "XRz cz out vss rppd w=0.5u l=3.663u", "pins": [ { "id": "p", "net": "cz" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM7", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "g" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XRz", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "cz", "ground": false, "terminals": [ { "device": "XCc", "pin": "n" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota2p" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Bias reference", "devices": [ { "scope": "dut", "device": "XMB" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "Tail current source", "devices": [ { "scope": "dut", "device": "XMT" } ], "inferredStages": [ 1 ] }, { "id": "block-3", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 1 ] }, { "id": "block-4", "label": "Mirror load", "devices": [ { "scope": "dut", "device": "XM3" }, { "scope": "dut", "device": "XM4" } ], "inferredStages": [ 1 ] }, { "id": "block-5", "label": "Second stage", "devices": [ { "scope": "dut", "device": "XM6" } ], "inferredStages": [ 2 ] }, { "id": "block-6", "label": "Second-stage current source; N copies of MB", "devices": [ { "scope": "dut", "device": "XM7" } ], "inferredStages": [ 2 ] }, { "id": "block-7", "label": "Miller compensation", "devices": [ { "scope": "dut", "device": "XCc" } ], "inferredStages": [ "comp" ] }, { "id": "block-8", "label": "Nulling resistor", "devices": [ { "scope": "dut", "device": "XRz" } ], "inferredStages": [ "comp" ] } ], "edges": [ { "id": "net-1", "net": "ib", "nodes": [ "block-1", "block-2", "block-6" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "tail", "nodes": [ "block-2", "block-3" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "d1", "nodes": [ "block-3", "block-4" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "d2", "nodes": [ "block-3", "block-4", "block-5", "block-7" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "out", "nodes": [ "block-5", "block-6", "block-8" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "cz", "nodes": [ "block-7", "block-8" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota2p", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota2p", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota2p" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "5p", "source": "Cl out 0 5p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 350m ac 1", "source": "Vin inp 0 dc 350m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfb", "displayName": "Lfb", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfb out inn 1t", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cfb", "displayName": "Cfb", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cfb inn 0 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" }, { "device": "Cfb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Lfb", "pin": "n" }, { "device": "Cfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Lfb", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota2p", "name": "ota2p", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=1", "source": "XM1 d1 inn tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=1", "source": "XM2 d2 inp tail vdd sg13_lv_pmos w=10u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XM3 d1 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=1", "source": "XM4 d2 d1 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=2u ng=1 m=10", "source": "XM6 out d2 vss vss sg13_lv_nmos w=4u l=2u ng=1 m=10", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": 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"ota2p", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", 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