{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ota-2stage", "name": "Two-stage Miller OTA", "group": "Op amps and OTAs", "subgroup": "Two-stage op amps", "title": "Two-stage Miller OTA", "summary": "This amplifier uses two stages to turn a small input-voltage difference into a larger output. A capacitor keeps the feedback loop stable by slowing the first stage. A series resistor helps recover speed without losing too much stability.", "reference": { "kind": "book", "authors": "P. E. Allen and D. R. Holberg", "title": "CMOS Analog Circuit Design", "edition": "3rd ed.", "publisher": "Oxford University Press", "year": 2012, "where": "CMOS Operational Amplifiers - the two-stage op amp and its design procedure", "takes": "The topology, the current-matching rule between the two stages, and the nulling resistor in series with the Miller capacitor.", "also": [ { "authors": "B. Razavi", "title": "Design of Analog CMOS Integrated Circuits", "edition": "2nd ed.", "year": 2017, "where": "Stability and Frequency Compensation - Miller compensation and the right-half-plane zero" } ] }, "resources": { "record": "/circuits/ota-2stage.json", "page": "/index.html#ota-2stage", "achieved": "/achieved/ota-2stage.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "inp", "kind": "input", "polarity": "+" }, { "name": "inn", "kind": "input", "polarity": "-" }, { "name": "out", "kind": "output" }, { "name": "bn", "kind": "bias", "note": "inject I_b into Mb's diode-connected node; the core mirrors this externally supplied reference current" }, { "name": "vdd", "kind": "supply", "value": "VDD" }, { "name": "0", "kind": "ground" } ], "devices": [ { "name": "Mb", "type": "nmos", "nodes": "bn bn 0 0", "sizedBy": [ "Wb", "Lb" ], "role": "bias mirror, diode-connected", "fingers": 2, "copies": 1 }, { "name": "Mt", "type": "nmos", "nodes": "tail bn 0 0", "sizedBy": [ "Wb", "Lb" ], "role": "tail current source", "fingers": 2, "copies": 1 }, { "name": "M1", "type": "nmos", "nodes": "n1 inn tail 0", "sizedBy": [ "W", "L" ], "role": "input pair, inverting input", "fingers": 4, "copies": 1 }, { "name": "M2", "type": "nmos", "nodes": "n2 inp tail 0", "sizedBy": [ "W", "L" ], "role": "input pair, non-inverting input", "fingers": 4, "copies": 1 }, { "name": "M3", "type": "pmos", "nodes": "n1 n1 vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "load mirror, diode-connected", "fingers": 4, "copies": 1 }, { "name": "M4", "type": "pmos", "nodes": "n2 n1 vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "load mirror", "fingers": 4, "copies": 1 }, { "name": "M5", "type": "pmos", "nodes": "out n2 vdd vdd", "sizedBy": [ "Wp", "Lp", "N5" ], "role": "second stage, common source; N5 copies of the load device", "fingers": 4, "copies": 8 }, { "name": "M6", "type": "nmos", "nodes": "out bn 0 0", "sizedBy": [ "Wb", "Lb", "N6" ], "role": "second stage current sink; N6 copies of the bias device", "fingers": 2, "copies": 4 }, { "name": "Cc", "type": "capacitor", "sizedBy": [ "Cc" ], "role": "Miller compensation" }, { "name": "Rz", "type": "resistor", "sizedBy": [ "Rz" ], "role": "nulling resistor" } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "Input pair. Their mismatch is the amplifier's input-referred offset." }, { "rule": "match", "of": [ "M3", "M4" ], "why": "Load mirror. Mismatch here becomes offset and common-mode gain." }, { "rule": "ratio", "of": [ "M5", "M3", "M6", "Mb" ], "expr": "N5 = 2·N6", "why": "The current M5 sources must be the current M6 sinks. M5 copies the load device, which carries half the tail current (I_bias/2); M6 copies the bias device, which carries all of I_bias. So balance needs twice as many copies on the P side: 8 = 2 × 4 as shipped. Break it and the first stage's output moves to wherever M5 carries what M6 sinks: with the loop closed that is a systematic offset and a squeezed input device, open it is an output on a rail." }, { "rule": "unit-devices", "of": [ "M5", "M6" ], "expr": "M5 = N5 × M3, M6 = N6 × Mb", "why": "Each ratio is made by repeating the reference device, never by drawing one wider device. In SG13G2 a narrow NMOS has a higher threshold than a wide one: with 0.3 V on the gate a 40 µm NMOS carries 6.3 times what a 10 µm one does, not 4, and even at 1.2 V it is 4.3. Drawn as one 40 µm device, M6 sinks 127 µA where four copies sink 87 µA: the second stage draws 46 % more current than designed, and n2 moves 28 mV so that M5 can match it, which leaves 1.2 mV of systematic offset at the input. Copies of one device share its threshold, and changing that device's W or L changes every copy with it, so the ratio cannot drift." }, { "rule": "input-polarity", "of": [ "M1", "M2" ], "constraint": "feedback closes on M1's gate (inn); M2's (inp) is non-inverting", "why": "Two inversions: M2 pulls n2 down, and the PMOS second stage turns that round again, so the output follows M2's gate and M2's is the non-inverting input. Feed back to it and the loop latches with the output on a rail. The sky130 version of this deck had the two inputs the other way round; its solver happened to settle on the balanced point anyway, and a .nodeset was written to keep it there. PSP's does not, which is how the wiring was caught." }, { "rule": "compensation", "of": [ "Cc", "Rz" ], "constraint": "R_z > 1/g_m5; phase margin ≥ 60° at every corner", "why": "C_c sets the unity-gain frequency, 22 MHz. R_z, 3 kΩ against 1/g_m5 = 0.81 kΩ, puts C_c's zero in the left half plane near 50 MHz, where it gives phase back at the crossover: 73.0° at the typical corner, 65.6° at the worst, fast and cold with the supply 10 % high. The fast corner is the hard one: C_c and R_z are both 10 % low there, which moves the crossover out and the zero up. With 2 kΩ the zero sat near 90 MHz and that corner kept only 59.9°; with no R_z it is a right-half-plane zero and the typical margin is 49.5°." } ], "specs": [ { "key": "a0", "label": "Open-loop DC gain", "unit": "dB", "direction": "max", "typical": 60 }, { "key": "gbw", "label": "Unity-gain frequency", "unit": "Hz", "direction": "max" }, { "key": "pm", "label": "Phase margin", "unit": "deg", "direction": "min", "constraint": ">= 60 for a unity-gain loop" }, { "key": "idd", "label": "Supply current", "unit": "A", "direction": "min" } ], "explanation": { "idea": "This amplifier uses two stages to turn a small input-voltage difference into a larger output. A capacitor keeps the feedback loop stable by slowing the first stage. A series resistor helps recover speed without losing too much stability.", "detail": "A two-stage OTA for more gain than one SG13G2 stage gives: a five-transistor first stage drives a common-source second stage, so the two gains multiply. Two high-impedance nodes mean two low poles, so C_c, bridging the second stage, splits them: Miller multiplication makes n2 dominant while the output pole moves out. C_c also feeds n2 forward to the output, a right-half-plane zero; R_z in series moves it away.", "lesson": { "relation": 3, "symbols": "ω_z is the signed zero-location parameter in rad/s; C_c is Miller capacitance in F; g_m5 is second-stage transconductance in S; R_z is the series resistor in Ω. The stated convention makes positive ω_z a right-half-plane zero.", "assumptions": "Small signals around the default bias point, with the intended dominant pole and the other internal poles above crossover. Device and load parasitics make the relation approximate.", "exercise": { "param": "Rz", "value": 0, "analysis": "ac", "expect": "With the nulling resistor removed, expect lower phase margin because the Miller capacitor leaves a right-half-plane zero. Compare the Bode plot with the default 3 kΩ case." }, "limits": "Supply a suitable bias current and respect the input common-mode range, output swing and specified load. Qualification applies to the default design and declared conditions, not every editable setting." }, "path": [ { "part": "Input pair", "devices": "M1, M2", "does": "Splits the tail current by the input difference. A rise on inp pulls n2 down through M2; the second stage inverts it back, so the output follows inp." }, { "part": "Mirror load", "devices": "M3, M4", "does": "M3 turns M1's current into the gate voltage n1; M4 copies it onto n2, where both halves of the signal current add." }, { "part": "Second stage", "devices": "M5, M6", "does": "M5, a common-source PMOS driven from n2, amplifies and inverts against the mirrored sink M6, which sets its current." }, { "part": "Compensation", "devices": "Cc, Rz", "does": "Cc from the output back to n2 is multiplied by the second stage's gain, making n2 the dominant pole; Rz sets where Cc's feed-forward zero lands." } ], "bias": "I_bias, 20 µA by default, is supplied externally into the bn port and sets its voltage through the diode-connected Mb; Mt copies it as the tail, and M6, N6 copies of Mb, sinks N6·I_bias. M5, N5 copies of a load device carrying I_bias/2, sources N5·I_bias/2, so the stages agree only when N5 = 2·N6, as the defaults 8 and 4 do.", "relations": [ { "what": "DC gain", "expr": "A_0 ≈ g_m1 (r_o2 ∥ r_o4) · g_m5 (r_o5 ∥ r_o6)", "note": "In each stage the NMOS r_o is the smaller one and sets the gain." }, { "what": "Unity-gain frequency", "expr": "GBW ≈ g_m1/(2π·C_c)", "note": "Set by the input pair and C_c, 1.5 pF by default; C_L barely enters while ω_p2 stays above it." }, { "what": "Output pole", "expr": "ω_p2 ≈ g_m5/C_L", "note": "About 2.2 times the unity-gain frequency gives 60° of margin if any right-half-plane zero is ten times out." }, { "what": "Miller zero", "expr": "ω_z = 1/[C_c (1/g_m5 − R_z)]", "note": "A right-half-plane zero while R_z < 1/g_m5; the default 3 kΩ exceeds that and puts it in the left half plane, near 50 MHz, where it gives phase back at the crossover. The published minimum 60° phase margin is checked numerically at each qualification condition." }, { "what": "Current balance", "expr": "N5·I_bias/2 = N6·I_bias ⇒ N5 = 2·N6", "note": "Break it and n2 moves until M5 carries what M6 sinks: offset closed-loop, a railed output open." } ], "tradeoffs": [ "Raising C_c lowers the unity-gain frequency and the slew rate, I_bias/C_c, and buys phase margin by pulling the crossover further below g_m5/C_L.", "Setting R_z to 0 leaves the right-half-plane zero g_m5/C_c, which subtracts phase where the gain crosses 0 dB; a few kΩ turns it into lead.", "Raising N5 and N6 together, keeping N5 = 2·N6, raises g_m5 and pushes the output pole out, for more margin at more supply current.", "Raising I_bias raises g_m1, the bandwidth and the slew rate, but shortens every r_o: DC gain falls as supply current rises." ] }, "sizing": [ { "key": "W", "label": "W input pair", "unit": "m", "value": 0.00002, "min": 1.5e-7, "max": 0.0002, "kind": "si" }, { "key": "L", "label": "L input pair", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.00001, "kind": "si" }, { "key": "Wp", "label": "W load", "unit": "m", "value": 0.00002, "min": 1.5e-7, "max": 0.0002, "kind": "si" }, { "key": "Lp", "label": "L load", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.00001, "kind": "si" }, { "key": "Wb", "label": "W tail", "unit": "m", "value": 0.00001, "min": 1.5e-7, "max": 0.0002, "kind": "si" }, { "key": "Lb", "label": "L tail", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.00001, "kind": "si" }, { "key": "N5", "label": "M5 = N5 × load device", "unit": "", "value": 8, "min": 1, "max": 32, "kind": "int" }, { "key": "N6", "label": "M6 = N6 × bias device", "unit": "", "value": 4, "min": 1, "max": 16, "kind": "int" }, { "key": "Ib", "label": "I_bias", "unit": "A", "value": 0.00002, "min": 0.000001, "max": 0.0005, "kind": "si" }, { "key": "Cc", "label": "C_c", "unit": "F", "value": 1.5e-12, "min": 1e-14, "max": 2e-11, "kind": "si" }, { "key": "Rz", "label": "R_z", "unit": "Ω", "value": 3000, "min": 0, "max": 100000, "kind": "si" }, { "key": "CL", "label": "C_L", "unit": "F", "value": 2e-12, "min": 1e-14, "max": 5e-11, "kind": "si" }, { "key": "VCM", "label": "V_CM", "unit": "V", "value": 0.6, "min": 0.3, "max": 1, "kind": "si" } ], "testbenches": [ { "id": "ac", "label": "Open-loop response", "note": "", "measures": [ "a0", "f3db", "funity", "pm" ], "metricKeys": [ "dc_gain_db", "ugf_hz", "pm_deg" ], "acceptance": [ "pm_deg" ], "acceptanceRules": [ { "key": "pm_deg", "unit": "deg", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Two-stage Miller-compensated OTA - open-loop gain and phase\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\nVdd vdd 0 1.2\n* tail current mirror\nIb vdd bn 20u\nXMb bn bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=1\nXMt tail bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=1\n* First stage. The output follows M2's gate - M2 pulls n2 down, and the\n* PMOS second stage inverts n2 - so M2 takes the non-inverting input and\n* M1, on the diode side, the inverting one the feedback closes on.\nXM1 n1 inn tail 0 sg13_lv_nmos w=20u l=1u ng=4 m=1\nXM2 n2 inp tail 0 sg13_lv_nmos w=20u l=1u ng=4 m=1\nXM3 n1 n1 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM4 n2 n1 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\n* Second stage: a common-source PMOS against a mirrored current sink.\n* Both are built from unit devices: M5 is N5 copies of the load device\n* M3/M4, M6 is N6 copies of the bias device Mb. Its gate on n2 and source\n* on vdd put M5 in mirror with M3/M4, so it carries N5 * I_D3, and M6\n* carries N6 * I_bias. One wider device instead of N copies does not give\n* N times the current: the threshold depends on width, and near weak\n* inversion a few mV of it is tens of percent of current. The two stages\n* then disagree, and the first stage's output drops until M2 is crushed.\nXM5 out n2 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=8\nXM6 out bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=4\n* Miller compensation\nXCc n2 nz cap_cmim w=22.307u l=22.307u m=2\nXRz nz out 0 rppd w=0.5u l=5.632u\nCl out 0 2p\n* Unity-gain feedback at DC, fully open across the sweep. A 1 TH coil is\n* a dead short at DC and an open at every frequency visited; the 1 TF cap\n* is the reverse. Without this the operating point of a 70 dB amplifier\n* lands on a rail and the plot is the gain of a switched-off circuit.\nLfb out inn 1t\nCfb inn 0 1t\nVin inp 0 dc 600m ac 1\n.ac dec 25 1 10g\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas ac a0_db FIND vdb(out) AT=1\n.meas ac funity WHEN vdb(out)=0 FALL=1\n.end" } ], "measurements": { "pm_deg": { "label": "Phase margin", "unit": "deg", "spec": { "min": 60, "max": null } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "6693dda96763b69f1212cee4e23ebf8ec9febdb51722c4a80513988b432ada6f" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ota-2stage.js", "sha256": "521b1f182b8b8971086494f95dfd1eeb1358a694ced843aa6a240f8dc841b301" }, "simulationFingerprints": { "ac": "b32062ee2d50eb830f5f3837db7132a51c9698c70fd86e09a789be2fde35723c" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "63a24d61d82484e50527bfe303e645e49de5b0bed2019397532757613786c96f", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ota-2stage", "parameters": { "W": 0.00002, "L": 0.000001, "Wp": 0.00002, "Lp": 0.000001, "Wb": 0.00001, "Lb": 0.000002, "N5": 8, "N6": 4, "Ib": 0.00002, "Cc": 1.5e-12, "Rz": 3000, "CL": 2e-12, "VCM": 0.6 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ota-2stage/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [], "scopes": [ { "id": "dut", "name": "top", "ports": [ { "name": "bn", "net": "bn", "kind": "bias" }, { "name": "gnd", "net": "0", "kind": "ground" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "inp", "net": "inp", "kind": "input" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "out", "net": "out", "kind": "output" } ], "definitions": [], "devices": [ { "id": "XMb", "displayName": "Mb", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMb bn bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "bn" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMt", "displayName": "Mt", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMt tail bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM1 n1 inn tail 0 sg13_lv_nmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM2 n2 inp tail 0 sg13_lv_nmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM3 n1 n1 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n1" }, { "id": "g", "net": "n1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM4 n2 n1 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n2" }, { "id": "g", "net": "n1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=8", "source": "XM5 out n2 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=8", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "n2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM6 out bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=22.307u l=22.307u m=2", "source": "XCc n2 nz cap_cmim w=22.307u l=22.307u m=2", "pins": [ { "id": "p", "net": "n2" }, { "id": "n", "net": "nz" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=5.632u", "source": "XRz nz out 0 rppd w=0.5u l=5.632u", "pins": [ { "id": "p", "net": "nz" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "bn", "ground": false, "terminals": [ { "device": "XMb", "pin": "d" }, { "device": "XMb", "pin": "g" }, { "device": "XMt", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [ "bn" ], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "XMb", "pin": "s" }, { "device": "XMb", "pin": "b" }, { "device": "XMt", "pin": "s" }, { "device": "XMt", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "gnd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMt", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "n1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "n2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XRz", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "nz", "ground": false, "terminals": [ { "device": "XCc", "pin": "n" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "1.2", "source": "Vdd vdd 0 1.2", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "20u", "source": "Ib vdd bn 20u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "bn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "XMb", "displayName": "Mb", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMb bn bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "bn" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMt", "displayName": "Mt", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMt tail bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM1 n1 inn tail 0 sg13_lv_nmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM2 n2 inp tail 0 sg13_lv_nmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM3 n1 n1 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n1" }, { "id": "g", "net": "n1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM4 n2 n1 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n2" }, { "id": "g", "net": "n1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=8", "source": "XM5 out n2 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=8", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "n2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XM6 out bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=22.307u l=22.307u m=2", "source": "XCc n2 nz cap_cmim w=22.307u l=22.307u m=2", "pins": [ { "id": "p", "net": "n2" }, { "id": "n", "net": "nz" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=5.632u", "source": "XRz nz out 0 rppd w=0.5u l=5.632u", "pins": [ { "id": "p", "net": "nz" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cl out 0 2p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfb", "displayName": "Lfb", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfb out inn 1t", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cfb", "displayName": "Cfb", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cfb inn 0 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m ac 1", "source": "Vin inp 0 dc 600m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "XMb", "pin": "s" }, { "device": "XMb", "pin": "b" }, { "device": "XMt", "pin": "s" }, { "device": "XMt", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XRz", "pin": "substrate" }, { "device": "Cl", "pin": "n" }, { "device": "Cfb", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "bn", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "XMb", "pin": "d" }, { "device": "XMb", "pin": "g" }, { "device": "XMt", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMt", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "n1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "Lfb", "pin": "n" }, { "device": "Cfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "n2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XRz", "pin": "n" }, { "device": "Cl", "pin": "p" }, { "device": "Lfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "nz", "ground": false, "terminals": [ { "device": "XCc", "pin": "n" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "top-level-device-set", "scope": "top", "devices": [ "XMb", "XMt", "XM1", "XM2", "XM3", "XM4", "XM5", "XM6", "XCc", "XRz" ] } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Bias mirror", "devices": [ { "scope": "dut", "device": "XMb" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "Tail current source", "devices": [ { "scope": "dut", "device": "XMt" } ], "inferredStages": [ 1 ] }, { "id": "block-3", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 1 ] }, { "id": "block-4", "label": "Load mirror", "devices": [ { "scope": "dut", "device": "XM3" }, { "scope": "dut", "device": "XM4" } ], "inferredStages": [ 1 ] }, { "id": "block-5", "label": "Second stage", "devices": [ { "scope": "dut", "device": "XM5" } ], "inferredStages": [ 2 ] }, { "id": "block-6", "label": "Second stage current sink; N6 copies of the bias device", "devices": [ { "scope": "dut", "device": "XM6" } ], "inferredStages": [ 2 ] }, { "id": "block-7", "label": "Miller compensation", "devices": [ { "scope": "dut", "device": "XCc" } ], "inferredStages": [ "comp" ] }, { "id": "block-8", "label": "Nulling resistor", "devices": [ { "scope": "dut", "device": "XRz" } ], "inferredStages": [ "comp" ] } ], "edges": [ { "id": "net-1", "net": "bn", "nodes": [ "block-1", "block-2", "block-6" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "tail", "nodes": [ "block-2", "block-3" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "n1", "nodes": [ "block-3", "block-4" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "n2", "nodes": [ "block-3", "block-4", "block-5", "block-7" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "out", "nodes": [ "block-5", "block-6", "block-8" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "nz", "nodes": [ "block-7", "block-8" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "bn", "net": "bn", "kind": "bias" }, { "name": "gnd", "net": "0", "kind": "ground" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "inp", "net": "inp", "kind": "input" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "out", "net": "out", "kind": "output" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." } ], "views": [ { "bench": "ac", "source": { "recordField": "testbenches", "id": "ac", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota-2stage/ac-schematic.svg", "asset": "ac-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Two-stage Miller OTA", "instances": [] } ] }, "benchDiagram": { "graph": "graph-2", "svg": { "url": "/circuits/ota-2stage/ac-bench.svg", "asset": "ac-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota-2stage/ac-block.svg", "asset": "ac-block.svg" } } } ] } }