{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ota-5t-pmos", "name": "Five-transistor OTA, PMOS input", "group": "Op amps and OTAs", "subgroup": "Single-stage OTAs", "title": "Five-transistor OTA, PMOS input", "summary": "This small amplifier uses a PMOS input pair to handle signals near ground. A current mirror combines the two branch currents into one output. Its simplicity saves current, but limits gain and output swing; the load capacitor sets much of its speed.", "reference": { "kind": "book", "authors": "H. Pretl, M. Koefinger, S. Dorrer", "title": "Analog Circuit Design", "year": 2024, "where": "Open course material for the IHP SG13G2 130 nm PDK (https://github.com/iic-jku/analog-circuit-design)", "publisher": "Institute for Integrated Circuits, Johannes Kepler University Linz / Zenodo", "doi": "10.5281/zenodo.14387481", "takes": "The topology - a differential pair, a current-mirror load and a tail source - and the g_m/I_D sizing method the course teaches in SG13G2. The PMOS input, chosen for an input range that reaches ground, and the sizing are this library's." }, "resources": { "record": "/circuits/ota-5t-pmos.json", "page": "/index.html#ota-5t-pmos", "achieved": "/achieved/ota-5t-pmos.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice" ], "ports": [ { "name": "inp", "kind": "input" }, { "name": "inn", "kind": "input" }, { "name": "out", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the reference current, drawn out of this pin" } ], "devices": [ { "name": "MB", "type": "pmos", "nodes": "ib ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "bias reference, diode-connected", "fingers": 6, "copies": 1 }, { "name": "MT", "type": "pmos", "nodes": "tail ib vdd vdd", "sizedBy": [ "Wp", "Lp", "K" ], "role": "tail current source, K copies of MB", "fingers": 6, "copies": 2 }, { "name": "M1", "type": "pmos", "nodes": "d1 inp tail vdd", "sizedBy": [ "W1", "L1" ], "role": "input pair, non-inverting input, on the mirror's diode side", "fingers": 8, "copies": 1 }, { "name": "M2", "type": "pmos", "nodes": "out inn tail vdd", "sizedBy": [ "W1", "L1" ], "role": "input pair, inverting input", "fingers": 8, "copies": 1 }, { "name": "M3", "type": "nmos", "nodes": "d1 d1 vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "mirror load, diode-connected", "fingers": 2, "copies": 1 }, { "name": "M4", "type": "nmos", "nodes": "out d1 vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "mirror load, drives the output", "fingers": 2, "copies": 1 } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "The input pair: any difference between them is input offset. 36 µm × 1 µm each keeps the threshold spread small, and the width puts the pair near weak inversion, where g_m per µA is highest." }, { "rule": "match", "of": [ "M3", "M4" ], "why": "The mirror load: a mismatch copies the wrong current onto out and appears as offset." }, { "rule": "unit-copies", "of": [ "MB", "MT" ], "constraint": "MT = K copies of MB", "why": "The tail is a ratio of the reference, made by repeating MB, never by drawing a wider device: copies share its threshold, a wider device does not." }, { "rule": "input-range", "of": [ "M1", "M2", "M3" ], "constraint": "V_GS3 + V_DSAT1 ≤ V_SG1 with the input at ground", "why": "The pair's drains sit a mirror V_GS above ground and its sources a V_SG above the input, so the input reaches ground only if the mirror's V_GS is low and the pair's V_SG high: the mirror is wide enough to sit at 0.33 V, and the pair's n-well is on vdd, where body effect adds to its V_SG. Hot, the pair's threshold falls and the range stops about 0.07 V short of ground." }, { "rule": "balance", "of": [ "M3", "M4" ], "constraint": "V_CM ≈ V_GS3", "why": "With matched devices and the output at the diode's voltage, M3 and M4 have the same V_DS, suppressing systematic mirror error. Random mismatch still produces offset. The design common mode, 0.35 V, is chosen next to the mirror's 0.33 V for that." }, { "rule": "single-pole", "of": [ "out" ], "constraint": "C_L sets the unity-gain frequency, g_m1/(2π C_L)", "why": "When the loaded output pole dominates the mirror and other internal poles, phase margin can be large without a separate compensation capacitor. In that approximation, four times C_L gives roughly a quarter of the bandwidth with little DC-gain change; light loads or changed sizing can invalidate it." } ], "specs": [ { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.000035 A", "min": null, "max": 0.000035, "why": "The 10 µA reference and a 20 µA tail; the reference is held at every corner, so this barely moves." }, { "key": "dc_gain_db", "label": "DC open-loop gain", "unit": "dB", "direction": "max", "constraint": ">= 29 dB", "min": 29, "max": null, "why": "One stage: g_m1 (r_o2 ∥ r_o4), and the NMOS mirror's r_o, with g_m/g_ds near 33, is the short one. About 31 dB is what a five-transistor OTA makes in SG13G2; 29 dB holds at every corner." }, { "key": "ugf_hz", "label": "Unity-gain frequency", "unit": "Hz", "direction": "max", "constraint": ">= 18000000 Hz", "min": 18000000, "max": null, "why": "g_m1/(2π C_L) with 1 pF: 26 MHz at 27 °C, 21 MHz hot, where g_m/I_D of the weakly inverted pair falls." }, { "key": "pm_deg", "label": "Phase margin", "unit": "deg", "direction": "max", "constraint": ">= 70 deg", "min": 70, "max": null, "why": "The only other pole is the mirror's, g_m3 over the gates of M3 and M4, far above the crossover." }, { "key": "t_settle", "label": "Settling time, 1 %", "unit": "s", "direction": "min", "constraint": "<= 5e-8 s", "min": null, "max": 5e-8, "why": "A 0.2 V step barely slews and settles on the single pole, a 6 ns time constant: under 30 ns at every corner." }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 60 dB", "min": 60, "max": null, "why": "A ripple on V_DD moves the tail current, a common-mode signal the mirror rejects." }, { "key": "cmrr_db", "label": "Common-mode rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 55 dB", "min": 55, "max": null, "why": "Set by the tail's output resistance and the pair's match: 65 dB or more at every corner, and about 58 dB in the worst of 200 mismatch draws." }, { "key": "icmr_lo", "label": "Lowest input common mode", "unit": "V", "direction": "min", "constraint": "<= 0.1 V", "min": null, "max": 0.1, "why": "The reason for a PMOS pair: the input works down to ground at 27 °C and within 0.07 V of it hot." }, { "key": "icmr_hi", "label": "Highest input common mode", "unit": "V", "direction": "max", "constraint": ">= 0.5 V", "min": 0.5, "max": null, "why": "The tail needs V_SG1 + V_DSAT,T below the supply; 0.5 V holds with the supply 10 % low." }, { "key": "swing_lo", "label": "Lowest output", "unit": "V", "direction": "min", "constraint": "<= 0.25 V", "min": null, "max": 0.25, "why": "M4 leaves saturation at its V_DSAT, about 0.16 V." }, { "key": "swing_hi", "label": "Highest output", "unit": "V", "direction": "max", "constraint": ">= 0.55 V", "min": 0.55, "max": null, "why": "M2 leaves saturation a V_DSAT below the tail node, about 0.68 V with the input at 0.35 V." } ], "explanation": { "idea": "This small amplifier uses a PMOS input pair to handle signals near ground. A current mirror combines the two branch currents into one output. Its simplicity saves current, but limits gain and output swing; the load capacitor sets much of its speed.", "detail": "The five-transistor OTA with its pair in PMOS. M1 and M2 split the tail current by the input difference; the NMOS mirror M3–M4 copies M1's share onto the output, where M2 delivers its own, so the two halves of the signal current add in the output resistance. The pair's drains sit only a mirror V_GS above ground while its sources sit a V_SG above the input, so the input can go down to ground - the range an NMOS pair gives up. The output is the only high-impedance node, and the load capacitance is the whole compensation.", "lesson": { "relation": 1, "symbols": "f_u (also called GBW here) is unity-gain frequency in Hz; g_m1 is one input transistor's small-signal transconductance in S; C_L is load capacitance in F. Where angular frequency is used, ω_u = 2π f_u.", "assumptions": "Small signals, saturated devices and an output-dominated response. The simple relation neglects device capacitance and higher-frequency internal poles.", "exercise": { "param": "CL", "value": 2e-12, "analysis": "open_loop", "expect": "Doubling the load capacitance should reduce unity-gain frequency, roughly by half if the load dominates. Compare phase margin and DC gain rather than expecting every metric to halve." }, "limits": "Provide the bias current and keep input common mode and output swing inside their separate measured ranges. This is not a rail-to-rail input/output guarantee." }, "path": [ { "part": "Input pair", "devices": "M1, M2, MT", "does": "MT's tail current divides between M1 and M2 as inp and inn differ. inp drives M1, on the mirror's diode side: a rise there starves M1, so out follows inp." }, { "part": "Mirror load", "devices": "M3, M4", "does": "M3 turns M1's current into a gate voltage on d1, and M4 copies that current onto out." }, { "part": "Output node", "devices": "M2, M4", "does": "M2's current and M4's copy move in opposite directions, so the whole signal current flows into r_o2 ∥ r_o4 and into C_L." } ], "bias": "The testbench draws the 10 µA reference out of the diode MB; MT is K = 2 copies of it and feeds the pair with 20 µA, 10 µA a side, which puts the wide pair near weak inversion (g_m/I_D about 18). The mirror is sized to sit at 0.33 V, next to the 0.35 V design common mode: with the output there, M3 and M4 have the same V_DS and the output carries almost no systematic offset.", "relations": [ { "what": "DC gain", "expr": "A_0 ≈ g_m2 (r_o2 ∥ r_o4)", "note": "M4's r_o is the short one - an SG13G2 core NMOS reaches g_m/g_ds of about 33 at this length and drain voltage, the PMOS pair about 180 - so the gain is near 31 dB." }, { "what": "Unity-gain frequency", "expr": "f_u ≈ g_m1/(2π C_L)", "note": "About 0.18 mS into 1 pF and the output's own capacitance: 26 MHz." }, { "what": "Lowest input", "expr": "V_CM,min = V_GS3 + V_DSAT1 − V_SG1", "note": "M1 stays saturated while its drain, at the mirror's V_GS, is a V_DSAT below its source. 0.33 + 0.13 − 0.47 V is just below zero: the range reaches ground." }, { "what": "Highest input", "expr": "V_CM,max = V_DD − V_SG1 − V_DSAT,T", "note": "The tail source needs its own V_DSAT; above this its current, and with it g_m1 and the bandwidth, falls." }, { "what": "Output swing", "expr": "V_DSAT4 ≤ v_out ≤ V_tail − V_DSAT2", "note": "About 0.16 V to 0.68 V with the input at 0.35 V: as a buffer the output cannot follow the input all the way to ground." }, { "what": "Slew rate", "expr": "SR = I_tail/C_L", "note": "The large-signal limit, with the pair fully steered. The step bench's 0.2 V step is mostly linear settling on the 6 ns time constant and reads about half of it." } ], "tradeoffs": [ "A wider NMOS mirror lowers its V_GS and extends the input range towards ground, but lowers r_o4 per µA and the gain with it: at 3.6 µm, with the common mode at 0.4 V, the gain was 32.5 dB and the range stopped 0.14 V above ground hot.", "A longer NMOS mirror raises r_o4 and the gain, but loads d1 with gate capacitance: at 4 µm the mirror pole came down near the crossover and the phase margin fell below 70°.", "More tail current (K) raises g_m1, the bandwidth and the slew rate, and takes the pair out of weak inversion, raising V_SG1: the input range gains at the bottom and loses at the top.", "A wider input pair lowers the offset and adds g_m per µA, but lowers V_SG1, which the input range at ground depends on, and adds input capacitance." ] }, "sizing": [ { "key": "Ib", "label": "Reference current", "unit": "A", "value": 0.00001, "min": 0.000001, "max": 0.00005, "kind": "si" }, { "key": "K", "label": "Tail current, in Ib", "unit": "", "value": 2, "min": 1, "max": 8, "kind": "int" }, { "key": "W1", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.000036, "min": 0.000001, "max": 0.0001, "kind": "si" }, { "key": "L1", "label": "L input pair", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wn", "label": "W NMOS mirror (M3, M4)", "unit": "m", "value": 0.0000075, "min": 5e-7, "max": 0.00003, "kind": "si" }, { "key": "Ln", "label": "L NMOS mirror", "unit": "m", "value": 0.0000025, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Wp", "label": "W PMOS unit (MB, MT)", "unit": "m", "value": 0.000024, "min": 0.000001, "max": 0.00005, "kind": "si" }, { "key": "Lp", "label": "L PMOS unit", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "CL", "label": "Load capacitance", "unit": "F", "value": 1e-12, "min": 1e-13, "max": 2e-11, "kind": "si" }, { "key": "VCM", "label": "Input common mode", "unit": "V", "value": 0.35, "min": 0, "max": 0.6, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.", "measures": [], "metricKeys": [ "i_supply", "vout_dc", "vos" ], "acceptance": [ "i_supply" ], "acceptanceRules": [ { "key": "i_supply", "unit": "A", "min": null, "max": 0.000035, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Five-transistor OTA, PMOS input - operating point as a unity-gain buffer\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt ota5p inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, K copies of it as the tail\nXMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2\n* the PMOS pair, its n-well on vdd\nXM1 d1 inp tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1\nXM2 out inn tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1\n* the NMOS mirror load: M4 copies M1's current onto out, where M2 adds its own\nXM3 d1 d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1\nXM4 out d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1\n.ends\nXdut inp inn out vdd 0 ib ota5p\nCl out 0 1p\nVin inp 0 dc 350m\n* the output drives the inverting input: a unity-gain buffer\nVfb inn out 0\n.op\n.end" }, { "id": "open_loop", "label": "Open-loop gain", "note": "Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.", "measures": [], "metricKeys": [ "dc_gain_db", "ugf_hz", "pm_deg", "gm_db" ], "acceptance": [ "dc_gain_db", "ugf_hz", "pm_deg" ], "acceptanceRules": [ { "key": "dc_gain_db", "unit": "dB", "min": 29, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "ugf_hz", "unit": "Hz", "min": 18000000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "pm_deg", "unit": "deg", "min": 70, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Five-transistor OTA, PMOS input - open-loop gain and phase\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt ota5p inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, K copies of it as the tail\nXMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2\n* the PMOS pair, its n-well on vdd\nXM1 d1 inp tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1\nXM2 out inn tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1\n* the NMOS mirror load: M4 copies M1's current onto out, where M2 adds its own\nXM3 d1 d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1\nXM4 out d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1\n.ends\nXdut inp inn out vdd 0 ib ota5p\nCl out 0 1p\nVin inp 0 dc 350m ac 1\n* the loop closed at DC and open at every frequency the sweep visits\nLfb out inn 1t\nCfb inn 0 1t\n.ac dec 25 0.1 10g\n.end" }, { "id": "step", "label": "Step response", "note": "A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.", "measures": [], "metricKeys": [ "sr", "t_settle", "overshoot_pct" ], "acceptance": [ "t_settle" ], "acceptanceRules": [ { "key": "t_settle", "unit": "s", "min": null, "max": 5e-8, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Five-transistor OTA, PMOS input - step response of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt ota5p inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, K copies of it as the tail\nXMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2\n* the PMOS pair, its n-well on vdd\nXM1 d1 inp tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1\nXM2 out inn tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1\n* the NMOS mirror load: M4 copies M1's current onto out, where M2 adds its own\nXM3 d1 d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1\nXM4 out d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1\n.ends\nXdut inp inn out vdd 0 ib ota5p\nCl out 0 1p\nVin inp 0 pulse(250m 450m 50n 1n 1n 250n 1u)\nVfb inn out 0\n.tran 125p 500n\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.", "measures": [], "metricKeys": [ "psrr_db" ], "acceptance": [ "psrr_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Five-transistor OTA, PMOS input - supply rejection of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD} ac 1\nIb ib 0 10u\n.subckt ota5p inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, K copies of it as the tail\nXMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2\n* the PMOS pair, its n-well on vdd\nXM1 d1 inp tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1\nXM2 out inn tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1\n* the NMOS mirror load: M4 copies M1's current onto out, where M2 adds its own\nXM3 d1 d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1\nXM4 out d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1\n.ends\nXdut inp inn out vdd 0 ib ota5p\nCl out 0 1p\nVin inp 0 dc 350m\nVfb inn out 0\n.ac dec 25 1 100meg\n.end" }, { "id": "cmrr", "label": "Common-mode rejection", "note": "Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.", "measures": [], "metricKeys": [ "cmrr_db" ], "acceptance": [ "cmrr_db" ], "acceptanceRules": [ { "key": "cmrr_db", "unit": "dB", "min": 55, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Five-transistor OTA, PMOS input - common-mode rejection\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt ota5p inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, K copies of it as the tail\nXMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2\n* the PMOS pair, its n-well on vdd\nXM1 d1 inp tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1\nXM2 out inn tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1\n* the NMOS mirror load: M4 copies M1's current onto out, where M2 adds its own\nXM3 d1 d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1\nXM4 out d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1\n.ends\nXdut inp inn out vdd 0 ib ota5p\nCl out 0 1p\nVsrc src 0 dc 350m\n* va on the non-inverting input, vb in the feedback path: both inputs move with the signal\nVa inp src dc 0 ac 1\nVb inn out dc 0 ac 1\n.ac dec 25 1 100meg\n.end" }, { "id": "noise", "label": "Noise", "note": "Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.", "measures": [], "metricKeys": [ "vn_1k", "vn_int" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Five-transistor OTA, PMOS input - input-referred noise\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt ota5p inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, K copies of it as the tail\nXMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2\n* the PMOS pair, its n-well on vdd\nXM1 d1 inp tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1\nXM2 out inn tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1\n* the NMOS mirror load: M4 copies M1's current onto out, where M2 adds its own\nXM3 d1 d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1\nXM4 out d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1\n.ends\nXdut inp inn out vdd 0 ib ota5p\nCl out 0 1p\nVin inp 0 dc 350m ac 1\nVfb inn out 0\n.control\nnoise v(out) Vin dec 20 1 1meg\nsetplot noise1\n* 20 points a decade from 1 Hz: point 60 is 1 kHz\nlet vn_1k = inoise_spectrum[60]\nprint vn_1k\nsetplot noise2\nprint inoise_total\n.endc\n.op\n.end" }, { "id": "icmr", "label": "Input common-mode range", "note": "Both inputs swept together while the output is held at one level. The range is where open-loop gain falls by no more than 6 dB and unity-gain frequency by no more than 5 % from their values at the design common mode; increases are allowed.", "measures": [], "metricKeys": [ "icmr_lo", "icmr_hi" ], "acceptance": [ "icmr_lo", "icmr_hi" ], "acceptanceRules": [ { "key": "icmr_lo", "unit": "V", "min": null, "max": 0.1, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "icmr_hi", "unit": "V", "min": 0.5, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Five-transistor OTA, PMOS input - input common-mode range, the output held at one level\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt ota5p inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, K copies of it as the tail\nXMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2\n* the PMOS pair, its n-well on vdd\nXM1 d1 inp tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1\nXM2 out inn tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1\n* the NMOS mirror load: M4 copies M1's current onto out, where M2 adds its own\nXM3 d1 d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1\nXM4 out d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1\n.ends\nXdut inp inn out vdd 0 ib ota5p\nCl out 0 1p\nVin inp 0 dc 350m ac 1\nVpark park 0 dc 350m\n* inn is inp shifted by how far out is from park: the loop holds out at park\n* while both inputs follow inp, and it is closed at DC only, as in the\n* open-loop bench, so each ac sweep sees the open loop\nEfb fb inp out park 1\nLfb fb inn 1t\nCfb inn 0 1t\n.control\n* point 0 is the design common mode, the reference; then every level\nac dec 20 0.1 10g\nmeas ac a0_0 find vdb(out) at=0.1\nmeas ac fu_0 when vdb(out)=0 fall=1\nalter vin dc = 0\nac dec 20 0.1 10g\nmeas ac a0_1 find vdb(out) at=0.1\nmeas ac fu_1 when vdb(out)=0 fall=1\nalter vin dc = 30m\nac dec 20 0.1 10g\nmeas ac a0_2 find vdb(out) at=0.1\nmeas ac fu_2 when vdb(out)=0 fall=1\nalter vin dc = 60m\nac dec 20 0.1 10g\nmeas ac a0_3 find vdb(out) at=0.1\nmeas ac fu_3 when vdb(out)=0 fall=1\nalter vin dc = 90m\nac dec 20 0.1 10g\nmeas ac a0_4 find vdb(out) at=0.1\nmeas ac fu_4 when vdb(out)=0 fall=1\nalter vin dc = 120m\nac dec 20 0.1 10g\nmeas ac a0_5 find vdb(out) at=0.1\nmeas ac fu_5 when vdb(out)=0 fall=1\nalter vin dc = 150m\nac dec 20 0.1 10g\nmeas ac a0_6 find vdb(out) at=0.1\nmeas ac fu_6 when vdb(out)=0 fall=1\nalter vin dc = 180m\nac dec 20 0.1 10g\nmeas ac a0_7 find vdb(out) at=0.1\nmeas ac fu_7 when vdb(out)=0 fall=1\nalter vin dc = 210m\nac dec 20 0.1 10g\nmeas ac a0_8 find vdb(out) at=0.1\nmeas ac fu_8 when vdb(out)=0 fall=1\nalter vin dc = 240m\nac dec 20 0.1 10g\nmeas ac a0_9 find vdb(out) at=0.1\nmeas ac fu_9 when vdb(out)=0 fall=1\nalter vin dc = 270m\nac dec 20 0.1 10g\nmeas ac a0_10 find vdb(out) at=0.1\nmeas ac fu_10 when vdb(out)=0 fall=1\nalter vin dc = 300m\nac dec 20 0.1 10g\nmeas ac a0_11 find vdb(out) at=0.1\nmeas ac fu_11 when vdb(out)=0 fall=1\nalter vin dc = 330m\nac dec 20 0.1 10g\nmeas ac a0_12 find vdb(out) at=0.1\nmeas ac fu_12 when vdb(out)=0 fall=1\nalter vin dc = 360m\nac dec 20 0.1 10g\nmeas ac a0_13 find vdb(out) at=0.1\nmeas ac fu_13 when vdb(out)=0 fall=1\nalter vin dc = 390m\nac dec 20 0.1 10g\nmeas ac a0_14 find vdb(out) at=0.1\nmeas ac fu_14 when vdb(out)=0 fall=1\nalter vin dc = 420m\nac dec 20 0.1 10g\nmeas ac a0_15 find vdb(out) at=0.1\nmeas ac fu_15 when vdb(out)=0 fall=1\nalter vin dc = 450m\nac dec 20 0.1 10g\nmeas ac a0_16 find vdb(out) at=0.1\nmeas ac fu_16 when vdb(out)=0 fall=1\nalter vin dc = 480m\nac dec 20 0.1 10g\nmeas ac a0_17 find vdb(out) at=0.1\nmeas ac fu_17 when vdb(out)=0 fall=1\nalter vin dc = 510m\nac dec 20 0.1 10g\nmeas ac a0_18 find vdb(out) at=0.1\nmeas ac fu_18 when vdb(out)=0 fall=1\nalter vin dc = 540m\nac dec 20 0.1 10g\nmeas ac a0_19 find vdb(out) at=0.1\nmeas ac fu_19 when vdb(out)=0 fall=1\nalter vin dc = 570m\nac dec 20 0.1 10g\nmeas ac a0_20 find vdb(out) at=0.1\nmeas ac fu_20 when vdb(out)=0 fall=1\nalter vin dc = 600m\nac dec 20 0.1 10g\nmeas ac a0_21 find vdb(out) at=0.1\nmeas ac fu_21 when vdb(out)=0 fall=1\nalter vin dc = 630m\nac dec 20 0.1 10g\nmeas ac a0_22 find vdb(out) at=0.1\nmeas ac fu_22 when vdb(out)=0 fall=1\nalter vin dc = 660m\nac dec 20 0.1 10g\nmeas ac a0_23 find vdb(out) at=0.1\nmeas ac fu_23 when vdb(out)=0 fall=1\nalter vin dc = 690m\nac dec 20 0.1 10g\nmeas ac a0_24 find vdb(out) at=0.1\nmeas ac fu_24 when vdb(out)=0 fall=1\nalter vin dc = 720m\nac dec 20 0.1 10g\nmeas ac a0_25 find vdb(out) at=0.1\nmeas ac fu_25 when vdb(out)=0 fall=1\nalter vin dc = 750m\nac dec 20 0.1 10g\nmeas ac a0_26 find vdb(out) at=0.1\nmeas ac fu_26 when vdb(out)=0 fall=1\nalter vin dc = 780m\nac dec 20 0.1 10g\nmeas ac a0_27 find vdb(out) at=0.1\nmeas ac fu_27 when vdb(out)=0 fall=1\nalter vin dc = 810m\nac dec 20 0.1 10g\nmeas ac a0_28 find vdb(out) at=0.1\nmeas ac fu_28 when vdb(out)=0 fall=1\nalter vin dc = 840m\nac dec 20 0.1 10g\nmeas ac a0_29 find vdb(out) at=0.1\nmeas ac fu_29 when vdb(out)=0 fall=1\nalter vin dc = 870m\nac dec 20 0.1 10g\nmeas ac a0_30 find vdb(out) at=0.1\nmeas ac fu_30 when vdb(out)=0 fall=1\nalter vin dc = 900m\nac dec 20 0.1 10g\nmeas ac a0_31 find vdb(out) at=0.1\nmeas ac fu_31 when vdb(out)=0 fall=1\nalter vin dc = 930m\nac dec 20 0.1 10g\nmeas ac a0_32 find vdb(out) at=0.1\nmeas ac fu_32 when vdb(out)=0 fall=1\nalter vin dc = 960m\nac dec 20 0.1 10g\nmeas ac a0_33 find vdb(out) at=0.1\nmeas ac fu_33 when vdb(out)=0 fall=1\nalter vin dc = 990m\nac dec 20 0.1 10g\nmeas ac a0_34 find vdb(out) at=0.1\nmeas ac fu_34 when vdb(out)=0 fall=1\nalter vin dc = 1.02\nac dec 20 0.1 10g\nmeas ac a0_35 find vdb(out) at=0.1\nmeas ac fu_35 when vdb(out)=0 fall=1\nalter vin dc = 1.05\nac dec 20 0.1 10g\nmeas ac a0_36 find vdb(out) at=0.1\nmeas ac fu_36 when vdb(out)=0 fall=1\nalter vin dc = 1.08\nac dec 20 0.1 10g\nmeas ac a0_37 find vdb(out) at=0.1\nmeas ac fu_37 when vdb(out)=0 fall=1\nalter vin dc = 1.11\nac dec 20 0.1 10g\nmeas ac a0_38 find vdb(out) at=0.1\nmeas ac fu_38 when vdb(out)=0 fall=1\nalter vin dc = 1.14\nac dec 20 0.1 10g\nmeas ac a0_39 find vdb(out) at=0.1\nmeas ac fu_39 when vdb(out)=0 fall=1\nalter vin dc = 1.17\nac dec 20 0.1 10g\nmeas ac a0_40 find vdb(out) at=0.1\nmeas ac fu_40 when vdb(out)=0 fall=1\nalter vin dc = 1.2\nac dec 20 0.1 10g\nmeas ac a0_41 find vdb(out) at=0.1\nmeas ac fu_41 when vdb(out)=0 fall=1\nalter vin dc = 1.23\nac dec 20 0.1 10g\nmeas ac a0_42 find vdb(out) at=0.1\nmeas ac fu_42 when vdb(out)=0 fall=1\nalter vin dc = 1.26\nac dec 20 0.1 10g\nmeas ac a0_43 find vdb(out) at=0.1\nmeas ac fu_43 when vdb(out)=0 fall=1\nalter vin dc = 1.29\nac dec 20 0.1 10g\nmeas ac a0_44 find vdb(out) at=0.1\nmeas ac fu_44 when vdb(out)=0 fall=1\nalter vin dc = 1.32\nac dec 20 0.1 10g\nmeas ac a0_45 find vdb(out) at=0.1\nmeas ac fu_45 when vdb(out)=0 fall=1\n.endc\n.dc Vin 0 1.32 30m\n.end" }, { "id": "swing", "label": "Output swing", "note": "The amplifier as an inverting gain of one - its inverting input at the midpoint of the output and a signal, through two ideal controlled sources that load nothing - with the signal swept so the output crosses from rail to rail, and at each level the open-loop gain: the swing is where the gain stays within 6 dB of its value with the output at the input common mode.", "measures": [], "metricKeys": [ "swing_lo", "swing_hi" ], "acceptance": [ "swing_lo", "swing_hi" ], "acceptanceRules": [ { "key": "swing_lo", "unit": "V", "min": null, "max": 0.25, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "swing_hi", "unit": "V", "min": 0.55, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Five-transistor OTA, PMOS input - output swing, as an inverting amplifier of gain one\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt ota5p inp inn out vdd vss ib\n* bias: the reference current into a PMOS diode, K copies of it as the tail\nXMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2\n* the PMOS pair, its n-well on vdd\nXM1 d1 inp tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1\nXM2 out inn tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1\n* the NMOS mirror load: M4 copies M1's current onto out, where M2 adds its own\nXM3 d1 d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1\nXM4 out d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1\n.ends\nXdut inp inn out vdd 0 ib ota5p\nCl out 0 1p\nVcm inp 0 dc 350m ac 1\nVsig sig 0 dc 350m\n* inn is the midpoint of out and sig: v(out) = 2 V_CM - v(sig). Closed at DC\n* only, so each ac sweep reads the open-loop gain at that output level\nE1 fbn mid out 0 0.5\nE2 mid 0 sig 0 0.5\nLfb fbn inn 1t\nCfb inn 0 1t\n.control\n* point 0 has the output at the input common mode, the reference\nac dec 1 0.1 1\nmeas ac a0_0 find vdb(out) at=0.1\nalter vsig dc = 700m\nac dec 1 0.1 1\nmeas ac a0_1 find vdb(out) at=0.1\nalter vsig dc = 670m\nac dec 1 0.1 1\nmeas ac a0_2 find vdb(out) at=0.1\nalter vsig dc = 640m\nac dec 1 0.1 1\nmeas ac a0_3 find vdb(out) at=0.1\nalter vsig dc = 610m\nac dec 1 0.1 1\nmeas ac a0_4 find vdb(out) at=0.1\nalter vsig dc = 580m\nac dec 1 0.1 1\nmeas ac a0_5 find vdb(out) at=0.1\nalter vsig dc = 550m\nac dec 1 0.1 1\nmeas ac a0_6 find vdb(out) at=0.1\nalter vsig dc = 520m\nac dec 1 0.1 1\nmeas ac a0_7 find vdb(out) at=0.1\nalter vsig dc = 490m\nac dec 1 0.1 1\nmeas ac a0_8 find vdb(out) at=0.1\nalter vsig dc = 460m\nac dec 1 0.1 1\nmeas ac a0_9 find vdb(out) at=0.1\nalter vsig dc = 430m\nac dec 1 0.1 1\nmeas ac a0_10 find vdb(out) at=0.1\nalter vsig dc = 400m\nac dec 1 0.1 1\nmeas ac a0_11 find vdb(out) at=0.1\nalter vsig dc = 370m\nac dec 1 0.1 1\nmeas ac a0_12 find vdb(out) at=0.1\nalter vsig dc = 340m\nac dec 1 0.1 1\nmeas ac a0_13 find vdb(out) at=0.1\nalter vsig dc = 310m\nac dec 1 0.1 1\nmeas ac a0_14 find vdb(out) at=0.1\nalter vsig dc = 280m\nac dec 1 0.1 1\nmeas ac a0_15 find vdb(out) at=0.1\nalter vsig dc = 250m\nac dec 1 0.1 1\nmeas ac a0_16 find vdb(out) at=0.1\nalter vsig dc = 220m\nac dec 1 0.1 1\nmeas ac a0_17 find vdb(out) at=0.1\nalter vsig dc = 190m\nac dec 1 0.1 1\nmeas ac a0_18 find vdb(out) at=0.1\nalter vsig dc = 160m\nac dec 1 0.1 1\nmeas ac a0_19 find vdb(out) at=0.1\nalter vsig dc = 130m\nac dec 1 0.1 1\nmeas ac a0_20 find vdb(out) at=0.1\nalter vsig dc = 100m\nac dec 1 0.1 1\nmeas ac a0_21 find vdb(out) at=0.1\nalter vsig dc = 70m\nac dec 1 0.1 1\nmeas ac a0_22 find vdb(out) at=0.1\nalter vsig dc = 40m\nac dec 1 0.1 1\nmeas ac a0_23 find vdb(out) at=0.1\nalter vsig dc = 10m\nac dec 1 0.1 1\nmeas ac a0_24 find vdb(out) at=0.1\nalter vsig dc = -20m\nac dec 1 0.1 1\nmeas ac a0_25 find vdb(out) at=0.1\nalter vsig dc = -50m\nac dec 1 0.1 1\nmeas ac a0_26 find vdb(out) at=0.1\nalter vsig dc = -80m\nac dec 1 0.1 1\nmeas ac a0_27 find vdb(out) at=0.1\nalter vsig dc = -110m\nac dec 1 0.1 1\nmeas ac a0_28 find vdb(out) at=0.1\nalter vsig dc = -140m\nac dec 1 0.1 1\nmeas ac a0_29 find vdb(out) at=0.1\nalter vsig dc = -170m\nac dec 1 0.1 1\nmeas ac a0_30 find vdb(out) at=0.1\nalter vsig dc = -200m\nac dec 1 0.1 1\nmeas ac a0_31 find vdb(out) at=0.1\nalter vsig dc = -230m\nac dec 1 0.1 1\nmeas ac a0_32 find vdb(out) at=0.1\nalter vsig dc = -260m\nac dec 1 0.1 1\nmeas ac a0_33 find vdb(out) at=0.1\nalter vsig dc = -290m\nac dec 1 0.1 1\nmeas ac a0_34 find vdb(out) at=0.1\nalter vsig dc = -320m\nac dec 1 0.1 1\nmeas ac a0_35 find vdb(out) at=0.1\nalter vsig dc = -350m\nac dec 1 0.1 1\nmeas ac a0_36 find vdb(out) at=0.1\nalter vsig dc = -380m\nac dec 1 0.1 1\nmeas ac a0_37 find vdb(out) at=0.1\nalter vsig dc = -410m\nac dec 1 0.1 1\nmeas ac a0_38 find vdb(out) at=0.1\nalter vsig dc = -440m\nac dec 1 0.1 1\nmeas ac a0_39 find vdb(out) at=0.1\nalter vsig dc = -470m\nac dec 1 0.1 1\nmeas ac a0_40 find vdb(out) at=0.1\nalter vsig dc = -500m\nac dec 1 0.1 1\nmeas ac a0_41 find vdb(out) at=0.1\n.endc\n.dc Vsig -500m 700m 30m\n.end" } ], "measurements": { "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.000035 } }, "dc_gain_db": { "label": "DC open-loop gain", "unit": "dB", "spec": { "min": 29, "max": null } }, "ugf_hz": { "label": "Unity-gain frequency", "unit": "Hz", "spec": { "min": 18000000, "max": null } }, "pm_deg": { "label": "Phase margin", "unit": "deg", "spec": { "min": 70, "max": null } }, "t_settle": { "label": "Settling time, 1 %", "unit": "s", "spec": { "min": null, "max": 5e-8 } }, "psrr_db": { "label": "Supply rejection at 1 kHz", "unit": "dB", "spec": { "min": 60, "max": null } }, "cmrr_db": { "label": "Common-mode rejection at 1 kHz", "unit": "dB", "spec": { "min": 55, "max": null } }, "icmr_lo": { "label": "Lowest input common mode", "unit": "V", "spec": { "min": null, "max": 0.1 } }, "icmr_hi": { "label": "Highest input common mode", "unit": "V", "spec": { "min": 0.5, "max": null } }, "swing_lo": { "label": "Lowest output", "unit": "V", "spec": { "min": null, "max": 0.25 } }, "swing_hi": { "label": "Highest output", "unit": "V", "spec": { "min": 0.55, "max": null } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "7ab8c6841a3ea4a0ff78c7af50b21913173390708152039d0527b50d09e7c377" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ota-5t-pmos.js", "sha256": "863ba003ec96c52458dc6fd3a4e81e8d782ca790b81dd0a4e6116dfaad627296" }, "simulationFingerprints": { "op": "1e54b6d7faa954dc14f7864fac6d31b9bfceeb58a1a703c7f7e2c65f9eff50f4", "open_loop": "2d324168f1fa588e286752964c09cb1a1cb0df3b0542549f5cfdbf948af9cae2", "step": "2ce2026ef4e324aa3362c0b5e616157d10275aa0aa818bfc315b8dc611a0514f", "psrr": "bfa009fd1cc6fbb6588ab748a3cbac3c11080aebfa870a3cb1f6ffd4a077fecd", "cmrr": "e47dfe55004e9cb92087587d7800d4c8a61a1d37d596d77cc5fa0beff95b82d3", "noise": "f4f0c948fa0ad82a596f183f5d4a6c9839b36cf144e87228c94ad606c5ec6622", "icmr": "266c8ddad6d2c4843d515d906e51372f61e934d38d9e17fa0b9b26cb059f0232", "swing": "d69477772a347805f2ae288e64c1c787dad8dfdc15bbc2bedf2f4bb84931f276" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "755facc36447172eeb44b506970d206bdd6a1e8209bba1d2d22127af8b7c5869", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ota-5t-pmos", "parameters": { "Ib": 0.00001, "K": 2, "W1": 0.000036, "L1": 0.000001, "Wn": 0.0000075, "Ln": 0.0000025, "Wp": 0.000024, "Lp": 0.000002, "CL": 1e-12, "VCM": 0.35 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ota-5t-pmos/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "ota5p", "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=36u l=1u ng=8 m=1", "source": "XM1 d1 inp tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=36u l=1u ng=8 m=1", "source": "XM2 out inn tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=7.5u l=2.5u ng=2 m=1", "source": "XM3 d1 d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=7.5u l=2.5u ng=2 m=1", "source": "XM4 out d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota5p", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota5p", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota5p" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "1p", "source": "Cl out 0 1p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 350m", "source": "Vin inp 0 dc 350m", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota5p", "name": "ota5p", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=36u l=1u ng=8 m=1", "source": "XM1 d1 inp tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=36u l=1u ng=8 m=1", "source": "XM2 out inn tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=7.5u l=2.5u ng=2 m=1", "source": "XM3 d1 d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=7.5u l=2.5u ng=2 m=1", "source": "XM4 out d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota5p" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Bias reference", "devices": [ { "scope": "dut", "device": "XMB" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "Tail current source", "devices": [ { "scope": "dut", "device": "XMT" } ], "inferredStages": [ 1 ] }, { "id": "block-3", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 1 ] }, { "id": "block-4", "label": "Mirror load", "devices": [ { "scope": "dut", "device": "XM3" }, { "scope": "dut", "device": "XM4" } ], "inferredStages": [ 1 ] } ], "edges": [ { "id": "net-1", "net": "ib", "nodes": [ "block-1", "block-2" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "tail", "nodes": [ "block-2", "block-3" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "d1", "nodes": [ "block-3", "block-4" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "out", "nodes": [ "block-3", "block-4" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota5p", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota5p", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota5p" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "1p", "source": "Cl out 0 1p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 350m ac 1", "source": "Vin inp 0 dc 350m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfb", "displayName": "Lfb", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfb out inn 1t", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cfb", "displayName": "Cfb", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cfb inn 0 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" }, { "device": "Cfb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Lfb", "pin": "n" }, { "device": "Cfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Lfb", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota5p", "name": "ota5p", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=36u l=1u ng=8 m=1", "source": "XM1 d1 inp tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=36u l=1u ng=8 m=1", "source": "XM2 out inn tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=7.5u l=2.5u ng=2 m=1", "source": "XM3 d1 d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=7.5u l=2.5u ng=2 m=1", "source": "XM4 out d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota5p" } }, { "id": "graph-5", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota5p", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota5p", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota5p" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "1p", "source": "Cl out 0 1p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "pulse(250m 450m 50n 1n 1n 250n 1u)", "source": "Vin inp 0 pulse(250m 450m 50n 1n 1n 250n 1u)", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota5p", "name": "ota5p", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=36u l=1u ng=8 m=1", "source": "XM1 d1 inp tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=36u l=1u ng=8 m=1", "source": "XM2 out inn tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=7.5u l=2.5u ng=2 m=1", "source": "XM3 d1 d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=7.5u l=2.5u ng=2 m=1", "source": "XM4 out d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota5p" } }, { "id": "graph-6", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD} ac 1", "source": "Vdd vdd 0 dc {VDD} ac 1", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota5p", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota5p", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota5p" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "1p", "source": "Cl out 0 1p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 350m", "source": "Vin inp 0 dc 350m", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota5p", "name": "ota5p", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=36u l=1u ng=8 m=1", "source": "XM1 d1 inp tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=36u l=1u ng=8 m=1", "source": "XM2 out inn tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=7.5u l=2.5u ng=2 m=1", "source": "XM3 d1 d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=7.5u l=2.5u ng=2 m=1", "source": "XM4 out d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota5p" } }, { "id": "graph-7", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota5p", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota5p", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota5p" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "1p", "source": "Cl out 0 1p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vsrc", "displayName": "Vsrc", "spiceType": "V", "model": null, "parametersOrValue": "dc 350m", "source": "Vsrc src 0 dc 350m", "pins": [ { "id": "p", "net": "src" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Va", "displayName": "Va", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Va inp src dc 0 ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "src" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vb", "displayName": "Vb", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Vb inn out dc 0 ac 1", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vsrc", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Va", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "src", "ground": false, "terminals": [ { "device": "Vsrc", "pin": "p" }, { "device": "Va", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota5p", "name": "ota5p", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=36u l=1u ng=8 m=1", "source": "XM1 d1 inp tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=36u l=1u ng=8 m=1", "source": "XM2 out inn tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=7.5u l=2.5u ng=2 m=1", "source": "XM3 d1 d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=7.5u l=2.5u ng=2 m=1", "source": "XM4 out d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota5p" } }, { "id": "graph-8", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota5p", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota5p", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota5p" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "1p", "source": "Cl out 0 1p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 350m ac 1", "source": "Vin inp 0 dc 350m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota5p", "name": "ota5p", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=36u l=1u ng=8 m=1", "source": "XM1 d1 inp tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=36u l=1u ng=8 m=1", "source": "XM2 out inn tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=7.5u l=2.5u ng=2 m=1", "source": "XM3 d1 d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=7.5u l=2.5u ng=2 m=1", "source": "XM4 out d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota5p" } }, { "id": "graph-9", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota5p", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota5p", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota5p" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "1p", "source": "Cl out 0 1p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 350m ac 1", "source": "Vin inp 0 dc 350m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vpark", "displayName": "Vpark", "spiceType": "V", "model": null, "parametersOrValue": "dc 350m", "source": "Vpark park 0 dc 350m", "pins": [ { "id": "p", "net": "park" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efb", "displayName": "Efb", "spiceType": "E", "model": null, "parametersOrValue": "1", "source": "Efb fb inp out park 1", "pins": [ { "id": "p", "net": "fb" }, { "id": "n", "net": "inp" }, { "id": "cp", "net": "out" }, { "id": "cn", "net": "park" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfb", "displayName": "Lfb", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfb fb inn 1t", "pins": [ { "id": "p", "net": "fb" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cfb", "displayName": "Cfb", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cfb inn 0 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" }, { "device": "Vpark", "pin": "n" }, { "device": "Cfb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" }, { "device": "Efb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Lfb", "pin": "n" }, { "device": "Cfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Efb", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "park", "ground": false, "terminals": [ { "device": "Vpark", "pin": "p" }, { "device": "Efb", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "fb", "ground": false, "terminals": [ { "device": "Efb", "pin": "p" }, { "device": "Lfb", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota5p", "name": "ota5p", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=36u l=1u ng=8 m=1", "source": "XM1 d1 inp tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=36u l=1u ng=8 m=1", "source": "XM2 out inn tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=7.5u l=2.5u ng=2 m=1", "source": "XM3 d1 d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=7.5u l=2.5u ng=2 m=1", "source": "XM4 out d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota5p" } }, { "id": "graph-10", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota5p", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota5p", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota5p" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "1p", "source": "Cl out 0 1p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vcm", "displayName": "Vcm", "spiceType": "V", "model": null, "parametersOrValue": "dc 350m ac 1", "source": "Vcm inp 0 dc 350m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vsig", "displayName": "Vsig", "spiceType": "V", "model": null, "parametersOrValue": "dc 350m", "source": "Vsig sig 0 dc 350m", "pins": [ { "id": "p", "net": "sig" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "E1", "displayName": "E1", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "E1 fbn mid out 0 0.5", "pins": [ { "id": "p", "net": "fbn" }, { "id": "n", "net": "mid" }, { "id": "cp", "net": "out" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "E2", "displayName": "E2", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "E2 mid 0 sig 0 0.5", "pins": [ { "id": "p", "net": "mid" }, { "id": "n", "net": "0" }, { "id": "cp", "net": "sig" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfb", "displayName": "Lfb", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfb fbn inn 1t", "pins": [ { "id": "p", "net": "fbn" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cfb", "displayName": "Cfb", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cfb inn 0 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vcm", "pin": "n" }, { "device": "Vsig", "pin": "n" }, { "device": "E1", "pin": "cn" }, { "device": "E2", "pin": "n" }, { "device": "E2", "pin": "cn" }, { "device": "Cfb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vcm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Lfb", "pin": "n" }, { "device": "Cfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "E1", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "sig", "ground": false, "terminals": [ { "device": "Vsig", "pin": "p" }, { "device": "E2", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "fbn", "ground": false, "terminals": [ { "device": "E1", "pin": "p" }, { "device": "Lfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "mid", "ground": false, "terminals": [ { "device": "E1", "pin": "n" }, { "device": "E2", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota5p", "name": "ota5p", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=24u l=2u ng=6 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=24u l=2u ng=6 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=36u l=1u ng=8 m=1", "source": "XM1 d1 inp tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=36u l=1u ng=8 m=1", "source": "XM2 out inn tail vdd sg13_lv_pmos w=36u l=1u ng=8 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=7.5u l=2.5u ng=2 m=1", "source": "XM3 d1 d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=7.5u l=2.5u ng=2 m=1", "source": "XM4 out d1 vss vss sg13_lv_nmos w=7.5u l=2.5u ng=2 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "d1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota5p" } } ], "views": [ { "bench": "op", "source": { "recordField": "testbenches", "id": "op", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota-5t-pmos/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Five-transistor OTA, PMOS input", "instances": [] } ] }, "benchDiagram": { "graph": "graph-2", "svg": { "url": "/circuits/ota-5t-pmos/op-bench.svg", "asset": "op-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota-5t-pmos/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "open_loop", "source": { "recordField": "testbenches", "id": "open_loop", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota-5t-pmos/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Five-transistor OTA, PMOS input", "instances": [] } ] }, "benchDiagram": { "graph": "graph-4", "svg": { "url": "/circuits/ota-5t-pmos/open_loop-bench.svg", "asset": "open_loop-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota-5t-pmos/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "step", "source": { "recordField": "testbenches", "id": "step", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota-5t-pmos/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Five-transistor OTA, PMOS input", "instances": [] } ] }, "benchDiagram": { "graph": "graph-5", "svg": { "url": "/circuits/ota-5t-pmos/step-bench.svg", "asset": "step-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota-5t-pmos/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "psrr", "source": { "recordField": "testbenches", "id": "psrr", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota-5t-pmos/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Five-transistor OTA, PMOS input", "instances": [] } ] }, "benchDiagram": { "graph": "graph-6", "svg": { "url": "/circuits/ota-5t-pmos/psrr-bench.svg", "asset": "psrr-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota-5t-pmos/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "cmrr", "source": { "recordField": "testbenches", "id": "cmrr", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota-5t-pmos/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Five-transistor OTA, PMOS input", "instances": [] } ] }, "benchDiagram": { "graph": "graph-7", "svg": { "url": "/circuits/ota-5t-pmos/cmrr-bench.svg", "asset": "cmrr-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota-5t-pmos/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "noise", "source": { "recordField": "testbenches", "id": "noise", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota-5t-pmos/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Five-transistor OTA, PMOS input", "instances": [] } ] }, "benchDiagram": { "graph": "graph-8", "svg": { "url": "/circuits/ota-5t-pmos/noise-bench.svg", "asset": "noise-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota-5t-pmos/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "icmr", "source": { "recordField": "testbenches", "id": "icmr", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota-5t-pmos/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Five-transistor OTA, PMOS input", "instances": [] } ] }, "benchDiagram": { "graph": "graph-9", "svg": { "url": "/circuits/ota-5t-pmos/icmr-bench.svg", "asset": "icmr-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota-5t-pmos/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "swing", "source": { "recordField": "testbenches", "id": "swing", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota-5t-pmos/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Five-transistor OTA, PMOS input", "instances": [] } ] }, "benchDiagram": { "graph": "graph-10", "svg": { "url": "/circuits/ota-5t-pmos/swing-bench.svg", "asset": "swing-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota-5t-pmos/op-block.svg", "asset": "op-block.svg" } } } ] } }