{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ota-5t", "name": "Five-transistor OTA", "group": "Op amps and OTAs", "subgroup": "Single-stage OTAs", "title": "Five-transistor OTA", "summary": "This simple amplifier steers a shared current between two input transistors. A current mirror combines their changes at one output. The load capacitor sets much of the speed: a larger load responds more slowly but generally makes feedback easier to stabilize.", "reference": { "kind": "book", "authors": "P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer", "title": "Analysis and Design of Analog Integrated Circuits", "edition": "5th ed.", "publisher": "Wiley", "year": 2009, "where": "the single-stage differential amplifier with an active current-mirror load", "takes": "The topology and the results this bench measures: A0 = gm1*(ro2||ro4), a dominant pole at the output, and a slew rate of I_tail/C_L." }, "resources": { "record": "/circuits/ota-5t.json", "page": "/index.html#ota-5t", "achieved": "/achieved/ota-5t.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice" ], "ports": [ { "name": "inp", "kind": "input", "polarity": "+" }, { "name": "inn", "kind": "input", "polarity": "-" }, { "name": "out", "kind": "output" }, { "name": "bn", "kind": "bias", "note": "inject I_b into Mb's diode-connected node; the tail mirrors this externally supplied reference current" }, { "name": "vdd", "kind": "supply" }, { "name": "0", "kind": "ground", "note": "NMOS substrate and bias-current return" } ], "devices": [ { "name": "Mb", "type": "nmos", "nodes": "bn bn 0 0", "sizedBy": [ "Wb", "Lb" ], "role": "bias mirror, diode-connected", "fingers": 2, "copies": 1 }, { "name": "Mt", "type": "nmos", "nodes": "tail bn 0 0", "sizedBy": [ "Wb", "Lb" ], "role": "tail current source", "fingers": 2, "copies": 1 }, { "name": "M1", "type": "nmos", "nodes": "n1 inp tail 0", "sizedBy": [ "W", "L" ], "role": "input pair", "fingers": 2, "copies": 1 }, { "name": "M2", "type": "nmos", "nodes": "out inn tail 0", "sizedBy": [ "W", "L" ], "role": "input pair", "fingers": 2, "copies": 1 }, { "name": "M3", "type": "pmos", "nodes": "n1 n1 vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "load mirror, diode-connected", "fingers": 2, "copies": 1 }, { "name": "M4", "type": "pmos", "nodes": "out n1 vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "load mirror", "fingers": 2, "copies": 1 } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "Input pair; their mismatch is the input-referred offset." }, { "rule": "match", "of": [ "M3", "M4" ], "why": "Load mirror; mismatch becomes offset and limits common-mode rejection." }, { "rule": "same-length", "of": [ "M3", "M4" ], "why": "The load is a mirror and only mirrors while both share a length." }, { "rule": "single-pole", "of": [ "out" ], "constraint": "dominant pole at the output, set by C_L", "why": "When the loaded output pole dominates and the mirror pole is sufficiently higher, the one-stage amplifier can have a large phase margin without a separate compensation capacitor. In that approximation, four times C_L gives roughly a quarter of the unity-gain frequency with little DC-gain change. Light loads or changed sizing can bring other poles into play." }, { "rule": "slew", "of": [ "Mt" ], "constraint": "SR = I_tail/C_L", "why": "During a slew the input pair is fully steered, so the small-signal gain has no say: the tail current and the load capacitance are the whole answer." } ], "specs": [ { "key": "a0", "label": "Open-loop DC gain", "unit": "dB", "direction": "max" }, { "key": "funity", "label": "Unity-gain frequency", "unit": "Hz", "direction": "max" }, { "key": "pm", "label": "Phase margin", "unit": "deg", "direction": "min" }, { "key": "sr", "label": "Slew rate", "unit": "V/s", "direction": "max" } ], "explanation": { "idea": "This simple amplifier steers a shared current between two input transistors. A current mirror combines their changes at one output. The load capacitor sets much of the speed: a larger load responds more slowly but generally makes feedback easier to stabilize.", "detail": "The smallest useful OTA: it turns the voltage difference between inp and inn into a current and, in its own output resistance, into a single-ended output voltage. The pair M1–M2 splits the tail current by the input difference; the mirror M3–M4 copies M1's current onto the output, where M2 draws its own, so the two equal and opposite signal changes add. The output is the only high-impedance node, so C_L sets the bandwidth directly and the default load supplies the needed dominant-pole compensation.", "lesson": { "relation": 1, "symbols": "f_u (also called GBW here) is unity-gain frequency in Hz; g_m1 is one input transistor's small-signal transconductance in S; C_L is load capacitance in F. Where angular frequency is used, ω_u = 2π f_u.", "assumptions": "Small signals, saturated devices and an output-dominated response. The simple relation neglects device capacitance and higher-frequency internal poles.", "exercise": { "param": "CL", "value": 1e-12, "analysis": "ac", "expect": "Doubling the load capacitance should reduce unity-gain frequency, roughly by half if the load dominates. Compare phase margin and DC gain rather than expecting every metric to halve." }, "limits": "Provide the bias current and verify input common-mode and output-swing headroom for the intended load. This entry does not implement separate range sweeps and is not a rail-to-rail input/output guarantee." }, "path": [ { "part": "Input pair", "devices": "M1, M2", "does": "Splits the tail current by the input difference. inp drives M1, on the mirror's diode side, so the output follows inp." }, { "part": "Current-mirror load", "devices": "M3, M4", "does": "M3 turns M1's current into a gate voltage on n1; M4 copies that current onto the output." }, { "part": "Output node", "devices": "M2, M4", "does": "M4's copy and M2's current move in opposite directions, so the whole signal current flows into the output resistance and C_L." } ], "bias": "I_bias, 20 µA by default, enters the external bn port and sets the gate voltage of the diode-connected Mb, and Mt, the same size, copies it as the tail current, so each branch carries I_bias/2 at balance. Mb, Mt and the NMOS bodies return to the ground port. In the open-loop bench a DC-only feedback path holds the output at V_CM, 0.6 V by default.", "relations": [ { "what": "DC gain", "expr": "A_0 ≈ g_m1 (r_o2 ∥ r_o4)", "note": "M2's r_o is the short one: SG13G2 core NMOS reach far lower g_m/g_ds than the PMOS load." }, { "what": "Unity-gain frequency", "expr": "GBW ≈ g_m1/(2π·C_L)", "note": "Four times C_L is a quarter of the bandwidth; the DC gain does not move." }, { "what": "Dominant pole", "expr": "ω_p1 ≈ 1/[(r_o2 ∥ r_o4)·C_L]", "note": "The output is the only high-impedance node, so this pole dominates." }, { "what": "Mirror pole", "expr": "ω_p2 ≈ g_m3/C_n1", "note": "Half the signal bypasses n1, giving a zero at 2·ω_p2; lighter loads push the crossover towards it." }, { "what": "Slew rate", "expr": "SR = I_tail/C_L", "note": "The pair is fully steered during a large step; measured lower, as the output also carries device capacitance." } ], "tradeoffs": [ "Doubling C_L halves the unity-gain frequency and the slew rate and adds phase margin; the DC gain does not move.", "A longer L input pair raises r_o2, the resistance that limits the gain, but lowers g_m1 at fixed width and adds input capacitance.", "Raising I_bias raises g_m1, bandwidth and slew rate together, but shortens every r_o, so the DC gain falls a little.", "Widening W input pair moves the pair towards weak inversion: more g_m1 per µA and less offset from mismatch, but more capacitance on the inputs." ] }, "sizing": [ { "key": "W", "label": "W input pair", "unit": "m", "value": 0.00001, "min": 1.5e-7, "max": 0.0002, "kind": "si" }, { "key": "L", "label": "L input pair", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.00001, "kind": "si" }, { "key": "Wp", "label": "W load", "unit": "m", "value": 0.00001, "min": 1.5e-7, "max": 0.0002, "kind": "si" }, { "key": "Lp", "label": "L load", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.00001, "kind": "si" }, { "key": "Wb", "label": "W tail", "unit": "m", "value": 0.00001, "min": 1.5e-7, "max": 0.0002, "kind": "si" }, { "key": "Lb", "label": "L tail", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.00001, "kind": "si" }, { "key": "Ib", "label": "I_bias", "unit": "A", "value": 0.00002, "min": 0.000001, "max": 0.0005, "kind": "si" }, { "key": "CL", "label": "C_L", "unit": "F", "value": 5e-13, "min": 1e-14, "max": 5e-11, "kind": "si" }, { "key": "VCM", "label": "V_CM", "unit": "V", "value": 0.6, "min": 0.3, "max": 1, "kind": "si" } ], "testbenches": [ { "id": "ac", "label": "Open-loop response", "note": "", "measures": [ "a0", "f3db", "funity", "pm" ], "metricKeys": [ "dc_gain_db", "ugf_hz", "pm_deg" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Five-transistor OTA - open-loop gain and phase\n.include sg13g2_lv_tt.spice\nVdd vdd 0 1.2\n* tail current mirror\nIb vdd bn 20u\nXMb bn bn 0 0 sg13_lv_nmos w=10u l=1u ng=2 m=1\nXMt tail bn 0 0 sg13_lv_nmos w=10u l=1u ng=2 m=1\n* input pair\nXM1 n1 inp tail 0 sg13_lv_nmos w=10u l=2u ng=2 m=1\nXM2 out inn tail 0 sg13_lv_nmos w=10u l=2u ng=2 m=1\n* current-mirror load\nXM3 n1 n1 vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXM4 out n1 vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nCl out 0 500f\n* Unity-gain feedback at DC, fully open across the sweep: a 1 TH coil is a\n* dead short at DC and an open at every frequency visited, the 1 TF cap the\n* reverse. Without it a 40 dB amplifier has no defined output operating\n* point and the sweep reports the gain of a switched-off circuit.\nLfb out inn 1t\nCfb inn 0 1t\nVin inp 0 dc 600m ac 1\n.nodeset v(out)=600m v(inn)=600m\n.ac dec 25 1 10g\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas ac a0_db FIND vdb(out) AT=1\n.meas ac funity WHEN vdb(out)=0 FALL=1\n.end" }, { "id": "step", "label": "Unity-gain step", "note": "", "measures": [ "sr", "offset" ], "metricKeys": [ "sr", "vos" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Five-transistor OTA as a unity-gain buffer - large-signal step\n.include sg13g2_lv_tt.spice\nVdd vdd 0 1.2\n* the feedback is a wire: the inverting input IS the output node\n* tail current mirror\nIb vdd bn 20u\nXMb bn bn 0 0 sg13_lv_nmos w=10u l=1u ng=2 m=1\nXMt tail bn 0 0 sg13_lv_nmos w=10u l=1u ng=2 m=1\n* input pair\nXM1 n1 inp tail 0 sg13_lv_nmos w=10u l=2u ng=2 m=1\nXM2 out out tail 0 sg13_lv_nmos w=10u l=2u ng=2 m=1\n* current-mirror load\nXM3 n1 n1 vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nXM4 out n1 vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1\nCl out 0 500f\nVin inp 0 pulse(400m 800m 4n 100p 100p 18n 40n)\n.tran 13.3333p 40n\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas tran settled FIND v(out) AT=21.6n\n.end" } ], "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "067ba2f980eeee1cee012a24029310585a758bff29b7a91c8ea15c2079556a5c" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ota-5t.js", "sha256": "8d31e40a12b4353f47a85ef6430cc3e86eae2b4b22f1331a294ffe0a8ba56355" }, "simulationFingerprints": { "ac": "20925081c0b461943ee6aba05b2c2c3360750e331e3537f24087d7d5eb306604", "step": "b974a110b540e6db983ac9d297d4c7f83845de0535f1db57a754d77e0bc8d5af" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "ea3e3caf9751783aa985eb00fe70d775c81f87718ebf954f3ccc9118db6c2bcc", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ota-5t", "parameters": { "W": 0.00001, "L": 0.000002, "Wp": 0.00001, "Lp": 0.000002, "Wb": 0.00001, "Lb": 0.000001, "Ib": 0.00002, "CL": 5e-13, "VCM": 0.6 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ota-5t/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [], "scopes": [ { "id": "dut", "name": "top", "ports": [ { "name": "bn", "net": "bn", "kind": "bias" }, { "name": "gnd", "net": "0", "kind": "ground" }, { "name": "inp", "net": "inp", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "vdd", "net": "vdd", "kind": "supply" } ], "definitions": [], "devices": [ { "id": "XMb", "displayName": "Mb", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XMb bn bn 0 0 sg13_lv_nmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "bn" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMt", "displayName": "Mt", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XMt tail bn 0 0 sg13_lv_nmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XM1 n1 inp tail 0 sg13_lv_nmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "n1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XM2 out inn tail 0 sg13_lv_nmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XM3 n1 n1 vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "n1" }, { "id": "g", "net": "n1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XM4 out n1 vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "n1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "bn", "ground": false, "terminals": [ { "device": "XMb", "pin": "d" }, { "device": "XMb", "pin": "g" }, { "device": "XMt", "pin": "g" } ], "ports": [ "bn" ], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "XMb", "pin": "s" }, { "device": "XMb", "pin": "b" }, { "device": "XMt", "pin": "s" }, { "device": "XMt", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" } ], "ports": [ "gnd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMt", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "n1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "1.2", "source": "Vdd vdd 0 1.2", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "20u", "source": "Ib vdd bn 20u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "bn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "XMb", "displayName": "Mb", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XMb bn bn 0 0 sg13_lv_nmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "bn" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMt", "displayName": "Mt", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XMt tail bn 0 0 sg13_lv_nmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XM1 n1 inp tail 0 sg13_lv_nmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "n1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XM2 out inn tail 0 sg13_lv_nmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XM3 n1 n1 vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "n1" }, { "id": "g", "net": "n1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XM4 out n1 vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "n1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "500f", "source": "Cl out 0 500f", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfb", "displayName": "Lfb", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfb out inn 1t", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cfb", "displayName": "Cfb", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cfb inn 0 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 600m ac 1", "source": "Vin inp 0 dc 600m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "XMb", "pin": "s" }, { "device": "XMb", "pin": "b" }, { "device": "XMt", "pin": "s" }, { "device": "XMt", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "Cl", "pin": "n" }, { "device": "Cfb", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "bn", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "XMb", "pin": "d" }, { "device": "XMb", "pin": "g" }, { "device": "XMt", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMt", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "n1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "Cl", "pin": "p" }, { "device": "Lfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" }, { "device": "Lfb", "pin": "n" }, { "device": "Cfb", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "top-level-device-set", "scope": "top", "devices": [ "XMb", "XMt", "XM1", "XM2", "XM3", "XM4" ] } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Bias mirror", "devices": [ { "scope": "dut", "device": "XMb" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "Tail current source", "devices": [ { "scope": "dut", "device": "XMt" } ], "inferredStages": [ 1 ] }, { "id": "block-3", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 1 ] }, { "id": "block-4", "label": "Load mirror", "devices": [ { "scope": "dut", "device": "XM3" }, { "scope": "dut", "device": "XM4" } ], "inferredStages": [ 1 ] } ], "edges": [ { "id": "net-1", "net": "bn", "nodes": [ "block-1", "block-2" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "tail", "nodes": [ "block-2", "block-3" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "n1", "nodes": [ "block-3", "block-4" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "out", "nodes": [ "block-3", "block-4" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "bn", "net": "bn", "kind": "bias" }, { "name": "gnd", "net": "0", "kind": "ground" }, { "name": "inp", "net": "inp", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "vdd", "net": "vdd", "kind": "supply" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [], "scopes": [ { "id": "dut", "name": "top", "ports": [ { "name": "bn", "net": "bn", "kind": "bias" }, { "name": "gnd", "net": "0", "kind": "ground" }, { "name": "inp", "net": "inp", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" } ], "definitions": [], "devices": [ { "id": "XMb", "displayName": "Mb", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XMb bn bn 0 0 sg13_lv_nmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "bn" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMt", "displayName": "Mt", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XMt tail bn 0 0 sg13_lv_nmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XM1 n1 inp tail 0 sg13_lv_nmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "n1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XM2 out out tail 0 sg13_lv_nmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "out" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XM3 n1 n1 vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "n1" }, { "id": "g", "net": "n1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XM4 out n1 vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "n1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "bn", "ground": false, "terminals": [ { "device": "XMb", "pin": "d" }, { "device": "XMb", "pin": "g" }, { "device": "XMt", "pin": "g" } ], "ports": [ "bn" ], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "XMb", "pin": "s" }, { "device": "XMb", "pin": "b" }, { "device": "XMt", "pin": "s" }, { "device": "XMt", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" } ], "ports": [ "gnd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMt", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "n1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM2", "pin": "g" }, { "device": "XM4", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] } ] } ] }, { "id": "graph-5", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "1.2", "source": "Vdd vdd 0 1.2", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "20u", "source": "Ib vdd bn 20u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "bn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "XMb", "displayName": "Mb", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XMb bn bn 0 0 sg13_lv_nmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "bn" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMt", "displayName": "Mt", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XMt tail bn 0 0 sg13_lv_nmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XM1 n1 inp tail 0 sg13_lv_nmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "n1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XM2 out out tail 0 sg13_lv_nmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "out" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XM3 n1 n1 vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "n1" }, { "id": "g", "net": "n1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XM4 out n1 vdd vdd sg13_lv_pmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "n1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "500f", "source": "Cl out 0 500f", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "pulse(400m 800m 4n 100p 100p 18n 40n)", "source": "Vin inp 0 pulse(400m 800m 4n 100p 100p 18n 40n)", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "XMb", "pin": "s" }, { "device": "XMb", "pin": "b" }, { "device": "XMt", "pin": "s" }, { "device": "XMt", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "bn", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "XMb", "pin": "d" }, { "device": "XMb", "pin": "g" }, { "device": "XMt", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMt", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "n1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM2", "pin": "g" }, { "device": "XM4", "pin": "d" }, { "device": "Cl", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "top-level-device-set", "scope": "top", "devices": [ "XMb", "XMt", "XM1", "XM2", "XM3", "XM4" ] } }, { "id": "graph-6", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Bias mirror", "devices": [ { "scope": "dut", "device": "XMb" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "Tail current source", "devices": [ { "scope": "dut", "device": "XMt" } ], "inferredStages": [ 1 ] }, { "id": "block-3", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 1, 2 ] }, { "id": "block-4", "label": "Load mirror", "devices": [ { "scope": "dut", "device": "XM3" }, { "scope": "dut", "device": "XM4" } ], "inferredStages": [ 1, 2 ] } ], "edges": [ { "id": "net-1", "net": "bn", "nodes": [ "block-1", "block-2" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "tail", "nodes": [ "block-2", "block-3" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "n1", "nodes": [ "block-3", "block-4" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "out", "nodes": [ "block-3", "block-4" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "bn", "net": "bn", "kind": "bias" }, { "name": "gnd", "net": "0", "kind": "ground" }, { "name": "inp", "net": "inp", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." } ], "views": [ { "bench": "ac", "source": { "recordField": "testbenches", "id": "ac", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota-5t/ac-schematic.svg", "asset": "ac-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Five-transistor OTA", "instances": [] } ] }, "benchDiagram": { "graph": "graph-2", "svg": { "url": "/circuits/ota-5t/ac-bench.svg", "asset": "ac-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota-5t/ac-block.svg", "asset": "ac-block.svg" } } }, { "bench": "step", "source": { "recordField": "testbenches", "id": "step", "field": "netlist" }, "schematic": { "graph": "graph-4", "svg": { "url": "/circuits/ota-5t/step-schematic.svg", "asset": "step-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Five-transistor OTA", "instances": [] } ] }, "benchDiagram": { "graph": "graph-5", "svg": { "url": "/circuits/ota-5t/step-bench.svg", "asset": "step-bench.svg" } }, "blockDiagram": { "graph": "graph-6", "electricalGraph": "graph-4", "svg": { "url": "/circuits/ota-5t/step-block.svg", "asset": "step-block.svg" } } } ] } }