{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ota-folded-cascode", "name": "Folded-cascode OTA", "group": "Op amps and OTAs", "subgroup": "Single-stage OTAs", "title": "Folded-cascode OTA", "summary": "This amplifier increases gain by keeping internal transistor voltages nearly constant. Its folded current path separates the input stage from the output stack, improving the available voltage range. The tradeoff is extra bias current and careful sharing of a small supply voltage.", "reference": { "kind": "paper", "authors": "M. Scherzer, M. Auer", "title": "CORA-OpAmp: A Compact Open-Source Reinforcement-Learning Approach for Operational Amplifier Optimization in IHP SG13G2", "year": 2025, "where": "2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1-4", "doi": "10.1109/ICECS66544.2025.11270673", "takes": "The topology that paper sizes in SG13G2: a PMOS pair folding into NMOS sinks, NMOS cascodes, and a PMOS cascode mirror whose gates hang on its cascode's drain. The on-chip cascode biases, the headroom budget, the sizing and the spec targets are this library's." }, "resources": { "record": "/circuits/ota-folded-cascode.json", "page": "/index.html#ota-folded-cascode", "achieved": "/achieved/ota-folded-cascode.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice" ], "ports": [ { "name": "inp", "kind": "input" }, { "name": "inn", "kind": "input" }, { "name": "out", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the reference current, drawn out of this pin" } ], "devices": [ { "name": "MB", "type": "pmos", "nodes": "ib ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "bias reference, diode-connected", "fingers": 4, "copies": 1 }, { "name": "MT", "type": "pmos", "nodes": "tail ib vdd vdd", "sizedBy": [ "Wp", "Lp", "H" ], "role": "tail current source, 2H copies of MB", "fingers": 4, "copies": 4 }, { "name": "MB1", "type": "pmos", "nodes": "nb ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "copies the reference into MN", "fingers": 4, "copies": 1 }, { "name": "MB2", "type": "pmos", "nodes": "cn ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "copies the reference into the NMOS cascode-bias pair", "fingers": 4, "copies": 1 }, { "name": "MN", "type": "nmos", "nodes": "nb nb vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "NMOS reference, diode-connected", "fingers": 6, "copies": 1 }, { "name": "MCN", "type": "nmos", "nodes": "cn cn zn vss", "sizedBy": [ "Wc", "Lc" ], "role": "one NMOS cascode unit as a diode: sets the cascode gate cn", "fingers": 4, "copies": 1 }, { "name": "MZN", "type": "nmos", "nodes": "zn cn vss vss", "sizedBy": [ "Wzn", "Ln" ], "role": "in triode under MCN: its drop is the folding sinks' headroom", "fingers": 1, "copies": 1 }, { "name": "MN2", "type": "nmos", "nodes": "cp nb vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "draws the reference through the PMOS cascode-bias pair", "fingers": 6, "copies": 1 }, { "name": "MCP", "type": "pmos", "nodes": "cp cp zp vdd", "sizedBy": [ "Wpc", "Lpc" ], "role": "one PMOS cascode unit as a diode: sets the cascode gate cp", "fingers": 6, "copies": 1 }, { "name": "MZP", "type": "pmos", "nodes": "zp cp vdd vdd", "sizedBy": [ "Wzp", "Lm" ], "role": "in triode above MCP: its drop is the PMOS mirror's headroom", "fingers": 1, "copies": 1 }, { "name": "M1", "type": "pmos", "nodes": "f1 inp tail tail", "sizedBy": [ "W1", "L1" ], "role": "input pair, non-inverting input", "fingers": 8, "copies": 1 }, { "name": "M2", "type": "pmos", "nodes": "f2 inn tail tail", "sizedBy": [ "W1", "L1" ], "role": "input pair, inverting input", "fingers": 8, "copies": 1 }, { "name": "M3", "type": "nmos", "nodes": "f1 nb vss vss", "sizedBy": [ "Wn", "Ln", "H", "C" ], "role": "folding sink, H + C copies of MN", "fingers": 6, "copies": 4 }, { "name": "M4", "type": "nmos", "nodes": "f2 nb vss vss", "sizedBy": [ "Wn", "Ln", "H", "C" ], "role": "folding sink, H + C copies of MN", "fingers": 6, "copies": 4 }, { "name": "M5", "type": "nmos", "nodes": "gp cn f1 vss", "sizedBy": [ "Wc", "Lc", "C" ], "role": "NMOS cascode, mirror side; C units", "fingers": 4, "copies": 2 }, { "name": "M6", "type": "nmos", "nodes": "out cn f2 vss", "sizedBy": [ "Wc", "Lc", "C" ], "role": "NMOS cascode, output side; C units", "fingers": 4, "copies": 2 }, { "name": "M7", "type": "pmos", "nodes": "x1 gp vdd vdd", "sizedBy": [ "Wm", "Lm" ], "role": "PMOS mirror, input side", "fingers": 2, "copies": 1 }, { "name": "M8", "type": "pmos", "nodes": "x2 gp vdd vdd", "sizedBy": [ "Wm", "Lm" ], "role": "PMOS mirror, output side", "fingers": 2, "copies": 1 }, { "name": "M9", "type": "pmos", "nodes": "gp cp x1 vdd", "sizedBy": [ "Wpc", "Lpc", "C" ], "role": "PMOS cascode, mirror side; its drain is the mirror's gate line", "fingers": 6, "copies": 2 }, { "name": "M10", "type": "pmos", "nodes": "out cp x2 vdd", "sizedBy": [ "Wpc", "Lpc", "C" ], "role": "PMOS cascode, output side", "fingers": 6, "copies": 2 } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "The input pair: any difference is input offset. Each sits in its own n-well tied to the tail, which also takes the body effect out of its V_SG." }, { "rule": "match", "of": [ "M3", "M4" ], "why": "The folding sinks: a difference between them is a current the output must absorb, so it is offset." }, { "rule": "unit-copies", "of": [ "MB", "MT", "MB1", "MB2", "MN", "MN2", "M3", "M4" ], "constraint": "MT = 2H copies of MB; M3, M4 = H + C copies of MN", "why": "Every current is a copy of the reference: the pair gets H Ib a side, each sink draws H + C, so C Ib is left for each cascode branch whatever the process does." }, { "rule": "slew", "of": [ "M3", "M4", "MT" ], "constraint": "H + C ≥ 2H: each sink carries at least the whole tail", "why": "During a large step the whole tail current lands on one fold node. A sink that draws less than that lets the node rise until the input device leaves saturation, and the recovery is slow; C = H makes each sink exactly the tail." }, { "rule": "cascode-bias", "of": [ "MCN", "MZN", "M5", "M6", "M3", "M4" ], "constraint": "MCN = one unit of M5/M6; V_DS,MZN ≈ V_DSAT,M3 + 0.06 V", "why": "cn is a cascode unit's V_GS above the drop across MZN, held in triode. MCN matches M5 and M6 in current density, so the fold nodes sit at MZN's drop whatever the process and temperature do; MZN, in strong inversion, gains drop as it gets hot just as the sinks' V_DSAT grows. A plain diode in strong inversion instead drifted 50 mV the wrong way hot and put M6 into triode." }, { "rule": "cascode-bias", "of": [ "MCP", "MZP", "M9", "M10", "M7", "M8" ], "constraint": "V_DSAT,M7 ≤ V_SD,MZP ≤ V_SG,M7 − V_DSAT,M9", "why": "The mirror's gates hang on M9's drain, so M7 and M9 are both saturated only while MZP's drop sits in this window, 0.23 V wide at 27 °C and 0.12 V hot. MZP is sized to sit near its lower edge at 27 °C because hot the window closes from above while the drop rises with M7's V_DSAT." }, { "rule": "headroom", "of": [ "out" ], "constraint": "V_DS,M3 + V_DSAT,M6 ≤ v_out ≤ V_DD − V_SD,M8 − V_DSAT,M10", "why": "Two saturation voltages at each end leave the output 0.30 V to 0.84 V at 27 °C and 0.38 V to 0.67 V slow, hot and 10 % low. As a unity-gain buffer the input must fit that window too, under the pair's own ceiling: the design common mode, 0.5 V, is the one level inside it at every corner." } ], "specs": [ { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.00014 A", "min": null, "max": 0.00014, "why": "40 µA in the pair, 2 × 20 µA through the cascodes and 40 µA of bias, all copies of the 10 µA reference, which is held at every corner." }, { "key": "dc_gain_db", "label": "DC open-loop gain", "unit": "dB", "direction": "max", "constraint": ">= 48 dB", "min": 48, "max": null, "why": "g_m1 times the output resistance, which the NMOS side sets: a cascode with g_m/g_ds near 23 on a folding sink with 0.2 V across it. About 52 dB; 49.6 dB hot, slow and at the low supply." }, { "key": "ugf_hz", "label": "Unity-gain frequency", "unit": "Hz", "direction": "max", "constraint": ">= 18000000 Hz", "min": 18000000, "max": null, "why": "g_m1/(2π C_L) with 2 pF: 27 MHz at 27 °C, 20.8 MHz slow and hot." }, { "key": "pm_deg", "label": "Phase margin", "unit": "deg", "direction": "max", "constraint": ">= 70 deg", "min": 70, "max": null, "why": "The fold nodes and the mirror's gate line gp are low-impedance nodes whose poles sit far above the crossover: 77° to 79° at every corner." }, { "key": "t_settle", "label": "Settling time, 1 %", "unit": "s", "direction": "min", "constraint": "<= 5e-8 s", "min": null, "max": 5e-8, "why": "A 0.1 V step - the buffer's window allows no more at the slow, hot corner - settles on the single pole in 20 to 32 ns." }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 45 dB", "min": 45, "max": null, "why": "The PMOS mirror and its cascode bias are referred to V_DD, so a ripple there reaches the output through the mirror's finite output resistance." }, { "key": "cmrr_db", "label": "Common-mode rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 65 dB", "min": 65, "max": null, "why": "The tail's output resistance against the pair's match: 71 dB or more at every corner, and 69 dB in the worst of 200 mismatch draws." }, { "key": "icmr_lo", "label": "Lowest input common mode", "unit": "V", "direction": "min", "constraint": "<= 0.15 V", "min": null, "max": 0.15, "why": "A PMOS pair folding into NMOS sinks: its drains sit at 0.2 V, so the input works down to ground, and to within 0.08 V of it hot." }, { "key": "icmr_hi", "label": "Highest input common mode", "unit": "V", "direction": "max", "constraint": ">= 0.5 V", "min": 0.5, "max": null, "why": "The tail needs V_SG1 + V_DSAT,T below the supply; the pair's n-well on its source takes the body effect out of V_SG1. 0.56 V slow, hot and 10 % low." }, { "key": "swing_lo", "label": "Lowest output", "unit": "V", "direction": "min", "constraint": "<= 0.45 V", "min": null, "max": 0.45, "why": "The sink's headroom, set by MZN, plus the NMOS cascode's V_DSAT: 0.30 V at 27 °C, 0.38 V hot, where every V_DSAT grows." }, { "key": "swing_hi", "label": "Highest output", "unit": "V", "direction": "max", "constraint": ">= 0.62 V", "min": 0.62, "max": null, "why": "V_DD less the mirror's headroom, set by MZP, and the PMOS cascode's V_DSAT: 0.84 V at 27 °C, 0.67 V with the supply 10 % low and hot." } ], "explanation": { "idea": "This amplifier increases gain by keeping internal transistor voltages nearly constant. Its folded current path separates the input stage from the output stack, improving the available voltage range. The tradeoff is extra bias current and careful sharing of a small supply voltage.", "detail": "A single-stage OTA that reaches cascode output resistance without stacking cascodes on its input pair, so the input range and the output swing no longer compete for the same volts. The PMOS pair M1–M2 pushes its signal current down into the fold nodes f1 and f2, where NMOS common-gate devices M5–M6 carry it up to a cascoded PMOS mirror that recombines both halves at out. The output is the only high-impedance node, so the load sets the dominant pole. At 1.2 V the design is a headroom budget: both cascode gates are generated on chip, each from a copy of the cascode it biases, so they track process, supply and temperature.", "lesson": { "relation": 1, "symbols": "f_u (also called GBW here) is unity-gain frequency in Hz; g_m1 is one input transistor's small-signal transconductance in S; C_L is load capacitance in F. Where angular frequency is used, ω_u = 2π f_u.", "assumptions": "Small signals, saturated devices and an output-dominated response. The simple relation neglects device capacitance and higher-frequency internal poles.", "exercise": { "param": "CL", "value": 4e-12, "analysis": "open_loop", "expect": "Doubling the load capacitance should reduce unity-gain frequency, roughly by half if the load dominates. Compare phase margin and DC gain rather than expecting every metric to halve." }, "limits": "Provide the bias current and keep input common mode and output swing inside their separate measured ranges. This is not a rail-to-rail input/output guarantee." }, "path": [ { "part": "Input pair", "devices": "M1, M2, MT", "does": "MT's 40 µA divides between M1 and M2 as inp and inn differ, and each drain delivers its share to a fold node. A rise on inp cuts M1's current." }, { "part": "Folding sinks", "devices": "M3, M4", "does": "Each draws a fixed 40 µA from its fold node, so whatever an input device stops delivering, the cascode above it must: the signal current reverses direction and folds upwards." }, { "part": "NMOS cascodes", "devices": "M5, M6", "does": "Common-gate at cn: they pass the current changes up to gp and out while holding the fold nodes, low-impedance, almost still." }, { "part": "Cascode mirror", "devices": "M7, M8, M9, M10", "does": "M7 and M8 take their gates from gp, M9's drain, so M5's current is copied through M10 onto out, where M6 draws its own: a rise on inp raises M5's current and out." }, { "part": "Cascode bias", "devices": "MCN, MZN, MCP, MZP", "does": "Each cascode gate is a cascode unit's V_GS (MCN, MCP) above the drop across a device held in triode (MZN, MZP): the fold nodes sit at MZN's drop and the mirror's drains at MZP's." } ], "bias": "Only the 10 µA reference comes from outside, drawn out of the diode MB. MT, four copies, gives the pair 20 µA a side; MB1 and MB2 copy it into the NMOS reference MN and into the stack MCN–MZN, and MN2 draws it through MCP–MZP. The sinks M3 and M4 are four copies of MN, so 20 µA is left for each cascode branch: 120 µA in all. MCN is one unit of the cascodes M5–M6 and MCP one of M9–M10, at their current density.", "relations": [ { "what": "DC gain", "expr": "A_0 ≈ g_m1 · {[g_m6 r_o6 (r_o4 ∥ r_o2)] ∥ [g_m10 r_o10 r_o8]}", "note": "The NMOS side is the smaller, about 1 MΩ against 20 MΩ: M6's g_m/g_ds is only 23 with 0.3 V across it, and the sink has 0.2 V. About 52 dB." }, { "what": "Unity-gain frequency", "expr": "f_u ≈ g_m1/(2π C_L)", "note": "0.36 mS into 2 pF and the output's own capacitance: 27 MHz." }, { "what": "Output swing", "expr": "V_DS,MZN + V_DSAT6 ≤ v_out ≤ V_DD − V_SD,MZP − V_DSAT10", "note": "Two saturation voltages at each end: 0.30 V to 0.84 V at 27 °C, 0.38 V to 0.67 V slow, hot and with the supply 10 % low." }, { "what": "PMOS mirror window", "expr": "V_DSAT7 ≤ V_SD,MZP ≤ V_SG7 − V_DSAT9", "note": "Where M7 and M9 are both saturated: 0.23 V wide at 27 °C, 0.12 V hot, and MZP's drop - 0.29 V, 0.34 V hot - sits in it at every corner." }, { "what": "Highest input", "expr": "V_CM,max = V_DD − V_DSAT,T − V_SG1", "note": "With the pair's n-well on its source V_SG1 is 0.41 V rather than 0.46 V: the range reaches 0.67 V, 0.56 V at the worst corner." }, { "what": "Slew rate", "expr": "SR = I_tail/C_L", "note": "Holds because each sink draws the whole tail current, so no fold node is ever left without a path." } ], "tradeoffs": [ "The design common mode must sit in the buffer's window, above the output's floor and under the pair's ceiling: 0.38 V to 0.56 V at the slow, hot, low-supply corner, which is why it is 0.5 V and the step only 0.1 V.", "Longer NMOS cascodes raise the gain, 55 dB at 2 µm, but raise their V_DSAT and lift the output's floor to where M6 reaches the edge of saturation hot.", "A wider MZN lowers its drop: more room at the bottom of the output swing, less under the folding sinks - and they are the devices whose V_DSAT grows most hot.", "More tail current (H) raises g_m1 and the bandwidth, but the sinks must grow with it (C ≥ H for slewing), and their extra current lowers their r_o and the gain." ] }, "sizing": [ { "key": "Ib", "label": "Reference current", "unit": "A", "value": 0.00001, "min": 0.000001, "max": 0.00005, "kind": "si" }, { "key": "H", "label": "Each input device's current, in Ib", "unit": "", "value": 2, "min": 1, "max": 8, "kind": "int" }, { "key": "C", "label": "Each cascode branch's current, in Ib", "unit": "", "value": 2, "min": 1, "max": 8, "kind": "int" }, { "key": "W1", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.00004, "min": 0.000001, "max": 0.0002, "kind": "si" }, { "key": "L1", "label": "L input pair", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wp", "label": "W PMOS bias unit (MB, MT, MB1, MB2)", "unit": "m", "value": 0.000012, "min": 0.000001, "max": 0.00005, "kind": "si" }, { "key": "Lp", "label": "L PMOS bias unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Wn", "label": "W NMOS unit (MN, MN2, M3, M4)", "unit": "m", "value": 0.000022, "min": 5e-7, "max": 0.00005, "kind": "si" }, { "key": "Ln", "label": "L NMOS unit, and MZN", "unit": "m", "value": 0.000004, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Wc", "label": "W NMOS cascode unit (MCN, M5, M6)", "unit": "m", "value": 0.000011, "min": 5e-7, "max": 0.00005, "kind": "si" }, { "key": "Lc", "label": "L NMOS cascode", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wzn", "label": "W NMOS triode device (MZN)", "unit": "m", "value": 0.0000032, "min": 1.5e-7, "max": 0.00002, "kind": "si" }, { "key": "Wpc", "label": "W PMOS cascode unit (MCP, M9, M10)", "unit": "m", "value": 0.000022, "min": 0.000001, "max": 0.0001, "kind": "si" }, { "key": "Lpc", "label": "L PMOS cascode", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wm", "label": "W PMOS mirror (M7, M8)", "unit": "m", "value": 0.00001, "min": 0.000001, "max": 0.0001, "kind": "si" }, { "key": "Lm", "label": "L PMOS mirror, and MZP", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wzp", "label": "W PMOS triode device (MZP)", "unit": "m", "value": 0.0000017, "min": 1.5e-7, "max": 0.00002, "kind": "si" }, { "key": "CL", "label": "Load capacitance", "unit": "F", "value": 2e-12, "min": 1e-13, "max": 2e-11, "kind": "si" }, { "key": "VCM", "label": "Input common mode", "unit": "V", "value": 0.5, "min": 0, "max": 0.7, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.", "measures": [], "metricKeys": [ "i_supply", "vout_dc", "vos" ], "acceptance": [ "i_supply" ], "acceptanceRules": [ { "key": "i_supply", "unit": "A", "min": null, "max": 0.00014, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Folded-cascode OTA - operating point as a unity-gain buffer\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt otafc inp inn out vdd vss ib\n* bias: the reference into a PMOS diode, and copies of it\nXMB ib ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4\nXMB1 nb ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMB2 cn ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\n* the NMOS reference the folding sinks copy\nXMN nb nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1\n* the NMOS cascode gate: a cascode unit as a diode on a device in triode\nXMCN cn cn zn vss sg13_lv_nmos w=11u l=1u ng=4 m=1\nXMZN zn cn vss vss sg13_lv_nmos w=3.2u l=4u ng=1 m=1\n* the PMOS cascode gate, the same way up from vdd\nXMN2 cp nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1\nXMCP cp cp zp vdd sg13_lv_pmos w=22u l=500n ng=6 m=1\nXMZP zp cp vdd vdd sg13_lv_pmos w=1.7u l=1u ng=1 m=1\n* the PMOS pair, its n-well on its own sources; inp drives M1, on the side of\n* the mirror's diode\nXM1 f1 inp tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1\nXM2 f2 inn tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1\n* the folding sinks, H + C copies of MN each\nXM3 f1 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4\nXM4 f2 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4\n* the NMOS cascodes, C units each, carry what the sinks draw beyond the pair\nXM5 gp cn f1 vss sg13_lv_nmos w=11u l=1u ng=4 m=2\nXM6 out cn f2 vss sg13_lv_nmos w=11u l=1u ng=4 m=2\n* the PMOS cascode mirror: M7 and M8 take their gates from gp, M9's drain\nXM7 x1 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1\nXM8 x2 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1\nXM9 gp cp x1 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2\nXM10 out cp x2 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2\n.ends\nXdut inp inn out vdd 0 ib otafc\nCl out 0 2p\nVin inp 0 dc 500m\n* the output drives the inverting input: a unity-gain buffer\nVfb inn out 0\n.op\n.end" }, { "id": "open_loop", "label": "Open-loop gain", "note": "Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.", "measures": [], "metricKeys": [ "dc_gain_db", "ugf_hz", "pm_deg", "gm_db" ], "acceptance": [ "dc_gain_db", "ugf_hz", "pm_deg" ], "acceptanceRules": [ { "key": "dc_gain_db", "unit": "dB", "min": 48, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "ugf_hz", "unit": "Hz", "min": 18000000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "pm_deg", "unit": "deg", "min": 70, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Folded-cascode OTA - open-loop gain and phase\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt otafc inp inn out vdd vss ib\n* bias: the reference into a PMOS diode, and copies of it\nXMB ib ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4\nXMB1 nb ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMB2 cn ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\n* the NMOS reference the folding sinks copy\nXMN nb nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1\n* the NMOS cascode gate: a cascode unit as a diode on a device in triode\nXMCN cn cn zn vss sg13_lv_nmos w=11u l=1u ng=4 m=1\nXMZN zn cn vss vss sg13_lv_nmos w=3.2u l=4u ng=1 m=1\n* the PMOS cascode gate, the same way up from vdd\nXMN2 cp nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1\nXMCP cp cp zp vdd sg13_lv_pmos w=22u l=500n ng=6 m=1\nXMZP zp cp vdd vdd sg13_lv_pmos w=1.7u l=1u ng=1 m=1\n* the PMOS pair, its n-well on its own sources; inp drives M1, on the side of\n* the mirror's diode\nXM1 f1 inp tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1\nXM2 f2 inn tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1\n* the folding sinks, H + C copies of MN each\nXM3 f1 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4\nXM4 f2 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4\n* the NMOS cascodes, C units each, carry what the sinks draw beyond the pair\nXM5 gp cn f1 vss sg13_lv_nmos w=11u l=1u ng=4 m=2\nXM6 out cn f2 vss sg13_lv_nmos w=11u l=1u ng=4 m=2\n* the PMOS cascode mirror: M7 and M8 take their gates from gp, M9's drain\nXM7 x1 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1\nXM8 x2 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1\nXM9 gp cp x1 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2\nXM10 out cp x2 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2\n.ends\nXdut inp inn out vdd 0 ib otafc\nCl out 0 2p\nVin inp 0 dc 500m ac 1\n* the loop closed at DC and open at every frequency the sweep visits\nLfb out inn 1t\nCfb inn 0 1t\n.ac dec 25 0.1 10g\n.end" }, { "id": "step", "label": "Step response", "note": "A 100mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.", "measures": [], "metricKeys": [ "sr", "t_settle", "overshoot_pct" ], "acceptance": [ "t_settle" ], "acceptanceRules": [ { "key": "t_settle", "unit": "s", "min": null, "max": 5e-8, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Folded-cascode OTA - step response of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt otafc inp inn out vdd vss ib\n* bias: the reference into a PMOS diode, and copies of it\nXMB ib ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4\nXMB1 nb ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMB2 cn ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\n* the NMOS reference the folding sinks copy\nXMN nb nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1\n* the NMOS cascode gate: a cascode unit as a diode on a device in triode\nXMCN cn cn zn vss sg13_lv_nmos w=11u l=1u ng=4 m=1\nXMZN zn cn vss vss sg13_lv_nmos w=3.2u l=4u ng=1 m=1\n* the PMOS cascode gate, the same way up from vdd\nXMN2 cp nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1\nXMCP cp cp zp vdd sg13_lv_pmos w=22u l=500n ng=6 m=1\nXMZP zp cp vdd vdd sg13_lv_pmos w=1.7u l=1u ng=1 m=1\n* the PMOS pair, its n-well on its own sources; inp drives M1, on the side of\n* the mirror's diode\nXM1 f1 inp tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1\nXM2 f2 inn tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1\n* the folding sinks, H + C copies of MN each\nXM3 f1 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4\nXM4 f2 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4\n* the NMOS cascodes, C units each, carry what the sinks draw beyond the pair\nXM5 gp cn f1 vss sg13_lv_nmos w=11u l=1u ng=4 m=2\nXM6 out cn f2 vss sg13_lv_nmos w=11u l=1u ng=4 m=2\n* the PMOS cascode mirror: M7 and M8 take their gates from gp, M9's drain\nXM7 x1 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1\nXM8 x2 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1\nXM9 gp cp x1 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2\nXM10 out cp x2 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2\n.ends\nXdut inp inn out vdd 0 ib otafc\nCl out 0 2p\nVin inp 0 pulse(450m 550m 50n 1n 1n 250n 1u)\nVfb inn out 0\n.tran 125p 500n\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.", "measures": [], "metricKeys": [ "psrr_db" ], "acceptance": [ "psrr_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 45, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Folded-cascode OTA - supply rejection of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD} ac 1\nIb ib 0 10u\n.subckt otafc inp inn out vdd vss ib\n* bias: the reference into a PMOS diode, and copies of it\nXMB ib ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4\nXMB1 nb ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMB2 cn ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\n* the NMOS reference the folding sinks copy\nXMN nb nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1\n* the NMOS cascode gate: a cascode unit as a diode on a device in triode\nXMCN cn cn zn vss sg13_lv_nmos w=11u l=1u ng=4 m=1\nXMZN zn cn vss vss sg13_lv_nmos w=3.2u l=4u ng=1 m=1\n* the PMOS cascode gate, the same way up from vdd\nXMN2 cp nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1\nXMCP cp cp zp vdd sg13_lv_pmos w=22u l=500n ng=6 m=1\nXMZP zp cp vdd vdd sg13_lv_pmos w=1.7u l=1u ng=1 m=1\n* the PMOS pair, its n-well on its own sources; inp drives M1, on the side of\n* the mirror's diode\nXM1 f1 inp tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1\nXM2 f2 inn tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1\n* the folding sinks, H + C copies of MN each\nXM3 f1 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4\nXM4 f2 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4\n* the NMOS cascodes, C units each, carry what the sinks draw beyond the pair\nXM5 gp cn f1 vss sg13_lv_nmos w=11u l=1u ng=4 m=2\nXM6 out cn f2 vss sg13_lv_nmos w=11u l=1u ng=4 m=2\n* the PMOS cascode mirror: M7 and M8 take their gates from gp, M9's drain\nXM7 x1 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1\nXM8 x2 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1\nXM9 gp cp x1 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2\nXM10 out cp x2 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2\n.ends\nXdut inp inn out vdd 0 ib otafc\nCl out 0 2p\nVin inp 0 dc 500m\nVfb inn out 0\n.ac dec 25 1 100meg\n.end" }, { "id": "cmrr", "label": "Common-mode rejection", "note": "Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.", "measures": [], "metricKeys": [ "cmrr_db" ], "acceptance": [ "cmrr_db" ], "acceptanceRules": [ { "key": "cmrr_db", "unit": "dB", "min": 65, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Folded-cascode OTA - common-mode rejection\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt otafc inp inn out vdd vss ib\n* bias: the reference into a PMOS diode, and copies of it\nXMB ib ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4\nXMB1 nb ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMB2 cn ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\n* the NMOS reference the folding sinks copy\nXMN nb nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1\n* the NMOS cascode gate: a cascode unit as a diode on a device in triode\nXMCN cn cn zn vss sg13_lv_nmos w=11u l=1u ng=4 m=1\nXMZN zn cn vss vss sg13_lv_nmos w=3.2u l=4u ng=1 m=1\n* the PMOS cascode gate, the same way up from vdd\nXMN2 cp nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1\nXMCP cp cp zp vdd sg13_lv_pmos w=22u l=500n ng=6 m=1\nXMZP zp cp vdd vdd sg13_lv_pmos w=1.7u l=1u ng=1 m=1\n* the PMOS pair, its n-well on its own sources; inp drives M1, on the side of\n* the mirror's diode\nXM1 f1 inp tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1\nXM2 f2 inn tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1\n* the folding sinks, H + C copies of MN each\nXM3 f1 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4\nXM4 f2 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4\n* the NMOS cascodes, C units each, carry what the sinks draw beyond the pair\nXM5 gp cn f1 vss sg13_lv_nmos w=11u l=1u ng=4 m=2\nXM6 out cn f2 vss sg13_lv_nmos w=11u l=1u ng=4 m=2\n* the PMOS cascode mirror: M7 and M8 take their gates from gp, M9's drain\nXM7 x1 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1\nXM8 x2 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1\nXM9 gp cp x1 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2\nXM10 out cp x2 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2\n.ends\nXdut inp inn out vdd 0 ib otafc\nCl out 0 2p\nVsrc src 0 dc 500m\n* va on the non-inverting input, vb in the feedback path: both inputs move with the signal\nVa inp src dc 0 ac 1\nVb inn out dc 0 ac 1\n.ac dec 25 1 100meg\n.end" }, { "id": "noise", "label": "Noise", "note": "Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.", "measures": [], "metricKeys": [ "vn_1k", "vn_int" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Folded-cascode OTA - input-referred noise\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt otafc inp inn out vdd vss ib\n* bias: the reference into a PMOS diode, and copies of it\nXMB ib ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4\nXMB1 nb ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMB2 cn ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\n* the NMOS reference the folding sinks copy\nXMN nb nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1\n* the NMOS cascode gate: a cascode unit as a diode on a device in triode\nXMCN cn cn zn vss sg13_lv_nmos w=11u l=1u ng=4 m=1\nXMZN zn cn vss vss sg13_lv_nmos w=3.2u l=4u ng=1 m=1\n* the PMOS cascode gate, the same way up from vdd\nXMN2 cp nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1\nXMCP cp cp zp vdd sg13_lv_pmos w=22u l=500n ng=6 m=1\nXMZP zp cp vdd vdd sg13_lv_pmos w=1.7u l=1u ng=1 m=1\n* the PMOS pair, its n-well on its own sources; inp drives M1, on the side of\n* the mirror's diode\nXM1 f1 inp tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1\nXM2 f2 inn tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1\n* the folding sinks, H + C copies of MN each\nXM3 f1 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4\nXM4 f2 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4\n* the NMOS cascodes, C units each, carry what the sinks draw beyond the pair\nXM5 gp cn f1 vss sg13_lv_nmos w=11u l=1u ng=4 m=2\nXM6 out cn f2 vss sg13_lv_nmos w=11u l=1u ng=4 m=2\n* the PMOS cascode mirror: M7 and M8 take their gates from gp, M9's drain\nXM7 x1 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1\nXM8 x2 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1\nXM9 gp cp x1 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2\nXM10 out cp x2 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2\n.ends\nXdut inp inn out vdd 0 ib otafc\nCl out 0 2p\nVin inp 0 dc 500m ac 1\nVfb inn out 0\n.control\nnoise v(out) Vin dec 20 1 1meg\nsetplot noise1\n* 20 points a decade from 1 Hz: point 60 is 1 kHz\nlet vn_1k = inoise_spectrum[60]\nprint vn_1k\nsetplot noise2\nprint inoise_total\n.endc\n.op\n.end" }, { "id": "icmr", "label": "Input common-mode range", "note": "Both inputs swept together while the output is held at one level. The range is where open-loop gain falls by no more than 6 dB and unity-gain frequency by no more than 5 % from their values at the design common mode; increases are allowed.", "measures": [], "metricKeys": [ "icmr_lo", "icmr_hi" ], "acceptance": [ "icmr_lo", "icmr_hi" ], "acceptanceRules": [ { "key": "icmr_lo", "unit": "V", "min": null, "max": 0.15, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "icmr_hi", "unit": "V", "min": 0.5, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Folded-cascode OTA - input common-mode range, the output held at one level\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt otafc inp inn out vdd vss ib\n* bias: the reference into a PMOS diode, and copies of it\nXMB ib ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4\nXMB1 nb ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMB2 cn ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\n* the NMOS reference the folding sinks copy\nXMN nb nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1\n* the NMOS cascode gate: a cascode unit as a diode on a device in triode\nXMCN cn cn zn vss sg13_lv_nmos w=11u l=1u ng=4 m=1\nXMZN zn cn vss vss sg13_lv_nmos w=3.2u l=4u ng=1 m=1\n* the PMOS cascode gate, the same way up from vdd\nXMN2 cp nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1\nXMCP cp cp zp vdd sg13_lv_pmos w=22u l=500n ng=6 m=1\nXMZP zp cp vdd vdd sg13_lv_pmos w=1.7u l=1u ng=1 m=1\n* the PMOS pair, its n-well on its own sources; inp drives M1, on the side of\n* the mirror's diode\nXM1 f1 inp tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1\nXM2 f2 inn tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1\n* the folding sinks, H + C copies of MN each\nXM3 f1 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4\nXM4 f2 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4\n* the NMOS cascodes, C units each, carry what the sinks draw beyond the pair\nXM5 gp cn f1 vss sg13_lv_nmos w=11u l=1u ng=4 m=2\nXM6 out cn f2 vss sg13_lv_nmos w=11u l=1u ng=4 m=2\n* the PMOS cascode mirror: M7 and M8 take their gates from gp, M9's drain\nXM7 x1 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1\nXM8 x2 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1\nXM9 gp cp x1 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2\nXM10 out cp x2 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2\n.ends\nXdut inp inn out vdd 0 ib otafc\nCl out 0 2p\nVin inp 0 dc 500m ac 1\nVpark park 0 dc 500m\n* inn is inp shifted by how far out is from park: the loop holds out at park\n* while both inputs follow inp, and it is closed at DC only, as in the\n* open-loop bench, so each ac sweep sees the open loop\nEfb fb inp out park 1\nLfb fb inn 1t\nCfb inn 0 1t\n.control\n* point 0 is the design common mode, the reference; then every level\nac dec 20 0.1 10g\nmeas ac a0_0 find vdb(out) at=0.1\nmeas ac fu_0 when vdb(out)=0 fall=1\nalter vin dc = 0\nac dec 20 0.1 10g\nmeas ac a0_1 find vdb(out) at=0.1\nmeas ac fu_1 when vdb(out)=0 fall=1\nalter vin dc = 30m\nac dec 20 0.1 10g\nmeas ac a0_2 find vdb(out) at=0.1\nmeas ac fu_2 when vdb(out)=0 fall=1\nalter vin dc = 60m\nac dec 20 0.1 10g\nmeas ac a0_3 find vdb(out) at=0.1\nmeas ac fu_3 when vdb(out)=0 fall=1\nalter vin dc = 90m\nac dec 20 0.1 10g\nmeas ac a0_4 find vdb(out) at=0.1\nmeas ac fu_4 when vdb(out)=0 fall=1\nalter vin dc = 120m\nac dec 20 0.1 10g\nmeas ac a0_5 find vdb(out) at=0.1\nmeas ac fu_5 when vdb(out)=0 fall=1\nalter vin dc = 150m\nac dec 20 0.1 10g\nmeas ac a0_6 find vdb(out) at=0.1\nmeas ac fu_6 when vdb(out)=0 fall=1\nalter vin dc = 180m\nac dec 20 0.1 10g\nmeas ac a0_7 find vdb(out) at=0.1\nmeas ac fu_7 when vdb(out)=0 fall=1\nalter vin dc = 210m\nac dec 20 0.1 10g\nmeas ac a0_8 find vdb(out) at=0.1\nmeas ac fu_8 when vdb(out)=0 fall=1\nalter vin dc = 240m\nac dec 20 0.1 10g\nmeas ac a0_9 find vdb(out) at=0.1\nmeas ac fu_9 when vdb(out)=0 fall=1\nalter vin dc = 270m\nac dec 20 0.1 10g\nmeas ac a0_10 find vdb(out) at=0.1\nmeas ac fu_10 when vdb(out)=0 fall=1\nalter vin dc = 300m\nac dec 20 0.1 10g\nmeas ac a0_11 find vdb(out) at=0.1\nmeas ac fu_11 when vdb(out)=0 fall=1\nalter vin dc = 330m\nac dec 20 0.1 10g\nmeas ac a0_12 find vdb(out) at=0.1\nmeas ac fu_12 when vdb(out)=0 fall=1\nalter vin dc = 360m\nac dec 20 0.1 10g\nmeas ac a0_13 find vdb(out) at=0.1\nmeas ac fu_13 when vdb(out)=0 fall=1\nalter vin dc = 390m\nac dec 20 0.1 10g\nmeas ac a0_14 find vdb(out) at=0.1\nmeas ac fu_14 when vdb(out)=0 fall=1\nalter vin dc = 420m\nac dec 20 0.1 10g\nmeas ac a0_15 find vdb(out) at=0.1\nmeas ac fu_15 when vdb(out)=0 fall=1\nalter vin dc = 450m\nac dec 20 0.1 10g\nmeas ac a0_16 find vdb(out) at=0.1\nmeas ac fu_16 when vdb(out)=0 fall=1\nalter vin dc = 480m\nac dec 20 0.1 10g\nmeas ac a0_17 find vdb(out) at=0.1\nmeas ac fu_17 when vdb(out)=0 fall=1\nalter vin dc = 510m\nac dec 20 0.1 10g\nmeas ac a0_18 find vdb(out) at=0.1\nmeas ac fu_18 when vdb(out)=0 fall=1\nalter vin dc = 540m\nac dec 20 0.1 10g\nmeas ac a0_19 find vdb(out) at=0.1\nmeas ac fu_19 when vdb(out)=0 fall=1\nalter vin dc = 570m\nac dec 20 0.1 10g\nmeas ac a0_20 find vdb(out) at=0.1\nmeas ac fu_20 when vdb(out)=0 fall=1\nalter vin dc = 600m\nac dec 20 0.1 10g\nmeas ac a0_21 find vdb(out) at=0.1\nmeas ac fu_21 when vdb(out)=0 fall=1\nalter vin dc = 630m\nac dec 20 0.1 10g\nmeas ac a0_22 find vdb(out) at=0.1\nmeas ac fu_22 when vdb(out)=0 fall=1\nalter vin dc = 660m\nac dec 20 0.1 10g\nmeas ac a0_23 find vdb(out) at=0.1\nmeas ac fu_23 when vdb(out)=0 fall=1\nalter vin dc = 690m\nac dec 20 0.1 10g\nmeas ac a0_24 find vdb(out) at=0.1\nmeas ac fu_24 when vdb(out)=0 fall=1\nalter vin dc = 720m\nac dec 20 0.1 10g\nmeas ac a0_25 find vdb(out) at=0.1\nmeas ac fu_25 when vdb(out)=0 fall=1\nalter vin dc = 750m\nac dec 20 0.1 10g\nmeas ac a0_26 find vdb(out) at=0.1\nmeas ac fu_26 when vdb(out)=0 fall=1\nalter vin dc = 780m\nac dec 20 0.1 10g\nmeas ac a0_27 find vdb(out) at=0.1\nmeas ac fu_27 when vdb(out)=0 fall=1\nalter vin dc = 810m\nac dec 20 0.1 10g\nmeas ac a0_28 find vdb(out) at=0.1\nmeas ac fu_28 when vdb(out)=0 fall=1\nalter vin dc = 840m\nac dec 20 0.1 10g\nmeas ac a0_29 find vdb(out) at=0.1\nmeas ac fu_29 when vdb(out)=0 fall=1\nalter vin dc = 870m\nac dec 20 0.1 10g\nmeas ac a0_30 find vdb(out) at=0.1\nmeas ac fu_30 when vdb(out)=0 fall=1\nalter vin dc = 900m\nac dec 20 0.1 10g\nmeas ac a0_31 find vdb(out) at=0.1\nmeas ac fu_31 when vdb(out)=0 fall=1\nalter vin dc = 930m\nac dec 20 0.1 10g\nmeas ac a0_32 find vdb(out) at=0.1\nmeas ac fu_32 when vdb(out)=0 fall=1\nalter vin dc = 960m\nac dec 20 0.1 10g\nmeas ac a0_33 find vdb(out) at=0.1\nmeas ac fu_33 when vdb(out)=0 fall=1\nalter vin dc = 990m\nac dec 20 0.1 10g\nmeas ac a0_34 find vdb(out) at=0.1\nmeas ac fu_34 when vdb(out)=0 fall=1\nalter vin dc = 1.02\nac dec 20 0.1 10g\nmeas ac a0_35 find vdb(out) at=0.1\nmeas ac fu_35 when vdb(out)=0 fall=1\nalter vin dc = 1.05\nac dec 20 0.1 10g\nmeas ac a0_36 find vdb(out) at=0.1\nmeas ac fu_36 when vdb(out)=0 fall=1\nalter vin dc = 1.08\nac dec 20 0.1 10g\nmeas ac a0_37 find vdb(out) at=0.1\nmeas ac fu_37 when vdb(out)=0 fall=1\nalter vin dc = 1.11\nac dec 20 0.1 10g\nmeas ac a0_38 find vdb(out) at=0.1\nmeas ac fu_38 when vdb(out)=0 fall=1\nalter vin dc = 1.14\nac dec 20 0.1 10g\nmeas ac a0_39 find vdb(out) at=0.1\nmeas ac fu_39 when vdb(out)=0 fall=1\nalter vin dc = 1.17\nac dec 20 0.1 10g\nmeas ac a0_40 find vdb(out) at=0.1\nmeas ac fu_40 when vdb(out)=0 fall=1\nalter vin dc = 1.2\nac dec 20 0.1 10g\nmeas ac a0_41 find vdb(out) at=0.1\nmeas ac fu_41 when vdb(out)=0 fall=1\nalter vin dc = 1.23\nac dec 20 0.1 10g\nmeas ac a0_42 find vdb(out) at=0.1\nmeas ac fu_42 when vdb(out)=0 fall=1\nalter vin dc = 1.26\nac dec 20 0.1 10g\nmeas ac a0_43 find vdb(out) at=0.1\nmeas ac fu_43 when vdb(out)=0 fall=1\nalter vin dc = 1.29\nac dec 20 0.1 10g\nmeas ac a0_44 find vdb(out) at=0.1\nmeas ac fu_44 when vdb(out)=0 fall=1\nalter vin dc = 1.32\nac dec 20 0.1 10g\nmeas ac a0_45 find vdb(out) at=0.1\nmeas ac fu_45 when vdb(out)=0 fall=1\n.endc\n.dc Vin 0 1.32 30m\n.end" }, { "id": "swing", "label": "Output swing", "note": "The amplifier as an inverting gain of one - its inverting input at the midpoint of the output and a signal, through two ideal controlled sources that load nothing - with the signal swept so the output crosses from rail to rail, and at each level the open-loop gain: the swing is where the gain stays within 6 dB of its value with the output at the input common mode.", "measures": [], "metricKeys": [ "swing_lo", "swing_hi" ], "acceptance": [ "swing_lo", "swing_hi" ], "acceptanceRules": [ { "key": "swing_lo", "unit": "V", "min": null, "max": 0.45, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "swing_hi", "unit": "V", "min": 0.62, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Folded-cascode OTA - output swing, as an inverting amplifier of gain one\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 10u\n.subckt otafc inp inn out vdd vss ib\n* bias: the reference into a PMOS diode, and copies of it\nXMB ib ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMT tail ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4\nXMB1 nb ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\nXMB2 cn ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1\n* the NMOS reference the folding sinks copy\nXMN nb nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1\n* the NMOS cascode gate: a cascode unit as a diode on a device in triode\nXMCN cn cn zn vss sg13_lv_nmos w=11u l=1u ng=4 m=1\nXMZN zn cn vss vss sg13_lv_nmos w=3.2u l=4u ng=1 m=1\n* the PMOS cascode gate, the same way up from vdd\nXMN2 cp nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1\nXMCP cp cp zp vdd sg13_lv_pmos w=22u l=500n ng=6 m=1\nXMZP zp cp vdd vdd sg13_lv_pmos w=1.7u l=1u ng=1 m=1\n* the PMOS pair, its n-well on its own sources; inp drives M1, on the side of\n* the mirror's diode\nXM1 f1 inp tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1\nXM2 f2 inn tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1\n* the folding sinks, H + C copies of MN each\nXM3 f1 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4\nXM4 f2 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4\n* the NMOS cascodes, C units each, carry what the sinks draw beyond the pair\nXM5 gp cn f1 vss sg13_lv_nmos w=11u l=1u ng=4 m=2\nXM6 out cn f2 vss sg13_lv_nmos w=11u l=1u ng=4 m=2\n* the PMOS cascode mirror: M7 and M8 take their gates from gp, M9's drain\nXM7 x1 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1\nXM8 x2 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1\nXM9 gp cp x1 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2\nXM10 out cp x2 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2\n.ends\nXdut inp inn out vdd 0 ib otafc\nCl out 0 2p\nVcm inp 0 dc 500m ac 1\nVsig sig 0 dc 500m\n* inn is the midpoint of out and sig: v(out) = 2 V_CM - v(sig). Closed at DC\n* only, so each ac sweep reads the open-loop gain at that output level\nE1 fbn mid out 0 0.5\nE2 mid 0 sig 0 0.5\nLfb fbn inn 1t\nCfb inn 0 1t\n.control\n* point 0 has the output at the input common mode, the reference\nac dec 1 0.1 1\nmeas ac a0_0 find vdb(out) at=0.1\nalter vsig dc = 1\nac dec 1 0.1 1\nmeas ac a0_1 find vdb(out) at=0.1\nalter vsig dc = 970m\nac dec 1 0.1 1\nmeas ac a0_2 find vdb(out) at=0.1\nalter vsig dc = 940m\nac dec 1 0.1 1\nmeas ac a0_3 find vdb(out) at=0.1\nalter vsig dc = 910m\nac dec 1 0.1 1\nmeas ac a0_4 find vdb(out) at=0.1\nalter vsig dc = 880m\nac dec 1 0.1 1\nmeas ac a0_5 find vdb(out) at=0.1\nalter vsig dc = 850m\nac dec 1 0.1 1\nmeas ac a0_6 find vdb(out) at=0.1\nalter vsig dc = 820m\nac dec 1 0.1 1\nmeas ac a0_7 find vdb(out) at=0.1\nalter vsig dc = 790m\nac dec 1 0.1 1\nmeas ac a0_8 find vdb(out) at=0.1\nalter vsig dc = 760m\nac dec 1 0.1 1\nmeas ac a0_9 find vdb(out) at=0.1\nalter vsig dc = 730m\nac dec 1 0.1 1\nmeas ac a0_10 find vdb(out) at=0.1\nalter vsig dc = 700m\nac dec 1 0.1 1\nmeas ac a0_11 find vdb(out) at=0.1\nalter vsig dc = 670m\nac dec 1 0.1 1\nmeas ac a0_12 find vdb(out) at=0.1\nalter vsig dc = 640m\nac dec 1 0.1 1\nmeas ac a0_13 find vdb(out) at=0.1\nalter vsig dc = 610m\nac dec 1 0.1 1\nmeas ac a0_14 find vdb(out) at=0.1\nalter vsig dc = 580m\nac dec 1 0.1 1\nmeas ac a0_15 find vdb(out) at=0.1\nalter vsig dc = 550m\nac dec 1 0.1 1\nmeas ac a0_16 find vdb(out) at=0.1\nalter vsig dc = 520m\nac dec 1 0.1 1\nmeas ac a0_17 find vdb(out) at=0.1\nalter vsig dc = 490m\nac dec 1 0.1 1\nmeas ac a0_18 find vdb(out) at=0.1\nalter vsig dc = 460m\nac dec 1 0.1 1\nmeas ac a0_19 find vdb(out) at=0.1\nalter vsig dc = 430m\nac dec 1 0.1 1\nmeas ac a0_20 find vdb(out) at=0.1\nalter vsig dc = 400m\nac dec 1 0.1 1\nmeas ac a0_21 find vdb(out) at=0.1\nalter vsig dc = 370m\nac dec 1 0.1 1\nmeas ac a0_22 find vdb(out) at=0.1\nalter vsig dc = 340m\nac dec 1 0.1 1\nmeas ac a0_23 find vdb(out) at=0.1\nalter vsig dc = 310m\nac dec 1 0.1 1\nmeas ac a0_24 find vdb(out) at=0.1\nalter vsig dc = 280m\nac dec 1 0.1 1\nmeas ac a0_25 find vdb(out) at=0.1\nalter vsig dc = 250m\nac dec 1 0.1 1\nmeas ac a0_26 find vdb(out) at=0.1\nalter vsig dc = 220m\nac dec 1 0.1 1\nmeas ac a0_27 find vdb(out) at=0.1\nalter vsig dc = 190m\nac dec 1 0.1 1\nmeas ac a0_28 find vdb(out) at=0.1\nalter vsig dc = 160m\nac dec 1 0.1 1\nmeas ac a0_29 find vdb(out) at=0.1\nalter vsig dc = 130m\nac dec 1 0.1 1\nmeas ac a0_30 find vdb(out) at=0.1\nalter vsig dc = 100m\nac dec 1 0.1 1\nmeas ac a0_31 find vdb(out) at=0.1\nalter vsig dc = 70m\nac dec 1 0.1 1\nmeas ac a0_32 find vdb(out) at=0.1\nalter vsig dc = 40m\nac dec 1 0.1 1\nmeas ac a0_33 find vdb(out) at=0.1\nalter vsig dc = 10m\nac dec 1 0.1 1\nmeas ac a0_34 find vdb(out) at=0.1\nalter vsig dc = -20m\nac dec 1 0.1 1\nmeas ac a0_35 find vdb(out) at=0.1\nalter vsig dc = -50m\nac dec 1 0.1 1\nmeas ac a0_36 find vdb(out) at=0.1\nalter vsig dc = -80m\nac dec 1 0.1 1\nmeas ac a0_37 find vdb(out) at=0.1\nalter vsig dc = -110m\nac dec 1 0.1 1\nmeas ac a0_38 find vdb(out) at=0.1\nalter vsig dc = -140m\nac dec 1 0.1 1\nmeas ac a0_39 find vdb(out) at=0.1\nalter vsig dc = -170m\nac dec 1 0.1 1\nmeas ac a0_40 find vdb(out) at=0.1\nalter vsig dc = -200m\nac dec 1 0.1 1\nmeas ac a0_41 find vdb(out) at=0.1\n.endc\n.dc Vsig -200m 1 30m\n.end" } ], "measurements": { "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.00014 } }, "dc_gain_db": { "label": "DC open-loop gain", "unit": "dB", "spec": { "min": 48, "max": null } }, "ugf_hz": { "label": "Unity-gain frequency", "unit": "Hz", "spec": { "min": 18000000, "max": null } }, "pm_deg": { "label": "Phase margin", "unit": "deg", "spec": { "min": 70, "max": null } }, "t_settle": { "label": "Settling time, 1 %", "unit": "s", "spec": { "min": null, "max": 5e-8 } }, "psrr_db": { "label": "Supply rejection at 1 kHz", "unit": "dB", "spec": { "min": 45, "max": null } }, "cmrr_db": { "label": "Common-mode rejection at 1 kHz", "unit": "dB", "spec": { "min": 65, "max": null } }, "icmr_lo": { "label": "Lowest input common mode", "unit": "V", "spec": { "min": null, "max": 0.15 } }, "icmr_hi": { "label": "Highest input common mode", "unit": "V", "spec": { "min": 0.5, "max": null } }, "swing_lo": { "label": "Lowest output", "unit": "V", "spec": { "min": null, "max": 0.45 } }, "swing_hi": { "label": "Highest output", "unit": "V", "spec": { "min": 0.62, "max": null } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "72785129fa543e751a0dd086b99774c3c7397d5478f384b7fa59da4007553e43" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ota-folded-cascode.js", "sha256": "2b3de99d90ae40d0ce71f25706f01d4025941418d532d40c7ba08a7853fa826a" }, "simulationFingerprints": { "op": "35f51ba7ada9cdd5b3d9666f49f460e3a5c53bc38e9d2107deca6143db7ad744", "open_loop": "b425f4d327928d777aa1b90ebcd0dc8d8255f3b3e4ae2265badcce99f9af81fa", "step": "b0a845f87d9bf17bbe10756be2fe22be65af45442ece0df452a2ad8047945752", "psrr": "1a666ad09505de82dcf207b08bb9a95d3a444cb581e83a8b23313303a2d4899a", "cmrr": "62746d1f5f5b2ad88a772377e9bad569781fe66fc006c149c8fa9dc3ed2c14b0", "noise": "33f9f9ffe5904a639d1b29aa1fdc8b6feaba0777eaf80796334cbefdad9a105b", "icmr": "84281bac0f4efde67d8f5c7e9897924edc92f309a687a1cfb39a733f4db93a54", "swing": "9305d81c4cc116780c3e50b0661012d34d68af64b471dcd7f72ecac5f72a3723" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "2836cfdcf42bfc73b9566b0917da2151698a447fd64907f8471736fec0bf3c15", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ota-folded-cascode", "parameters": { "Ib": 0.00001, "H": 2, "C": 2, "W1": 0.00004, "L1": 5e-7, "Wp": 0.000012, "Lp": 0.000001, "Wn": 0.000022, "Ln": 0.000004, "Wc": 0.000011, "Lc": 0.000001, "Wzn": 0.0000032, "Wpc": 0.000022, "Lpc": 5e-7, "Wm": 0.00001, "Lm": 0.000001, "Wzp": 0.0000017, "CL": 2e-12, "VCM": 0.5 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ota-folded-cascode/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "otafc", "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=4", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB2 cn ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN", "displayName": "MN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=1", "source": "XMN nb nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCN", "displayName": "MCN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=1", "source": "XMCN cn cn zn vss sg13_lv_nmos w=11u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "zn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZN", "displayName": "MZN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=4u ng=1 m=1", "source": "XMZN zn cn vss vss sg13_lv_nmos w=3.2u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "zn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=1", "source": "XMN2 cp nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCP", "displayName": "MCP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=1", "source": "XMCP cp cp zp vdd sg13_lv_pmos w=22u l=500n ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "zp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZP", "displayName": "MZP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.7u l=1u ng=1 m=1", "source": "XMZP zp cp vdd vdd sg13_lv_pmos w=1.7u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "zp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=500n ng=8 m=1", "source": "XM1 f1 inp tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=500n ng=8 m=1", "source": "XM2 f2 inn tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=4", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=4", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=2", "source": "XM5 gp cn f1 vss sg13_lv_nmos w=11u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=2", "source": "XM6 out cn f2 vss sg13_lv_nmos w=11u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XM7 x1 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XM8 x2 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=2", "source": "XM9 gp cp x1 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=2", "source": "XM10 out cp x2 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMCP", "pin": "b" }, { "device": "XMZP", "pin": "s" }, { "device": "XMZP", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMN", "pin": "d" }, { "device": "XMN", "pin": "g" }, { "device": "XMN2", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cn", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XMCN", "pin": "d" }, { "device": "XMCN", "pin": "g" }, { "device": "XMZN", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMN", "pin": "s" }, { "device": "XMN", "pin": "b" }, { "device": "XMCN", "pin": "b" }, { "device": "XMZN", "pin": "s" }, { "device": "XMZN", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "zn", "ground": false, "terminals": [ { "device": "XMCN", "pin": "s" }, { "device": "XMZN", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cp", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XMCP", "pin": "d" }, { "device": "XMCP", "pin": "g" }, { "device": "XMZP", "pin": "g" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zp", "ground": false, "terminals": [ { "device": "XMCP", "pin": "s" }, { "device": "XMZP", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "gp", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM9", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "otafc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib otafc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/otafc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cl out 0 2p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 500m", "source": "Vin inp 0 dc 500m", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/otafc", "name": "otafc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=4", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB2 cn ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN", "displayName": "MN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=1", "source": "XMN nb nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCN", "displayName": "MCN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=1", "source": "XMCN cn cn zn vss sg13_lv_nmos w=11u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "zn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZN", "displayName": "MZN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=4u ng=1 m=1", "source": "XMZN zn cn vss vss sg13_lv_nmos w=3.2u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "zn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=1", "source": "XMN2 cp nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCP", "displayName": "MCP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=1", "source": "XMCP cp cp zp vdd sg13_lv_pmos w=22u l=500n ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "zp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZP", "displayName": "MZP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.7u l=1u ng=1 m=1", "source": "XMZP zp cp vdd vdd sg13_lv_pmos w=1.7u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "zp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=500n ng=8 m=1", "source": "XM1 f1 inp tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=500n ng=8 m=1", "source": "XM2 f2 inn tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=4", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=4", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=2", "source": "XM5 gp cn f1 vss sg13_lv_nmos w=11u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=2", "source": "XM6 out cn f2 vss sg13_lv_nmos w=11u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XM7 x1 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XM8 x2 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=2", "source": "XM9 gp cp x1 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=2", "source": "XM10 out cp x2 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMCP", "pin": "b" }, { "device": "XMZP", "pin": "s" }, { "device": "XMZP", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMN", "pin": "d" }, { "device": "XMN", "pin": "g" }, { "device": "XMN2", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cn", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XMCN", "pin": "d" }, { "device": "XMCN", "pin": "g" }, { "device": "XMZN", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMN", "pin": "s" }, { "device": "XMN", "pin": "b" }, { "device": "XMCN", "pin": "b" }, { "device": "XMZN", "pin": "s" }, { "device": "XMZN", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "zn", "ground": false, "terminals": [ { "device": "XMCN", "pin": "s" }, { "device": "XMZN", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cp", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XMCP", "pin": "d" }, { "device": "XMCP", "pin": "g" }, { "device": "XMZP", "pin": "g" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zp", "ground": false, "terminals": [ { "device": "XMCP", "pin": "s" }, { "device": "XMZP", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "gp", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM9", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/otafc" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Bias reference", "devices": [ { "scope": "dut", "device": "XMB" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "Tail current source", "devices": [ { "scope": "dut", "device": "XMT" } ], "inferredStages": [ 1 ] }, { "id": "block-3", "label": "Copies the reference into MN", "devices": [ { "scope": "dut", "device": "XMB1" } ], "inferredStages": [ "bias" ] }, { "id": "block-4", "label": "Copies the reference into the NMOS cascode-bias pair", "devices": [ { "scope": "dut", "device": "XMB2" } ], "inferredStages": [ "bias" ] }, { "id": "block-5", "label": "NMOS reference", "devices": [ { "scope": "dut", "device": "XMN" } ], "inferredStages": [ "bias" ] }, { "id": "block-6", "label": "One NMOS cascode unit as a diode: sets the cascode gate cn", "devices": [ { "scope": "dut", "device": "XMCN" } ], "inferredStages": [ "bias" ] }, { "id": "block-7", "label": "In triode under MCN: its drop is the folding sinks' headroom", "devices": [ { "scope": "dut", "device": "XMZN" } ], "inferredStages": [ "bias" ] }, { "id": "block-8", "label": "Draws the reference through the PMOS cascode-bias pair", "devices": [ { "scope": "dut", "device": "XMN2" } ], "inferredStages": [ "bias" ] }, { "id": "block-9", "label": "One PMOS cascode unit as a diode: sets the cascode gate cp", "devices": [ { "scope": "dut", "device": "XMCP" } ], "inferredStages": [ "bias" ] }, { "id": "block-10", "label": "In triode above MCP: its drop is the PMOS mirror's headroom", "devices": [ { "scope": "dut", "device": "XMZP" } ], "inferredStages": [ "bias" ] }, { "id": "block-11", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 1 ] }, { "id": "block-12", "label": "Folding sink", "devices": [ { "scope": "dut", "device": "XM3" }, { "scope": "dut", "device": "XM4" } ], "inferredStages": [ 1 ] }, { "id": "block-13", "label": "NMOS cascode", "devices": [ { "scope": "dut", "device": "XM5" }, { "scope": "dut", "device": "XM6" } ], "inferredStages": [ 2 ] }, { "id": "block-14", "label": "PMOS mirror", "devices": [ { "scope": "dut", "device": "XM7" }, { "scope": "dut", "device": "XM8" } ], "inferredStages": [ 3 ] }, { "id": "block-15", "label": "PMOS cascode", "devices": [ { "scope": "dut", "device": "XM9" }, { "scope": "dut", "device": "XM10" } ], "inferredStages": [ 2 ] } ], "edges": [ { "id": "net-1", "net": "ib", "nodes": [ "block-1", "block-2", "block-3", "block-4" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "tail", "nodes": [ "block-2", "block-11" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "nb", "nodes": [ "block-3", "block-5", "block-8", "block-12" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "cn", "nodes": [ "block-4", "block-6", "block-7", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "zn", "nodes": [ "block-6", "block-7" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "cp", "nodes": [ "block-8", "block-9", "block-10", "block-15" ], "direction": "undirected-shared-net" }, { "id": "net-7", "net": "zp", "nodes": [ "block-9", "block-10" ], "direction": "undirected-shared-net" }, { "id": "net-8", "net": "f1", "nodes": [ "block-11", "block-12", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-9", "net": "f2", "nodes": [ "block-11", "block-12", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-10", "net": "gp", "nodes": [ "block-13", "block-14", "block-15" ], "direction": "undirected-shared-net" }, { "id": "net-11", "net": "out", "nodes": [ "block-13", "block-15" ], "direction": "undirected-shared-net" }, { "id": "net-12", "net": "x1", "nodes": [ "block-14", "block-15" ], "direction": "undirected-shared-net" }, { "id": "net-13", "net": "x2", "nodes": [ "block-14", "block-15" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "otafc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib otafc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/otafc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cl out 0 2p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 500m ac 1", "source": "Vin inp 0 dc 500m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfb", "displayName": "Lfb", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfb out inn 1t", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cfb", "displayName": "Cfb", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cfb inn 0 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" }, { "device": "Cfb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Lfb", "pin": "n" }, { "device": "Cfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Lfb", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/otafc", "name": "otafc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=4", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB2 cn ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN", "displayName": "MN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=1", "source": "XMN nb nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCN", "displayName": "MCN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=1", "source": "XMCN cn cn zn vss sg13_lv_nmos w=11u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "zn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZN", "displayName": "MZN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=4u ng=1 m=1", "source": "XMZN zn cn vss vss sg13_lv_nmos w=3.2u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "zn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=1", "source": "XMN2 cp nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCP", "displayName": "MCP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=1", "source": "XMCP cp cp zp vdd sg13_lv_pmos w=22u l=500n ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "zp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZP", "displayName": "MZP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.7u l=1u ng=1 m=1", "source": "XMZP zp cp vdd vdd sg13_lv_pmos w=1.7u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "zp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=500n ng=8 m=1", "source": "XM1 f1 inp tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=500n ng=8 m=1", "source": "XM2 f2 inn tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=4", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=4", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=2", "source": "XM5 gp cn f1 vss sg13_lv_nmos w=11u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=2", "source": "XM6 out cn f2 vss sg13_lv_nmos w=11u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XM7 x1 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XM8 x2 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=2", "source": "XM9 gp cp x1 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=2", "source": "XM10 out cp x2 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMCP", "pin": "b" }, { "device": "XMZP", "pin": "s" }, { "device": "XMZP", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMN", "pin": "d" }, { "device": "XMN", "pin": "g" }, { "device": "XMN2", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cn", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XMCN", "pin": "d" }, { "device": "XMCN", "pin": "g" }, { "device": "XMZN", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMN", "pin": "s" }, { "device": "XMN", "pin": "b" }, { "device": "XMCN", "pin": "b" }, { "device": "XMZN", "pin": "s" }, { "device": "XMZN", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "zn", "ground": false, "terminals": [ { "device": "XMCN", "pin": "s" }, { "device": "XMZN", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cp", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XMCP", "pin": "d" }, { "device": "XMCP", "pin": "g" }, { "device": "XMZP", "pin": "g" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zp", "ground": false, "terminals": [ { "device": "XMCP", "pin": "s" }, { "device": "XMZP", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "gp", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM9", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/otafc" } }, { "id": "graph-5", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "otafc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib otafc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/otafc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cl out 0 2p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "pulse(450m 550m 50n 1n 1n 250n 1u)", "source": "Vin inp 0 pulse(450m 550m 50n 1n 1n 250n 1u)", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/otafc", "name": "otafc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=4", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB2 cn ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN", "displayName": "MN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=1", "source": "XMN nb nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCN", "displayName": "MCN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=1", "source": "XMCN cn cn zn vss sg13_lv_nmos w=11u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "zn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZN", "displayName": "MZN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=4u ng=1 m=1", "source": "XMZN zn cn vss vss sg13_lv_nmos w=3.2u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "zn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=1", "source": "XMN2 cp nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCP", "displayName": "MCP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=1", "source": "XMCP cp cp zp vdd sg13_lv_pmos w=22u l=500n ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "zp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZP", "displayName": "MZP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.7u l=1u ng=1 m=1", "source": "XMZP zp cp vdd vdd sg13_lv_pmos w=1.7u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "zp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=500n ng=8 m=1", "source": "XM1 f1 inp tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=500n ng=8 m=1", "source": "XM2 f2 inn tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=4", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=4", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=2", "source": "XM5 gp cn f1 vss sg13_lv_nmos w=11u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=2", "source": "XM6 out cn f2 vss sg13_lv_nmos w=11u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XM7 x1 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XM8 x2 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=2", "source": "XM9 gp cp x1 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=2", "source": "XM10 out cp x2 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMCP", "pin": "b" }, { "device": "XMZP", "pin": "s" }, { "device": "XMZP", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMN", "pin": "d" }, { "device": "XMN", "pin": "g" }, { "device": "XMN2", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cn", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XMCN", "pin": "d" }, { "device": "XMCN", "pin": "g" }, { "device": "XMZN", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMN", "pin": "s" }, { "device": "XMN", "pin": "b" }, { "device": "XMCN", "pin": "b" }, { "device": "XMZN", "pin": "s" }, { "device": "XMZN", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "zn", "ground": false, "terminals": [ { "device": "XMCN", "pin": "s" }, { "device": "XMZN", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cp", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XMCP", "pin": "d" }, { "device": "XMCP", "pin": "g" }, { "device": "XMZP", "pin": "g" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zp", "ground": false, "terminals": [ { "device": "XMCP", "pin": "s" }, { "device": "XMZP", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "gp", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM9", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/otafc" } }, { "id": "graph-6", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD} ac 1", "source": "Vdd vdd 0 dc {VDD} ac 1", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "otafc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib otafc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/otafc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cl out 0 2p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 500m", "source": "Vin inp 0 dc 500m", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/otafc", "name": "otafc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=4", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB2 cn ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN", "displayName": "MN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=1", "source": "XMN nb nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCN", "displayName": "MCN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=1", "source": "XMCN cn cn zn vss sg13_lv_nmos w=11u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "zn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZN", "displayName": "MZN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=4u ng=1 m=1", "source": "XMZN zn cn vss vss sg13_lv_nmos w=3.2u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "zn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=1", "source": "XMN2 cp nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCP", "displayName": "MCP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=1", "source": "XMCP cp cp zp vdd sg13_lv_pmos w=22u l=500n ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "zp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZP", "displayName": "MZP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.7u l=1u ng=1 m=1", "source": "XMZP zp cp vdd vdd sg13_lv_pmos w=1.7u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "zp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=500n ng=8 m=1", "source": "XM1 f1 inp tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=500n ng=8 m=1", "source": "XM2 f2 inn tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=4", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=4", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=2", "source": "XM5 gp cn f1 vss sg13_lv_nmos w=11u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=2", "source": "XM6 out cn f2 vss sg13_lv_nmos w=11u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XM7 x1 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XM8 x2 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=2", "source": "XM9 gp cp x1 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=2", "source": "XM10 out cp x2 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMCP", "pin": "b" }, { "device": "XMZP", "pin": "s" }, { "device": "XMZP", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMN", "pin": "d" }, { "device": "XMN", "pin": "g" }, { "device": "XMN2", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cn", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XMCN", "pin": "d" }, { "device": "XMCN", "pin": "g" }, { "device": "XMZN", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMN", "pin": "s" }, { "device": "XMN", "pin": "b" }, { "device": "XMCN", "pin": "b" }, { "device": "XMZN", "pin": "s" }, { "device": "XMZN", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "zn", "ground": false, "terminals": [ { "device": "XMCN", "pin": "s" }, { "device": "XMZN", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cp", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XMCP", "pin": "d" }, { "device": "XMCP", "pin": "g" }, { "device": "XMZP", "pin": "g" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zp", "ground": false, "terminals": [ { "device": "XMCP", "pin": "s" }, { "device": "XMZP", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "gp", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM9", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/otafc" } }, { "id": "graph-7", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "otafc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib otafc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/otafc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cl out 0 2p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vsrc", "displayName": "Vsrc", "spiceType": "V", "model": null, "parametersOrValue": "dc 500m", "source": "Vsrc src 0 dc 500m", "pins": [ { "id": "p", "net": "src" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Va", "displayName": "Va", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Va inp src dc 0 ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "src" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vb", "displayName": "Vb", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Vb inn out dc 0 ac 1", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vsrc", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Va", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "src", "ground": false, "terminals": [ { "device": "Vsrc", "pin": "p" }, { "device": "Va", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/otafc", "name": "otafc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=4", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB2 cn ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN", "displayName": "MN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=1", "source": "XMN nb nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCN", "displayName": "MCN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=1", "source": "XMCN cn cn zn vss sg13_lv_nmos w=11u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "zn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZN", "displayName": "MZN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=4u ng=1 m=1", "source": "XMZN zn cn vss vss sg13_lv_nmos w=3.2u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "zn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=1", "source": "XMN2 cp nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCP", "displayName": "MCP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=1", "source": "XMCP cp cp zp vdd sg13_lv_pmos w=22u l=500n ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "zp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZP", "displayName": "MZP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.7u l=1u ng=1 m=1", "source": "XMZP zp cp vdd vdd sg13_lv_pmos w=1.7u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "zp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=500n ng=8 m=1", "source": "XM1 f1 inp tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=500n ng=8 m=1", "source": "XM2 f2 inn tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=4", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=4", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=2", "source": "XM5 gp cn f1 vss sg13_lv_nmos w=11u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=2", "source": "XM6 out cn f2 vss sg13_lv_nmos w=11u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XM7 x1 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XM8 x2 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=2", "source": "XM9 gp cp x1 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=2", "source": "XM10 out cp x2 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMCP", "pin": "b" }, { "device": "XMZP", "pin": "s" }, { "device": "XMZP", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMN", "pin": "d" }, { "device": "XMN", "pin": "g" }, { "device": "XMN2", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cn", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XMCN", "pin": "d" }, { "device": "XMCN", "pin": "g" }, { "device": "XMZN", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMN", "pin": "s" }, { "device": "XMN", "pin": "b" }, { "device": "XMCN", "pin": "b" }, { "device": "XMZN", "pin": "s" }, { "device": "XMZN", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "zn", "ground": false, "terminals": [ { "device": "XMCN", "pin": "s" }, { "device": "XMZN", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cp", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XMCP", "pin": "d" }, { "device": "XMCP", "pin": "g" }, { "device": "XMZP", "pin": "g" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zp", "ground": false, "terminals": [ { "device": "XMCP", "pin": "s" }, { "device": "XMZP", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "gp", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM9", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/otafc" } }, { "id": "graph-8", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "otafc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib otafc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/otafc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cl out 0 2p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 500m ac 1", "source": "Vin inp 0 dc 500m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/otafc", "name": "otafc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=4", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB2 cn ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN", "displayName": "MN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=1", "source": "XMN nb nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCN", "displayName": "MCN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=1", "source": "XMCN cn cn zn vss sg13_lv_nmos w=11u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "zn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZN", "displayName": "MZN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=4u ng=1 m=1", "source": "XMZN zn cn vss vss sg13_lv_nmos w=3.2u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "zn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=1", "source": "XMN2 cp nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCP", "displayName": "MCP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=1", "source": "XMCP cp cp zp vdd sg13_lv_pmos w=22u l=500n ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "zp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZP", "displayName": "MZP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.7u l=1u ng=1 m=1", "source": "XMZP zp cp vdd vdd sg13_lv_pmos w=1.7u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "zp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=500n ng=8 m=1", "source": "XM1 f1 inp tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=500n ng=8 m=1", "source": "XM2 f2 inn tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=4", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=4", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=2", "source": "XM5 gp cn f1 vss sg13_lv_nmos w=11u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=2", "source": "XM6 out cn f2 vss sg13_lv_nmos w=11u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XM7 x1 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XM8 x2 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=2", "source": "XM9 gp cp x1 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=2", "source": "XM10 out cp x2 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMCP", "pin": "b" }, { "device": "XMZP", "pin": "s" }, { "device": "XMZP", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMN", "pin": "d" }, { "device": "XMN", "pin": "g" }, { "device": "XMN2", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cn", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XMCN", "pin": "d" }, { "device": "XMCN", "pin": "g" }, { "device": "XMZN", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMN", "pin": "s" }, { "device": "XMN", "pin": "b" }, { "device": "XMCN", "pin": "b" }, { "device": "XMZN", "pin": "s" }, { "device": "XMZN", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "zn", "ground": false, "terminals": [ { "device": "XMCN", "pin": "s" }, { "device": "XMZN", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cp", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XMCP", "pin": "d" }, { "device": "XMCP", "pin": "g" }, { "device": "XMZP", "pin": "g" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zp", "ground": false, "terminals": [ { "device": "XMCP", "pin": "s" }, { "device": "XMZP", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "gp", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM9", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/otafc" } }, { "id": "graph-9", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "otafc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib otafc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/otafc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cl out 0 2p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 500m ac 1", "source": "Vin inp 0 dc 500m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vpark", "displayName": "Vpark", "spiceType": "V", "model": null, "parametersOrValue": "dc 500m", "source": "Vpark park 0 dc 500m", "pins": [ { "id": "p", "net": "park" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efb", "displayName": "Efb", "spiceType": "E", "model": null, "parametersOrValue": "1", "source": "Efb fb inp out park 1", "pins": [ { "id": "p", "net": "fb" }, { "id": "n", "net": "inp" }, { "id": "cp", "net": "out" }, { "id": "cn", "net": "park" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfb", "displayName": "Lfb", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfb fb inn 1t", "pins": [ { "id": "p", "net": "fb" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cfb", "displayName": "Cfb", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cfb inn 0 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" }, { "device": "Vpark", "pin": "n" }, { "device": "Cfb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" }, { "device": "Efb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Lfb", "pin": "n" }, { "device": "Cfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Efb", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "park", "ground": false, "terminals": [ { "device": "Vpark", "pin": "p" }, { "device": "Efb", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "fb", "ground": false, "terminals": [ { "device": "Efb", "pin": "p" }, { "device": "Lfb", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/otafc", "name": "otafc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=4", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB2 cn ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN", "displayName": "MN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=1", "source": "XMN nb nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCN", "displayName": "MCN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=1", "source": "XMCN cn cn zn vss sg13_lv_nmos w=11u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "zn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZN", "displayName": "MZN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=4u ng=1 m=1", "source": "XMZN zn cn vss vss sg13_lv_nmos w=3.2u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "zn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=1", "source": "XMN2 cp nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCP", "displayName": "MCP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=1", "source": "XMCP cp cp zp vdd sg13_lv_pmos w=22u l=500n ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "zp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZP", "displayName": "MZP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.7u l=1u ng=1 m=1", "source": "XMZP zp cp vdd vdd sg13_lv_pmos w=1.7u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "zp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=500n ng=8 m=1", "source": "XM1 f1 inp tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=500n ng=8 m=1", "source": "XM2 f2 inn tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=4", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=4", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=2", "source": "XM5 gp cn f1 vss sg13_lv_nmos w=11u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=2", "source": "XM6 out cn f2 vss sg13_lv_nmos w=11u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XM7 x1 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XM8 x2 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=2", "source": "XM9 gp cp x1 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=2", "source": "XM10 out cp x2 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMCP", "pin": "b" }, { "device": "XMZP", "pin": "s" }, { "device": "XMZP", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMN", "pin": "d" }, { "device": "XMN", "pin": "g" }, { "device": "XMN2", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cn", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XMCN", "pin": "d" }, { "device": "XMCN", "pin": "g" }, { "device": "XMZN", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMN", "pin": "s" }, { "device": "XMN", "pin": "b" }, { "device": "XMCN", "pin": "b" }, { "device": "XMZN", "pin": "s" }, { "device": "XMZN", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "zn", "ground": false, "terminals": [ { "device": "XMCN", "pin": "s" }, { "device": "XMZN", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cp", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XMCP", "pin": "d" }, { "device": "XMCP", "pin": "g" }, { "device": "XMZP", "pin": "g" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zp", "ground": false, "terminals": [ { "device": "XMCP", "pin": "s" }, { "device": "XMZP", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "gp", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM9", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/otafc" } }, { "id": "graph-10", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "10u", "source": "Ib ib 0 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "otafc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib otafc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/otafc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cl out 0 2p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vcm", "displayName": "Vcm", "spiceType": "V", "model": null, "parametersOrValue": "dc 500m ac 1", "source": "Vcm inp 0 dc 500m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vsig", "displayName": "Vsig", "spiceType": "V", "model": null, "parametersOrValue": "dc 500m", "source": "Vsig sig 0 dc 500m", "pins": [ { "id": "p", "net": "sig" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "E1", "displayName": "E1", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "E1 fbn mid out 0 0.5", "pins": [ { "id": "p", "net": "fbn" }, { "id": "n", "net": "mid" }, { "id": "cp", "net": "out" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "E2", "displayName": "E2", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "E2 mid 0 sig 0 0.5", "pins": [ { "id": "p", "net": "mid" }, { "id": "n", "net": "0" }, { "id": "cp", "net": "sig" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfb", "displayName": "Lfb", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfb fbn inn 1t", "pins": [ { "id": "p", "net": "fbn" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cfb", "displayName": "Cfb", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cfb inn 0 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vcm", "pin": "n" }, { "device": "Vsig", "pin": "n" }, { "device": "E1", "pin": "cn" }, { "device": "E2", "pin": "n" }, { "device": "E2", "pin": "cn" }, { "device": "Cfb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vcm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Lfb", "pin": "n" }, { "device": "Cfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "E1", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "sig", "ground": false, "terminals": [ { "device": "Vsig", "pin": "p" }, { "device": "E2", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "fbn", "ground": false, "terminals": [ { "device": "E1", "pin": "p" }, { "device": "Lfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "mid", "ground": false, "terminals": [ { "device": "E1", "pin": "n" }, { "device": "E2", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/otafc", "name": "otafc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=4", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB1", "displayName": "MB1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB1 nb ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMB2", "displayName": "MB2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=12u l=1u ng=4 m=1", "source": "XMB2 cn ib vdd vdd sg13_lv_pmos w=12u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN", "displayName": "MN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=1", "source": "XMN nb nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "nb" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCN", "displayName": "MCN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=1", "source": "XMCN cn cn zn vss sg13_lv_nmos w=11u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "zn" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZN", "displayName": "MZN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=4u ng=1 m=1", "source": "XMZN zn cn vss vss sg13_lv_nmos w=3.2u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "zn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=1", "source": "XMN2 cp nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCP", "displayName": "MCP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=1", "source": "XMCP cp cp zp vdd sg13_lv_pmos w=22u l=500n ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "zp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZP", "displayName": "MZP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.7u l=1u ng=1 m=1", "source": "XMZP zp cp vdd vdd sg13_lv_pmos w=1.7u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "zp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=500n ng=8 m=1", "source": "XM1 f1 inp tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=40u l=500n ng=8 m=1", "source": "XM2 f2 inn tail tail sg13_lv_pmos w=40u l=500n ng=8 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=4", "source": "XM3 f1 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=22u l=4u ng=6 m=4", "source": "XM4 f2 nb vss vss sg13_lv_nmos w=22u l=4u ng=6 m=4", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "nb" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=2", "source": "XM5 gp cn f1 vss sg13_lv_nmos w=11u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=11u l=1u ng=4 m=2", "source": "XM6 out cn f2 vss sg13_lv_nmos w=11u l=1u ng=4 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XM7 x1 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=1u ng=2 m=1", "source": "XM8 x2 gp vdd vdd sg13_lv_pmos w=10u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=2", "source": "XM9 gp cp x1 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=22u l=500n ng=6 m=2", "source": "XM10 out cp x2 vdd sg13_lv_pmos w=22u l=500n ng=6 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMB1", "pin": "g" }, { "device": "XMB2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMB1", "pin": "s" }, { "device": "XMB1", "pin": "b" }, { "device": "XMB2", "pin": "s" }, { "device": "XMB2", "pin": "b" }, { "device": "XMCP", "pin": "b" }, { "device": "XMZP", "pin": "s" }, { "device": "XMZP", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "nb", "ground": false, "terminals": [ { "device": "XMB1", "pin": "d" }, { "device": "XMN", "pin": "d" }, { "device": "XMN", "pin": "g" }, { "device": "XMN2", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "cn", "ground": false, "terminals": [ { "device": "XMB2", "pin": "d" }, { "device": "XMCN", "pin": "d" }, { "device": "XMCN", "pin": "g" }, { "device": "XMZN", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMN", "pin": "s" }, { "device": "XMN", "pin": "b" }, { "device": "XMCN", "pin": "b" }, { "device": "XMZN", "pin": "s" }, { "device": "XMZN", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "zn", "ground": false, "terminals": [ { "device": "XMCN", "pin": "s" }, { "device": "XMZN", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cp", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XMCP", "pin": "d" }, { "device": "XMCP", "pin": "g" }, { "device": "XMZP", "pin": "g" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zp", "ground": false, "terminals": [ { "device": "XMCP", "pin": "s" }, { "device": "XMZP", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "gp", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM9", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM10", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM7", "pin": "d" }, { "device": "XM9", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "x2", "ground": false, "terminals": [ { "device": "XM8", "pin": "d" }, { "device": "XM10", "pin": "s" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/otafc" } } ], "views": [ { "bench": "op", "source": { "recordField": "testbenches", "id": "op", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota-folded-cascode/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Folded-cascode OTA", "instances": [] } ] }, "benchDiagram": { "graph": "graph-2", "svg": { "url": "/circuits/ota-folded-cascode/op-bench.svg", "asset": "op-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota-folded-cascode/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "open_loop", "source": { "recordField": "testbenches", "id": "open_loop", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota-folded-cascode/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Folded-cascode OTA", "instances": [] } ] }, "benchDiagram": { "graph": "graph-4", "svg": { "url": "/circuits/ota-folded-cascode/open_loop-bench.svg", "asset": "open_loop-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota-folded-cascode/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "step", "source": { "recordField": "testbenches", "id": "step", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota-folded-cascode/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Folded-cascode OTA", "instances": [] } ] }, "benchDiagram": { "graph": "graph-5", "svg": { "url": "/circuits/ota-folded-cascode/step-bench.svg", "asset": "step-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota-folded-cascode/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "psrr", "source": { "recordField": "testbenches", "id": "psrr", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota-folded-cascode/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Folded-cascode OTA", "instances": [] } ] }, "benchDiagram": { "graph": "graph-6", "svg": { "url": "/circuits/ota-folded-cascode/psrr-bench.svg", "asset": "psrr-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota-folded-cascode/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "cmrr", "source": { "recordField": "testbenches", "id": "cmrr", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota-folded-cascode/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Folded-cascode OTA", "instances": [] } ] }, "benchDiagram": { "graph": "graph-7", "svg": { "url": "/circuits/ota-folded-cascode/cmrr-bench.svg", "asset": "cmrr-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota-folded-cascode/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "noise", "source": { "recordField": "testbenches", "id": "noise", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota-folded-cascode/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Folded-cascode OTA", "instances": [] } ] }, "benchDiagram": { "graph": "graph-8", "svg": { "url": "/circuits/ota-folded-cascode/noise-bench.svg", "asset": "noise-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota-folded-cascode/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "icmr", "source": { "recordField": "testbenches", "id": "icmr", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota-folded-cascode/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Folded-cascode OTA", "instances": [] } ] }, "benchDiagram": { "graph": "graph-9", "svg": { "url": "/circuits/ota-folded-cascode/icmr-bench.svg", "asset": "icmr-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota-folded-cascode/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "swing", "source": { "recordField": "testbenches", "id": "swing", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota-folded-cascode/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Folded-cascode OTA", "instances": [] } ] }, "benchDiagram": { "graph": "graph-10", "svg": { "url": "/circuits/ota-folded-cascode/swing-bench.svg", "asset": "swing-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota-folded-cascode/op-block.svg", "asset": "op-block.svg" } } } ] } }