{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ota-telescopic", "name": "Telescopic-cascode OTA", "group": "Op amps and OTAs", "subgroup": "Single-stage OTAs", "title": "Telescopic-cascode OTA", "summary": "This amplifier stacks transistors to obtain more gain from the same signal current. The output sees a large resistance, so even a small current change creates a useful voltage change. The stack saves power but leaves a narrow input and output voltage range.", "reference": { "kind": "book", "authors": "B. Razavi", "title": "Design of Analog CMOS Integrated Circuits", "year": 2016, "where": "Sec. 11.5.1 'Telescopic Op Amp' (p. 473); the topology is introduced in Ch. 9 'Operational Amplifiers', Sec. 9.2 'One-Stage Op Amps'", "publisher": "McGraw-Hill", "edition": "2nd", "takes": "The topology - an NMOS pair with NMOS cascodes under a cascoded PMOS mirror whose gates hang on its cascode's drain - and the headroom analysis of a telescopic stage in unity-gain feedback. The on-chip cascode biases, the one that stands on the tail node, the sizing and the spec targets are this library's." }, "resources": { "record": "/circuits/ota-telescopic.json", "page": "/index.html#ota-telescopic", "achieved": "/achieved/ota-telescopic.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice" ], "ports": [ { "name": "inp", "kind": "input" }, { "name": "inn", "kind": "input" }, { "name": "out", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the reference current, fed into this pin" } ], "devices": [ { "name": "MB", "type": "nmos", "nodes": "ib ib vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "bias reference, diode-connected", "fingers": 6, "copies": 1 }, { "name": "MT", "type": "nmos", "nodes": "tail ib vss vss", "sizedBy": [ "Wn", "Ln", "C" ], "role": "tail current source, 2C + 1 copies of MB", "fingers": 6, "copies": 5 }, { "name": "MN1", "type": "nmos", "nodes": "pb ib vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "copies the reference into MP", "fingers": 6, "copies": 1 }, { "name": "MP", "type": "pmos", "nodes": "pb pb vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "PMOS reference, diode-connected", "fingers": 2, "copies": 1 }, { "name": "MPC", "type": "pmos", "nodes": "cn pb vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "feeds the NMOS cascode-bias stack", "fingers": 2, "copies": 1 }, { "name": "MCN", "type": "nmos", "nodes": "cn cn zc vss", "sizedBy": [ "Wc", "Lc" ], "role": "one NMOS cascode unit as a diode: sets the cascode gate cn", "fingers": 4, "copies": 1 }, { "name": "MZC", "type": "nmos", "nodes": "zc cn tail vss", "sizedBy": [ "Wzc", "L1" ], "role": "narrow device under MCN on the tail node: the drop across it is the input pair's drain voltage", "fingers": 1, "copies": 1 }, { "name": "MN2", "type": "nmos", "nodes": "cp ib vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "draws the reference through the PMOS cascode-bias stack", "fingers": 6, "copies": 1 }, { "name": "MCP", "type": "pmos", "nodes": "cp cp zp vdd", "sizedBy": [ "Wpc", "Lpc" ], "role": "one PMOS cascode unit as a diode: sets the cascode gate cp", "fingers": 2, "copies": 1 }, { "name": "MZP", "type": "pmos", "nodes": "zp cp vdd vdd", "sizedBy": [ "Wzp", "Lm" ], "role": "in triode under vdd: its drop is the PMOS mirror's headroom", "fingers": 1, "copies": 1 }, { "name": "M1", "type": "nmos", "nodes": "d1 inp tail vss", "sizedBy": [ "W1", "L1" ], "role": "input pair, non-inverting input", "fingers": 1, "copies": 1 }, { "name": "M2", "type": "nmos", "nodes": "d2 inn tail vss", "sizedBy": [ "W1", "L1" ], "role": "input pair, inverting input", "fingers": 1, "copies": 1 }, { "name": "M3", "type": "nmos", "nodes": "gp cn d1 vss", "sizedBy": [ "Wc", "Lc", "C" ], "role": "NMOS cascode, mirror side; C units", "fingers": 4, "copies": 2 }, { "name": "M4", "type": "nmos", "nodes": "out cn d2 vss", "sizedBy": [ "Wc", "Lc", "C" ], "role": "NMOS cascode, output side; C units", "fingers": 4, "copies": 2 }, { "name": "M5", "type": "pmos", "nodes": "gp cp x1 vdd", "sizedBy": [ "Wpc", "Lpc", "C" ], "role": "PMOS cascode, mirror side; its drain is the mirror's gate line", "fingers": 2, "copies": 2 }, { "name": "M6", "type": "pmos", "nodes": "out cp x2 vdd", "sizedBy": [ "Wpc", "Lpc", "C" ], "role": "PMOS cascode, output side", "fingers": 2, "copies": 2 }, { "name": "M7", "type": "pmos", "nodes": "x1 gp vdd vdd", "sizedBy": [ "Wm", "Lm" ], "role": "PMOS mirror, input side", "fingers": 4, "copies": 1 }, { "name": "M8", "type": "pmos", "nodes": "x2 gp vdd vdd", "sizedBy": [ "Wm", "Lm" ], "role": "PMOS mirror, output side", "fingers": 4, "copies": 1 } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "The input pair: any difference is input offset. At 1.2 × 0.5 µm each the pair is small - the headroom rule below makes it so - and its mismatch gives an offset near 8 mV σ." }, { "rule": "match", "of": [ "M3", "M4" ], "why": "The NMOS cascodes: they share cn, and a difference in their V_GS moves the pair's drains apart, a systematic offset." }, { "rule": "unit-copies", "of": [ "MB", "MT", "MN1", "MN2" ], "constraint": "MT = 2C + 1 copies of MB", "why": "The tail feeds the pair, C Ib a side, and one Ib more for the NMOS cascode-bias stack that stands on it: all copies of one reference unit." }, { "rule": "buffer-headroom", "of": [ "M1", "M2", "M3", "M4" ], "constraint": "V_GS1 ≥ V_DSAT1 + V_DSAT4 + margins, at 125 °C", "why": "As a unity-gain buffer the output sits at the input, so the input device and its cascode share exactly one V_GS1. Hot, V_GS1 falls with the threshold and both V_DSAT grow, so the pair is made short (0.5 µm, for a higher threshold) and strongly inverted, and the cascodes weakly inverted: a pair in moderate inversion left M4 in triode at 125 °C." }, { "rule": "cascode-bias", "of": [ "MCN", "MZC", "M3", "M4", "MT" ], "constraint": "MCN = one cascode unit; MZC stands on the tail node", "why": "cn is a cascode unit's V_GS above the drop across MZC, and MZC's source is the tail: when the input common mode moves, the pair's drains move with it and keep their voltage, so the input range is limited by the tail and the mirror, not by a fixed cascode gate." }, { "rule": "cascode-bias", "of": [ "MCP", "MZP", "M5", "M6", "M7", "M8" ], "constraint": "V_DSAT7 ≤ V_SD,MZP ≤ V_SG7 − V_DSAT5", "why": "The mirror's gates hang on M5's drain, so M7 and M5 are both saturated only while MZP's drop sits in this window; it narrows hot, and MZP is sized for the middle of it there." }, { "rule": "headroom", "of": [ "out" ], "constraint": "one common mode serves every corner: 0.66 V", "why": "The tail wants the input high, the mirror side's cascode M3 wants the tail node low, under V_DD − V_SG7 less the pair's and M3's drops. At 27 °C there is room from about 0.56 V to 0.8 V; at the slow, hot corner with the supply 10 % low it has all but closed - at 0.66 V the tail keeps 1 mV of saturation margin and M3 10 mV. That corner is the telescopic stage's limit as a buffer at 1.08 V." } ], "specs": [ { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.00005 A", "min": null, "max": 0.00005, "why": "About 19 µA in the pair, 6 µA through the NMOS cascode-bias stack and 17 µA in the reference and its two copies for the bias: 42 µA, all from the 5 µA reference, held at every corner." }, { "key": "dc_gain_db", "label": "DC open-loop gain", "unit": "dB", "direction": "max", "constraint": ">= 45 dB", "min": 45, "max": null, "why": "g_m1 times the NMOS side's resistance, g_m4 r_o4 r_o2: the short, strongly inverted pair the headroom demands has g_m/g_ds near 15, so about 52 dB, 47 dB hot." }, { "key": "ugf_hz", "label": "Unity-gain frequency", "unit": "Hz", "direction": "max", "constraint": ">= 5000000 Hz", "min": 5000000, "max": null, "why": "g_m1/(2π C_L) with 2 pF: 7.5 MHz at 27 °C, 5.8 MHz slow and hot, where the pair's g_m/I_D falls." }, { "key": "pm_deg", "label": "Phase margin", "unit": "deg", "direction": "max", "constraint": ">= 75 deg", "min": 75, "max": null, "why": "One high-impedance node; the cascodes' sources and the mirror's gate line are low-impedance: 84° at every corner." }, { "key": "t_settle", "label": "Settling time, 1 %", "unit": "s", "direction": "min", "constraint": "<= 1.5e-7 s", "min": null, "max": 1.5e-7, "why": "A 0.1 V step - the most the buffer's window holds at the slow, hot corner - settles on the single pole in 72 to 113 ns." }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 40 dB", "min": 40, "max": null, "why": "The PMOS mirror and its cascode bias are referred to V_DD; the ripple reaches the output through their finite resistance." }, { "key": "cmrr_db", "label": "Common-mode rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 55 dB", "min": 55, "max": null, "why": "The tail's output resistance and the pair's match: 58.6 dB at the slow, hot, low corner, 63 dB or more in every mismatch draw." }, { "key": "icmr_lo", "label": "Lowest input common mode", "unit": "V", "direction": "min", "constraint": "<= 0.65 V", "min": null, "max": 0.65, "why": "The tail needs V_GS1 + V_DSAT,T under the input: about 0.56 V, 0.6 V at the slow corners." }, { "key": "icmr_hi", "label": "Highest input common mode", "unit": "V", "direction": "max", "constraint": ">= 0.7 V", "min": 0.7, "max": null, "why": "Above, the NMOS cascodes, riding on the tail node, push the pair's drains into the mirror side's headroom: 0.82 V at 27 °C, 0.72 V hot." }, { "key": "swing_lo", "label": "Lowest output", "unit": "V", "direction": "min", "constraint": "<= 0.65 V", "min": null, "max": 0.65, "why": "With the input at 0.66 V the output must stay a V_GS1 minus MZC's drop, plus M4's V_DSAT, above the tail node: 0.53 V at 27 °C, 0.60 V hot." }, { "key": "swing_hi", "label": "Highest output", "unit": "V", "direction": "max", "constraint": ">= 0.72 V", "min": 0.72, "max": null, "why": "V_DD less MZP's drop and M6's V_DSAT: 0.90 V at 27 °C, 0.75 V slow, hot and 10 % low." } ], "explanation": { "idea": "This amplifier stacks transistors to obtain more gain from the same signal current. The output sees a large resistance, so even a small current change creates a useful voltage change. The stack saves power but leaves a narrow input and output voltage range.", "detail": "A single-stage OTA that cascodes both the pair and the mirror of the five-transistor OTA in one stack, multiplying the output resistance - and so the gain - by g_m·r_o on each side without spending any extra current. The price is headroom: tail, input device, NMOS cascode, PMOS cascode and mirror stand in series between the rails. At 1.2 V the output keeps every device saturated only between about 0.53 V and 0.90 V, and as a unity-gain buffer, with the output at the input, the input device and its cascode must share one V_GS. The cascode gates are generated on chip: the NMOS one stands on the tail node so it follows the input.", "lesson": { "relation": 1, "symbols": "f_u (also called GBW here) is unity-gain frequency in Hz; g_m1 is one input transistor's small-signal transconductance in S; C_L is load capacitance in F. Where angular frequency is used, ω_u = 2π f_u.", "assumptions": "Small signals, saturated devices and an output-dominated response. The simple relation neglects device capacitance and higher-frequency internal poles.", "exercise": { "param": "CL", "value": 4e-12, "analysis": "open_loop", "expect": "Doubling the load capacitance should reduce unity-gain frequency, roughly by half if the load dominates. Compare phase margin and DC gain rather than expecting every metric to halve." }, "limits": "Provide the bias current and keep input common mode and output swing inside their separate measured ranges. This is not a rail-to-rail input/output guarantee." }, "path": [ { "part": "Input pair", "devices": "M1, M2, MT", "does": "MT's current, less the Ib its bias stack takes, divides between M1 and M2 by inp − inn. inp drives M1, under the mirror's diode side, so out follows inp." }, { "part": "NMOS cascodes", "devices": "M3, M4", "does": "Common-gate at cn: they pass the pair's current changes up unchanged and hold the pair's drains d1 and d2 almost still, multiplying the NMOS side's resistance by g_m4 r_o4." }, { "part": "Cascode mirror", "devices": "M5, M6, M7, M8", "does": "M7 and M8 take their gates from gp, M5's drain, so M1's current is copied through M6 onto out, where M4 draws M2's." }, { "part": "Cascode bias", "devices": "MCN, MZC, MCP, MZP", "does": "cn is a cascode unit's V_GS (MCN) above the drop across MZC, whose source is the tail node, so the pair's drains ride with the input; cp is a PMOS cascode unit's V_SG (MCP) below the drop across MZP, in triode under vdd." } ], "bias": "The testbench feeds the 5 µA reference into the diode MB. MT, five copies of it, carries 25 µA: about 6 µA through the bias stack MCN–MZC, which MPC feeds from the PMOS reference MP, and 9.4 µA to each input device. MN1 and MN2 run about a fifth above Ib, their drains far above MB's. The pair is short (0.5 µm) and strongly inverted so its V_GS, about 0.47 V, has room for its own V_DSAT and its cascode's; the cascodes, tail and mirror run near weak inversion, where their V_DSAT is smallest. 42 µA in all.", "relations": [ { "what": "DC gain", "expr": "A_0 ≈ g_m1 · [(g_m4 r_o4 r_o2) ∥ (g_m6 r_o6 r_o8)]", "note": "The NMOS side is the smaller, about 4 MΩ against 24 MΩ: the short input device has g_m/g_ds near 15. About 52 dB." }, { "what": "Unity-gain frequency", "expr": "f_u ≈ g_m1/(2π C_L)", "note": "0.1 mS into 2 pF: 7.5 MHz." }, { "what": "Buffer headroom", "expr": "V_DS1 + V_DS4 = V_GS1 ≥ V_DSAT1 + V_DSAT4", "note": "With the output at the input, the pair and its cascode share one V_GS. Hot the threshold falls 70 mV while both V_DSAT grow, which is why the pair is short and strongly inverted." }, { "what": "Output swing", "expr": "V_tail + V_DS1 + V_DSAT4 ≤ v_out ≤ V_DD − V_SD,MZP − V_DSAT6", "note": "With the input at 0.66 V: 0.53 V to 0.90 V at 27 °C, 0.57 V to 0.75 V slow, hot and 10 % low - under 0.2 V." }, { "what": "Mirror-side headroom", "expr": "V_tail + V_DS1 + V_DSAT3 ≤ V_DD − V_SG7", "note": "M3's drain is the mirror's gate line gp. With the tail's own V_DSAT under it this sets the stack: the one common mode that serves every corner is about 0.66 V." }, { "what": "Slew rate", "expr": "SR = I_pair/C_L", "note": "The pair's 19 µA into 2 pF is about 9 V/µs; the 0.1 V step barely steers the pair and reads 2 V/µs." } ], "tradeoffs": [ "The input pair's size is set by headroom, not by noise or matching: at 1.2 × 0.5 µm it gives about 930 nV/√Hz at 1 kHz and an offset near 8 mV σ. Longer, it would lose threshold; wider, V_GS - either takes M4 out of saturation hot.", "Longer NMOS cascodes raise g_m4 r_o4 and the gain at no headroom cost, since their gate comes from a unit of their own: 2 µm gives 51.6 dB against 49.6 dB at 1 µm.", "A wider MZC lowers the pair's drain voltage: more room for M4 and for M3 on the mirror side, less for the input devices.", "More current per branch (C) raises g_m1 and the bandwidth and lets the pair grow in area at the same inversion, at the cost of supply current; the bias stacks stay at one Ib." ] }, "sizing": [ { "key": "Ib", "label": "Reference current", "unit": "A", "value": 0.000005, "min": 0.000001, "max": 0.00005, "kind": "si" }, { "key": "C", "label": "Each branch's current, in Ib", "unit": "", "value": 2, "min": 1, "max": 8, "kind": "int" }, { "key": "W1", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.0000012, "min": 5e-7, "max": 0.00005, "kind": "si" }, { "key": "L1", "label": "L input pair, and MZC", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wn", "label": "W NMOS bias unit (MB, MT, MN1, MN2)", "unit": "m", "value": 0.00003, "min": 5e-7, "max": 0.00005, "kind": "si" }, { "key": "Ln", "label": "L NMOS bias unit", "unit": "m", "value": 0.000004, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Wp", "label": "W PMOS bias unit (MP, MPC)", "unit": "m", "value": 0.000006, "min": 5e-7, "max": 0.00005, "kind": "si" }, { "key": "Lp", "label": "L PMOS bias unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Wc", "label": "W NMOS cascode unit (MCN, M3, M4)", "unit": "m", "value": 0.000014, "min": 5e-7, "max": 0.00005, "kind": "si" }, { "key": "Lc", "label": "L NMOS cascode", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wzc", "label": "W NMOS triode device (MZC)", "unit": "m", "value": 5e-7, "min": 1.5e-7, "max": 0.00002, "kind": "si" }, { "key": "Wpc", "label": "W PMOS cascode unit (MCP, M5, M6)", "unit": "m", "value": 0.00001, "min": 5e-7, "max": 0.0001, "kind": "si" }, { "key": "Lpc", "label": "L PMOS cascode", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wm", "label": "W PMOS mirror (M7, M8)", "unit": "m", "value": 0.000014, "min": 0.000001, "max": 0.0001, "kind": "si" }, { "key": "Lm", "label": "L PMOS mirror, and MZP", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Wzp", "label": "W PMOS triode device (MZP)", "unit": "m", "value": 0.0000018, "min": 1.5e-7, "max": 0.00002, "kind": "si" }, { "key": "CL", "label": "Load capacitance", "unit": "F", "value": 2e-12, "min": 1e-13, "max": 2e-11, "kind": "si" }, { "key": "VCM", "label": "Input common mode", "unit": "V", "value": 0.66, "min": 0.3, "max": 1, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.", "measures": [], "metricKeys": [ "i_supply", "vout_dc", "vos" ], "acceptance": [ "i_supply" ], "acceptanceRules": [ { "key": "i_supply", "unit": "A", "min": null, "max": 0.00005, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Telescopic-cascode OTA - operating point as a unity-gain buffer\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb vdd ib 5u\n.subckt otatc inp inn out vdd vss ib\n* bias: the reference into an NMOS diode, and copies of it\nXMB ib ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMT tail ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=5\nXMN1 pb ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMP pb pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\n* the NMOS cascode gate: a cascode unit as a diode on a narrow device that\n* stands on the tail node, so it follows the input common mode\nXMPC cn pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\nXMCN cn cn zc vss sg13_lv_nmos w=14u l=2u ng=4 m=1\nXMZC zc cn tail vss sg13_lv_nmos w=500n l=500n ng=1 m=1\n* the PMOS cascode gate, the same way down from vdd\nXMN2 cp ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMCP cp cp zp vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXMZP zp cp vdd vdd sg13_lv_pmos w=1.8u l=1u ng=1 m=1\n* the NMOS pair; inp drives M1, under the mirror's diode side\nXM1 d1 inp tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1\nXM2 d2 inn tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1\n* the NMOS cascodes, C units each\nXM3 gp cn d1 vss sg13_lv_nmos w=14u l=2u ng=4 m=2\nXM4 out cn d2 vss sg13_lv_nmos w=14u l=2u ng=4 m=2\n* the PMOS cascodes, C units each, and the mirror under them: M7 and M8 take\n* their gates from gp, M5's drain\nXM5 gp cp x1 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2\nXM6 out cp x2 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2\nXM7 x1 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1\nXM8 x2 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1\n.ends\nXdut inp inn out vdd 0 ib otatc\nCl out 0 2p\nVin inp 0 dc 660m\n* the output drives the inverting input: a unity-gain buffer\nVfb inn out 0\n.op\n.end" }, { "id": "open_loop", "label": "Open-loop gain", "note": "Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.", "measures": [], "metricKeys": [ "dc_gain_db", "ugf_hz", "pm_deg", "gm_db" ], "acceptance": [ "dc_gain_db", "ugf_hz", "pm_deg" ], "acceptanceRules": [ { "key": "dc_gain_db", "unit": "dB", "min": 45, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "ugf_hz", "unit": "Hz", "min": 5000000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "pm_deg", "unit": "deg", "min": 75, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Telescopic-cascode OTA - open-loop gain and phase\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb vdd ib 5u\n.subckt otatc inp inn out vdd vss ib\n* bias: the reference into an NMOS diode, and copies of it\nXMB ib ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMT tail ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=5\nXMN1 pb ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMP pb pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\n* the NMOS cascode gate: a cascode unit as a diode on a narrow device that\n* stands on the tail node, so it follows the input common mode\nXMPC cn pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\nXMCN cn cn zc vss sg13_lv_nmos w=14u l=2u ng=4 m=1\nXMZC zc cn tail vss sg13_lv_nmos w=500n l=500n ng=1 m=1\n* the PMOS cascode gate, the same way down from vdd\nXMN2 cp ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMCP cp cp zp vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXMZP zp cp vdd vdd sg13_lv_pmos w=1.8u l=1u ng=1 m=1\n* the NMOS pair; inp drives M1, under the mirror's diode side\nXM1 d1 inp tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1\nXM2 d2 inn tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1\n* the NMOS cascodes, C units each\nXM3 gp cn d1 vss sg13_lv_nmos w=14u l=2u ng=4 m=2\nXM4 out cn d2 vss sg13_lv_nmos w=14u l=2u ng=4 m=2\n* the PMOS cascodes, C units each, and the mirror under them: M7 and M8 take\n* their gates from gp, M5's drain\nXM5 gp cp x1 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2\nXM6 out cp x2 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2\nXM7 x1 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1\nXM8 x2 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1\n.ends\nXdut inp inn out vdd 0 ib otatc\nCl out 0 2p\nVin inp 0 dc 660m ac 1\n* the loop closed at DC and open at every frequency the sweep visits\nLfb out inn 1t\nCfb inn 0 1t\n.ac dec 25 0.1 10g\n.end" }, { "id": "step", "label": "Step response", "note": "A 100mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.", "measures": [], "metricKeys": [ "sr", "t_settle", "overshoot_pct" ], "acceptance": [ "t_settle" ], "acceptanceRules": [ { "key": "t_settle", "unit": "s", "min": null, "max": 1.5e-7, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Telescopic-cascode OTA - step response of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb vdd ib 5u\n.subckt otatc inp inn out vdd vss ib\n* bias: the reference into an NMOS diode, and copies of it\nXMB ib ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMT tail ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=5\nXMN1 pb ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMP pb pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\n* the NMOS cascode gate: a cascode unit as a diode on a narrow device that\n* stands on the tail node, so it follows the input common mode\nXMPC cn pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\nXMCN cn cn zc vss sg13_lv_nmos w=14u l=2u ng=4 m=1\nXMZC zc cn tail vss sg13_lv_nmos w=500n l=500n ng=1 m=1\n* the PMOS cascode gate, the same way down from vdd\nXMN2 cp ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMCP cp cp zp vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXMZP zp cp vdd vdd sg13_lv_pmos w=1.8u l=1u ng=1 m=1\n* the NMOS pair; inp drives M1, under the mirror's diode side\nXM1 d1 inp tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1\nXM2 d2 inn tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1\n* the NMOS cascodes, C units each\nXM3 gp cn d1 vss sg13_lv_nmos w=14u l=2u ng=4 m=2\nXM4 out cn d2 vss sg13_lv_nmos w=14u l=2u ng=4 m=2\n* the PMOS cascodes, C units each, and the mirror under them: M7 and M8 take\n* their gates from gp, M5's drain\nXM5 gp cp x1 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2\nXM6 out cp x2 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2\nXM7 x1 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1\nXM8 x2 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1\n.ends\nXdut inp inn out vdd 0 ib otatc\nCl out 0 2p\nVin inp 0 pulse(610m 710m 50n 1n 1n 250n 1u)\nVfb inn out 0\n.tran 125p 500n\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.", "measures": [], "metricKeys": [ "psrr_db" ], "acceptance": [ "psrr_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 40, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Telescopic-cascode OTA - supply rejection of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD} ac 1\nIb vdd ib 5u\n.subckt otatc inp inn out vdd vss ib\n* bias: the reference into an NMOS diode, and copies of it\nXMB ib ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMT tail ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=5\nXMN1 pb ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMP pb pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\n* the NMOS cascode gate: a cascode unit as a diode on a narrow device that\n* stands on the tail node, so it follows the input common mode\nXMPC cn pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\nXMCN cn cn zc vss sg13_lv_nmos w=14u l=2u ng=4 m=1\nXMZC zc cn tail vss sg13_lv_nmos w=500n l=500n ng=1 m=1\n* the PMOS cascode gate, the same way down from vdd\nXMN2 cp ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMCP cp cp zp vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXMZP zp cp vdd vdd sg13_lv_pmos w=1.8u l=1u ng=1 m=1\n* the NMOS pair; inp drives M1, under the mirror's diode side\nXM1 d1 inp tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1\nXM2 d2 inn tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1\n* the NMOS cascodes, C units each\nXM3 gp cn d1 vss sg13_lv_nmos w=14u l=2u ng=4 m=2\nXM4 out cn d2 vss sg13_lv_nmos w=14u l=2u ng=4 m=2\n* the PMOS cascodes, C units each, and the mirror under them: M7 and M8 take\n* their gates from gp, M5's drain\nXM5 gp cp x1 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2\nXM6 out cp x2 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2\nXM7 x1 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1\nXM8 x2 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1\n.ends\nXdut inp inn out vdd 0 ib otatc\nCl out 0 2p\nVin inp 0 dc 660m\nVfb inn out 0\n.ac dec 25 1 100meg\n.end" }, { "id": "cmrr", "label": "Common-mode rejection", "note": "Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.", "measures": [], "metricKeys": [ "cmrr_db" ], "acceptance": [ "cmrr_db" ], "acceptanceRules": [ { "key": "cmrr_db", "unit": "dB", "min": 55, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Telescopic-cascode OTA - common-mode rejection\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb vdd ib 5u\n.subckt otatc inp inn out vdd vss ib\n* bias: the reference into an NMOS diode, and copies of it\nXMB ib ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMT tail ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=5\nXMN1 pb ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMP pb pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\n* the NMOS cascode gate: a cascode unit as a diode on a narrow device that\n* stands on the tail node, so it follows the input common mode\nXMPC cn pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\nXMCN cn cn zc vss sg13_lv_nmos w=14u l=2u ng=4 m=1\nXMZC zc cn tail vss sg13_lv_nmos w=500n l=500n ng=1 m=1\n* the PMOS cascode gate, the same way down from vdd\nXMN2 cp ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMCP cp cp zp vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXMZP zp cp vdd vdd sg13_lv_pmos w=1.8u l=1u ng=1 m=1\n* the NMOS pair; inp drives M1, under the mirror's diode side\nXM1 d1 inp tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1\nXM2 d2 inn tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1\n* the NMOS cascodes, C units each\nXM3 gp cn d1 vss sg13_lv_nmos w=14u l=2u ng=4 m=2\nXM4 out cn d2 vss sg13_lv_nmos w=14u l=2u ng=4 m=2\n* the PMOS cascodes, C units each, and the mirror under them: M7 and M8 take\n* their gates from gp, M5's drain\nXM5 gp cp x1 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2\nXM6 out cp x2 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2\nXM7 x1 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1\nXM8 x2 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1\n.ends\nXdut inp inn out vdd 0 ib otatc\nCl out 0 2p\nVsrc src 0 dc 660m\n* va on the non-inverting input, vb in the feedback path: both inputs move with the signal\nVa inp src dc 0 ac 1\nVb inn out dc 0 ac 1\n.ac dec 25 1 100meg\n.end" }, { "id": "noise", "label": "Noise", "note": "Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.", "measures": [], "metricKeys": [ "vn_1k", "vn_int" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Telescopic-cascode OTA - input-referred noise\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb vdd ib 5u\n.subckt otatc inp inn out vdd vss ib\n* bias: the reference into an NMOS diode, and copies of it\nXMB ib ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMT tail ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=5\nXMN1 pb ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMP pb pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\n* the NMOS cascode gate: a cascode unit as a diode on a narrow device that\n* stands on the tail node, so it follows the input common mode\nXMPC cn pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\nXMCN cn cn zc vss sg13_lv_nmos w=14u l=2u ng=4 m=1\nXMZC zc cn tail vss sg13_lv_nmos w=500n l=500n ng=1 m=1\n* the PMOS cascode gate, the same way down from vdd\nXMN2 cp ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMCP cp cp zp vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXMZP zp cp vdd vdd sg13_lv_pmos w=1.8u l=1u ng=1 m=1\n* the NMOS pair; inp drives M1, under the mirror's diode side\nXM1 d1 inp tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1\nXM2 d2 inn tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1\n* the NMOS cascodes, C units each\nXM3 gp cn d1 vss sg13_lv_nmos w=14u l=2u ng=4 m=2\nXM4 out cn d2 vss sg13_lv_nmos w=14u l=2u ng=4 m=2\n* the PMOS cascodes, C units each, and the mirror under them: M7 and M8 take\n* their gates from gp, M5's drain\nXM5 gp cp x1 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2\nXM6 out cp x2 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2\nXM7 x1 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1\nXM8 x2 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1\n.ends\nXdut inp inn out vdd 0 ib otatc\nCl out 0 2p\nVin inp 0 dc 660m ac 1\nVfb inn out 0\n.control\nnoise v(out) Vin dec 20 1 1meg\nsetplot noise1\n* 20 points a decade from 1 Hz: point 60 is 1 kHz\nlet vn_1k = inoise_spectrum[60]\nprint vn_1k\nsetplot noise2\nprint inoise_total\n.endc\n.op\n.end" }, { "id": "icmr", "label": "Input common-mode range", "note": "Both inputs swept together while the output is held at one level. The range is where open-loop gain falls by no more than 6 dB and unity-gain frequency by no more than 5 % from their values at the design common mode; increases are allowed.", "measures": [], "metricKeys": [ "icmr_lo", "icmr_hi" ], "acceptance": [ "icmr_lo", "icmr_hi" ], "acceptanceRules": [ { "key": "icmr_lo", "unit": "V", "min": null, "max": 0.65, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "icmr_hi", "unit": "V", "min": 0.7, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Telescopic-cascode OTA - input common-mode range, the output held at one level\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb vdd ib 5u\n.subckt otatc inp inn out vdd vss ib\n* bias: the reference into an NMOS diode, and copies of it\nXMB ib ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMT tail ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=5\nXMN1 pb ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMP pb pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\n* the NMOS cascode gate: a cascode unit as a diode on a narrow device that\n* stands on the tail node, so it follows the input common mode\nXMPC cn pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\nXMCN cn cn zc vss sg13_lv_nmos w=14u l=2u ng=4 m=1\nXMZC zc cn tail vss sg13_lv_nmos w=500n l=500n ng=1 m=1\n* the PMOS cascode gate, the same way down from vdd\nXMN2 cp ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMCP cp cp zp vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXMZP zp cp vdd vdd sg13_lv_pmos w=1.8u l=1u ng=1 m=1\n* the NMOS pair; inp drives M1, under the mirror's diode side\nXM1 d1 inp tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1\nXM2 d2 inn tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1\n* the NMOS cascodes, C units each\nXM3 gp cn d1 vss sg13_lv_nmos w=14u l=2u ng=4 m=2\nXM4 out cn d2 vss sg13_lv_nmos w=14u l=2u ng=4 m=2\n* the PMOS cascodes, C units each, and the mirror under them: M7 and M8 take\n* their gates from gp, M5's drain\nXM5 gp cp x1 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2\nXM6 out cp x2 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2\nXM7 x1 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1\nXM8 x2 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1\n.ends\nXdut inp inn out vdd 0 ib otatc\nCl out 0 2p\nVin inp 0 dc 660m ac 1\nVpark park 0 dc 660m\n* inn is inp shifted by how far out is from park: the loop holds out at park\n* while both inputs follow inp, and it is closed at DC only, as in the\n* open-loop bench, so each ac sweep sees the open loop\nEfb fb inp out park 1\nLfb fb inn 1t\nCfb inn 0 1t\n.control\n* point 0 is the design common mode, the reference; then every level\nac dec 20 0.1 10g\nmeas ac a0_0 find vdb(out) at=0.1\nmeas ac fu_0 when vdb(out)=0 fall=1\nalter vin dc = 0\nac dec 20 0.1 10g\nmeas ac a0_1 find vdb(out) at=0.1\nmeas ac fu_1 when vdb(out)=0 fall=1\nalter vin dc = 30m\nac dec 20 0.1 10g\nmeas ac a0_2 find vdb(out) at=0.1\nmeas ac fu_2 when vdb(out)=0 fall=1\nalter vin dc = 60m\nac dec 20 0.1 10g\nmeas ac a0_3 find vdb(out) at=0.1\nmeas ac fu_3 when vdb(out)=0 fall=1\nalter vin dc = 90m\nac dec 20 0.1 10g\nmeas ac a0_4 find vdb(out) at=0.1\nmeas ac fu_4 when vdb(out)=0 fall=1\nalter vin dc = 120m\nac dec 20 0.1 10g\nmeas ac a0_5 find vdb(out) at=0.1\nmeas ac fu_5 when vdb(out)=0 fall=1\nalter vin dc = 150m\nac dec 20 0.1 10g\nmeas ac a0_6 find vdb(out) at=0.1\nmeas ac fu_6 when vdb(out)=0 fall=1\nalter vin dc = 180m\nac dec 20 0.1 10g\nmeas ac a0_7 find vdb(out) at=0.1\nmeas ac fu_7 when vdb(out)=0 fall=1\nalter vin dc = 210m\nac dec 20 0.1 10g\nmeas ac a0_8 find vdb(out) at=0.1\nmeas ac fu_8 when vdb(out)=0 fall=1\nalter vin dc = 240m\nac dec 20 0.1 10g\nmeas ac a0_9 find vdb(out) at=0.1\nmeas ac fu_9 when vdb(out)=0 fall=1\nalter vin dc = 270m\nac dec 20 0.1 10g\nmeas ac a0_10 find vdb(out) at=0.1\nmeas ac fu_10 when vdb(out)=0 fall=1\nalter vin dc = 300m\nac dec 20 0.1 10g\nmeas ac a0_11 find vdb(out) at=0.1\nmeas ac fu_11 when vdb(out)=0 fall=1\nalter vin dc = 330m\nac dec 20 0.1 10g\nmeas ac a0_12 find vdb(out) at=0.1\nmeas ac fu_12 when vdb(out)=0 fall=1\nalter vin dc = 360m\nac dec 20 0.1 10g\nmeas ac a0_13 find vdb(out) at=0.1\nmeas ac fu_13 when vdb(out)=0 fall=1\nalter vin dc = 390m\nac dec 20 0.1 10g\nmeas ac a0_14 find vdb(out) at=0.1\nmeas ac fu_14 when vdb(out)=0 fall=1\nalter vin dc = 420m\nac dec 20 0.1 10g\nmeas ac a0_15 find vdb(out) at=0.1\nmeas ac fu_15 when vdb(out)=0 fall=1\nalter vin dc = 450m\nac dec 20 0.1 10g\nmeas ac a0_16 find vdb(out) at=0.1\nmeas ac fu_16 when vdb(out)=0 fall=1\nalter vin dc = 480m\nac dec 20 0.1 10g\nmeas ac a0_17 find vdb(out) at=0.1\nmeas ac fu_17 when vdb(out)=0 fall=1\nalter vin dc = 510m\nac dec 20 0.1 10g\nmeas ac a0_18 find vdb(out) at=0.1\nmeas ac fu_18 when vdb(out)=0 fall=1\nalter vin dc = 540m\nac dec 20 0.1 10g\nmeas ac a0_19 find vdb(out) at=0.1\nmeas ac fu_19 when vdb(out)=0 fall=1\nalter vin dc = 570m\nac dec 20 0.1 10g\nmeas ac a0_20 find vdb(out) at=0.1\nmeas ac fu_20 when vdb(out)=0 fall=1\nalter vin dc = 600m\nac dec 20 0.1 10g\nmeas ac a0_21 find vdb(out) at=0.1\nmeas ac fu_21 when vdb(out)=0 fall=1\nalter vin dc = 630m\nac dec 20 0.1 10g\nmeas ac a0_22 find vdb(out) at=0.1\nmeas ac fu_22 when vdb(out)=0 fall=1\nalter vin dc = 660m\nac dec 20 0.1 10g\nmeas ac a0_23 find vdb(out) at=0.1\nmeas ac fu_23 when vdb(out)=0 fall=1\nalter vin dc = 690m\nac dec 20 0.1 10g\nmeas ac a0_24 find vdb(out) at=0.1\nmeas ac fu_24 when vdb(out)=0 fall=1\nalter vin dc = 720m\nac dec 20 0.1 10g\nmeas ac a0_25 find vdb(out) at=0.1\nmeas ac fu_25 when vdb(out)=0 fall=1\nalter vin dc = 750m\nac dec 20 0.1 10g\nmeas ac a0_26 find vdb(out) at=0.1\nmeas ac fu_26 when vdb(out)=0 fall=1\nalter vin dc = 780m\nac dec 20 0.1 10g\nmeas ac a0_27 find vdb(out) at=0.1\nmeas ac fu_27 when vdb(out)=0 fall=1\nalter vin dc = 810m\nac dec 20 0.1 10g\nmeas ac a0_28 find vdb(out) at=0.1\nmeas ac fu_28 when vdb(out)=0 fall=1\nalter vin dc = 840m\nac dec 20 0.1 10g\nmeas ac a0_29 find vdb(out) at=0.1\nmeas ac fu_29 when vdb(out)=0 fall=1\nalter vin dc = 870m\nac dec 20 0.1 10g\nmeas ac a0_30 find vdb(out) at=0.1\nmeas ac fu_30 when vdb(out)=0 fall=1\nalter vin dc = 900m\nac dec 20 0.1 10g\nmeas ac a0_31 find vdb(out) at=0.1\nmeas ac fu_31 when vdb(out)=0 fall=1\nalter vin dc = 930m\nac dec 20 0.1 10g\nmeas ac a0_32 find vdb(out) at=0.1\nmeas ac fu_32 when vdb(out)=0 fall=1\nalter vin dc = 960m\nac dec 20 0.1 10g\nmeas ac a0_33 find vdb(out) at=0.1\nmeas ac fu_33 when vdb(out)=0 fall=1\nalter vin dc = 990m\nac dec 20 0.1 10g\nmeas ac a0_34 find vdb(out) at=0.1\nmeas ac fu_34 when vdb(out)=0 fall=1\nalter vin dc = 1.02\nac dec 20 0.1 10g\nmeas ac a0_35 find vdb(out) at=0.1\nmeas ac fu_35 when vdb(out)=0 fall=1\nalter vin dc = 1.05\nac dec 20 0.1 10g\nmeas ac a0_36 find vdb(out) at=0.1\nmeas ac fu_36 when vdb(out)=0 fall=1\nalter vin dc = 1.08\nac dec 20 0.1 10g\nmeas ac a0_37 find vdb(out) at=0.1\nmeas ac fu_37 when vdb(out)=0 fall=1\nalter vin dc = 1.11\nac dec 20 0.1 10g\nmeas ac a0_38 find vdb(out) at=0.1\nmeas ac fu_38 when vdb(out)=0 fall=1\nalter vin dc = 1.14\nac dec 20 0.1 10g\nmeas ac a0_39 find vdb(out) at=0.1\nmeas ac fu_39 when vdb(out)=0 fall=1\nalter vin dc = 1.17\nac dec 20 0.1 10g\nmeas ac a0_40 find vdb(out) at=0.1\nmeas ac fu_40 when vdb(out)=0 fall=1\nalter vin dc = 1.2\nac dec 20 0.1 10g\nmeas ac a0_41 find vdb(out) at=0.1\nmeas ac fu_41 when vdb(out)=0 fall=1\nalter vin dc = 1.23\nac dec 20 0.1 10g\nmeas ac a0_42 find vdb(out) at=0.1\nmeas ac fu_42 when vdb(out)=0 fall=1\nalter vin dc = 1.26\nac dec 20 0.1 10g\nmeas ac a0_43 find vdb(out) at=0.1\nmeas ac fu_43 when vdb(out)=0 fall=1\nalter vin dc = 1.29\nac dec 20 0.1 10g\nmeas ac a0_44 find vdb(out) at=0.1\nmeas ac fu_44 when vdb(out)=0 fall=1\nalter vin dc = 1.32\nac dec 20 0.1 10g\nmeas ac a0_45 find vdb(out) at=0.1\nmeas ac fu_45 when vdb(out)=0 fall=1\n.endc\n.dc Vin 0 1.32 30m\n.end" }, { "id": "swing", "label": "Output swing", "note": "The amplifier as an inverting gain of one - its inverting input at the midpoint of the output and a signal, through two ideal controlled sources that load nothing - with the signal swept so the output crosses from rail to rail, and at each level the open-loop gain: the swing is where the gain stays within 6 dB of its value with the output at the input common mode.", "measures": [], "metricKeys": [ "swing_lo", "swing_hi" ], "acceptance": [ "swing_lo", "swing_hi" ], "acceptanceRules": [ { "key": "swing_lo", "unit": "V", "min": null, "max": 0.65, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "swing_hi", "unit": "V", "min": 0.72, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* Telescopic-cascode OTA - output swing, as an inverting amplifier of gain one\n.include sg13g2_lv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb vdd ib 5u\n.subckt otatc inp inn out vdd vss ib\n* bias: the reference into an NMOS diode, and copies of it\nXMB ib ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMT tail ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=5\nXMN1 pb ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMP pb pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\n* the NMOS cascode gate: a cascode unit as a diode on a narrow device that\n* stands on the tail node, so it follows the input common mode\nXMPC cn pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\nXMCN cn cn zc vss sg13_lv_nmos w=14u l=2u ng=4 m=1\nXMZC zc cn tail vss sg13_lv_nmos w=500n l=500n ng=1 m=1\n* the PMOS cascode gate, the same way down from vdd\nXMN2 cp ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1\nXMCP cp cp zp vdd sg13_lv_pmos w=10u l=500n ng=2 m=1\nXMZP zp cp vdd vdd sg13_lv_pmos w=1.8u l=1u ng=1 m=1\n* the NMOS pair; inp drives M1, under the mirror's diode side\nXM1 d1 inp tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1\nXM2 d2 inn tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1\n* the NMOS cascodes, C units each\nXM3 gp cn d1 vss sg13_lv_nmos w=14u l=2u ng=4 m=2\nXM4 out cn d2 vss sg13_lv_nmos w=14u l=2u ng=4 m=2\n* the PMOS cascodes, C units each, and the mirror under them: M7 and M8 take\n* their gates from gp, M5's drain\nXM5 gp cp x1 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2\nXM6 out cp x2 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2\nXM7 x1 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1\nXM8 x2 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1\n.ends\nXdut inp inn out vdd 0 ib otatc\nCl out 0 2p\nVcm inp 0 dc 660m ac 1\nVsig sig 0 dc 660m\n* inn is the midpoint of out and sig: v(out) = 2 V_CM - v(sig). Closed at DC\n* only, so each ac sweep reads the open-loop gain at that output level\nE1 fbn mid out 0 0.5\nE2 mid 0 sig 0 0.5\nLfb fbn inn 1t\nCfb inn 0 1t\n.control\n* point 0 has the output at the input common mode, the reference\nac dec 1 0.1 1\nmeas ac a0_0 find vdb(out) at=0.1\nalter vsig dc = 1.32\nac dec 1 0.1 1\nmeas ac a0_1 find vdb(out) at=0.1\nalter vsig dc = 1.29\nac dec 1 0.1 1\nmeas ac a0_2 find vdb(out) at=0.1\nalter vsig dc = 1.26\nac dec 1 0.1 1\nmeas ac a0_3 find vdb(out) at=0.1\nalter vsig dc = 1.23\nac dec 1 0.1 1\nmeas ac a0_4 find vdb(out) at=0.1\nalter vsig dc = 1.2\nac dec 1 0.1 1\nmeas ac a0_5 find vdb(out) at=0.1\nalter vsig dc = 1.17\nac dec 1 0.1 1\nmeas ac a0_6 find vdb(out) at=0.1\nalter vsig dc = 1.14\nac dec 1 0.1 1\nmeas ac a0_7 find vdb(out) at=0.1\nalter vsig dc = 1.11\nac dec 1 0.1 1\nmeas ac a0_8 find vdb(out) at=0.1\nalter vsig dc = 1.08\nac dec 1 0.1 1\nmeas ac a0_9 find vdb(out) at=0.1\nalter vsig dc = 1.05\nac dec 1 0.1 1\nmeas ac a0_10 find vdb(out) at=0.1\nalter vsig dc = 1.02\nac dec 1 0.1 1\nmeas ac a0_11 find vdb(out) at=0.1\nalter vsig dc = 990m\nac dec 1 0.1 1\nmeas ac a0_12 find vdb(out) at=0.1\nalter vsig dc = 960m\nac dec 1 0.1 1\nmeas ac a0_13 find vdb(out) at=0.1\nalter vsig dc = 930m\nac dec 1 0.1 1\nmeas ac a0_14 find vdb(out) at=0.1\nalter vsig dc = 900m\nac dec 1 0.1 1\nmeas ac a0_15 find vdb(out) at=0.1\nalter vsig dc = 870m\nac dec 1 0.1 1\nmeas ac a0_16 find vdb(out) at=0.1\nalter vsig dc = 840m\nac dec 1 0.1 1\nmeas ac a0_17 find vdb(out) at=0.1\nalter vsig dc = 810m\nac dec 1 0.1 1\nmeas ac a0_18 find vdb(out) at=0.1\nalter vsig dc = 780m\nac dec 1 0.1 1\nmeas ac a0_19 find vdb(out) at=0.1\nalter vsig dc = 750m\nac dec 1 0.1 1\nmeas ac a0_20 find vdb(out) at=0.1\nalter vsig dc = 720m\nac dec 1 0.1 1\nmeas ac a0_21 find vdb(out) at=0.1\nalter vsig dc = 690m\nac dec 1 0.1 1\nmeas ac a0_22 find vdb(out) at=0.1\nalter vsig dc = 660m\nac dec 1 0.1 1\nmeas ac a0_23 find vdb(out) at=0.1\nalter vsig dc = 630m\nac dec 1 0.1 1\nmeas ac a0_24 find vdb(out) at=0.1\nalter vsig dc = 600m\nac dec 1 0.1 1\nmeas ac a0_25 find vdb(out) at=0.1\nalter vsig dc = 570m\nac dec 1 0.1 1\nmeas ac a0_26 find vdb(out) at=0.1\nalter vsig dc = 540m\nac dec 1 0.1 1\nmeas ac a0_27 find vdb(out) at=0.1\nalter vsig dc = 510m\nac dec 1 0.1 1\nmeas ac a0_28 find vdb(out) at=0.1\nalter vsig dc = 480m\nac dec 1 0.1 1\nmeas ac a0_29 find vdb(out) at=0.1\nalter vsig dc = 450m\nac dec 1 0.1 1\nmeas ac a0_30 find vdb(out) at=0.1\nalter vsig dc = 420m\nac dec 1 0.1 1\nmeas ac a0_31 find vdb(out) at=0.1\nalter vsig dc = 390m\nac dec 1 0.1 1\nmeas ac a0_32 find vdb(out) at=0.1\nalter vsig dc = 360m\nac dec 1 0.1 1\nmeas ac a0_33 find vdb(out) at=0.1\nalter vsig dc = 330m\nac dec 1 0.1 1\nmeas ac a0_34 find vdb(out) at=0.1\nalter vsig dc = 300m\nac dec 1 0.1 1\nmeas ac a0_35 find vdb(out) at=0.1\nalter vsig dc = 270m\nac dec 1 0.1 1\nmeas ac a0_36 find vdb(out) at=0.1\nalter vsig dc = 240m\nac dec 1 0.1 1\nmeas ac a0_37 find vdb(out) at=0.1\nalter vsig dc = 210m\nac dec 1 0.1 1\nmeas ac a0_38 find vdb(out) at=0.1\nalter vsig dc = 180m\nac dec 1 0.1 1\nmeas ac a0_39 find vdb(out) at=0.1\nalter vsig dc = 150m\nac dec 1 0.1 1\nmeas ac a0_40 find vdb(out) at=0.1\nalter vsig dc = 120m\nac dec 1 0.1 1\nmeas ac a0_41 find vdb(out) at=0.1\n.endc\n.dc Vsig 120m 1.32 30m\n.end" } ], "measurements": { "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.00005 } }, "dc_gain_db": { "label": "DC open-loop gain", "unit": "dB", "spec": { "min": 45, "max": null } }, "ugf_hz": { "label": "Unity-gain frequency", "unit": "Hz", "spec": { "min": 5000000, "max": null } }, "pm_deg": { "label": "Phase margin", "unit": "deg", "spec": { "min": 75, "max": null } }, "t_settle": { "label": "Settling time, 1 %", "unit": "s", "spec": { "min": null, "max": 1.5e-7 } }, "psrr_db": { "label": "Supply rejection at 1 kHz", "unit": "dB", "spec": { "min": 40, "max": null } }, "cmrr_db": { "label": "Common-mode rejection at 1 kHz", "unit": "dB", "spec": { "min": 55, "max": null } }, "icmr_lo": { "label": "Lowest input common mode", "unit": "V", "spec": { "min": null, "max": 0.65 } }, "icmr_hi": { "label": "Highest input common mode", "unit": "V", "spec": { "min": 0.7, "max": null } }, "swing_lo": { "label": "Lowest output", "unit": "V", "spec": { "min": null, "max": 0.65 } }, "swing_hi": { "label": "Highest output", "unit": "V", "spec": { "min": 0.72, "max": null } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "2a663d4db99aad13be3ee4e7d770c02b7fc33c7a269c771ad79ad0b7153a28e4" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ota-telescopic.js", "sha256": "432fb08cacbbe5b8ec4d5b6d14544232d258668e759c1f41b13557608f8c586a" }, "simulationFingerprints": { "op": "d43f5a3034022b9a46f5d2723665846a3ae86f910084be9b7b0459995af916b9", "open_loop": "3d151a4664fa04dd4c7bde8bb5fe27e7821e3dc9e94928e910ac0f53258b9548", "step": "b7cb93a69e0fac8baa2490a3dd1c7cddd25d28cf2a62172828d8ad13ecd6f602", "psrr": "794d48f4f233adc372c65cd89fa53c93fec55f7154377205a9d62f217abfbb79", "cmrr": "ee11ae6df2aef04dfeb40be40a06b679799ab735782103ea710cd6ca1304364e", "noise": "cf2e4ad070c0c271ec5f9ef6011e912f3c41b1f23be10144979e4cac0b498fc6", "icmr": "fbef60af92dc7b72e8f26877eca27e264f06d26d8809d3826099156c823b862a", "swing": "a59334d452084eea8e7645f4efa82d5de314aaa1096aa786b8d1021b5af309c0" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "09a3ecfeed7ca9582ab55324c4fc47ff631c5108de669087ecf0ddbe4d11e0fa", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ota-telescopic", "parameters": { "Ib": 0.000005, "C": 2, "W1": 0.0000012, "L1": 5e-7, "Wn": 0.00003, "Ln": 0.000004, "Wp": 0.000006, "Lp": 0.000001, "Wc": 0.000014, "Lc": 0.000002, "Wzc": 5e-7, "Wpc": 0.00001, "Lpc": 5e-7, "Wm": 0.000014, "Lm": 0.000001, "Wzp": 0.0000018, "CL": 2e-12, "VCM": 0.66 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ota-telescopic/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "otatc", "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=5", "source": "XMT tail ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=5", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN1", "displayName": "MN1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMN1 pb ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "pb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=1u ng=2 m=1", "source": "XMP pb pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "pb" }, { "id": "g", "net": "pb" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMPC", "displayName": "MPC", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=1u ng=2 m=1", "source": "XMPC cn pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "pb" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCN", "displayName": "MCN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=14u l=2u ng=4 m=1", "source": "XMCN cn cn zc vss sg13_lv_nmos w=14u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "zc" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZC", "displayName": "MZC", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=500n ng=1 m=1", "source": "XMZC zc cn tail vss sg13_lv_nmos w=500n l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "zc" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMN2 cp ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCP", "displayName": "MCP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=1", "source": "XMCP cp cp zp vdd sg13_lv_pmos w=10u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "zp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZP", "displayName": "MZP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.8u l=1u ng=1 m=1", "source": "XMZP zp cp vdd vdd sg13_lv_pmos w=1.8u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "zp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.2u l=500n ng=1 m=1", "source": "XM1 d1 inp tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.2u l=500n ng=1 m=1", "source": "XM2 d2 inn tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=14u l=2u ng=4 m=2", "source": "XM3 gp cn d1 vss sg13_lv_nmos w=14u l=2u ng=4 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "d1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=14u l=2u ng=4 m=2", "source": "XM4 out cn d2 vss sg13_lv_nmos w=14u l=2u ng=4 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=2", "source": "XM5 gp cp x1 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=2", "source": "XM6 out cp x2 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=14u l=1u ng=4 m=1", "source": "XM7 x1 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=14u l=1u ng=4 m=1", "source": "XM8 x2 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMN1", "pin": "g" }, { "device": "XMN2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMN1", "pin": "s" }, { "device": "XMN1", "pin": "b" }, { "device": "XMCN", "pin": "b" }, { "device": "XMZC", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XMZC", "pin": "s" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "pb", "ground": false, "terminals": [ { "device": "XMN1", "pin": "d" }, { "device": "XMP", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XMPC", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" }, { "device": "XMPC", "pin": "s" }, { "device": "XMPC", "pin": "b" }, { "device": "XMCP", "pin": "b" }, { "device": "XMZP", "pin": "s" }, { "device": "XMZP", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "cn", "ground": false, "terminals": [ { "device": "XMPC", "pin": "d" }, { "device": "XMCN", "pin": "d" }, { "device": "XMCN", "pin": "g" }, { "device": "XMZC", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zc", "ground": false, "terminals": [ { "device": "XMCN", "pin": "s" }, { "device": "XMZC", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cp", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XMCP", "pin": "d" }, { "device": "XMCP", "pin": "g" }, { "device": "XMZP", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zp", "ground": false, "terminals": [ { "device": "XMCP", "pin": "s" }, { "device": "XMZP", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "gp", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "s" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "x2", "ground": false, "terminals": [ { "device": "XM6", "pin": "s" }, { "device": "XM8", "pin": "d" } ], "ports": [], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ib vdd ib 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "otatc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib otatc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/otatc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cl out 0 2p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 660m", "source": "Vin inp 0 dc 660m", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/otatc", "name": "otatc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=5", "source": "XMT tail ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=5", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN1", "displayName": "MN1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMN1 pb ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "pb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=1u ng=2 m=1", "source": "XMP pb pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "pb" }, { "id": "g", "net": "pb" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMPC", "displayName": "MPC", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=1u ng=2 m=1", "source": "XMPC cn pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "pb" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCN", "displayName": "MCN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=14u l=2u ng=4 m=1", "source": "XMCN cn cn zc vss sg13_lv_nmos w=14u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "zc" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZC", "displayName": "MZC", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=500n ng=1 m=1", "source": "XMZC zc cn tail vss sg13_lv_nmos w=500n l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "zc" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMN2 cp ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCP", "displayName": "MCP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=1", "source": "XMCP cp cp zp vdd sg13_lv_pmos w=10u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "zp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZP", "displayName": "MZP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.8u l=1u ng=1 m=1", "source": "XMZP zp cp vdd vdd sg13_lv_pmos w=1.8u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "zp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.2u l=500n ng=1 m=1", "source": "XM1 d1 inp tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.2u l=500n ng=1 m=1", "source": "XM2 d2 inn tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=14u l=2u ng=4 m=2", "source": "XM3 gp cn d1 vss sg13_lv_nmos w=14u l=2u ng=4 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "d1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=14u l=2u ng=4 m=2", "source": "XM4 out cn d2 vss sg13_lv_nmos w=14u l=2u ng=4 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=2", "source": "XM5 gp cp x1 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=2", "source": "XM6 out cp x2 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=14u l=1u ng=4 m=1", "source": "XM7 x1 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=14u l=1u ng=4 m=1", "source": "XM8 x2 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMN1", "pin": "g" }, { "device": "XMN2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMN1", "pin": "s" }, { "device": "XMN1", "pin": "b" }, { "device": "XMCN", "pin": "b" }, { "device": "XMZC", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XMZC", "pin": "s" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "pb", "ground": false, "terminals": [ { "device": "XMN1", "pin": "d" }, { "device": "XMP", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XMPC", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" }, { "device": "XMPC", "pin": "s" }, { "device": "XMPC", "pin": "b" }, { "device": "XMCP", "pin": "b" }, { "device": "XMZP", "pin": "s" }, { "device": "XMZP", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "cn", "ground": false, "terminals": [ { "device": "XMPC", "pin": "d" }, { "device": "XMCN", "pin": "d" }, { "device": "XMCN", "pin": "g" }, { "device": "XMZC", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zc", "ground": false, "terminals": [ { "device": "XMCN", "pin": "s" }, { "device": "XMZC", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cp", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XMCP", "pin": "d" }, { "device": "XMCP", "pin": "g" }, { "device": "XMZP", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zp", "ground": false, "terminals": [ { "device": "XMCP", "pin": "s" }, { "device": "XMZP", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "gp", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "s" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "x2", "ground": false, "terminals": [ { "device": "XM6", "pin": "s" }, { "device": "XM8", "pin": "d" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/otatc" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Bias reference", "devices": [ { "scope": "dut", "device": "XMB" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "Tail current source", "devices": [ { "scope": "dut", "device": "XMT" } ], "inferredStages": [ 1 ] }, { "id": "block-3", "label": "Copies the reference into MP", "devices": [ { "scope": "dut", "device": "XMN1" } ], "inferredStages": [ "bias" ] }, { "id": "block-4", "label": "PMOS reference", "devices": [ { "scope": "dut", "device": "XMP" } ], "inferredStages": [ "bias" ] }, { "id": "block-5", "label": "Feeds the NMOS cascode-bias stack", "devices": [ { "scope": "dut", "device": "XMPC" } ], "inferredStages": [ 3 ] }, { "id": "block-6", "label": "One NMOS cascode unit as a diode: sets the cascode gate cn", "devices": [ { "scope": "dut", "device": "XMCN" } ], "inferredStages": [ 3 ] }, { "id": "block-7", "label": "Narrow device under MCN on the tail node: the drop across it is the input pair's drain voltage", "devices": [ { "scope": "dut", "device": "XMZC" } ], "inferredStages": [ 2 ] }, { "id": "block-8", "label": "Draws the reference through the PMOS cascode-bias stack", "devices": [ { "scope": "dut", "device": "XMN2" } ], "inferredStages": [ "bias" ] }, { "id": "block-9", "label": "One PMOS cascode unit as a diode: sets the cascode gate cp", "devices": [ { "scope": "dut", "device": "XMCP" } ], "inferredStages": [ "bias" ] }, { "id": "block-10", "label": "In triode under vdd: its drop is the PMOS mirror's headroom", "devices": [ { "scope": "dut", "device": "XMZP" } ], "inferredStages": [ "bias" ] }, { "id": "block-11", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 1 ] }, { "id": "block-12", "label": "NMOS cascode", "devices": [ { "scope": "dut", "device": "XM3" }, { "scope": "dut", "device": "XM4" } ], "inferredStages": [ 2 ] }, { "id": "block-13", "label": "PMOS cascode", "devices": [ { "scope": "dut", "device": "XM5" }, { "scope": "dut", "device": "XM6" } ], "inferredStages": [ 2 ] }, { "id": "block-14", "label": "PMOS mirror", "devices": [ { "scope": "dut", "device": "XM7" }, { "scope": "dut", "device": "XM8" } ], "inferredStages": [ 3 ] } ], "edges": [ { "id": "net-1", "net": "ib", "nodes": [ "block-1", "block-2", "block-3", "block-8" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "tail", "nodes": [ "block-2", "block-7", "block-11" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "pb", "nodes": [ "block-3", "block-4", "block-5" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "cn", "nodes": [ "block-5", "block-6", "block-7", "block-12" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "zc", "nodes": [ "block-6", "block-7" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "cp", "nodes": [ "block-8", "block-9", "block-10", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-7", "net": "zp", "nodes": [ "block-9", "block-10" ], "direction": "undirected-shared-net" }, { "id": "net-8", "net": "d1", "nodes": [ "block-11", "block-12" ], "direction": "undirected-shared-net" }, { "id": "net-9", "net": "d2", "nodes": [ "block-11", "block-12" ], "direction": "undirected-shared-net" }, { "id": "net-10", "net": "gp", "nodes": [ "block-12", "block-13", "block-14" ], "direction": "undirected-shared-net" }, { "id": "net-11", "net": "out", "nodes": [ "block-12", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-12", "net": "x1", "nodes": [ "block-13", "block-14" ], "direction": "undirected-shared-net" }, { "id": "net-13", "net": "x2", "nodes": [ "block-13", "block-14" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ib vdd ib 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "otatc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib otatc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/otatc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cl out 0 2p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 660m ac 1", "source": "Vin inp 0 dc 660m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfb", "displayName": "Lfb", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfb out inn 1t", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cfb", "displayName": "Cfb", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cfb inn 0 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" }, { "device": "Cfb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Lfb", "pin": "n" }, { "device": "Cfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Lfb", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/otatc", "name": "otatc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=5", "source": "XMT tail ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=5", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN1", "displayName": "MN1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMN1 pb ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "pb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=1u ng=2 m=1", "source": "XMP pb pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "pb" }, { "id": "g", "net": "pb" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMPC", "displayName": "MPC", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=1u ng=2 m=1", "source": "XMPC cn pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "pb" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCN", "displayName": "MCN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=14u l=2u ng=4 m=1", "source": "XMCN cn cn zc vss sg13_lv_nmos w=14u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "zc" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZC", "displayName": "MZC", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=500n ng=1 m=1", "source": "XMZC zc cn tail vss sg13_lv_nmos w=500n l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "zc" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMN2 cp ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCP", "displayName": "MCP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=1", "source": "XMCP cp cp zp vdd sg13_lv_pmos w=10u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "zp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZP", "displayName": "MZP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.8u l=1u ng=1 m=1", "source": "XMZP zp cp vdd vdd sg13_lv_pmos w=1.8u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "zp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.2u l=500n ng=1 m=1", "source": "XM1 d1 inp tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.2u l=500n ng=1 m=1", "source": "XM2 d2 inn tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=14u l=2u ng=4 m=2", "source": "XM3 gp cn d1 vss sg13_lv_nmos w=14u l=2u ng=4 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "d1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=14u l=2u ng=4 m=2", "source": "XM4 out cn d2 vss sg13_lv_nmos w=14u l=2u ng=4 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=2", "source": "XM5 gp cp x1 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=2", "source": "XM6 out cp x2 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=14u l=1u ng=4 m=1", "source": "XM7 x1 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=14u l=1u ng=4 m=1", "source": "XM8 x2 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMN1", "pin": "g" }, { "device": "XMN2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMN1", "pin": "s" }, { "device": "XMN1", "pin": "b" }, { "device": "XMCN", "pin": "b" }, { "device": "XMZC", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XMZC", "pin": "s" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "pb", "ground": false, "terminals": [ { "device": "XMN1", "pin": "d" }, { "device": "XMP", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XMPC", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" }, { "device": "XMPC", "pin": "s" }, { "device": "XMPC", "pin": "b" }, { "device": "XMCP", "pin": "b" }, { "device": "XMZP", "pin": "s" }, { "device": "XMZP", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "cn", "ground": false, "terminals": [ { "device": "XMPC", "pin": "d" }, { "device": "XMCN", "pin": "d" }, { "device": "XMCN", "pin": "g" }, { "device": "XMZC", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zc", "ground": false, "terminals": [ { "device": "XMCN", "pin": "s" }, { "device": "XMZC", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cp", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XMCP", "pin": "d" }, { "device": "XMCP", "pin": "g" }, { "device": "XMZP", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zp", "ground": false, "terminals": [ { "device": "XMCP", "pin": "s" }, { "device": "XMZP", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "gp", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "s" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "x2", "ground": false, "terminals": [ { "device": "XM6", "pin": "s" }, { "device": "XM8", "pin": "d" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/otatc" } }, { "id": "graph-5", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. 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[] } ] }, { "id": "subckt/otatc", "name": "otatc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=5", "source": "XMT tail ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=5", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, 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}, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/otatc", "name": "otatc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=5", "source": "XMT tail ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=5", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN1", 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"pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCP", "displayName": "MCP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=1", "source": "XMCP cp cp zp vdd sg13_lv_pmos w=10u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "zp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZP", "displayName": "MZP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.8u l=1u ng=1 m=1", "source": "XMZP zp cp vdd vdd sg13_lv_pmos w=1.8u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "zp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", 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"net": "cp" }, { "id": "s", "net": "x2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=14u l=1u ng=4 m=1", "source": "XM7 x1 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=14u l=1u ng=4 m=1", "source": "XM8 x2 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMN1", "pin": "g" }, { "device": "XMN2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMN1", "pin": "s" }, { "device": "XMN1", "pin": "b" }, { "device": "XMCN", "pin": "b" }, { "device": "XMZC", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XMZC", "pin": "s" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "pb", "ground": false, "terminals": [ { "device": "XMN1", "pin": "d" }, { "device": "XMP", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XMPC", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" }, { "device": "XMPC", "pin": "s" }, { "device": "XMPC", "pin": "b" }, { "device": "XMCP", "pin": "b" }, { "device": "XMZP", "pin": "s" }, { "device": "XMZP", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "cn", "ground": false, "terminals": [ { "device": "XMPC", "pin": "d" }, { "device": "XMCN", "pin": "d" }, { "device": "XMCN", "pin": "g" }, { "device": "XMZC", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zc", "ground": false, "terminals": [ { "device": "XMCN", "pin": "s" }, { "device": "XMZC", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cp", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XMCP", "pin": "d" }, { "device": "XMCP", "pin": "g" }, { "device": "XMZP", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zp", "ground": false, "terminals": [ { "device": "XMCP", "pin": "s" }, { "device": "XMZP", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "gp", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "s" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "x2", "ground": false, "terminals": [ { "device": "XM6", "pin": "s" }, { "device": "XM8", "pin": "d" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/otatc" } }, { "id": "graph-7", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ib vdd ib 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "otatc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib otatc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/otatc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cl out 0 2p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vsrc", "displayName": "Vsrc", "spiceType": "V", "model": null, "parametersOrValue": "dc 660m", "source": "Vsrc src 0 dc 660m", "pins": [ { "id": "p", "net": "src" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Va", "displayName": "Va", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Va inp src dc 0 ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "src" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vb", "displayName": "Vb", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Vb inn out dc 0 ac 1", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vsrc", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Va", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "src", "ground": false, "terminals": [ { "device": "Vsrc", "pin": "p" }, { "device": "Va", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/otatc", "name": "otatc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=5", "source": "XMT tail ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=5", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN1", "displayName": "MN1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMN1 pb ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "pb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=1u ng=2 m=1", "source": "XMP pb pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "pb" }, { "id": "g", "net": "pb" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMPC", "displayName": "MPC", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=1u ng=2 m=1", "source": "XMPC cn pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "pb" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCN", "displayName": "MCN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=14u l=2u ng=4 m=1", "source": "XMCN cn cn zc vss sg13_lv_nmos w=14u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "zc" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZC", "displayName": "MZC", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=500n ng=1 m=1", "source": "XMZC zc cn tail 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"X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.8u l=1u ng=1 m=1", "source": "XMZP zp cp vdd vdd sg13_lv_pmos w=1.8u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "zp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.2u l=500n ng=1 m=1", "source": "XM1 d1 inp tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.2u l=500n ng=1 m=1", "source": "XM2 d2 inn tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": 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"net": "gp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=2", "source": "XM6 out cp x2 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=14u l=1u ng=4 m=1", "source": "XM7 x1 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=14u l=1u ng=4 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{ "device": "XM4", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XMZC", "pin": "s" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "pb", "ground": false, "terminals": [ { "device": "XMN1", "pin": "d" }, { "device": "XMP", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XMPC", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" }, { "device": "XMPC", "pin": "s" }, { "device": "XMPC", "pin": "b" }, { "device": "XMCP", "pin": "b" }, { "device": "XMZP", "pin": "s" }, { "device": "XMZP", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "cn", "ground": false, "terminals": [ { "device": "XMPC", "pin": "d" }, { "device": "XMCN", "pin": "d" }, { "device": "XMCN", "pin": "g" }, { "device": "XMZC", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zc", "ground": false, "terminals": [ { "device": "XMCN", "pin": "s" }, { "device": "XMZC", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cp", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XMCP", "pin": "d" }, { "device": "XMCP", "pin": "g" }, { "device": "XMZP", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zp", "ground": false, "terminals": [ { "device": "XMCP", "pin": "s" }, { "device": "XMZP", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "gp", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "s" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "x2", "ground": false, "terminals": [ { "device": "XM6", "pin": "s" }, { "device": "XM8", "pin": "d" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/otatc" } }, { "id": "graph-8", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ib vdd ib 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "otatc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib otatc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/otatc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cl out 0 2p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 660m ac 1", "source": "Vin inp 0 dc 660m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/otatc", "name": "otatc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=5", "source": "XMT tail ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=5", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN1", "displayName": "MN1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMN1 pb ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "pb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=1u ng=2 m=1", "source": "XMP pb pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "pb" }, { "id": "g", "net": "pb" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMPC", "displayName": "MPC", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=1u ng=2 m=1", "source": "XMPC cn pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "pb" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCN", "displayName": "MCN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=14u l=2u ng=4 m=1", "source": "XMCN cn cn zc vss sg13_lv_nmos w=14u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "zc" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZC", "displayName": "MZC", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=500n ng=1 m=1", "source": "XMZC zc cn tail vss sg13_lv_nmos w=500n l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "zc" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMN2 cp ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCP", "displayName": "MCP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=1", "source": "XMCP cp cp zp vdd sg13_lv_pmos w=10u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "zp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZP", "displayName": "MZP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.8u l=1u ng=1 m=1", "source": "XMZP zp cp vdd vdd sg13_lv_pmos w=1.8u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "zp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.2u l=500n ng=1 m=1", "source": "XM1 d1 inp tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.2u l=500n ng=1 m=1", "source": "XM2 d2 inn tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=14u l=2u ng=4 m=2", "source": "XM3 gp cn d1 vss sg13_lv_nmos w=14u l=2u ng=4 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "d1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=14u l=2u ng=4 m=2", "source": "XM4 out cn d2 vss sg13_lv_nmos w=14u l=2u ng=4 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=2", "source": "XM5 gp cp x1 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=2", "source": "XM6 out cp x2 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=14u l=1u ng=4 m=1", "source": "XM7 x1 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=14u l=1u ng=4 m=1", "source": "XM8 x2 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMN1", "pin": "g" }, { "device": "XMN2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMN1", "pin": "s" }, { "device": "XMN1", "pin": "b" }, { "device": "XMCN", "pin": "b" }, { "device": "XMZC", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XMZC", "pin": "s" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "pb", "ground": false, "terminals": [ { "device": "XMN1", "pin": "d" }, { "device": "XMP", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XMPC", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" }, { "device": "XMPC", "pin": "s" }, { "device": "XMPC", "pin": "b" }, { "device": "XMCP", "pin": "b" }, { "device": "XMZP", "pin": "s" }, { "device": "XMZP", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "cn", "ground": false, "terminals": [ { "device": "XMPC", "pin": "d" }, { "device": "XMCN", "pin": "d" }, { "device": "XMCN", "pin": "g" }, { "device": "XMZC", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zc", "ground": false, "terminals": [ { "device": "XMCN", "pin": "s" }, { "device": "XMZC", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cp", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XMCP", "pin": "d" }, { "device": "XMCP", "pin": "g" }, { "device": "XMZP", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zp", "ground": false, "terminals": [ { "device": "XMCP", "pin": "s" }, { "device": "XMZP", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "gp", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "s" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "x2", "ground": false, "terminals": [ { "device": "XM6", "pin": "s" }, { "device": "XM8", "pin": "d" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/otatc" } }, { "id": "graph-9", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ib vdd ib 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "otatc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib otatc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/otatc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cl out 0 2p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 660m ac 1", "source": "Vin inp 0 dc 660m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vpark", "displayName": "Vpark", "spiceType": "V", "model": null, "parametersOrValue": "dc 660m", "source": "Vpark park 0 dc 660m", "pins": [ { "id": "p", "net": "park" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Efb", "displayName": "Efb", "spiceType": "E", "model": null, "parametersOrValue": "1", "source": "Efb fb inp out park 1", "pins": [ { "id": "p", "net": "fb" }, { "id": "n", "net": "inp" }, { "id": "cp", "net": "out" }, { "id": "cn", "net": "park" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfb", "displayName": "Lfb", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfb fb inn 1t", "pins": [ { "id": "p", "net": "fb" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cfb", "displayName": "Cfb", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cfb inn 0 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" }, { "device": "Vpark", "pin": "n" }, { "device": "Cfb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" }, { "device": "Efb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Lfb", "pin": "n" }, { "device": "Cfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Efb", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "park", "ground": false, "terminals": [ { "device": "Vpark", "pin": "p" }, { "device": "Efb", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "fb", "ground": false, "terminals": [ { "device": "Efb", "pin": "p" }, { "device": "Lfb", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/otatc", "name": "otatc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=5", "source": "XMT tail ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=5", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN1", "displayName": "MN1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMN1 pb ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "pb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=1u ng=2 m=1", "source": "XMP pb pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "pb" }, { "id": "g", "net": "pb" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMPC", "displayName": "MPC", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=1u ng=2 m=1", "source": "XMPC cn pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "pb" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCN", "displayName": "MCN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=14u l=2u ng=4 m=1", "source": "XMCN cn cn zc vss sg13_lv_nmos w=14u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "zc" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZC", "displayName": "MZC", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=500n ng=1 m=1", "source": "XMZC zc cn tail vss sg13_lv_nmos w=500n l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "zc" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMN2 cp ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCP", "displayName": "MCP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=1", "source": "XMCP cp cp zp vdd sg13_lv_pmos w=10u l=500n ng=2 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "zp" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZP", "displayName": "MZP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.8u l=1u ng=1 m=1", "source": "XMZP zp cp vdd vdd sg13_lv_pmos w=1.8u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "zp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.2u l=500n ng=1 m=1", "source": "XM1 d1 inp tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d1" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.2u l=500n ng=1 m=1", "source": "XM2 d2 inn tail vss sg13_lv_nmos w=1.2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=14u l=2u ng=4 m=2", "source": "XM3 gp cn d1 vss sg13_lv_nmos w=14u l=2u ng=4 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "d1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=14u l=2u ng=4 m=2", "source": "XM4 out cn d2 vss sg13_lv_nmos w=14u l=2u ng=4 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "d2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=2", "source": "XM5 gp cp x1 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2", "pins": [ { "id": "d", "net": "gp" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10u l=500n ng=2 m=2", "source": "XM6 out cp x2 vdd sg13_lv_pmos w=10u l=500n ng=2 m=2", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "cp" }, { "id": "s", "net": "x2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=14u l=1u ng=4 m=1", "source": "XM7 x1 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=14u l=1u ng=4 m=1", "source": "XM8 x2 gp vdd vdd sg13_lv_pmos w=14u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "x2" }, { "id": "g", "net": "gp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMN1", "pin": "g" }, { "device": "XMN2", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XMN1", "pin": "s" }, { "device": "XMN1", "pin": "b" }, { "device": "XMCN", "pin": "b" }, { "device": "XMZC", "pin": "b" }, { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XMZC", "pin": "s" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "pb", "ground": false, "terminals": [ { "device": "XMN1", "pin": "d" }, { "device": "XMP", "pin": "d" }, { "device": "XMP", "pin": "g" }, { "device": "XMPC", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMP", "pin": "s" }, { "device": "XMP", "pin": "b" }, { "device": "XMPC", "pin": "s" }, { "device": "XMPC", "pin": "b" }, { "device": "XMCP", "pin": "b" }, { "device": "XMZP", "pin": "s" }, { "device": "XMZP", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "cn", "ground": false, "terminals": [ { "device": "XMPC", "pin": "d" }, { "device": "XMCN", "pin": "d" }, { "device": "XMCN", "pin": "g" }, { "device": "XMZC", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zc", "ground": false, "terminals": [ { "device": "XMCN", "pin": "s" }, { "device": "XMZC", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "cp", "ground": false, "terminals": [ { "device": "XMN2", "pin": "d" }, { "device": "XMCP", "pin": "d" }, { "device": "XMCP", "pin": "g" }, { "device": "XMZP", "pin": "g" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "zp", "ground": false, "terminals": [ { "device": "XMCP", "pin": "s" }, { "device": "XMZP", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "gp", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "s" }, { "device": "XM7", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "x2", "ground": false, "terminals": [ { "device": "XM6", "pin": "s" }, { "device": "XM8", "pin": "d" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/otatc" } }, { "id": "graph-10", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "5u", "source": "Ib vdd ib 5u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "otatc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib otatc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/otatc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "2p", "source": "Cl out 0 2p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vcm", "displayName": "Vcm", "spiceType": "V", "model": null, "parametersOrValue": "dc 660m ac 1", "source": "Vcm inp 0 dc 660m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vsig", "displayName": "Vsig", "spiceType": "V", "model": null, "parametersOrValue": "dc 660m", "source": "Vsig sig 0 dc 660m", "pins": [ { "id": "p", "net": "sig" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "E1", "displayName": "E1", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "E1 fbn mid out 0 0.5", "pins": [ { "id": "p", "net": "fbn" }, { "id": "n", "net": "mid" }, { "id": "cp", "net": "out" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "E2", "displayName": "E2", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "E2 mid 0 sig 0 0.5", "pins": [ { "id": "p", "net": "mid" }, { "id": "n", "net": "0" }, { "id": "cp", "net": "sig" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfb", "displayName": "Lfb", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfb fbn inn 1t", "pins": [ { "id": "p", "net": "fbn" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cfb", "displayName": "Cfb", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cfb inn 0 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vcm", "pin": "n" }, { "device": "Vsig", "pin": "n" }, { "device": "E1", "pin": "cn" }, { "device": "E2", "pin": "n" }, { "device": "E2", "pin": "cn" }, { "device": "Cfb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vcm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Lfb", "pin": "n" }, { "device": "Cfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "E1", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "sig", "ground": false, "terminals": [ { "device": "Vsig", "pin": "p" }, { "device": "E2", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "fbn", "ground": false, "terminals": [ { "device": "E1", "pin": "p" }, { "device": "Lfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "mid", "ground": false, "terminals": [ { "device": "E1", "pin": "n" }, { "device": "E2", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/otatc", "name": "otatc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMB ib ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=5", "source": "XMT tail ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=5", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN1", "displayName": "MN1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMN1 pb ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "pb" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP", "displayName": "MP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=1u ng=2 m=1", "source": "XMP pb pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "pb" }, { "id": "g", "net": "pb" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMPC", "displayName": "MPC", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=1u ng=2 m=1", "source": "XMPC cn pb vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "pb" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCN", "displayName": "MCN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=14u l=2u ng=4 m=1", "source": "XMCN cn cn zc vss sg13_lv_nmos w=14u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "cn" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "zc" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMZC", "displayName": "MZC", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=500n ng=1 m=1", "source": "XMZC zc cn tail vss sg13_lv_nmos w=500n l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "zc" }, { "id": "g", "net": "cn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=30u l=4u ng=6 m=1", "source": "XMN2 cp ib vss vss sg13_lv_nmos w=30u l=4u ng=6 m=1", "pins": [ { "id": "d", "net": "cp" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMCP", "displayName": "MCP", "spiceType": "X", "model": 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