{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ota3-az", "name": "Three-stage op amp, active zero, cross feedforward", "group": "Op amps and OTAs", "subgroup": "Three-stage op amps", "title": "Three-stage op amp, active zero, cross feedforward", "summary": "This three-stage amplifier combines a regulated compensation buffer with two direct signal paths to the later stages. A resistor also helps counteract delay in the second-stage mirror. Larger matched devices improve common-mode rejection, while smaller local regulators keep the added feedback loops fast.", "reference": { "kind": "paper", "authors": "Z. Yan, P.-I. Mak, M.-K. Law, R. P. Martins", "title": "A 0.016-mm² 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With >0.95-MHz GBW", "year": 2013, "where": "IEEE Journal of Solid-State Circuits, 48(2):527-540", "doi": "10.1109/JSSC.2012.2229070", "takes": "The principle: a three-stage amplifier on current-buffer Miller compensation, with a parasitic pole cancelled by an active left-half-plane zero. The arrangement it is built with here - the current buffer as the first stage's regulated cascode, the zero made by gating the second-stage mirror's diode through a resistor, a cross-feedforward second-stage load on the first stage's mirror node and a feedforward output device - and the bias and every size are this library's, for SG13G2 at 1.2 V." }, "resources": { "record": "/circuits/ota3-az.json", "page": "/index.html#ota3-az", "achieved": "/achieved/ota3-az.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "inp", "kind": "input" }, { "name": "inn", "kind": "input" }, { "name": "out", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the reference current, drawn out of this pin" } ], "devices": [ { "name": "MB", "type": "pmos", "nodes": "ib ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "bias reference, diode-connected: takes Ib", "fingers": 6, "copies": 1 }, { "name": "M20", "type": "pmos", "nodes": "vbn ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "copies Ib into the NMOS bias diode", "fingers": 6, "copies": 1 }, { "name": "M21", "type": "nmos", "nodes": "vbn vbn vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "NMOS bias diode: sets the sinks' gate vbn", "fingers": 4, "copies": 1 }, { "name": "MT", "type": "pmos", "nodes": "tail ib vdd vdd", "sizedBy": [ "Wp", "Lp", "Kt" ], "role": "tail current source: Kt copies of MB", "fingers": 6, "copies": 1 }, { "name": "M1", "type": "pmos", "nodes": "f1 inn tail tail", "sizedBy": [ "W1", "L1" ], "role": "input pair, inverting input; bulk on its source", "fingers": 4, "copies": 1 }, { "name": "M2", "type": "pmos", "nodes": "f2 inp tail tail", "sizedBy": [ "W1", "L1" ], "role": "input pair, non-inverting input; bulk on its source", "fingers": 4, "copies": 1 }, { "name": "M3", "type": "nmos", "nodes": "f1 vbn vss vss", "sizedBy": [ "Wn", "Ln", "Ks" ], "role": "folding sink: Ks copies of M21", "fingers": 4, "copies": 2 }, { "name": "M4", "type": "nmos", "nodes": "f2 vbn vss vss", "sizedBy": [ "Wn", "Ln", "Ks" ], "role": "folding sink: Ks copies of M21", "fingers": 4, "copies": 2 }, { "name": "M5", "type": "nmos", "nodes": "x1 r1 f1 vss", "sizedBy": [ "Wc", "Lc" ], "role": "cascode, mirror side", "fingers": 1, "copies": 1 }, { "name": "M6", "type": "nmos", "nodes": "o1 r2 f2 vss", "sizedBy": [ "Wc", "Lc" ], "role": "cascode, output side", "fingers": 1, "copies": 1 }, { "name": "M7", "type": "pmos", "nodes": "x1 x1 vdd vdd", "sizedBy": [ "Wm", "Lm", "Km" ], "role": "mirror load, diode-connected: Km unit copies", "fingers": 1, "copies": 3 }, { "name": "M8", "type": "pmos", "nodes": "o1 x1 vdd vdd", "sizedBy": [ "Wm", "Lm", "Km" ], "role": "mirror load: the first stage's output o1; Km unit copies", "fingers": 1, "copies": 3 }, { "name": "MR", "type": "pmos", "nodes": "rr ib vdd vdd", "sizedBy": [ "WpReg", "LpReg" ], "role": "regulators' current source: two copies of the regulator PMOS unit", "fingers": 4, "copies": 2 }, { "name": "Rr1", "type": "resistor", "nodes": "rr r1", "sizedBy": [ "Rr" ], "role": "regulator load, mirror side" }, { "name": "Rr2", "type": "resistor", "nodes": "rr r2", "sizedBy": [ "Rr" ], "role": "regulator load, output side" }, { "name": "MA1", "type": "nmos", "nodes": "r1 f1 vss vss", "sizedBy": [ "WnReg", "LnReg" ], "role": "regulator unit: holds f1 near the sink unit's V_GS and drives M5's gate", "fingers": 1, "copies": 1 }, { "name": "MA2", "type": "nmos", "nodes": "r2 f2 vss vss", "sizedBy": [ "WnReg", "LnReg" ], "role": "regulator unit: holds f2 near the sink unit's V_GS and drives M6's gate", "fingers": 1, "copies": 1 }, { "name": "M9", "type": "pmos", "nodes": "d2 o1 vdd vdd", "sizedBy": [ "W2", "L2" ], "role": "second-stage input: turns o1 into a current", "fingers": 1, "copies": 1 }, { "name": "M10", "type": "nmos", "nodes": "d2 g2 vss vss", "sizedBy": [ "Wr", "Lr" ], "role": "second-stage mirror, diode-connected through Rz2", "fingers": 1, "copies": 1 }, { "name": "Rz2", "type": "resistor", "nodes": "d2 g2", "sizedBy": [ "Rz2" ], "role": "active zero: puts M10's gate capacitance behind a resistor" }, { "name": "M11", "type": "nmos", "nodes": "o2 d2 vss vss", "sizedBy": [ "Wr", "Lr" ], "role": "second-stage mirror: drives o2", "fingers": 1, "copies": 1 }, { "name": "M12", "type": "pmos", "nodes": "o2 x1 vdd vdd", "sizedBy": [ "Wm", "Lm", "K2" ], "role": "second-stage load: K2 copies of the M7 unit on x1 - adds the first stage's signal to o2 (cross feedforward)", "fingers": 1, "copies": 1 }, { "name": "M13", "type": "nmos", "nodes": "out o2 vss vss", "sizedBy": [ "W3", "L3", "N3" ], "role": "output device, common source on o2: N3 copies", "fingers": 2, "copies": 4 }, { "name": "M14", "type": "pmos", "nodes": "out o1 vdd vdd", "sizedBy": [ "W2", "L2", "Kf" ], "role": "output source and feedforward path: Kf copies of M9, driven from o1", "fingers": 1, "copies": 32 }, { "name": "Cm", "type": "capacitor", "nodes": "f2 out", "sizedBy": [ "Cm" ], "role": "the only Miller capacitor, returned to o1 through the regulated cascode M6" } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "The input pair: any difference between them is input offset." }, { "rule": "match", "of": [ "M3", "M4" ], "why": "The folding sinks: a mismatch unbalances the cascode currents and appears as offset." }, { "rule": "match", "of": [ "M7", "M8" ], "why": "The mirror load: a mismatch copies the wrong current to o1 and appears as offset." }, { "rule": "unit-copies", "of": [ "MB", "M20", "MT", "MR" ], "constraint": "MT = Kt copies of MB, MR = two regulator-PMOS copies", "why": "Repeating the same unit geometry preserves the intended nominal ratio and avoids geometry-dependent systematic shifts. Random mismatch and unequal drain voltages still cause current-copy errors." }, { "rule": "ratio", "of": [ "M3", "M4", "MT" ], "constraint": "Ks > Kt/2", "why": "Each sink carries its input device's share of the tail and its cascode's current: the cascodes get (Ks − Kt/2)·Ib, which must stay positive, or a cascode turns off and the first stage loses its gain." }, { "rule": "bias", "of": [ "MA1", "MA2", "MR", "Rr1", "Rr2" ], "constraint": "Ib·Rr ≈ 0.2 V", "why": "Each regulator holds its folding node at its own V_GS and drives the cascode's gate; the drop Ib·Rr across its load leaves MR saturated and sets the regulator's gain, (g_m/I_D)·Ib·Rr." }, { "rule": "match", "of": [ "M10", "M11" ], "why": "The second-stage mirror: a mismatch moves the balance between M11 and M12 and appears as offset." }, { "rule": "unit-copies", "of": [ "M9", "M14" ], "constraint": "M14 = Kf copies of M9", "why": "M14 shares M9's gate, o1, so its nominal current is approximately Kf times the second stage's while both devices remain saturated: the output stage's quiescent current is set by a ratio, not by a voltage." }, { "rule": "dominant-pole", "of": [ "Cm", "M1", "M2" ], "constraint": "ω_u ≈ g_m1/C_m", "why": "Cm's current, returned to o1 through M6, makes o1 the dominant pole: the angular unity-gain frequency is the input pair's g_m over Cm." }, { "rule": "current-buffer", "of": [ "M6", "MA2", "Rr2" ], "constraint": "r_x ≈ 1/(g_m6·(1 + g_mA2·R_r))", "why": "MA2 has its own 4 µm unit rather than the 8 µm sink unit, so its capacitance does not pull the local pole down; 200 kΩ then multiplies the cascode's transconductance by about seven. The buffer's corner stays far above the loop Cm closes, which remains damped over corners and mismatch." }, { "rule": "matching-area", "of": [ "M1", "M2", "M3", "M4", "MT", "MB", "M20" ], "constraint": "L1 = 2 µm; Lp = Ln = 8 µm; regulator units LpReg = LnReg = 4 µm", "why": "The input pair and the source and sink units are enlarged together so their random common-mode conversion falls without relying on a cancellation between unlike mismatch terms. The regulator devices stay smaller because giving them the same area moved their local poles into the signal band and made the step ring." }, { "rule": "active-zero", "of": [ "Rz2", "M10", "M11" ], "constraint": "g_m10·R_z2 ≈ 0.75", "why": "Rz2 puts M10's gate capacitance behind a resistor: a zero at 1/(Rz2·C_gs10) cancels the mirror's pole. Much larger, and the diode becomes an active inductor that rings with M11's gate - above about 100 kΩ the step oscillates." }, { "rule": "cross-feedforward", "of": [ "M12", "M7" ], "constraint": "M12 = K2 of the Km units of M7", "why": "M12 on x1 copies the first stage's signal into o2 in phase with the second stage's own: a second feedforward path. Being one of the Km units of the mirror, it sets the second stage's current at a fraction of the mirror's." } ], "specs": [ { "key": "dc_gain_db", "label": "DC open-loop gain", "unit": "dB", "direction": "max", "constraint": ">= 92 dB", "min": 92, "max": null, "why": "About 100 dB at tt: the regulated cascode gives back most of the gain its current ratio costs, and the stages lose a few dB when hot: 92 dB holds at every corner." }, { "key": "ugf_hz", "label": "Unity-gain frequency", "unit": "Hz", "direction": "max", "constraint": ">= 2000000 Hz", "min": 2000000, "max": null, "why": "A few MHz into the 10 pF load at tt; the limit holds at the slow, hot, low-supply corner, where the input pair's g_m is lowest." }, { "key": "pm_deg", "label": "Phase margin", "unit": "deg", "direction": "max", "constraint": ">= 60 deg", "min": 60, "max": null, "why": "A phase-margin target of 60° or more supports a well-damped unity-gain loop, but does not guarantee a ringing-free higher-order response. The separate step and gain-margin benches check additional behavior at the stated conditions." }, { "key": "gm_db", "label": "Gain margin", "unit": "dB", "direction": "max", "constraint": ">= 10 dB", "min": 10, "max": null, "why": "The margin the open-loop phase margin can hide: a three-stage amplifier's non-dominant pole pair can peak, and the gain margin is where that shows." }, { "key": "t_settle", "label": "Settling time, 1 %", "unit": "s", "direction": "min", "constraint": "<= 8e-7 s", "min": null, "max": 8e-7, "why": "The step bench can expose dynamics hidden by an open-loop margin. After the output change tracks 90–110 % of the commanded 0.2 V step, settling is measured within 1 % of that step amplitude around the final output; overshoot is checked separately. This is not a 1 % DC-accuracy limit." }, { "key": "overshoot_pct", "label": "Overshoot", "unit": "%", "direction": "min", "constraint": "<= 5 %", "min": null, "max": 5, "why": "A well-damped closed loop overshoots a few percent at most." }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 70 dB", "min": 70, "max": null, "why": "Supply ripple at 1 kHz reaching the buffer's output, as the rest of the library measures it." }, { "key": "cmrr_db", "label": "Common-mode rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 90 dB", "min": 90, "max": null, "why": "The long input, source and sink units reduce the folded first stage's random imbalance: 119 dB at tt, with the worst of forty mismatch draws still above 91 dB." }, { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.00007 A", "min": null, "max": 0.00007, "why": "Low power is what these compensation schemes are for: the whole amplifier, bias included, stays under this." } ], "explanation": { "idea": "This three-stage amplifier combines a regulated compensation buffer with two direct signal paths to the later stages. A resistor also helps counteract delay in the second-stage mirror. Larger matched devices improve common-mode rejection, while smaller local regulators keep the added feedback loops fast.", "detail": "A three-stage op amp compensated by one capacitor returned through the first stage's regulated cascode, with an active-zero mirror in the second stage and two feedforward paths: the output device on the first stage's output, and the second stage's load on the first stage's mirror node. The load makes the second stage slow, which keeps the loop the capacitor closes well damped. The input pair and the source and sink units use extra area for common-mode matching, while the two regulator transistors keep separate, smaller geometry so their local poles stay fast.", "lesson": { "relation": 1, "symbols": "ω_u is angular unity-gain frequency in rad/s; f_u = ω_u/(2π) is frequency in Hz; g_m1 is the input transistor's transconductance in S; C_m is the main compensation capacitance in F.", "assumptions": "Small signals around the default bias point, with the intended dominant pole and the other internal poles above crossover. Device and load parasitics make the relation approximate.", "exercise": { "param": "Cm", "value": 2.6e-12, "analysis": "open_loop", "expect": "Increasing the compensation capacitance should lower the unity-gain frequency. Compare the phase margin as well; a slower crossover does not by itself prove every internal loop is stable." }, "limits": "Provide the external bias current and use the specified load and common-mode level. Three gain stages contain interacting local loops: inspect gain margin and step settling as well as phase margin after changes." }, "path": [ { "part": "First stage", "devices": "M1, M2, MT, M3, M4, M5, M6, MA1, MA2, Rr1, Rr2, MR, M7, M8", "does": "The PMOS pair M1/M2 on the tail MT folds into the sinks M3/M4 and the cascodes M5/M6. Each cascode's gate is driven by a regulator, MA1 or MA2, off its own source and loaded by Rr1 or Rr2 from the source MR, so the folding nodes f1, f2 are held at the regulators' V_GS and look into a resistance several times lower. The mirror M7/M8 gives the output o1." }, { "part": "Second stage, active zero", "devices": "M9, M10, Rz2, M11", "does": "M9 turns o1 into a current into the diode M10, gated from d2 through Rz2; M11 mirrors it onto o2, with a gain that rises where the mirror's pole would fall." }, { "part": "Cross feedforward", "devices": "M12, M7", "does": "M12, one of the three units the mirror M7/M8 is built from, gated by x1, loads o2 and adds the first stage's signal to it in phase." }, { "part": "Output stage", "devices": "M13, M14", "does": "M13 on o2 sinks and M14 on o1 sources: a push-pull output, and M14, thirty-two copies of M9, is the feedforward path from o1 to the output. Both paths invert, so out follows inp." }, { "part": "Miller capacitor", "devices": "Cm, M6", "does": "Cm injects the output's current into f2, the regulated cascode M6's source, which carries it to o1 and sets the dominant pole." } ], "bias": "The testbench draws Ib (2.5 µA) out of MB. MT is one copy, each 2 µm input device carries half an Ib, and the 8 µm sink units leave 1.5 Ib for each cascode. The regulators MA1 and MA2 use dedicated 4 µm units, fed by a two-unit 4 µm PMOS source MR through Rr1 and Rr2 (200 kΩ); separating them from the 8 µm signal units preserves the regulator poles. M7/M8 are three units each and M12 one, so the second stage runs at 1.27 µA, and M14, thirty-two copies of M9, gives the output 40 µA.", "relations": [ { "what": "DC gain", "expr": "A_0 ≈ g_m1 R_o1 · g_m9 R_o2 · g_m13 R_o3", "note": "R_o1 is set mostly by the mirror M8, R_o2 and R_o3 by the NMOS M11 and M13, whose V_A is only 2-3 V: the reason those two are long." }, { "what": "Unity-gain frequency", "expr": "ω_u ≈ g_m1/C_m", "note": "About 3.6 MHz with Cm at 1.3 pF." }, { "what": "Buffer resistance", "expr": "r_x ≈ 1/(g_m6 (1 + g_m,MA2 R_r))", "note": "The 4 µm regulator unit and 200 kΩ load give a local gain near six without the capacitance of the 8 µm sink unit; the current buffer stays above the Miller loop over corners and mismatch." }, { "what": "Active zero", "expr": "i_M11/i_M9 ≈ (1 + s R_z2 C_gs10)/(1 + s C_d2/g_m10 + s^2 R_z2 C_gs10 C_d2/g_m10)", "note": "ζ ≈ 0.5 √(C_d2/(g_m10 R_z2 C_gs10)): with g_m10·Rz2 near 0.75 the mirror is just damped; much larger and it rings." } ], "tradeoffs": [ "Rz2: about 20 kΩ helps; much larger and the mirror rings.", "Km: more units per mirror make the second stage slower through M12, and the loop Cm closes better damped.", "Cm: larger lowers ω_u and raises the phase margin.", "First-stage area: longer input, source and sink units improve common-mode rejection, but using the 8 µm sink geometry in MA1 and MA2 pulled the regulator poles down and made the step ring; the dedicated 4 µm units avoid that tradeoff.", "Rr: 200 kΩ restores regulator gain with the smaller MA1 and MA2 units; lower values lost gain margin, while the verified value keeps MR saturated at every corner." ] }, "sizing": [ { "key": "Ib", "label": "Reference current", "unit": "A", "value": 0.0000025, "min": 5e-7, "max": 0.00002, "kind": "si" }, { "key": "Wp", "label": "W PMOS source unit (MB and its copies)", "unit": "m", "value": 0.0000215, "min": 5e-7, "max": 0.00005, "kind": "si" }, { "key": "Lp", "label": "L PMOS source unit", "unit": "m", "value": 0.000008, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "W1", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.0000179, "min": 5e-7, "max": 0.0001, "kind": "si" }, { "key": "L1", "label": "L input pair", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Wn", "label": "W NMOS sink unit (M21 and its copies)", "unit": "m", "value": 0.0000108, "min": 3e-7, "max": 0.00005, "kind": "si" }, { "key": "Ln", "label": "L NMOS sink unit", "unit": "m", "value": 0.000008, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Rr", "label": "Regulator load resistors (Rr1, Rr2)", "unit": "Ω", "value": 200000, "min": 10000, "max": 500000, "kind": "si" }, { "key": "Wc", "label": "W cascode unit (M5, M6)", "unit": "m", "value": 0.0000049, "min": 3e-7, "max": 0.00005, "kind": "si" }, { "key": "Lc", "label": "L cascode unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Wm", "label": "W mirror-load unit (M7, M8, M12)", "unit": "m", "value": 0.000004, "min": 5e-7, "max": 0.0001, "kind": "si" }, { "key": "Lm", "label": "L mirror-load unit", "unit": "m", "value": 0.000003, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Km", "label": "Mirror-load copies (M7, M8)", "unit": "", "value": 3, "min": 1, "max": 16, "kind": "int" }, { "key": "W2", "label": "W second-stage PMOS unit (M9, M14)", "unit": "m", "value": 0.0000025, "min": 5e-7, "max": 0.0001, "kind": "si" }, { "key": "L2", "label": "L second-stage PMOS unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Wr", "label": "W second-stage mirror (M10, M11)", "unit": "m", "value": 0.0000027, "min": 3e-7, "max": 0.0001, "kind": "si" }, { "key": "Lr", "label": "L second-stage mirror", "unit": "m", "value": 0.000004, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Rz2", "label": "Active-zero resistor in M10's gate", "unit": "Ω", "value": 20000, "min": 0, "max": 500000, "kind": "si" }, { "key": "W3", "label": "W output NMOS unit (M13)", "unit": "m", "value": 0.0000057, "min": 3e-7, "max": 0.0001, "kind": "si" }, { "key": "L3", "label": "L output NMOS unit", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Kt", "label": "Tail current, in Ib", "unit": "", "value": 1, "min": 1, "max": 16, "kind": "int" }, { "key": "Ks", "label": "Folding-sink current, in Ib", "unit": "", "value": 2, "min": 1, "max": 16, "kind": "int" }, { "key": "K2", "label": "Second-stage current, in unit copies", "unit": "", "value": 1, "min": 1, "max": 40, "kind": "int" }, { "key": "Kf", "label": "Output-stage current, in second-stage currents", "unit": "", "value": 32, "min": 1, "max": 40, "kind": "int" }, { "key": "N3", "label": "Output NMOS copies", "unit": "", "value": 4, "min": 1, "max": 40, "kind": "int" }, { "key": "WpReg", "label": "W regulator PMOS unit (MR)", "unit": "m", "value": 0.0000108, "min": 5e-7, "max": 0.00005, "kind": "si" }, { "key": "LpReg", "label": "L regulator PMOS unit (MR)", "unit": "m", "value": 0.000004, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "WnReg", "label": "W regulator NMOS unit (MA1, MA2)", "unit": "m", "value": 0.0000029, "min": 3e-7, "max": 0.00005, "kind": "si" }, { "key": "LnReg", "label": "L regulator NMOS unit (MA1, MA2)", "unit": "m", "value": 0.000004, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Cm", "label": "Miller capacitor (to f2)", "unit": "F", "value": 1.3e-12, "min": 2e-13, "max": 1e-11, "kind": "si" }, { "key": "CL", "label": "Load capacitance", "unit": "F", "value": 1e-11, "min": 1e-12, "max": 1e-10, "kind": "si" }, { "key": "VCM", "label": "Input common mode", "unit": "V", "value": 0.4, "min": 0, "max": 0.6, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.", "measures": [], "metricKeys": [ "i_supply", "vout_dc", "vos" ], "acceptance": [ "i_supply" ], "acceptanceRules": [ { "key": "i_supply", "unit": "A", "min": null, "max": 0.00007, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Three-stage op amp, active zero, cross feedforward - operating point as a unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 2.5u\n.subckt ota3az inp inn out vdd vss ib\n* bias: Ib into the PMOS diode MB; M20 copies it into the NMOS diode M21, which sets vbn\nXMB ib ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1\nXM20 vbn ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1\nXM21 vbn vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=1\n* first stage: PMOS pair M1/M2 on tail MT, folded into sinks M3/M4 and cascodes M5/M6 regulated by MA1/MA2, mirror load M7/M8 - o1 falls as inp rises\nXMT tail ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1\nXM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1\nXM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1\nXM3 f1 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2\nXM4 f2 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2\nXM5 x1 r1 f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM6 o1 r2 f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM7 x1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3\nXM8 o1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3\nXMR rr ib vdd vdd sg13_lv_pmos w=10.8u l=4u ng=4 m=2\nXRr1 rr r1 vss rhigh w=0.5u l=61.666u\nXRr2 rr r2 vss rhigh w=0.5u l=61.666u\nXMA1 r1 f1 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1\nXMA2 r2 f2 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1\n* second stage: M9 into the NMOS mirror M10/M11 (with an active zero), against M12 on x1 - o2 rises with o1\nXM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=1\nXM10 d2 g2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1\nXRz2 d2 g2 vss rhigh w=0.5u l=6.078u\nXM11 o2 d2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1\nXM12 o2 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=1\n* output stage: M13 on o2 sinks, M14 on o1 sources - a push-pull output that feeds o1 forward\nXM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4\nXM14 out o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=32\n* Miller capacitor Cm from out into f2, returned to o1 through the regulated cascode M6\nXCm f2 out cap_cmim w=29.386u l=29.386u\n.ends\nXdut inp inn out vdd 0 ib ota3az\nCl out 0 10p\nVin inp 0 dc 400m\n* the output drives the inverting input: a unity-gain buffer\nVfb inn out 0\n.op\n.end" }, { "id": "open_loop", "label": "Open-loop gain", "note": "Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.", "measures": [], "metricKeys": [ "dc_gain_db", "ugf_hz", "pm_deg", "gm_db" ], "acceptance": [ "dc_gain_db", "ugf_hz", "pm_deg", "gm_db" ], "acceptanceRules": [ { "key": "dc_gain_db", "unit": "dB", "min": 92, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "ugf_hz", "unit": "Hz", "min": 2000000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "pm_deg", "unit": "deg", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "gm_db", "unit": "dB", "min": 10, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Three-stage op amp, active zero, cross feedforward - open-loop gain and phase\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 2.5u\n.subckt ota3az inp inn out vdd vss ib\n* bias: Ib into the PMOS diode MB; M20 copies it into the NMOS diode M21, which sets vbn\nXMB ib ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1\nXM20 vbn ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1\nXM21 vbn vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=1\n* first stage: PMOS pair M1/M2 on tail MT, folded into sinks M3/M4 and cascodes M5/M6 regulated by MA1/MA2, mirror load M7/M8 - o1 falls as inp rises\nXMT tail ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1\nXM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1\nXM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1\nXM3 f1 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2\nXM4 f2 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2\nXM5 x1 r1 f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM6 o1 r2 f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM7 x1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3\nXM8 o1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3\nXMR rr ib vdd vdd sg13_lv_pmos w=10.8u l=4u ng=4 m=2\nXRr1 rr r1 vss rhigh w=0.5u l=61.666u\nXRr2 rr r2 vss rhigh w=0.5u l=61.666u\nXMA1 r1 f1 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1\nXMA2 r2 f2 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1\n* second stage: M9 into the NMOS mirror M10/M11 (with an active zero), against M12 on x1 - o2 rises with o1\nXM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=1\nXM10 d2 g2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1\nXRz2 d2 g2 vss rhigh w=0.5u l=6.078u\nXM11 o2 d2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1\nXM12 o2 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=1\n* output stage: M13 on o2 sinks, M14 on o1 sources - a push-pull output that feeds o1 forward\nXM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4\nXM14 out o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=32\n* Miller capacitor Cm from out into f2, returned to o1 through the regulated cascode M6\nXCm f2 out cap_cmim w=29.386u l=29.386u\n.ends\nXdut inp inn out vdd 0 ib ota3az\nCl out 0 10p\nVin inp 0 dc 400m ac 1\n* the loop closed at DC and open at every frequency the sweep visits\nLfb out inn 1t\nCfb inn 0 1t\n.ac dec 25 0.1 10g\n.end" }, { "id": "step", "label": "Step response", "note": "A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.", "measures": [], "metricKeys": [ "sr", "t_settle", "overshoot_pct" ], "acceptance": [ "t_settle", "overshoot_pct" ], "acceptanceRules": [ { "key": "t_settle", "unit": "s", "min": null, "max": 8e-7, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "overshoot_pct", "unit": "%", "min": null, "max": 5, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Three-stage op amp, active zero, cross feedforward - step response of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 2.5u\n.subckt ota3az inp inn out vdd vss ib\n* bias: Ib into the PMOS diode MB; M20 copies it into the NMOS diode M21, which sets vbn\nXMB ib ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1\nXM20 vbn ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1\nXM21 vbn vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=1\n* first stage: PMOS pair M1/M2 on tail MT, folded into sinks M3/M4 and cascodes M5/M6 regulated by MA1/MA2, mirror load M7/M8 - o1 falls as inp rises\nXMT tail ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1\nXM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1\nXM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1\nXM3 f1 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2\nXM4 f2 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2\nXM5 x1 r1 f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM6 o1 r2 f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM7 x1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3\nXM8 o1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3\nXMR rr ib vdd vdd sg13_lv_pmos w=10.8u l=4u ng=4 m=2\nXRr1 rr r1 vss rhigh w=0.5u l=61.666u\nXRr2 rr r2 vss rhigh w=0.5u l=61.666u\nXMA1 r1 f1 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1\nXMA2 r2 f2 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1\n* second stage: M9 into the NMOS mirror M10/M11 (with an active zero), against M12 on x1 - o2 rises with o1\nXM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=1\nXM10 d2 g2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1\nXRz2 d2 g2 vss rhigh w=0.5u l=6.078u\nXM11 o2 d2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1\nXM12 o2 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=1\n* output stage: M13 on o2 sinks, M14 on o1 sources - a push-pull output that feeds o1 forward\nXM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4\nXM14 out o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=32\n* Miller capacitor Cm from out into f2, returned to o1 through the regulated cascode M6\nXCm f2 out cap_cmim w=29.386u l=29.386u\n.ends\nXdut inp inn out vdd 0 ib ota3az\nCl out 0 10p\nVin inp 0 pulse(300m 500m 400n 1n 1n 2u 8u)\nVfb inn out 0\n.tran 1000p 4u\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.", "measures": [], "metricKeys": [ "psrr_db" ], "acceptance": [ "psrr_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 70, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Three-stage op amp, active zero, cross feedforward - supply rejection of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD} ac 1\nIb ib 0 2.5u\n.subckt ota3az inp inn out vdd vss ib\n* bias: Ib into the PMOS diode MB; M20 copies it into the NMOS diode M21, which sets vbn\nXMB ib ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1\nXM20 vbn ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1\nXM21 vbn vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=1\n* first stage: PMOS pair M1/M2 on tail MT, folded into sinks M3/M4 and cascodes M5/M6 regulated by MA1/MA2, mirror load M7/M8 - o1 falls as inp rises\nXMT tail ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1\nXM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1\nXM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1\nXM3 f1 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2\nXM4 f2 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2\nXM5 x1 r1 f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM6 o1 r2 f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM7 x1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3\nXM8 o1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3\nXMR rr ib vdd vdd sg13_lv_pmos w=10.8u l=4u ng=4 m=2\nXRr1 rr r1 vss rhigh w=0.5u l=61.666u\nXRr2 rr r2 vss rhigh w=0.5u l=61.666u\nXMA1 r1 f1 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1\nXMA2 r2 f2 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1\n* second stage: M9 into the NMOS mirror M10/M11 (with an active zero), against M12 on x1 - o2 rises with o1\nXM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=1\nXM10 d2 g2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1\nXRz2 d2 g2 vss rhigh w=0.5u l=6.078u\nXM11 o2 d2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1\nXM12 o2 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=1\n* output stage: M13 on o2 sinks, M14 on o1 sources - a push-pull output that feeds o1 forward\nXM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4\nXM14 out o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=32\n* Miller capacitor Cm from out into f2, returned to o1 through the regulated cascode M6\nXCm f2 out cap_cmim w=29.386u l=29.386u\n.ends\nXdut inp inn out vdd 0 ib ota3az\nCl out 0 10p\nVin inp 0 dc 400m\nVfb inn out 0\n.ac dec 25 1 100meg\n.end" }, { "id": "cmrr", "label": "Common-mode rejection", "note": "Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.", "measures": [], "metricKeys": [ "cmrr_db" ], "acceptance": [ "cmrr_db" ], "acceptanceRules": [ { "key": "cmrr_db", "unit": "dB", "min": 90, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Three-stage op amp, active zero, cross feedforward - common-mode rejection\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 2.5u\n.subckt ota3az inp inn out vdd vss ib\n* bias: Ib into the PMOS diode MB; M20 copies it into the NMOS diode M21, which sets vbn\nXMB ib ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1\nXM20 vbn ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1\nXM21 vbn vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=1\n* first stage: PMOS pair M1/M2 on tail MT, folded into sinks M3/M4 and cascodes M5/M6 regulated by MA1/MA2, mirror load M7/M8 - o1 falls as inp rises\nXMT tail ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1\nXM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1\nXM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1\nXM3 f1 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2\nXM4 f2 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2\nXM5 x1 r1 f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM6 o1 r2 f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM7 x1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3\nXM8 o1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3\nXMR rr ib vdd vdd sg13_lv_pmos w=10.8u l=4u ng=4 m=2\nXRr1 rr r1 vss rhigh w=0.5u l=61.666u\nXRr2 rr r2 vss rhigh w=0.5u l=61.666u\nXMA1 r1 f1 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1\nXMA2 r2 f2 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1\n* second stage: M9 into the NMOS mirror M10/M11 (with an active zero), against M12 on x1 - o2 rises with o1\nXM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=1\nXM10 d2 g2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1\nXRz2 d2 g2 vss rhigh w=0.5u l=6.078u\nXM11 o2 d2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1\nXM12 o2 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=1\n* output stage: M13 on o2 sinks, M14 on o1 sources - a push-pull output that feeds o1 forward\nXM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4\nXM14 out o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=32\n* Miller capacitor Cm from out into f2, returned to o1 through the regulated cascode M6\nXCm f2 out cap_cmim w=29.386u l=29.386u\n.ends\nXdut inp inn out vdd 0 ib ota3az\nCl out 0 10p\nVsrc src 0 dc 400m\n* va on the non-inverting input, vb in the feedback path: both inputs move with the signal\nVa inp src dc 0 ac 1\nVb inn out dc 0 ac 1\n.ac dec 25 1 100meg\n.end" }, { "id": "noise", "label": "Noise", "note": "Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.", "measures": [], "metricKeys": [ "vn_1k", "vn_int" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Three-stage op amp, active zero, cross feedforward - input-referred noise\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 2.5u\n.subckt ota3az inp inn out vdd vss ib\n* bias: Ib into the PMOS diode MB; M20 copies it into the NMOS diode M21, which sets vbn\nXMB ib ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1\nXM20 vbn ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1\nXM21 vbn vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=1\n* first stage: PMOS pair M1/M2 on tail MT, folded into sinks M3/M4 and cascodes M5/M6 regulated by MA1/MA2, mirror load M7/M8 - o1 falls as inp rises\nXMT tail ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1\nXM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1\nXM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1\nXM3 f1 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2\nXM4 f2 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2\nXM5 x1 r1 f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM6 o1 r2 f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM7 x1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3\nXM8 o1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3\nXMR rr ib vdd vdd sg13_lv_pmos w=10.8u l=4u ng=4 m=2\nXRr1 rr r1 vss rhigh w=0.5u l=61.666u\nXRr2 rr r2 vss rhigh w=0.5u l=61.666u\nXMA1 r1 f1 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1\nXMA2 r2 f2 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1\n* second stage: M9 into the NMOS mirror M10/M11 (with an active zero), against M12 on x1 - o2 rises with o1\nXM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=1\nXM10 d2 g2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1\nXRz2 d2 g2 vss rhigh w=0.5u l=6.078u\nXM11 o2 d2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1\nXM12 o2 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=1\n* output stage: M13 on o2 sinks, M14 on o1 sources - a push-pull output that feeds o1 forward\nXM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4\nXM14 out o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=32\n* Miller capacitor Cm from out into f2, returned to o1 through the regulated cascode M6\nXCm f2 out cap_cmim w=29.386u l=29.386u\n.ends\nXdut inp inn out vdd 0 ib ota3az\nCl out 0 10p\nVin inp 0 dc 400m ac 1\nVfb inn out 0\n.control\nnoise v(out) Vin dec 20 1 1meg\nsetplot noise1\n* 20 points a decade from 1 Hz: point 60 is 1 kHz\nlet vn_1k = inoise_spectrum[60]\nprint vn_1k\nsetplot noise2\nprint inoise_total\n.endc\n.op\n.end" } ], "measurements": { "dc_gain_db": { "label": "DC open-loop gain", "unit": "dB", "spec": { "min": 92, "max": null } }, "ugf_hz": { "label": "Unity-gain frequency", "unit": "Hz", "spec": { "min": 2000000, "max": null } }, "pm_deg": { "label": "Phase margin", "unit": "deg", "spec": { "min": 60, "max": null } }, "gm_db": { "label": "Gain margin", "unit": "dB", "spec": { "min": 10, "max": null } }, "t_settle": { "label": "Settling time, 1 %", "unit": "s", "spec": { "min": null, "max": 8e-7 } }, "overshoot_pct": { "label": "Overshoot", "unit": "%", "spec": { "min": null, "max": 5 } }, "psrr_db": { "label": "Supply rejection at 1 kHz", "unit": "dB", "spec": { "min": 70, "max": null } }, "cmrr_db": { "label": "Common-mode rejection at 1 kHz", "unit": "dB", "spec": { "min": 90, "max": null } }, "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.00007 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "c6c47fe6d333f11412aa8eb032ab9181474ccaee3fa4e04bf7cd26cd09ba6fc0" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ota3-az.js", "sha256": "caa861f624f2a1d936e191c8ec3aac112bd38d488cea784a4cb84f384823469c" }, "simulationFingerprints": { "op": "908d167bdc80378457bb2f295abd214ed661e58042647134509e5fdd4aed8804", "open_loop": "f15998fc33ed53b46cc720c986b4ac6cc823a30cb591610ab4bafb3733ece652", "step": "57e7b047c796bcd061338e3039bf2825ef16b5ad47a4a46ff55dd0b259ad8c34", "psrr": "27022421c8396205727b9a911f4c8d50d2925b4357ddb147ce5dd2066353010e", "cmrr": "39bb3b0c2c2dd70d329aa27b28a8650d293bdec6a0173b08f86a73c60e841b5a", "noise": "6c8a19ec0db651a1960cd0ea445d6e158f5f58a6c627f1932d2d6e1fa2fc1d7c" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "9ea9bb0923dc4f0f0ed31939ebe24336b07ad4b18cc619e63f2511252b76e4e6", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ota3-az", "parameters": { "Ib": 0.0000025, "Wp": 0.0000215, "Lp": 0.000008, "W1": 0.0000179, "L1": 0.000002, "Wn": 0.0000108, "Ln": 0.000008, "Rr": 200000, "Wc": 0.0000049, "Lc": 0.000001, "Wm": 0.000004, "Lm": 0.000003, "Km": 3, "W2": 0.0000025, "L2": 0.000001, "Wr": 0.0000027, "Lr": 0.000004, "Rz2": 20000, "W3": 0.0000057, "L3": 0.000002, "Kt": 1, "Ks": 2, "K2": 1, "Kf": 32, "N3": 4, "WpReg": 0.0000108, "LpReg": 0.000004, "WnReg": 0.0000029, "LnReg": 0.000004, "Cm": 1.3e-12, "CL": 1e-11, "VCM": 0.4 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ota3-az/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "ota3az", "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XM20 vbn ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM21", "displayName": "M21", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10.8u l=8u ng=4 m=1", "source": "XM21 vbn vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=17.9u l=2u ng=4 m=1", "source": "XM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=17.9u l=2u ng=4 m=1", "source": "XM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10.8u l=8u ng=4 m=2", "source": "XM3 f1 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10.8u l=8u ng=4 m=2", "source": "XM4 f2 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM5 x1 r1 f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "r1" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM6 o1 r2 f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "r2" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=3u ng=1 m=3", "source": "XM7 x1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=3u ng=1 m=3", "source": "XM8 o1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR", "displayName": "MR", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10.8u l=4u ng=4 m=2", "source": "XMR rr ib vdd vdd sg13_lv_pmos w=10.8u l=4u ng=4 m=2", "pins": [ { "id": "d", "net": "rr" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRr1", "displayName": "Rr1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRr1 rr r1 vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "rr" }, { "id": "n", "net": "r1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRr2", "displayName": "Rr2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRr2 rr r2 vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "rr" }, { "id": "n", "net": "r2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.9u l=4u ng=1 m=1", "source": "XMA1 r1 f1 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "r1" }, { "id": "g", "net": "f1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.9u l=4u ng=1 m=1", "source": "XMA2 r2 f2 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "r2" }, { "id": "g", "net": "f2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.5u l=1u ng=1 m=1", "source": "XM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.7u l=4u ng=1 m=1", "source": "XM10 d2 g2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "g2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRz2", "displayName": "Rz2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRz2 d2 g2 vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "g2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.7u l=4u ng=1 m=1", "source": "XM11 o2 d2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=3u ng=1 m=1", "source": "XM12 o2 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=2u ng=2 m=4", "source": "XM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.5u l=1u ng=1 m=32", "source": "XM14 out o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=32", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCm", "displayName": "Cm", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.386u l=29.386u", "source": "XCm f2 out cap_cmim w=29.386u l=29.386u", "pins": [ { "id": "p", "net": "f2" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM20", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMR", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM20", "pin": "s" }, { "device": "XM20", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XMR", "pin": "s" }, { "device": "XMR", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XM20", "pin": "d" }, { "device": "XM21", "pin": "d" }, { "device": "XM21", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM21", "pin": "s" }, { "device": "XM21", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XRr1", "pin": "substrate" }, { "device": "XRr2", "pin": "substrate" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "s" }, { "device": "XMA2", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XRz2", "pin": "substrate" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" }, { "device": "XMA1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" }, { "device": "XMA2", "pin": "g" }, { "device": "XCm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM12", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "r1", "ground": false, "terminals": [ { "device": "XM5", "pin": "g" }, { "device": "XRr1", "pin": "n" }, { "device": "XMA1", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "r2", "ground": false, "terminals": [ { "device": "XM6", "pin": "g" }, { "device": "XRr2", "pin": "n" }, { "device": "XMA2", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "rr", "ground": false, "terminals": [ { "device": "XMR", "pin": "d" }, { "device": "XRr1", "pin": "p" }, { "device": "XRr2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XRz2", "pin": "p" }, { "device": "XM11", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "g2", "ground": false, "terminals": [ { "device": "XM10", "pin": "g" }, { "device": "XRz2", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM13", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM13", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XCm", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2.5u", "source": "Ib ib 0 2.5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota3az", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota3az", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota3az" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m", "source": "Vin inp 0 dc 400m", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota3az", "name": "ota3az", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XM20 vbn ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM21", "displayName": "M21", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10.8u l=8u ng=4 m=1", "source": "XM21 vbn vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=17.9u l=2u ng=4 m=1", "source": "XM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inn" }, { 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vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM5 x1 r1 f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "r1" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM6 o1 r2 f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "r2" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=3u ng=1 m=3", "source": "XM7 x1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=3u ng=1 m=3", "source": "XM8 o1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR", "displayName": "MR", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10.8u l=4u ng=4 m=2", "source": "XMR rr ib vdd vdd sg13_lv_pmos w=10.8u l=4u ng=4 m=2", "pins": [ { "id": "d", "net": "rr" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRr1", "displayName": "Rr1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRr1 rr r1 vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "rr" }, { "id": "n", "net": "r1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRr2", "displayName": "Rr2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRr2 rr r2 vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "rr" }, { "id": "n", "net": "r2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.9u l=4u ng=1 m=1", "source": "XMA1 r1 f1 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "r1" }, { "id": "g", "net": "f1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], 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"net": "d2" }, { "id": "g", "net": "g2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRz2", "displayName": "Rz2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRz2 d2 g2 vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "g2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.7u l=4u ng=1 m=1", "source": "XM11 o2 d2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=3u ng=1 m=1", "source": "XM12 o2 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=2u ng=2 m=4", "source": "XM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.5u l=1u ng=1 m=32", "source": "XM14 out o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=32", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCm", "displayName": "Cm", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.386u l=29.386u", "source": "XCm f2 out cap_cmim w=29.386u l=29.386u", "pins": [ { "id": "p", "net": "f2" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM20", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMR", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM20", "pin": "s" }, { "device": "XM20", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XMR", "pin": "s" }, { "device": "XMR", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XM20", "pin": "d" }, { "device": "XM21", "pin": "d" }, { "device": "XM21", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM21", "pin": "s" }, { "device": "XM21", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XRr1", "pin": "substrate" }, { "device": "XRr2", "pin": "substrate" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "s" }, { "device": "XMA2", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XRz2", "pin": "substrate" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" }, { "device": "XMA1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" }, { "device": "XMA2", "pin": "g" }, { "device": "XCm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM12", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "r1", "ground": false, "terminals": [ { "device": "XM5", "pin": "g" }, { "device": "XRr1", "pin": "n" }, { "device": "XMA1", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "r2", "ground": false, "terminals": [ { "device": "XM6", "pin": "g" }, { "device": "XRr2", "pin": "n" }, { "device": "XMA2", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "rr", "ground": false, "terminals": [ { "device": "XMR", "pin": "d" }, { "device": "XRr1", "pin": "p" }, { "device": "XRr2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XRz2", "pin": "p" }, { "device": "XM11", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "g2", "ground": false, "terminals": [ { "device": "XM10", "pin": "g" }, { "device": "XRz2", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM13", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM13", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XCm", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota3az" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Bias reference", "devices": [ { "scope": "dut", "device": "XMB" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "Copies Ib into the NMOS bias diode", "devices": [ { "scope": "dut", "device": "XM20" } ], "inferredStages": [ "bias" ] }, { "id": "block-3", "label": "NMOS bias diode: sets the sinks' gate vbn", "devices": [ { "scope": "dut", "device": "XM21" } ], "inferredStages": [ "bias" ] }, { "id": "block-4", "label": "Tail current source: Kt copies of MB", "devices": [ { "scope": "dut", "device": "XMT" } ], "inferredStages": [ 1 ] }, { "id": "block-5", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 1 ] }, { "id": "block-6", "label": "Folding sink: Ks copies of M21", "devices": [ { "scope": "dut", "device": "XM3" }, { "scope": "dut", "device": "XM4" } ], "inferredStages": [ 1 ] }, { "id": "block-7", "label": "Cascode", "devices": [ { "scope": "dut", "device": "XM5" }, { "scope": "dut", "device": "XM6" } ], "inferredStages": [ 2 ] }, { "id": "block-8", "label": "Mirror load", "devices": [ { "scope": "dut", "device": "XM7" } ], "inferredStages": [ 2 ] }, { "id": "block-9", "label": "Mirror load: the first stage's output o1; Km unit copies", "devices": [ { "scope": "dut", "device": "XM8" } ], "inferredStages": [ 2 ] }, { "id": "block-10", "label": "Regulators' current source: two copies of the regulator PMOS unit", "devices": [ { "scope": "dut", "device": "XMR" } ], "inferredStages": [ "bias" ] }, { "id": "block-11", "label": "Regulator load", "devices": [ { "scope": "dut", "device": "XRr1" }, { "scope": "dut", "device": "XRr2" } ], "inferredStages": [ 2 ] }, { "id": "block-12", "label": "Regulator unit: holds f1 near the sink unit's V_GS and drives M5's gate", "devices": [ { "scope": "dut", "device": "XMA1" } ], "inferredStages": [ 2 ] }, { "id": "block-13", "label": "Regulator unit: holds f2 near the sink unit's V_GS and drives M6's gate", "devices": [ { "scope": "dut", "device": "XMA2" } ], "inferredStages": [ 2 ] }, { "id": "block-14", "label": "Second-stage input: turns o1 into a current", "devices": [ { "scope": "dut", "device": "XM9" } ], "inferredStages": [ 3 ] }, { "id": "block-15", "label": "Second-stage mirror", "devices": [ { "scope": "dut", "device": "XM10" } ], "inferredStages": [ 3 ] }, { "id": "block-16", "label": "Active zero: puts M10's gate capacitance behind a resistor", "devices": [ { "scope": "dut", "device": "XRz2" } ], "inferredStages": [ 3 ] }, { "id": "block-17", "label": "Second-stage mirror: drives o2", "devices": [ { "scope": "dut", "device": "XM11" } ], "inferredStages": [ 3 ] }, { "id": "block-18", "label": "Second-stage load: K2 copies of the M7 unit on x1 - adds the first stage's signal to o2 (cross feedforward)", "devices": [ { "scope": "dut", "device": "XM12" } ], "inferredStages": [ 3 ] }, { "id": "block-19", "label": "Output device", "devices": [ { "scope": "dut", "device": "XM13" } ], "inferredStages": [ 3 ] }, { "id": "block-20", "label": "Output source and feedforward path: Kf copies of M9", "devices": [ { "scope": "dut", "device": "XM14" } ], "inferredStages": [ 3 ] }, { "id": "block-21", "label": "The only Miller capacitor", "devices": [ { "scope": "dut", "device": "XCm" } ], "inferredStages": [ "comp" ] } ], "edges": [ { "id": "net-1", "net": "ib", "nodes": [ "block-1", "block-2", "block-4", "block-10" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "vbn", "nodes": [ "block-2", "block-3", "block-6" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "tail", "nodes": [ "block-4", "block-5" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "f1", "nodes": [ "block-5", "block-6", "block-7", "block-12" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "f2", "nodes": [ "block-5", "block-6", "block-7", "block-13", "block-21" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "x1", "nodes": [ "block-7", "block-8", "block-9", "block-18" ], "direction": "undirected-shared-net" }, { "id": "net-7", "net": "r1", "nodes": [ "block-7", "block-11", "block-12" ], "direction": "undirected-shared-net" }, { "id": "net-8", "net": "o1", "nodes": [ "block-7", "block-9", "block-14", "block-20" ], "direction": "undirected-shared-net" }, { "id": "net-9", "net": "r2", "nodes": [ "block-7", "block-11", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-10", "net": "rr", "nodes": [ "block-10", "block-11" ], "direction": "undirected-shared-net" }, { "id": "net-11", "net": "d2", "nodes": [ "block-14", "block-15", "block-16", "block-17" ], "direction": "undirected-shared-net" }, { "id": "net-12", "net": "g2", "nodes": [ "block-15", "block-16" ], "direction": "undirected-shared-net" }, { "id": "net-13", "net": "o2", "nodes": [ "block-17", "block-18", "block-19" ], "direction": "undirected-shared-net" }, { "id": "net-14", "net": "out", "nodes": [ "block-19", "block-20", "block-21" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2.5u", "source": "Ib ib 0 2.5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota3az", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota3az", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota3az" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m ac 1", "source": "Vin inp 0 dc 400m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfb", "displayName": "Lfb", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfb out inn 1t", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cfb", "displayName": "Cfb", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cfb inn 0 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" }, { "device": "Cfb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Lfb", "pin": "n" }, { "device": "Cfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Lfb", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota3az", "name": "ota3az", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XM20 vbn ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM21", "displayName": "M21", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10.8u l=8u ng=4 m=1", "source": "XM21 vbn vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=17.9u l=2u ng=4 m=1", "source": "XM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=17.9u l=2u ng=4 m=1", "source": "XM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10.8u l=8u ng=4 m=2", "source": "XM3 f1 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10.8u l=8u ng=4 m=2", "source": "XM4 f2 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM5 x1 r1 f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "r1" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM6 o1 r2 f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "r2" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=3u ng=1 m=3", "source": "XM7 x1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=3u ng=1 m=3", "source": "XM8 o1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR", "displayName": "MR", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10.8u l=4u ng=4 m=2", "source": "XMR rr ib vdd vdd sg13_lv_pmos w=10.8u l=4u ng=4 m=2", "pins": [ { "id": "d", "net": "rr" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRr1", "displayName": "Rr1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRr1 rr r1 vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "rr" }, { "id": "n", "net": "r1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRr2", "displayName": "Rr2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRr2 rr r2 vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "rr" }, { "id": "n", "net": "r2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.9u l=4u ng=1 m=1", "source": "XMA1 r1 f1 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "r1" }, { "id": "g", "net": "f1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.9u l=4u ng=1 m=1", "source": "XMA2 r2 f2 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "r2" }, { "id": "g", "net": "f2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.5u l=1u ng=1 m=1", "source": "XM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.7u l=4u ng=1 m=1", "source": "XM10 d2 g2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "g2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRz2", "displayName": "Rz2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRz2 d2 g2 vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "g2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.7u l=4u ng=1 m=1", "source": "XM11 o2 d2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=3u ng=1 m=1", "source": "XM12 o2 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=2u ng=2 m=4", "source": "XM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.5u l=1u ng=1 m=32", "source": "XM14 out o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=32", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCm", "displayName": "Cm", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.386u l=29.386u", "source": "XCm f2 out cap_cmim w=29.386u l=29.386u", "pins": [ { "id": "p", "net": "f2" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM20", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMR", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM20", "pin": "s" }, { "device": "XM20", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XMR", "pin": "s" }, { "device": "XMR", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XM20", "pin": "d" }, { "device": "XM21", "pin": "d" }, { "device": "XM21", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM21", "pin": "s" }, { "device": "XM21", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XRr1", "pin": "substrate" }, { "device": "XRr2", "pin": "substrate" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "s" }, { "device": "XMA2", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XRz2", "pin": "substrate" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" }, { "device": "XMA1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" }, { "device": "XMA2", "pin": "g" }, { "device": "XCm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM12", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "r1", "ground": false, "terminals": [ { "device": "XM5", "pin": "g" }, { "device": "XRr1", "pin": "n" }, { "device": "XMA1", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "r2", "ground": false, "terminals": [ { "device": "XM6", "pin": "g" }, { "device": "XRr2", "pin": "n" }, { "device": "XMA2", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "rr", "ground": false, "terminals": [ { "device": "XMR", "pin": "d" }, { "device": "XRr1", "pin": "p" }, { "device": "XRr2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XRz2", "pin": "p" }, { "device": "XM11", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "g2", "ground": false, "terminals": [ { "device": "XM10", "pin": "g" }, { "device": "XRz2", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM13", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM13", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XCm", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota3az" } }, { "id": "graph-5", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2.5u", "source": "Ib ib 0 2.5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota3az", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota3az", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota3az" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "pulse(300m 500m 400n 1n 1n 2u 8u)", "source": "Vin inp 0 pulse(300m 500m 400n 1n 1n 2u 8u)", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota3az", "name": "ota3az", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XM20 vbn ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM21", "displayName": "M21", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10.8u l=8u ng=4 m=1", "source": "XM21 vbn vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=17.9u l=2u ng=4 m=1", "source": "XM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=17.9u l=2u ng=4 m=1", "source": "XM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10.8u l=8u ng=4 m=2", "source": "XM3 f1 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10.8u l=8u ng=4 m=2", "source": "XM4 f2 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM5 x1 r1 f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "r1" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM6 o1 r2 f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "r2" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=3u ng=1 m=3", "source": "XM7 x1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=3u ng=1 m=3", "source": "XM8 o1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR", "displayName": "MR", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10.8u l=4u ng=4 m=2", "source": "XMR rr ib vdd vdd sg13_lv_pmos w=10.8u l=4u ng=4 m=2", "pins": [ { "id": "d", "net": "rr" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRr1", "displayName": "Rr1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRr1 rr r1 vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "rr" }, { "id": "n", "net": "r1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRr2", "displayName": "Rr2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRr2 rr r2 vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "rr" }, { "id": "n", "net": "r2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.9u l=4u ng=1 m=1", "source": "XMA1 r1 f1 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "r1" }, { "id": "g", "net": "f1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.9u l=4u ng=1 m=1", "source": "XMA2 r2 f2 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "r2" }, { "id": "g", "net": "f2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.5u l=1u ng=1 m=1", "source": "XM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.7u l=4u ng=1 m=1", "source": "XM10 d2 g2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "g2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRz2", "displayName": "Rz2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRz2 d2 g2 vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "g2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.7u l=4u ng=1 m=1", "source": "XM11 o2 d2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=3u ng=1 m=1", "source": "XM12 o2 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=2u ng=2 m=4", "source": "XM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.5u l=1u ng=1 m=32", "source": "XM14 out o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=32", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCm", "displayName": "Cm", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.386u l=29.386u", "source": "XCm f2 out cap_cmim w=29.386u l=29.386u", "pins": [ { "id": "p", "net": "f2" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM20", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMR", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM20", "pin": "s" }, { "device": "XM20", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XMR", "pin": "s" }, { "device": "XMR", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XM20", "pin": "d" }, { "device": "XM21", "pin": "d" }, { "device": "XM21", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM21", "pin": "s" }, { "device": "XM21", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XRr1", "pin": "substrate" }, { "device": "XRr2", "pin": "substrate" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "s" }, { "device": "XMA2", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XRz2", "pin": "substrate" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" }, { "device": "XMA1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" }, { "device": "XMA2", "pin": "g" }, { "device": "XCm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM12", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "r1", "ground": false, "terminals": [ { "device": "XM5", "pin": "g" }, { "device": "XRr1", "pin": "n" }, { "device": "XMA1", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "r2", "ground": false, "terminals": [ { "device": "XM6", "pin": "g" }, { "device": "XRr2", "pin": "n" }, { "device": "XMA2", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "rr", "ground": false, "terminals": [ { "device": "XMR", "pin": "d" }, { "device": "XRr1", "pin": "p" }, { "device": "XRr2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XRz2", "pin": "p" }, { "device": "XM11", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "g2", "ground": false, "terminals": [ { "device": "XM10", "pin": "g" }, { "device": "XRz2", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM13", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM13", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XCm", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota3az" } }, { "id": "graph-6", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD} ac 1", "source": "Vdd vdd 0 dc {VDD} ac 1", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2.5u", "source": "Ib ib 0 2.5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota3az", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota3az", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota3az" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m", "source": "Vin inp 0 dc 400m", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota3az", "name": "ota3az", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XM20 vbn ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM21", "displayName": "M21", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10.8u l=8u ng=4 m=1", "source": "XM21 vbn vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=17.9u l=2u ng=4 m=1", "source": "XM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=17.9u l=2u ng=4 m=1", "source": "XM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10.8u l=8u ng=4 m=2", "source": "XM3 f1 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10.8u l=8u ng=4 m=2", "source": "XM4 f2 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM5 x1 r1 f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "r1" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM6 o1 r2 f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "r2" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=3u ng=1 m=3", "source": "XM7 x1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=3u ng=1 m=3", "source": "XM8 o1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR", "displayName": "MR", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10.8u l=4u ng=4 m=2", "source": "XMR rr ib vdd vdd sg13_lv_pmos w=10.8u l=4u ng=4 m=2", "pins": [ { "id": "d", "net": "rr" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRr1", "displayName": "Rr1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRr1 rr r1 vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "rr" }, { "id": "n", "net": "r1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRr2", "displayName": "Rr2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRr2 rr r2 vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "rr" }, { "id": "n", "net": "r2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.9u l=4u ng=1 m=1", "source": "XMA1 r1 f1 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "r1" }, { "id": "g", "net": "f1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.9u l=4u ng=1 m=1", "source": "XMA2 r2 f2 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "r2" }, { "id": "g", "net": "f2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.5u l=1u ng=1 m=1", "source": "XM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.7u l=4u ng=1 m=1", "source": "XM10 d2 g2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "g2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRz2", "displayName": "Rz2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRz2 d2 g2 vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "g2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.7u l=4u ng=1 m=1", "source": "XM11 o2 d2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=3u ng=1 m=1", "source": "XM12 o2 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=2u ng=2 m=4", "source": "XM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.5u l=1u ng=1 m=32", "source": "XM14 out o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=32", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCm", "displayName": "Cm", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.386u l=29.386u", "source": "XCm f2 out cap_cmim w=29.386u l=29.386u", "pins": [ { "id": "p", "net": "f2" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM20", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMR", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM20", "pin": "s" }, { "device": "XM20", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XMR", "pin": "s" }, { "device": "XMR", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XM20", "pin": "d" }, { "device": "XM21", "pin": "d" }, { "device": "XM21", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM21", "pin": "s" }, { "device": "XM21", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XRr1", "pin": "substrate" }, { "device": "XRr2", "pin": "substrate" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "s" }, { "device": "XMA2", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XRz2", "pin": "substrate" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" }, { "device": "XMA1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" }, { "device": "XMA2", "pin": "g" }, { "device": "XCm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM12", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "r1", "ground": false, "terminals": [ { "device": "XM5", "pin": "g" }, { "device": "XRr1", "pin": "n" }, { "device": "XMA1", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "r2", "ground": false, "terminals": [ { "device": "XM6", "pin": "g" }, { "device": "XRr2", "pin": "n" }, { "device": "XMA2", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "rr", "ground": false, "terminals": [ { "device": "XMR", "pin": "d" }, { "device": "XRr1", "pin": "p" }, { "device": "XRr2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XRz2", "pin": "p" }, { "device": "XM11", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "g2", "ground": false, "terminals": [ { "device": "XM10", "pin": "g" }, { "device": "XRz2", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM13", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM13", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XCm", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota3az" } }, { "id": "graph-7", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2.5u", "source": "Ib ib 0 2.5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota3az", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota3az", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota3az" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vsrc", "displayName": "Vsrc", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m", "source": "Vsrc src 0 dc 400m", "pins": [ { "id": "p", "net": "src" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Va", "displayName": "Va", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Va inp src dc 0 ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "src" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vb", "displayName": "Vb", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Vb inn out dc 0 ac 1", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vsrc", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Va", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "src", "ground": false, "terminals": [ { "device": "Vsrc", "pin": "p" }, { "device": "Va", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota3az", "name": "ota3az", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XM20 vbn ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM21", "displayName": "M21", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10.8u l=8u ng=4 m=1", "source": "XM21 vbn vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=17.9u l=2u ng=4 m=1", "source": "XM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=17.9u l=2u ng=4 m=1", "source": "XM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10.8u l=8u ng=4 m=2", "source": "XM3 f1 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10.8u l=8u ng=4 m=2", "source": "XM4 f2 vbn vss vss sg13_lv_nmos w=10.8u l=8u ng=4 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM5 x1 r1 f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "r1" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM6 o1 r2 f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "r2" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=3u ng=1 m=3", "source": "XM7 x1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=3u ng=1 m=3", "source": "XM8 o1 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=3", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMR", "displayName": "MR", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=10.8u l=4u ng=4 m=2", "source": "XMR rr ib vdd vdd sg13_lv_pmos w=10.8u l=4u ng=4 m=2", "pins": [ { "id": "d", "net": "rr" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRr1", "displayName": "Rr1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRr1 rr r1 vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "rr" }, { "id": "n", "net": "r1" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XRr2", "displayName": "Rr2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=61.666u", "source": "XRr2 rr r2 vss rhigh w=0.5u l=61.666u", "pins": [ { "id": "p", "net": "rr" }, { "id": "n", "net": "r2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMA1", "displayName": "MA1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.9u l=4u ng=1 m=1", "source": "XMA1 r1 f1 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "r1" }, { "id": "g", "net": "f1" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMA2", "displayName": "MA2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.9u l=4u ng=1 m=1", "source": "XMA2 r2 f2 vss vss sg13_lv_nmos w=2.9u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "r2" }, { "id": "g", "net": "f2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.5u l=1u ng=1 m=1", "source": "XM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.7u l=4u ng=1 m=1", "source": "XM10 d2 g2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "g2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRz2", "displayName": "Rz2", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=6.078u", "source": "XRz2 d2 g2 vss rhigh w=0.5u l=6.078u", "pins": [ { "id": "p", "net": "d2" }, { "id": "n", "net": "g2" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2.7u l=4u ng=1 m=1", "source": "XM11 o2 d2 vss vss sg13_lv_nmos w=2.7u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=3u ng=1 m=1", "source": "XM12 o2 x1 vdd vdd sg13_lv_pmos w=4u l=3u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=2u ng=2 m=4", "source": "XM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.5u l=1u ng=1 m=32", "source": "XM14 out o1 vdd vdd sg13_lv_pmos w=2.5u l=1u ng=1 m=32", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCm", "displayName": "Cm", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=29.386u l=29.386u", "source": "XCm f2 out cap_cmim w=29.386u l=29.386u", "pins": [ { "id": "p", "net": "f2" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM20", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMR", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM20", "pin": "s" }, { "device": "XM20", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XMR", "pin": "s" }, { "device": "XMR", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XM20", "pin": "d" }, { "device": "XM21", "pin": "d" }, { "device": "XM21", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM21", "pin": "s" }, { "device": "XM21", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XRr1", "pin": "substrate" }, { "device": "XRr2", "pin": "substrate" }, { "device": "XMA1", "pin": "s" }, { "device": "XMA1", "pin": "b" }, { "device": "XMA2", "pin": "s" }, { "device": "XMA2", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XRz2", "pin": "substrate" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" }, { "device": "XMA1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" }, { "device": "XMA2", "pin": "g" }, { "device": "XCm", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM12", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "r1", "ground": false, "terminals": [ { "device": "XM5", "pin": "g" }, { "device": "XRr1", "pin": "n" }, { "device": "XMA1", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "r2", "ground": false, "terminals": [ { "device": "XM6", "pin": "g" }, { "device": "XRr2", "pin": "n" }, { "device": "XMA2", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "rr", "ground": false, "terminals": [ { "device": "XMR", "pin": "d" }, { "device": "XRr1", "pin": "p" }, { "device": "XRr2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XRz2", "pin": "p" }, { "device": "XM11", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "g2", "ground": false, "terminals": [ { "device": "XM10", "pin": "g" }, { "device": "XRz2", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM13", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM13", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XCm", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota3az" } }, { "id": "graph-8", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2.5u", "source": "Ib ib 0 2.5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota3az", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota3az", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota3az" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m ac 1", "source": "Vin inp 0 dc 400m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota3az", "name": "ota3az", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=21.5u l=8u ng=6 m=1", "source": "XM20 vbn ib vdd vdd sg13_lv_pmos w=21.5u l=8u ng=6 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": 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