{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ota3-dacfc", "name": "Three-stage op amp, dual active-capacitive feedback", "group": "Op amps and OTAs", "subgroup": "Three-stage op amps", "title": "Three-stage op amp, dual active-capacitive feedback", "summary": "This three-stage amplifier senses the current in one compensation capacitor and copies it into two internal nodes. A small additional input path helps the output settle. Sharing the compensation action saves one feedback capacitor, but requires accurate current matching and control of several interacting loops.", "reference": { "kind": "paper", "authors": "S. Guo, H. Lee", "title": "Dual Active-Capacitive-Feedback Compensation for Low-Power Large-Capacitive-Load Three-Stage Amplifiers", "year": 2011, "where": "IEEE Journal of Solid-State Circuits, 46(2):452-464", "doi": "10.1109/JSSC.2010.2092994", "takes": "The dual active-capacitive-feedback compensation (DACFC): one capacitor sensing the output, its current returned through current mirrors to both the first and the second stage's outputs, a capacitor on the first stage's output, a feedforward input pair into the second stage and a feedforward output device. The core amplifier, its bias, the density-matched sensor, the split and the source resistor of the feedforward pair and every size are this library's, for SG13G2 at 1.2 V." }, "resources": { "record": "/circuits/ota3-dacfc.json", "page": "/index.html#ota3-dacfc", "achieved": "/achieved/ota3-dacfc.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "inp", "kind": "input" }, { "name": "inn", "kind": "input" }, { "name": "out", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the reference current, drawn out of this pin" } ], "devices": [ { "name": "MB", "type": "pmos", "nodes": "ib ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "bias reference, diode-connected: takes Ib", "fingers": 2, "copies": 1 }, { "name": "M20", "type": "pmos", "nodes": "vbc ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "copies Ib into the NMOS bias branch", "fingers": 2, "copies": 1 }, { "name": "Rb", "type": "resistor", "nodes": "vbc vbn", "sizedBy": [ "Rb" ], "role": "lifts the cascode bias vbc to Ib·Rb above vbn" }, { "name": "M21", "type": "nmos", "nodes": "vbn vbn vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "NMOS bias diode: sets the sinks' gate vbn", "fingers": 2, "copies": 1 }, { "name": "MT", "type": "pmos", "nodes": "tail ib vdd vdd", "sizedBy": [ "Wp", "Lp", "Kt" ], "role": "tail current source: Kt copies of MB", "fingers": 2, "copies": 1 }, { "name": "M1", "type": "pmos", "nodes": "f1 inn tail tail", "sizedBy": [ "W1", "L1" ], "role": "input pair, inverting input; bulk on its source", "fingers": 2, "copies": 1 }, { "name": "M2", "type": "pmos", "nodes": "f2 inp tail tail", "sizedBy": [ "W1", "L1" ], "role": "input pair, non-inverting input; bulk on its source", "fingers": 2, "copies": 1 }, { "name": "M3", "type": "nmos", "nodes": "f1 vbn vss vss", "sizedBy": [ "Wn", "Ln", "Ks", "Kd" ], "role": "folding sink: Ks + Kd copies of M21", "fingers": 2, "copies": 5 }, { "name": "M4", "type": "nmos", "nodes": "f2 vbn vss vss", "sizedBy": [ "Wn", "Ln", "Ks" ], "role": "folding sink: Ks copies of M21", "fingers": 2, "copies": 2 }, { "name": "M5", "type": "nmos", "nodes": "x1 vbc f1 vss", "sizedBy": [ "Wc", "Lc" ], "role": "cascode, mirror side", "fingers": 1, "copies": 1 }, { "name": "M6", "type": "nmos", "nodes": "o1 vbc f2 vss", "sizedBy": [ "Wc", "Lc" ], "role": "cascode, output side", "fingers": 1, "copies": 1 }, { "name": "M7", "type": "pmos", "nodes": "x1 x1 vdd vdd", "sizedBy": [ "Wm", "Lm", "Km" ], "role": "mirror load, diode-connected: Km unit copies", "fingers": 1, "copies": 2 }, { "name": "M8", "type": "pmos", "nodes": "o1 x1 vdd vdd", "sizedBy": [ "Wm", "Lm", "Km" ], "role": "mirror load: the first stage's output o1; Km unit copies", "fingers": 1, "copies": 2 }, { "name": "M9", "type": "pmos", "nodes": "d2 o1 vdd vdd", "sizedBy": [ "W2", "L2" ], "role": "second-stage input: turns o1 into a current", "fingers": 1, "copies": 1 }, { "name": "M10", "type": "nmos", "nodes": "d2 d2 vss vss", "sizedBy": [ "Wr", "Lr" ], "role": "second-stage mirror, diode-connected", "fingers": 1, "copies": 1 }, { "name": "M11", "type": "nmos", "nodes": "o2 d2 vss vss", "sizedBy": [ "Wr", "Lr" ], "role": "second-stage mirror: drives o2", "fingers": 1, "copies": 1 }, { "name": "M12", "type": "pmos", "nodes": "o2 x1 vdd vdd", "sizedBy": [ "Wm", "Lm", "K2" ], "role": "second-stage load: K2 copies of the M7 unit on x1 - adds the first stage's signal to o2 (cross feedforward)", "fingers": 1, "copies": 1 }, { "name": "M13", "type": "nmos", "nodes": "out o2 vss vss", "sizedBy": [ "W3", "L3", "N3" ], "role": "output device, common source on o2: N3 copies", "fingers": 1, "copies": 4 }, { "name": "M14", "type": "pmos", "nodes": "out o1 vdd vdd", "sizedBy": [ "W2", "L2", "Kf" ], "role": "output source and feedforward path: Kf copies of M9, driven from o1", "fingers": 1, "copies": 16 }, { "name": "Ca", "type": "capacitor", "nodes": "s out", "sizedBy": [ "Ca" ], "role": "the one feedback capacitor, into the sensing diode M17" }, { "name": "M17", "type": "pmos", "nodes": "s s vdd vdd", "sizedBy": [ "Wm", "Lm", "Km" ], "role": "sensing diode: 2*Km mirror units, at M7's density", "fingers": 1, "copies": 4 }, { "name": "M19", "type": "pmos", "nodes": "x1 s vdd vdd", "sizedBy": [ "Wm", "Lm", "Km" ], "role": "copies the sensed current into x1", "fingers": 1, "copies": 4 }, { "name": "M22", "type": "nmos", "nodes": "s vbc sm vss", "sizedBy": [ "Wc", "Lc" ], "role": "sensor sink's cascode: two cascode units", "fingers": 1, "copies": 2 }, { "name": "M18", "type": "nmos", "nodes": "sm vbn vss vss", "sizedBy": [ "Wn", "Ln", "Kd" ], "role": "sensor sink: Kd copies of M21", "fingers": 2, "copies": 3 }, { "name": "M23", "type": "nmos", "nodes": "x1 vbc f1 vss", "sizedBy": [ "Wc", "Lc" ], "role": "two cascode units beside M5: M5 carries the sensor's current too, at the density of M6 and M22", "fingers": 1, "copies": 2 }, { "name": "Cf", "type": "capacitor", "nodes": "o1 vdd", "sizedBy": [ "Cf" ], "role": "loads o1 to V_DD and helps damp the Ca loop; imperfect supply tracking can still couple ripple into o1" }, { "name": "MT2", "type": "pmos", "nodes": "s15 ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "feedforward tail, non-inverting side: one copy of MB", "fingers": 2, "copies": 1 }, { "name": "MT3", "type": "pmos", "nodes": "s16 ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "feedforward tail, inverting side: one copy of MB", "fingers": 2, "copies": 1 }, { "name": "Rf", "type": "resistor", "nodes": "s15 s16", "sizedBy": [ "Rf" ], "role": "between the feedforward sources: keeps the pair linear through a step" }, { "name": "M15", "type": "pmos", "nodes": "o2 inp s15 s15", "sizedBy": [ "W1", "L1" ], "role": "feedforward input, non-inverting side: one unit, into o2", "fingers": 2, "copies": 1 }, { "name": "M24", "type": "pmos", "nodes": "vss inp s15 s15", "sizedBy": [ "W1", "L1", "Kx" ], "role": "the rest of that side: Kx units, to ground", "fingers": 2, "copies": 7 }, { "name": "M16", "type": "pmos", "nodes": "d2 inn s16 s16", "sizedBy": [ "W1", "L1" ], "role": "feedforward input, inverting side: one unit, into d2", "fingers": 2, "copies": 1 }, { "name": "M25", "type": "pmos", "nodes": "vss inn s16 s16", "sizedBy": [ "W1", "L1", "Kx" ], "role": "the rest of that side: Kx units, to ground", "fingers": 2, "copies": 7 } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "The input pair: any difference between them is input offset." }, { "rule": "match", "of": [ "M3", "M4" ], "why": "The folding sinks, apart from the extra copies M3 carries for the current fed into x1: any other difference unbalances the cascodes and appears as offset." }, { "rule": "match", "of": [ "M7", "M8" ], "why": "The mirror load: a mismatch copies the wrong current to o1 and appears as offset." }, { "rule": "unit-copies", "of": [ "MB", "M20", "MT" ], "constraint": "MT = Kt copies of MB", "why": "Repeating the same unit geometry preserves the intended nominal ratio and avoids geometry-dependent systematic shifts. Random mismatch and unequal drain voltages still cause current-copy errors." }, { "rule": "ratio", "of": [ "M3", "M4", "MT" ], "constraint": "Ks > Kt/2", "why": "Each sink carries its input device's share of the tail and its cascode's current: the cascodes get (Ks − Kt/2)·Ib, which must stay positive, or a cascode turns off and the first stage loses its gain." }, { "rule": "bias", "of": [ "Rb", "M3", "M4" ], "constraint": "Ib·Rb ≈ V_DSAT(M3) + 0.1 V", "why": "The cascode gates sit Ib·Rb above the sinks' gates, so the sinks keep that much V_DS less the cascodes' body effect: enough to stay saturated at every corner, not so much that the cascodes lose theirs." }, { "rule": "match", "of": [ "M10", "M11" ], "why": "The second-stage mirror: a mismatch moves the balance between M11 and M12 and appears as offset." }, { "rule": "unit-copies", "of": [ "M9", "M14" ], "constraint": "M14 = Kf copies of M9", "why": "M14 shares M9's gate, o1, so its nominal current is approximately Kf times the second stage's while both devices remain saturated: the output stage's quiescent current is set by a ratio, not by a voltage." }, { "rule": "dominant-pole", "of": [ "Ca", "M1", "M2" ], "constraint": "ω_u ≈ g_m1/C_a", "why": "The sensed current reaches o1 through the mirror as a Miller capacitor's would: the angular unity-gain frequency is the input pair's g_m over Ca." }, { "rule": "balance", "of": [ "M17", "M19", "M18", "M3" ], "constraint": "Kd·Ib = 2·(Ks − Kt/2)·Ib", "why": "M19 puts the sensor's DC current into x1 and Kd extra copies in M3 take it back. They cancel only if every device is at its twin's density: the sensor carries twice the cascode current, M5 with M23 is three cascode units, M22 two, M6 one, and M17/M19 are 2·Km mirror units - change Kt, Ks or Kd apart and the offset grows. What is left is random: the NMOS unit is long so that its copies match closely." }, { "rule": "dual-feedback", "of": [ "M8", "M12", "M7" ], "constraint": "i_o2/i_o1 = K2/Km", "why": "The same x1 signal drives M8 into o1 and M12 into o2: o2's capacitive feedback is K2/Km of o1's. A smaller share lets the o2 path, and the feedforward pair through it, integrate faster than the main path." }, { "rule": "feedforward", "of": [ "M15", "M24", "M16", "M25", "Rf" ], "constraint": "g_m,ff ≈ g_m,side/((1 + g_m,side·R_f/2)(1 + K_x))", "why": "Through o2 the feedforward pair meets only K2/Km of the Miller capacitance the main path meets at o1: all of it would set the crossover near 11 MHz, where the local loops have no margin. Splitting each side 1:Kx sends only its share to the second stage - signal and DC current alike, so the second stage keeps its gain - and Rf keeps that share linear through a step, where it helps the output settle." }, { "rule": "damping", "of": [ "Cf", "Ca" ], "constraint": "C_f ≈ 10·C_a, to vdd", "why": "Cf on o1 lowers the gain of the loop Ca closes through the sensor and the mirror, so that loop crosses below the sensor's and x1's poles; without it the amplifier oscillates. Tied to vdd rather than ground, it reduces the capacitor's response to supply changes that o1 also follows. Imperfect tracking and other supply-coupling paths still limit rejection." } ], "specs": [ { "key": "dc_gain_db", "label": "DC open-loop gain", "unit": "dB", "direction": "max", "constraint": ">= 88 dB", "min": 88, "max": null, "why": "About 96 dB at tt: the sensor needs a cascode current three times the input pair's, which takes first-stage gain; the feedforward pair sends only an eighth of its current into the second stage, which keeps its gain. Hot it falls to about 92 dB, and 88 dB holds at every corner." }, { "key": "ugf_hz", "label": "Unity-gain frequency", "unit": "Hz", "direction": "max", "constraint": ">= 2000000 Hz", "min": 2000000, "max": null, "why": "A few MHz into the 10 pF load at tt; the limit holds at the slow, hot, low-supply corner, where the input pair's g_m is lowest." }, { "key": "pm_deg", "label": "Phase margin", "unit": "deg", "direction": "max", "constraint": ">= 60 deg", "min": 60, "max": null, "why": "A phase-margin target of 60° or more supports a well-damped unity-gain loop, but does not guarantee a ringing-free higher-order response. The separate step and gain-margin benches check additional behavior at the stated conditions." }, { "key": "gm_db", "label": "Gain margin", "unit": "dB", "direction": "max", "constraint": ">= 6 dB", "min": 6, "max": null, "why": "The margin the open-loop phase margin can hide: a three-stage amplifier's non-dominant pole pair can peak, and the gain margin is where that shows." }, { "key": "t_settle", "label": "Settling time, 1 %", "unit": "s", "direction": "min", "constraint": "<= 8e-7 s", "min": null, "max": 8e-7, "why": "The step bench can expose dynamics hidden by an open-loop margin. After the output change tracks 90–110 % of the commanded 0.2 V step, settling is measured within 1 % of that step amplitude around the final output; overshoot is checked separately. This is not a 1 % DC-accuracy limit." }, { "key": "overshoot_pct", "label": "Overshoot", "unit": "%", "direction": "min", "constraint": "<= 5 %", "min": null, "max": 5, "why": "A well-damped closed loop overshoots a few percent at most." }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 65 dB", "min": 65, "max": null, "why": "Cf goes to V_DD, which o1 rides on, so the supply reaches o1 only through Ca from the sensing node, as it reaches any Miller-compensated first stage: about 72 dB." }, { "key": "cmrr_db", "label": "Common-mode rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 80 dB", "min": 80, "max": null, "why": "The 8 µm NMOS unit and 3 µm PMOS unit keep the sensor cancellation and the folded first stage matched: every draw in both twenty-seed sets remains above 81 dB." }, { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.00008 A", "min": null, "max": 0.00008, "why": "Low power is what these compensation schemes are for: the whole amplifier, bias included, stays under this." } ], "explanation": { "idea": "This three-stage amplifier senses the current in one compensation capacitor and copies it into two internal nodes. A small additional input path helps the output settle. Sharing the compensation action saves one feedback capacitor, but requires accurate current matching and control of several interacting loops.", "detail": "A three-stage op amp compensated by one capacitor whose current is sensed by a diode and mirrored into both the first and the second stage's outputs: a dual capacitive feedback, acting as Miller capacitors to o1 and to o2 at once. A capacitor on o1 keeps the loop through the sensor damped, a second input pair feeds a small, linear share of the input to the second stage, and the push-pull device feeds o1 forward to the output.", "lesson": { "relation": 1, "symbols": "ω_u is angular unity-gain frequency in rad/s; f_u = ω_u/(2π) is frequency in Hz; g_m1 is the input transistor's transconductance in S; C_a is the main compensation capacitance in F.", "assumptions": "Small signals around the default bias point, with the intended dominant pole and the other internal poles above crossover. Device and load parasitics make the relation approximate.", "exercise": { "param": "Ca", "value": 2e-12, "analysis": "open_loop", "expect": "Increasing the compensation capacitance should lower the unity-gain frequency. Compare the phase margin as well; a slower crossover does not by itself prove every internal loop is stable." }, "limits": "Provide the external bias current and use the specified load and common-mode level. Three gain stages contain interacting local loops: inspect gain margin and step settling as well as phase margin after changes." }, "path": [ { "part": "First stage", "devices": "M1, M2, MT, M3, M4, M5, M6, M7, M8", "does": "The PMOS pair M1/M2 on the tail MT folds into the sinks M3/M4 and the cascodes M5/M6; the mirror M7/M8 turns the two halves into one output, o1, which falls as inp rises." }, { "part": "Sensor", "devices": "Ca, M17, M22, M18, M19", "does": "Ca couples out into s, the diode M17, biased by M18 through the cascode M22; M19 copies M17's current into x1, the first stage's mirror diode." }, { "part": "Dual feedback", "devices": "M8, M12, M23", "does": "The sensed current reaches o1 through M8 and o2 through M12, the second stage's load, both on x1; M23 beside M5 keeps the cascodes at one density, so the sensor's DC current cancels." }, { "part": "Second stage", "devices": "M9, M10, M11, M12", "does": "M9 into the mirror M10/M11 against M12: a non-inverting stage onto o2. At the default K2 = 1 and Km = 2, stage 2 carries one unit of current, half the full two-unit mirror branch." }, { "part": "Feedforward pair", "devices": "M15, M24, M16, M25, MT2, MT3, Rf", "does": "M15 (inp) into o2 and M16 (inn) into the diode d2 push o2 the way the main path does. Each side has its own tail and seven more units beside it, M24 and M25, that take the rest of its current to ground, so an eighth reaches the second stage; Rf between the sources keeps that share linear through a step." }, { "part": "Output stage", "devices": "M13, M14", "does": "M13 on o2 sinks and M14 on o1 sources: a push-pull output, and M14, sixteen copies of M9, is the feedforward path from o1 to the output. Both paths invert, so out follows inp." }, { "part": "Capacitor on o1", "devices": "Cf", "does": "Cf from o1 to V_DD lowers the gain of the loop Ca closes, so it crosses below the sensor's and x1's poles; o1 approximately follows V_DD, reducing the capacitor's response to supply changes. Imperfect tracking and other coupling paths still limit supply rejection." } ], "bias": "The testbench draws Ib (2.5 µA) out of MB. MT is one copy, the sinks leave 1.5 Ib per cascode, and the sensor runs at 3 Ib: M18 is three copies of M21 and M3 three copies more than M4, which take back the current M19 puts into x1. M17 and M19 are copies of the mirror unit at M7's density, M22 and M23 two cascode units, M5 one, so every twin sits at the same V_DS; the NMOS unit is 8 µm and the PMOS unit 3 µm long, so the sensor copies and their cancellation match closely without the bandwidth cost of the earlier longer sink unit. M12 sets the second stage at 1.9 µA and M14, sixteen copies of M9, the output at 30 µA. Each feedforward side runs at Ib, an eighth of it into the second stage.", "relations": [ { "what": "DC gain", "expr": "A_0 ≈ g_m1 R_o1 · g_m9 R_o2 · g_m13 R_o3", "note": "R_o1 is set mostly by the mirror M8, R_o2 and R_o3 by the NMOS M11 and M13, whose V_A is only 2-3 V: the reason those two are long." }, { "what": "Unity-gain frequency", "expr": "ω_u ≈ g_m1/C_a", "note": "About 3.7 MHz with Ca at 1 pF." }, { "what": "Dual feedback", "expr": "i_o2/i_o1 = K_2/K_m", "note": "o2 receives half of what o1 does; a path through o2 integrates twice as fast as the main one." }, { "what": "Feedforward pair", "expr": "g_m,ff ≈ g_m,side/((1 + g_m,side R_f/2)(1 + K_x))", "note": "All of the pair would set the crossover near 11 MHz, where the local loops have no margin; an eighth, kept linear by Rf, adds to the step's damping instead." } ], "tradeoffs": [ "Cf: without it the loop through the sensor and the mirror oscillates; larger raises the gain margin a little and slows the step.", "Kx: fewer units to ground strengthen the feedforward pair - less overshoot, less gain margin - and send more current into the second stage's mirror, which costs gain.", "Rf: keeps the pair linear through a step; much larger and the pair stops helping the step, smaller and it saturates.", "Kd: the sensor's current must stay twice the cascode current, or the offset grows; its random part falls with the NMOS unit's area.", "Unit-device area: the 8 µm NMOS and 3 µm PMOS units keep the sensor cancellation matched across forty draws; longer sinks add little yield but more capacitance to the cascode and bias nodes." ] }, "sizing": [ { "key": "Ib", "label": "Reference current", "unit": "A", "value": 0.0000025, "min": 5e-7, "max": 0.00002, "kind": "si" }, { "key": "Wp", "label": "W PMOS source unit (MB and its copies)", "unit": "m", "value": 0.0000081, "min": 5e-7, "max": 0.00005, "kind": "si" }, { "key": "Lp", "label": "L PMOS source unit", "unit": "m", "value": 0.000003, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "W1", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.0000089, "min": 5e-7, "max": 0.0001, "kind": "si" }, { "key": "L1", "label": "L input pair", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Wn", "label": "W NMOS sink unit (M21 and its copies)", "unit": "m", "value": 0.0000057, "min": 3e-7, "max": 0.00005, "kind": "si" }, { "key": "Ln", "label": "L NMOS sink unit", "unit": "m", "value": 0.000008, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Rb", "label": "Cascode bias resistor", "unit": "Ω", "value": 116000, "min": 10000, "max": 500000, "kind": "si" }, { "key": "Wc", "label": "W cascode unit (M5, M6)", "unit": "m", "value": 0.0000049, "min": 3e-7, "max": 0.00005, "kind": "si" }, { "key": "Lc", "label": "L cascode unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Wm", "label": "W mirror-load unit (M7, M8, M12)", "unit": "m", "value": 0.000003, "min": 5e-7, "max": 0.0001, "kind": "si" }, { "key": "Lm", "label": "L mirror-load unit", "unit": "m", "value": 0.0000015, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Km", "label": "Mirror-load copies (M7, M8)", "unit": "", "value": 2, "min": 1, "max": 16, "kind": "int" }, { "key": "W2", "label": "W second-stage PMOS unit (M9, M14)", "unit": "m", "value": 0.0000019, "min": 5e-7, "max": 0.0001, "kind": "si" }, { "key": "L2", "label": "L second-stage PMOS unit", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Wr", "label": "W second-stage mirror (M10, M11)", "unit": "m", "value": 0.0000041, "min": 3e-7, "max": 0.0001, "kind": "si" }, { "key": "Lr", "label": "L second-stage mirror", "unit": "m", "value": 0.000004, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "W3", "label": "W output NMOS unit (M13)", "unit": "m", "value": 0.0000043, "min": 3e-7, "max": 0.0001, "kind": "si" }, { "key": "L3", "label": "L output NMOS unit", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Kt", "label": "Tail current, in Ib", "unit": "", "value": 1, "min": 1, "max": 16, "kind": "int" }, { "key": "Ks", "label": "Folding-sink current, in Ib", "unit": "", "value": 2, "min": 1, "max": 16, "kind": "int" }, { "key": "K2", "label": "Second-stage current, in unit copies", "unit": "", "value": 1, "min": 1, "max": 40, "kind": "int" }, { "key": "Kf", "label": "Output-stage current, in second-stage currents", "unit": "", "value": 16, "min": 1, "max": 40, "kind": "int" }, { "key": "N3", "label": "Output NMOS copies", "unit": "", "value": 4, "min": 1, "max": 40, "kind": "int" }, { "key": "Ca", "label": "Feedback capacitor (into the sensor)", "unit": "F", "value": 1e-12, "min": 2e-13, "max": 1e-11, "kind": "si" }, { "key": "Cf", "label": "Capacitor on o1 (to vdd)", "unit": "F", "value": 1e-11, "min": 5e-13, "max": 2e-11, "kind": "si" }, { "key": "Kd", "label": "Sensor current, in Ib", "unit": "", "value": 3, "min": 1, "max": 8, "kind": "int" }, { "key": "Rf", "label": "Feedforward pair source resistor", "unit": "Ω", "value": 50000, "min": 0, "max": 1000000, "kind": "si" }, { "key": "Kx", "label": "Feedforward units to ground, per side", "unit": "", "value": 7, "min": 0, "max": 20, "kind": "int" }, { "key": "CL", "label": "Load capacitance", "unit": "F", "value": 1e-11, "min": 1e-12, "max": 1e-10, "kind": "si" }, { "key": "VCM", "label": "Input common mode", "unit": "V", "value": 0.4, "min": 0, "max": 0.6, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.", "measures": [], "metricKeys": [ "i_supply", "vout_dc", "vos" ], "acceptance": [ "i_supply" ], "acceptanceRules": [ { "key": "i_supply", "unit": "A", "min": null, "max": 0.00008, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Three-stage op amp, dual active-capacitive feedback - operating point as a unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 2.5u\n.subckt ota3dacfc inp inn out vdd vss ib\n* bias: Ib into the PMOS diode MB; M20 copies it through Rb into the NMOS diode M21, so vbc sits Ib*Rb above vbn\nXMB ib ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXM20 vbc ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXRb vbc vbn vss rhigh w=0.5u l=35.725u\nXM21 vbn vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=1\n* first stage: PMOS pair M1/M2 on tail MT, folded into sinks M3/M4 and cascodes M5/M6, mirror load M7/M8 - o1 falls as inp rises\nXMT tail ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXM1 f1 inn tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM2 f2 inp tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM3 f1 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=5\nXM4 f2 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=2\nXM5 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM6 o1 vbc f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM7 x1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2\nXM8 o1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2\n* second stage: M9 into the NMOS mirror M10/M11, against M12 on x1 - o2 rises with o1\nXM9 d2 o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=1\nXM10 d2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1\nXM11 o2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1\nXM12 o2 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=1\n* output stage: M13 on o2 sinks, M14 on o1 sources - a push-pull output that feeds o1 forward\nXM13 out o2 vss vss sg13_lv_nmos w=4.3u l=2u ng=1 m=4\nXM14 out o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=16\n* dual active feedback: Ca from out into the diode M17, copied by M19 into x1, then to o1 (M8) and o2 (M12); Cf from o1 to vdd\nXCa s out cap_cmim w=25.767u l=25.767u\nXM17 s s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4\nXM19 x1 s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4\nXM22 s vbc sm vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2\nXM18 sm vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=3\nXM23 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2\nXCf o1 vdd cap_cmim w=28.814u l=28.814u m=8\n* feedforward pair: M15 (inp) into o2, M16 (inn) into d2, each one of 1+Kx units (M24, M25 to vss) on its own tail (MT2, MT3), Rf between the sources\nXMT2 s15 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXMT3 s16 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXRf s15 s16 vss rhigh w=0.5u l=15.342u\nXM15 o2 inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM24 vss inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=7\nXM16 d2 inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM25 vss inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=7\n.ends\nXdut inp inn out vdd 0 ib ota3dacfc\nCl out 0 10p\nVin inp 0 dc 400m\n* the output drives the inverting input: a unity-gain buffer\nVfb inn out 0\n.op\n.end" }, { "id": "open_loop", "label": "Open-loop gain", "note": "Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.", "measures": [], "metricKeys": [ "dc_gain_db", "ugf_hz", "pm_deg", "gm_db" ], "acceptance": [ "dc_gain_db", "ugf_hz", "pm_deg", "gm_db" ], "acceptanceRules": [ { "key": "dc_gain_db", "unit": "dB", "min": 88, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "ugf_hz", "unit": "Hz", "min": 2000000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "pm_deg", "unit": "deg", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "gm_db", "unit": "dB", "min": 6, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Three-stage op amp, dual active-capacitive feedback - open-loop gain and phase\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 2.5u\n.subckt ota3dacfc inp inn out vdd vss ib\n* bias: Ib into the PMOS diode MB; M20 copies it through Rb into the NMOS diode M21, so vbc sits Ib*Rb above vbn\nXMB ib ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXM20 vbc ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXRb vbc vbn vss rhigh w=0.5u l=35.725u\nXM21 vbn vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=1\n* first stage: PMOS pair M1/M2 on tail MT, folded into sinks M3/M4 and cascodes M5/M6, mirror load M7/M8 - o1 falls as inp rises\nXMT tail ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXM1 f1 inn tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM2 f2 inp tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM3 f1 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=5\nXM4 f2 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=2\nXM5 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM6 o1 vbc f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM7 x1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2\nXM8 o1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2\n* second stage: M9 into the NMOS mirror M10/M11, against M12 on x1 - o2 rises with o1\nXM9 d2 o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=1\nXM10 d2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1\nXM11 o2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1\nXM12 o2 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=1\n* output stage: M13 on o2 sinks, M14 on o1 sources - a push-pull output that feeds o1 forward\nXM13 out o2 vss vss sg13_lv_nmos w=4.3u l=2u ng=1 m=4\nXM14 out o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=16\n* dual active feedback: Ca from out into the diode M17, copied by M19 into x1, then to o1 (M8) and o2 (M12); Cf from o1 to vdd\nXCa s out cap_cmim w=25.767u l=25.767u\nXM17 s s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4\nXM19 x1 s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4\nXM22 s vbc sm vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2\nXM18 sm vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=3\nXM23 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2\nXCf o1 vdd cap_cmim w=28.814u l=28.814u m=8\n* feedforward pair: M15 (inp) into o2, M16 (inn) into d2, each one of 1+Kx units (M24, M25 to vss) on its own tail (MT2, MT3), Rf between the sources\nXMT2 s15 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXMT3 s16 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXRf s15 s16 vss rhigh w=0.5u l=15.342u\nXM15 o2 inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM24 vss inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=7\nXM16 d2 inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM25 vss inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=7\n.ends\nXdut inp inn out vdd 0 ib ota3dacfc\nCl out 0 10p\nVin inp 0 dc 400m ac 1\n* the loop closed at DC and open at every frequency the sweep visits\nLfb out inn 1t\nCfb inn 0 1t\n.ac dec 25 0.1 10g\n.end" }, { "id": "step", "label": "Step response", "note": "A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.", "measures": [], "metricKeys": [ "sr", "t_settle", "overshoot_pct" ], "acceptance": [ "t_settle", "overshoot_pct" ], "acceptanceRules": [ { "key": "t_settle", "unit": "s", "min": null, "max": 8e-7, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "overshoot_pct", "unit": "%", "min": null, "max": 5, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Three-stage op amp, dual active-capacitive feedback - step response of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 2.5u\n.subckt ota3dacfc inp inn out vdd vss ib\n* bias: Ib into the PMOS diode MB; M20 copies it through Rb into the NMOS diode M21, so vbc sits Ib*Rb above vbn\nXMB ib ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXM20 vbc ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXRb vbc vbn vss rhigh w=0.5u l=35.725u\nXM21 vbn vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=1\n* first stage: PMOS pair M1/M2 on tail MT, folded into sinks M3/M4 and cascodes M5/M6, mirror load M7/M8 - o1 falls as inp rises\nXMT tail ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXM1 f1 inn tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM2 f2 inp tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM3 f1 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=5\nXM4 f2 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=2\nXM5 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM6 o1 vbc f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM7 x1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2\nXM8 o1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2\n* second stage: M9 into the NMOS mirror M10/M11, against M12 on x1 - o2 rises with o1\nXM9 d2 o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=1\nXM10 d2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1\nXM11 o2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1\nXM12 o2 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=1\n* output stage: M13 on o2 sinks, M14 on o1 sources - a push-pull output that feeds o1 forward\nXM13 out o2 vss vss sg13_lv_nmos w=4.3u l=2u ng=1 m=4\nXM14 out o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=16\n* dual active feedback: Ca from out into the diode M17, copied by M19 into x1, then to o1 (M8) and o2 (M12); Cf from o1 to vdd\nXCa s out cap_cmim w=25.767u l=25.767u\nXM17 s s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4\nXM19 x1 s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4\nXM22 s vbc sm vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2\nXM18 sm vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=3\nXM23 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2\nXCf o1 vdd cap_cmim w=28.814u l=28.814u m=8\n* feedforward pair: M15 (inp) into o2, M16 (inn) into d2, each one of 1+Kx units (M24, M25 to vss) on its own tail (MT2, MT3), Rf between the sources\nXMT2 s15 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXMT3 s16 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXRf s15 s16 vss rhigh w=0.5u l=15.342u\nXM15 o2 inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM24 vss inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=7\nXM16 d2 inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM25 vss inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=7\n.ends\nXdut inp inn out vdd 0 ib ota3dacfc\nCl out 0 10p\nVin inp 0 pulse(300m 500m 400n 1n 1n 2u 8u)\nVfb inn out 0\n.tran 1000p 4u\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.", "measures": [], "metricKeys": [ "psrr_db" ], "acceptance": [ "psrr_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 65, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Three-stage op amp, dual active-capacitive feedback - supply rejection of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD} ac 1\nIb ib 0 2.5u\n.subckt ota3dacfc inp inn out vdd vss ib\n* bias: Ib into the PMOS diode MB; M20 copies it through Rb into the NMOS diode M21, so vbc sits Ib*Rb above vbn\nXMB ib ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXM20 vbc ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXRb vbc vbn vss rhigh w=0.5u l=35.725u\nXM21 vbn vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=1\n* first stage: PMOS pair M1/M2 on tail MT, folded into sinks M3/M4 and cascodes M5/M6, mirror load M7/M8 - o1 falls as inp rises\nXMT tail ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXM1 f1 inn tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM2 f2 inp tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM3 f1 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=5\nXM4 f2 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=2\nXM5 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM6 o1 vbc f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM7 x1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2\nXM8 o1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2\n* second stage: M9 into the NMOS mirror M10/M11, against M12 on x1 - o2 rises with o1\nXM9 d2 o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=1\nXM10 d2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1\nXM11 o2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1\nXM12 o2 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=1\n* output stage: M13 on o2 sinks, M14 on o1 sources - a push-pull output that feeds o1 forward\nXM13 out o2 vss vss sg13_lv_nmos w=4.3u l=2u ng=1 m=4\nXM14 out o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=16\n* dual active feedback: Ca from out into the diode M17, copied by M19 into x1, then to o1 (M8) and o2 (M12); Cf from o1 to vdd\nXCa s out cap_cmim w=25.767u l=25.767u\nXM17 s s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4\nXM19 x1 s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4\nXM22 s vbc sm vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2\nXM18 sm vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=3\nXM23 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2\nXCf o1 vdd cap_cmim w=28.814u l=28.814u m=8\n* feedforward pair: M15 (inp) into o2, M16 (inn) into d2, each one of 1+Kx units (M24, M25 to vss) on its own tail (MT2, MT3), Rf between the sources\nXMT2 s15 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXMT3 s16 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXRf s15 s16 vss rhigh w=0.5u l=15.342u\nXM15 o2 inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM24 vss inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=7\nXM16 d2 inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM25 vss inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=7\n.ends\nXdut inp inn out vdd 0 ib ota3dacfc\nCl out 0 10p\nVin inp 0 dc 400m\nVfb inn out 0\n.ac dec 25 1 100meg\n.end" }, { "id": "cmrr", "label": "Common-mode rejection", "note": "Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.", "measures": [], "metricKeys": [ "cmrr_db" ], "acceptance": [ "cmrr_db" ], "acceptanceRules": [ { "key": "cmrr_db", "unit": "dB", "min": 80, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Three-stage op amp, dual active-capacitive feedback - common-mode rejection\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 2.5u\n.subckt ota3dacfc inp inn out vdd vss ib\n* bias: Ib into the PMOS diode MB; M20 copies it through Rb into the NMOS diode M21, so vbc sits Ib*Rb above vbn\nXMB ib ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXM20 vbc ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXRb vbc vbn vss rhigh w=0.5u l=35.725u\nXM21 vbn vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=1\n* first stage: PMOS pair M1/M2 on tail MT, folded into sinks M3/M4 and cascodes M5/M6, mirror load M7/M8 - o1 falls as inp rises\nXMT tail ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXM1 f1 inn tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM2 f2 inp tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM3 f1 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=5\nXM4 f2 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=2\nXM5 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM6 o1 vbc f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM7 x1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2\nXM8 o1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2\n* second stage: M9 into the NMOS mirror M10/M11, against M12 on x1 - o2 rises with o1\nXM9 d2 o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=1\nXM10 d2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1\nXM11 o2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1\nXM12 o2 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=1\n* output stage: M13 on o2 sinks, M14 on o1 sources - a push-pull output that feeds o1 forward\nXM13 out o2 vss vss sg13_lv_nmos w=4.3u l=2u ng=1 m=4\nXM14 out o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=16\n* dual active feedback: Ca from out into the diode M17, copied by M19 into x1, then to o1 (M8) and o2 (M12); Cf from o1 to vdd\nXCa s out cap_cmim w=25.767u l=25.767u\nXM17 s s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4\nXM19 x1 s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4\nXM22 s vbc sm vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2\nXM18 sm vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=3\nXM23 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2\nXCf o1 vdd cap_cmim w=28.814u l=28.814u m=8\n* feedforward pair: M15 (inp) into o2, M16 (inn) into d2, each one of 1+Kx units (M24, M25 to vss) on its own tail (MT2, MT3), Rf between the sources\nXMT2 s15 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXMT3 s16 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXRf s15 s16 vss rhigh w=0.5u l=15.342u\nXM15 o2 inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM24 vss inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=7\nXM16 d2 inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM25 vss inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=7\n.ends\nXdut inp inn out vdd 0 ib ota3dacfc\nCl out 0 10p\nVsrc src 0 dc 400m\n* va on the non-inverting input, vb in the feedback path: both inputs move with the signal\nVa inp src dc 0 ac 1\nVb inn out dc 0 ac 1\n.ac dec 25 1 100meg\n.end" }, { "id": "noise", "label": "Noise", "note": "Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.", "measures": [], "metricKeys": [ "vn_1k", "vn_int" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Three-stage op amp, dual active-capacitive feedback - input-referred noise\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 2.5u\n.subckt ota3dacfc inp inn out vdd vss ib\n* bias: Ib into the PMOS diode MB; M20 copies it through Rb into the NMOS diode M21, so vbc sits Ib*Rb above vbn\nXMB ib ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXM20 vbc ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXRb vbc vbn vss rhigh w=0.5u l=35.725u\nXM21 vbn vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=1\n* first stage: PMOS pair M1/M2 on tail MT, folded into sinks M3/M4 and cascodes M5/M6, mirror load M7/M8 - o1 falls as inp rises\nXMT tail ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXM1 f1 inn tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM2 f2 inp tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM3 f1 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=5\nXM4 f2 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=2\nXM5 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM6 o1 vbc f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1\nXM7 x1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2\nXM8 o1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2\n* second stage: M9 into the NMOS mirror M10/M11, against M12 on x1 - o2 rises with o1\nXM9 d2 o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=1\nXM10 d2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1\nXM11 o2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1\nXM12 o2 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=1\n* output stage: M13 on o2 sinks, M14 on o1 sources - a push-pull output that feeds o1 forward\nXM13 out o2 vss vss sg13_lv_nmos w=4.3u l=2u ng=1 m=4\nXM14 out o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=16\n* dual active feedback: Ca from out into the diode M17, copied by M19 into x1, then to o1 (M8) and o2 (M12); Cf from o1 to vdd\nXCa s out cap_cmim w=25.767u l=25.767u\nXM17 s s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4\nXM19 x1 s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4\nXM22 s vbc sm vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2\nXM18 sm vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=3\nXM23 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2\nXCf o1 vdd cap_cmim w=28.814u l=28.814u m=8\n* feedforward pair: M15 (inp) into o2, M16 (inn) into d2, each one of 1+Kx units (M24, M25 to vss) on its own tail (MT2, MT3), Rf between the sources\nXMT2 s15 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXMT3 s16 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXRf s15 s16 vss rhigh w=0.5u l=15.342u\nXM15 o2 inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM24 vss inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=7\nXM16 d2 inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=1\nXM25 vss inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=7\n.ends\nXdut inp inn out vdd 0 ib ota3dacfc\nCl out 0 10p\nVin inp 0 dc 400m ac 1\nVfb inn out 0\n.control\nnoise v(out) Vin dec 20 1 1meg\nsetplot noise1\n* 20 points a decade from 1 Hz: point 60 is 1 kHz\nlet vn_1k = inoise_spectrum[60]\nprint vn_1k\nsetplot noise2\nprint inoise_total\n.endc\n.op\n.end" } ], "measurements": { "dc_gain_db": { "label": "DC open-loop gain", "unit": "dB", "spec": { "min": 88, "max": null } }, "ugf_hz": { "label": "Unity-gain frequency", "unit": "Hz", "spec": { "min": 2000000, "max": null } }, "pm_deg": { "label": "Phase margin", "unit": "deg", "spec": { "min": 60, "max": null } }, "gm_db": { "label": "Gain margin", "unit": "dB", "spec": { "min": 6, "max": null } }, "t_settle": { "label": "Settling time, 1 %", "unit": "s", "spec": { "min": null, "max": 8e-7 } }, "overshoot_pct": { "label": "Overshoot", "unit": "%", "spec": { "min": null, "max": 5 } }, "psrr_db": { "label": "Supply rejection at 1 kHz", "unit": "dB", "spec": { "min": 65, "max": null } }, "cmrr_db": { "label": "Common-mode rejection at 1 kHz", "unit": "dB", "spec": { "min": 80, "max": null } }, "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.00008 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "d596a70f1b021f38d8581db6876a1174d7a0c636c6e7390e68a88b95f5f90b5c" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ota3-dacfc.js", "sha256": "c838f77e2e7a2146b6ac55e2eabbb7341fb4a9bd4ea45b34057f8abbf4b215c4" }, "simulationFingerprints": { "op": "98baa22fad6fb877515dee4cddbad2a64c9cc1c45c65acb97f0679a3ee946fc6", "open_loop": "ddd9b37d36766fabf6bcb81289a689ae340be571695b69844b3bf82ddb61b527", "step": "aaa39fd133e1353d8c3495a2c89ff666b021d84dfea3599d584648c5e794e97c", "psrr": "8a1cf85224fd0b22ab4921a4bb935d55820cc448617a813444b54390d7049773", "cmrr": "1dec5e602cd511136b001234b36a40c30b9b019d6f81932b55bb7034b3c1ff8e", "noise": "444ac47d038e0188ac1f617b59e3479bccb934127e398023244884bc5aacce83" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "f8beb1075aec01a3c48fabed21f2d725b9ca6226897c0b49a9c2a2a99df1a452", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ota3-dacfc", "parameters": { "Ib": 0.0000025, "Wp": 0.0000081, "Lp": 0.000003, "W1": 0.0000089, "L1": 0.000001, "Wn": 0.0000057, "Ln": 0.000008, "Rb": 116000, "Wc": 0.0000049, "Lc": 0.000001, "Wm": 0.000003, "Lm": 0.0000015, "Km": 2, "W2": 0.0000019, "L2": 5e-7, "Wr": 0.0000041, "Lr": 0.000004, "W3": 0.0000043, "L3": 0.000002, "Kt": 1, "Ks": 2, "K2": 1, "Kf": 16, "N3": 4, "Ca": 1e-12, "Cf": 1e-11, "Kd": 3, "Rf": 50000, "Kx": 7, "CL": 1e-11, "VCM": 0.4 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ota3-dacfc/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "ota3dacfc", "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XM20 vbc ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=35.725u", "source": "XRb vbc vbn vss rhigh w=0.5u l=35.725u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM21", "displayName": "M21", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=1", "source": "XM21 vbn vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM1 f1 inn tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM2 f2 inp tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=5", "source": "XM3 f1 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=5", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=2", "source": "XM4 f2 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM5 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM6 o1 vbc f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=2", "source": "XM7 x1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=2", "source": "XM8 o1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.9u l=500n ng=1 m=1", "source": "XM9 d2 o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.1u l=4u ng=1 m=1", "source": "XM10 d2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.1u l=4u ng=1 m=1", "source": "XM11 o2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=1", "source": "XM12 o2 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.3u l=2u ng=1 m=4", "source": "XM13 out o2 vss vss sg13_lv_nmos w=4.3u l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.9u l=500n ng=1 m=16", "source": "XM14 out o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=16", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCa", "displayName": "Ca", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u", "source": "XCa s out cap_cmim w=25.767u l=25.767u", "pins": [ { "id": "p", "net": "s" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XM17", "displayName": "M17", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=4", "source": "XM17 s s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4", "pins": [ { "id": "d", "net": "s" }, { "id": "g", "net": "s" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM19", "displayName": "M19", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=4", "source": "XM19 x1 s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "s" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM22", "displayName": "M22", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=2", "source": "XM22 s vbc sm vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "s" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "sm" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM18", "displayName": "M18", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=3", "source": "XM18 sm vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=3", "pins": [ { "id": "d", "net": "sm" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM23", "displayName": "M23", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=2", "source": "XM23 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=8", "source": "XCf o1 vdd cap_cmim w=28.814u l=28.814u m=8", "pins": [ { "id": "p", "net": "o1" }, { "id": "n", "net": "vdd" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMT2", "displayName": "MT2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT2 s15 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "s15" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT3", "displayName": "MT3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT3 s16 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "s16" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRf", "displayName": "Rf", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=15.342u", "source": "XRf s15 s16 vss rhigh w=0.5u l=15.342u", "pins": [ { "id": "p", "net": "s15" }, { "id": "n", "net": "s16" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM15", "displayName": "M15", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM15 o2 inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "s15" }, { "id": "b", "net": "s15" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM24", "displayName": "M24", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=7", "source": "XM24 vss inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=7", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "s15" }, { "id": "b", "net": "s15" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM16", "displayName": "M16", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM16 d2 inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "s16" }, { "id": "b", "net": "s16" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM25", "displayName": "M25", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=7", "source": "XM25 vss inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=7", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "s16" }, { "id": "b", "net": "s16" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM20", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMT2", "pin": "g" }, { "device": "XMT3", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM20", "pin": "s" }, { "device": "XM20", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" }, { "device": "XM17", "pin": "s" }, { "device": "XM17", "pin": "b" }, { "device": "XM19", "pin": "s" }, { "device": "XM19", "pin": "b" }, { "device": "XCf", "pin": "n" }, { "device": "XMT2", "pin": "s" }, { "device": "XMT2", "pin": "b" }, { "device": "XMT3", "pin": "s" }, { "device": "XMT3", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XM20", "pin": "d" }, { "device": "XRb", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XM22", "pin": "g" }, { "device": "XM23", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRb", "pin": "n" }, { "device": "XM21", "pin": "d" }, { "device": "XM21", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XM18", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRb", "pin": "substrate" }, { "device": "XM21", "pin": "s" }, { "device": "XM21", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM22", "pin": "b" }, { "device": "XM18", "pin": "s" }, { "device": "XM18", "pin": "b" }, { "device": "XM23", "pin": "b" }, { "device": "XRf", "pin": "substrate" }, { "device": "XM24", "pin": "d" }, { "device": "XM25", "pin": "d" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" }, { "device": "XM23", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM16", "pin": "g" }, { "device": "XM25", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" }, { "device": "XM15", "pin": "g" }, { "device": "XM24", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM12", "pin": "g" }, { "device": "XM19", "pin": "d" }, { "device": "XM23", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM14", "pin": "g" }, { "device": "XCf", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XM10", "pin": "g" }, { "device": "XM11", "pin": "g" }, { "device": "XM16", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM13", "pin": "g" }, { "device": "XM15", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM13", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XCa", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "s", "ground": false, "terminals": [ { "device": "XCa", "pin": "p" }, { "device": "XM17", "pin": "d" }, { "device": "XM17", "pin": "g" }, { "device": "XM19", "pin": "g" }, { "device": "XM22", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "sm", "ground": false, "terminals": [ { "device": "XM22", "pin": "s" }, { "device": "XM18", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "s15", "ground": false, "terminals": [ { "device": "XMT2", "pin": "d" }, { "device": "XRf", "pin": "p" }, { "device": "XM15", "pin": "s" }, { "device": "XM15", "pin": "b" }, { "device": "XM24", "pin": "s" }, { "device": "XM24", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "s16", "ground": false, "terminals": [ { "device": "XMT3", "pin": "d" }, { "device": "XRf", "pin": "n" }, { "device": "XM16", "pin": "s" }, { "device": "XM16", "pin": "b" }, { "device": "XM25", "pin": "s" }, { "device": "XM25", "pin": "b" } ], "ports": [], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2.5u", "source": "Ib ib 0 2.5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota3dacfc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota3dacfc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota3dacfc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m", "source": "Vin inp 0 dc 400m", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota3dacfc", "name": "ota3dacfc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XM20 vbc ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=35.725u", "source": "XRb vbc vbn vss rhigh w=0.5u l=35.725u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM21", "displayName": "M21", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=1", "source": "XM21 vbn vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM1 f1 inn tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM2 f2 inp tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=5", "source": "XM3 f1 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=5", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=2", "source": "XM4 f2 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM5 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM6 o1 vbc f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=2", "source": "XM7 x1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=2", "source": "XM8 o1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.9u l=500n ng=1 m=1", "source": "XM9 d2 o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.1u l=4u ng=1 m=1", "source": "XM10 d2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.1u l=4u ng=1 m=1", "source": "XM11 o2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=1", "source": "XM12 o2 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.3u l=2u ng=1 m=4", "source": "XM13 out o2 vss vss sg13_lv_nmos w=4.3u l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.9u l=500n ng=1 m=16", "source": "XM14 out o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=16", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCa", "displayName": "Ca", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u", "source": "XCa s out cap_cmim w=25.767u l=25.767u", "pins": [ { "id": "p", "net": "s" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XM17", "displayName": "M17", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=4", "source": "XM17 s s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4", "pins": [ { "id": "d", "net": "s" }, { "id": "g", "net": "s" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM19", "displayName": "M19", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=4", "source": "XM19 x1 s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "s" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM22", "displayName": "M22", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=2", "source": "XM22 s vbc sm vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "s" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "sm" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM18", "displayName": "M18", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=3", "source": "XM18 sm vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=3", "pins": [ { "id": "d", "net": "sm" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM23", "displayName": "M23", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=2", "source": "XM23 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=8", "source": "XCf o1 vdd cap_cmim w=28.814u l=28.814u m=8", "pins": [ { "id": "p", "net": "o1" }, { "id": "n", "net": "vdd" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMT2", "displayName": "MT2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT2 s15 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "s15" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT3", "displayName": "MT3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT3 s16 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "s16" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRf", "displayName": "Rf", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=15.342u", "source": "XRf s15 s16 vss rhigh w=0.5u l=15.342u", "pins": [ { "id": "p", "net": "s15" }, { "id": "n", "net": "s16" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM15", "displayName": "M15", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM15 o2 inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "s15" }, { "id": "b", "net": "s15" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM24", "displayName": "M24", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=7", "source": "XM24 vss inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=7", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "s15" }, { "id": "b", "net": "s15" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM16", "displayName": "M16", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM16 d2 inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "s16" }, { "id": "b", "net": "s16" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM25", "displayName": "M25", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=7", "source": "XM25 vss inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=7", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "s16" }, { "id": "b", "net": "s16" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM20", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMT2", "pin": "g" }, { "device": "XMT3", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM20", "pin": "s" }, { "device": "XM20", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" }, { "device": "XM17", "pin": "s" }, { "device": "XM17", "pin": "b" }, { "device": "XM19", "pin": "s" }, { "device": "XM19", "pin": "b" }, { "device": "XCf", "pin": "n" }, { "device": "XMT2", "pin": "s" }, { "device": "XMT2", "pin": "b" }, { "device": "XMT3", "pin": "s" }, { "device": "XMT3", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XM20", "pin": "d" }, { "device": "XRb", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XM22", "pin": "g" }, { "device": "XM23", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRb", "pin": "n" }, { "device": "XM21", "pin": "d" }, { "device": "XM21", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XM18", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRb", "pin": "substrate" }, { "device": "XM21", "pin": "s" }, { "device": "XM21", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM22", "pin": "b" }, { "device": "XM18", "pin": "s" }, { "device": "XM18", "pin": "b" }, { "device": "XM23", "pin": "b" }, { "device": "XRf", "pin": "substrate" }, { "device": "XM24", "pin": "d" }, { "device": "XM25", "pin": "d" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" }, { "device": "XM23", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM16", "pin": "g" }, { "device": "XM25", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" }, { "device": "XM15", "pin": "g" }, { "device": "XM24", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM12", "pin": "g" }, { "device": "XM19", "pin": "d" }, { "device": "XM23", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM14", "pin": "g" }, { "device": "XCf", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XM10", "pin": "g" }, { "device": "XM11", "pin": "g" }, { "device": "XM16", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM13", "pin": "g" }, { "device": "XM15", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM13", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XCa", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "s", "ground": false, "terminals": [ { "device": "XCa", "pin": "p" }, { "device": "XM17", "pin": "d" }, { "device": "XM17", "pin": "g" }, { "device": "XM19", "pin": "g" }, { "device": "XM22", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "sm", "ground": false, "terminals": [ { "device": "XM22", "pin": "s" }, { "device": "XM18", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "s15", "ground": false, "terminals": [ { "device": "XMT2", "pin": "d" }, { "device": "XRf", "pin": "p" }, { "device": "XM15", "pin": "s" }, { "device": "XM15", "pin": "b" }, { "device": "XM24", "pin": "s" }, { "device": "XM24", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "s16", "ground": false, "terminals": [ { "device": "XMT3", "pin": "d" }, { "device": "XRf", "pin": "n" }, { "device": "XM16", "pin": "s" }, { "device": "XM16", "pin": "b" }, { "device": "XM25", "pin": "s" }, { "device": "XM25", "pin": "b" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota3dacfc" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Bias reference", "devices": [ { "scope": "dut", "device": "XMB" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "Copies Ib into the NMOS bias branch", "devices": [ { "scope": "dut", "device": "XM20" } ], "inferredStages": [ "bias" ] }, { "id": "block-3", "label": "Lifts the cascode bias vbc to Ib·Rb above vbn", "devices": [ { "scope": "dut", "device": "XRb" } ], "inferredStages": [ "bias" ] }, { "id": "block-4", "label": "NMOS bias diode: sets the sinks' gate vbn", "devices": [ { "scope": "dut", "device": "XM21" } ], "inferredStages": [ "bias" ] }, { "id": "block-5", "label": "Tail current source: Kt copies of MB", "devices": [ { "scope": "dut", "device": "XMT" } ], "inferredStages": [ 1 ] }, { "id": "block-6", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 1 ] }, { "id": "block-7", "label": "Folding sink: Ks + Kd copies of M21", "devices": [ { "scope": "dut", "device": "XM3" } ], "inferredStages": [ 1 ] }, { "id": "block-8", "label": "Folding sink: Ks copies of M21", "devices": [ { "scope": "dut", "device": "XM4" } ], "inferredStages": [ 1 ] }, { "id": "block-9", "label": "Cascode", "devices": [ { "scope": "dut", "device": "XM5" }, { "scope": "dut", "device": "XM6" } ], "inferredStages": [ 2 ] }, { "id": "block-10", "label": "Mirror load", "devices": [ { "scope": "dut", "device": "XM7" } ], "inferredStages": [ 2 ] }, { "id": "block-11", "label": "Mirror load: the first stage's output o1; Km unit copies", "devices": [ { "scope": "dut", "device": "XM8" } ], "inferredStages": [ 2 ] }, { "id": "block-12", "label": "Second-stage input: turns o1 into a current", "devices": [ { "scope": "dut", "device": "XM9" } ], "inferredStages": [ 1 ] }, { "id": "block-13", "label": "Second-stage mirror", "devices": [ { "scope": "dut", "device": "XM10" } ], "inferredStages": [ 1 ] }, { "id": "block-14", "label": "Second-stage mirror: drives o2", "devices": [ { "scope": "dut", "device": "XM11" } ], "inferredStages": [ 1 ] }, { "id": "block-15", "label": "Second-stage load: K2 copies of the M7 unit on x1 - adds the first stage's signal to o2 (cross feedforward)", "devices": [ { "scope": "dut", "device": "XM12" } ], "inferredStages": [ 1 ] }, { "id": "block-16", "label": "Output device", "devices": [ { "scope": "dut", "device": "XM13" } ], "inferredStages": [ 2 ] }, { "id": "block-17", "label": "Output source and feedforward path: Kf copies of M9", "devices": [ { "scope": "dut", "device": "XM14" } ], "inferredStages": [ 2 ] }, { "id": "block-18", "label": "The one feedback capacitor", "devices": [ { "scope": "dut", "device": "XCa" } ], "inferredStages": [ 2 ] }, { "id": "block-19", "label": "Sensing diode: 2*Km mirror units", "devices": [ { "scope": "dut", "device": "XM17" } ], "inferredStages": [ "bias" ] }, { "id": "block-20", "label": "Copies the sensed current into x1", "devices": [ { "scope": "dut", "device": "XM19" } ], "inferredStages": [ 2 ] }, { "id": "block-21", "label": "Sensor sink's cascode: two cascode units", "devices": [ { "scope": "dut", "device": "XM22" } ], "inferredStages": [ "bias" ] }, { "id": "block-22", "label": "Sensor sink: Kd copies of M21", "devices": [ { "scope": "dut", "device": "XM18" } ], "inferredStages": [ "bias" ] }, { "id": "block-23", "label": "Two cascode units beside M5: M5 carries the sensor's current too", "devices": [ { "scope": "dut", "device": "XM23" } ], "inferredStages": [ 2 ] }, { "id": "block-24", "label": "Loads o1 to V_DD and helps damp the Ca loop; imperfect supply tracking can still couple ripple into o1", "devices": [ { "scope": "dut", "device": "XCf" } ], "inferredStages": [ 2 ] }, { "id": "block-25", "label": "Feedforward tail", "devices": [ { "scope": "dut", "device": "XMT2" }, { "scope": "dut", "device": "XMT3" } ], "inferredStages": [ 1 ] }, { "id": "block-26", "label": "Between the feedforward sources: keeps the pair linear through a step", "devices": [ { "scope": "dut", "device": "XRf" } ], "inferredStages": [ 1 ] }, { "id": "block-27", "label": "Feedforward input", "devices": [ { "scope": "dut", "device": "XM15" }, { "scope": "dut", "device": "XM16" } ], "inferredStages": [ 1 ] }, { "id": "block-28", "label": "The rest of that side: Kx units", "devices": [ { "scope": "dut", "device": "XM24" }, { "scope": "dut", "device": "XM25" } ], "inferredStages": [ 1 ] } ], "edges": [ { "id": "net-1", "net": "ib", "nodes": [ "block-1", "block-2", "block-5", "block-25" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "vbc", "nodes": [ "block-2", "block-3", "block-9", "block-21", "block-23" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "vbn", "nodes": [ "block-3", "block-4", "block-7", "block-8", "block-22" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "tail", "nodes": [ "block-5", "block-6" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "f1", "nodes": [ "block-6", "block-7", "block-9", "block-23" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "inn", "nodes": [ "block-6", "block-27", "block-28" ], "direction": "undirected-shared-net" }, { "id": "net-7", "net": "f2", "nodes": [ "block-6", "block-8", "block-9" ], "direction": "undirected-shared-net" }, { "id": "net-8", "net": "inp", "nodes": [ "block-6", "block-27", "block-28" ], "direction": "undirected-shared-net" }, { "id": "net-9", "net": "x1", "nodes": [ "block-9", "block-10", "block-11", "block-15", "block-20", "block-23" ], "direction": "undirected-shared-net" }, { "id": "net-10", "net": "o1", "nodes": [ "block-9", "block-11", "block-12", "block-17", "block-24" ], "direction": "undirected-shared-net" }, { "id": "net-11", "net": "d2", "nodes": [ "block-12", "block-13", "block-14", "block-27" ], "direction": "undirected-shared-net" }, { "id": "net-12", "net": "o2", "nodes": [ "block-14", "block-15", "block-16", "block-27" ], "direction": "undirected-shared-net" }, { "id": "net-13", "net": "out", "nodes": [ "block-16", "block-17", "block-18" ], "direction": "undirected-shared-net" }, { "id": "net-14", "net": "s", "nodes": [ "block-18", "block-19", "block-20", "block-21" ], "direction": "undirected-shared-net" }, { "id": "net-15", "net": "sm", "nodes": [ "block-21", "block-22" ], "direction": "undirected-shared-net" }, { "id": "net-16", "net": "s15", "nodes": [ "block-25", "block-26", "block-27", "block-28" ], "direction": "undirected-shared-net" }, { "id": "net-17", "net": "s16", "nodes": [ "block-25", "block-26", "block-27", "block-28" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2.5u", "source": "Ib ib 0 2.5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota3dacfc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota3dacfc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota3dacfc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m ac 1", "source": "Vin inp 0 dc 400m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfb", "displayName": "Lfb", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfb out inn 1t", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cfb", "displayName": "Cfb", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cfb inn 0 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" }, { "device": "Cfb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Lfb", "pin": "n" }, { "device": "Cfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Lfb", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota3dacfc", "name": "ota3dacfc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XM20 vbc ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=35.725u", "source": "XRb vbc vbn vss rhigh w=0.5u l=35.725u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM21", "displayName": "M21", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=1", "source": "XM21 vbn vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM1 f1 inn tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM2 f2 inp tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=5", "source": "XM3 f1 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=5", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=2", "source": "XM4 f2 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM5 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM6 o1 vbc f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=2", "source": "XM7 x1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=2", "source": "XM8 o1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.9u l=500n ng=1 m=1", "source": "XM9 d2 o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.1u l=4u ng=1 m=1", "source": "XM10 d2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.1u l=4u ng=1 m=1", "source": "XM11 o2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=1", "source": "XM12 o2 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.3u l=2u ng=1 m=4", "source": "XM13 out o2 vss vss sg13_lv_nmos w=4.3u l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.9u l=500n ng=1 m=16", "source": "XM14 out o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=16", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCa", "displayName": "Ca", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u", "source": "XCa s out cap_cmim w=25.767u l=25.767u", "pins": [ { "id": "p", "net": "s" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XM17", "displayName": "M17", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=4", "source": "XM17 s s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4", "pins": [ { "id": "d", "net": "s" }, { "id": "g", "net": "s" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM19", "displayName": "M19", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=4", "source": "XM19 x1 s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "s" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM22", "displayName": "M22", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=2", "source": "XM22 s vbc sm vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "s" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "sm" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM18", "displayName": "M18", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=3", "source": "XM18 sm vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=3", "pins": [ { "id": "d", "net": "sm" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM23", "displayName": "M23", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=2", "source": "XM23 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=8", "source": "XCf o1 vdd cap_cmim w=28.814u l=28.814u m=8", "pins": [ { "id": "p", "net": "o1" }, { "id": "n", "net": "vdd" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMT2", "displayName": "MT2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT2 s15 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "s15" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT3", "displayName": "MT3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT3 s16 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "s16" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRf", "displayName": "Rf", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=15.342u", "source": "XRf s15 s16 vss rhigh w=0.5u l=15.342u", "pins": [ { "id": "p", "net": "s15" }, { "id": "n", "net": "s16" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM15", "displayName": "M15", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM15 o2 inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "s15" }, { "id": "b", "net": "s15" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM24", "displayName": "M24", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=7", "source": "XM24 vss inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=7", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "s15" }, { "id": "b", "net": "s15" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM16", "displayName": "M16", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM16 d2 inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "s16" }, { "id": "b", "net": "s16" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM25", "displayName": "M25", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=7", "source": "XM25 vss inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=7", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "s16" }, { "id": "b", "net": "s16" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM20", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMT2", "pin": "g" }, { "device": "XMT3", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM20", "pin": "s" }, { "device": "XM20", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" }, { "device": "XM17", "pin": "s" }, { "device": "XM17", "pin": "b" }, { "device": "XM19", "pin": "s" }, { "device": "XM19", "pin": "b" }, { "device": "XCf", "pin": "n" }, { "device": "XMT2", "pin": "s" }, { "device": "XMT2", "pin": "b" }, { "device": "XMT3", "pin": "s" }, { "device": "XMT3", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XM20", "pin": "d" }, { "device": "XRb", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XM22", "pin": "g" }, { "device": "XM23", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRb", "pin": "n" }, { "device": "XM21", "pin": "d" }, { "device": "XM21", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XM18", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRb", "pin": "substrate" }, { "device": "XM21", "pin": "s" }, { "device": "XM21", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM22", "pin": "b" }, { "device": "XM18", "pin": "s" }, { "device": "XM18", "pin": "b" }, { "device": "XM23", "pin": "b" }, { "device": "XRf", "pin": "substrate" }, { "device": "XM24", "pin": "d" }, { "device": "XM25", "pin": "d" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" }, { "device": "XM23", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM16", "pin": "g" }, { "device": "XM25", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" }, { "device": "XM15", "pin": "g" }, { "device": "XM24", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM12", "pin": "g" }, { "device": "XM19", "pin": "d" }, { "device": "XM23", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM14", "pin": "g" }, { "device": "XCf", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XM10", "pin": "g" }, { "device": "XM11", "pin": "g" }, { "device": "XM16", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM13", "pin": "g" }, { "device": "XM15", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM13", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XCa", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "s", "ground": false, "terminals": [ { "device": "XCa", "pin": "p" }, { "device": "XM17", "pin": "d" }, { "device": "XM17", "pin": "g" }, { "device": "XM19", "pin": "g" }, { "device": "XM22", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "sm", "ground": false, "terminals": [ { "device": "XM22", "pin": "s" }, { "device": "XM18", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "s15", "ground": false, "terminals": [ { "device": "XMT2", "pin": "d" }, { "device": "XRf", "pin": "p" }, { "device": "XM15", "pin": "s" }, { "device": "XM15", "pin": "b" }, { "device": "XM24", "pin": "s" }, { "device": "XM24", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "s16", "ground": false, "terminals": [ { "device": "XMT3", "pin": "d" }, { "device": "XRf", "pin": "n" }, { "device": "XM16", "pin": "s" }, { "device": "XM16", "pin": "b" }, { "device": "XM25", "pin": "s" }, { "device": "XM25", "pin": "b" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota3dacfc" } }, { "id": "graph-5", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2.5u", "source": "Ib ib 0 2.5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota3dacfc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota3dacfc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota3dacfc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "pulse(300m 500m 400n 1n 1n 2u 8u)", "source": "Vin inp 0 pulse(300m 500m 400n 1n 1n 2u 8u)", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota3dacfc", "name": "ota3dacfc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XM20 vbc ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=35.725u", "source": "XRb vbc vbn vss rhigh w=0.5u l=35.725u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM21", "displayName": "M21", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=1", "source": "XM21 vbn vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM1 f1 inn tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM2 f2 inp tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=5", "source": "XM3 f1 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=5", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=2", "source": "XM4 f2 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM5 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM6 o1 vbc f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=2", "source": "XM7 x1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=2", "source": "XM8 o1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.9u l=500n ng=1 m=1", "source": "XM9 d2 o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.1u l=4u ng=1 m=1", "source": "XM10 d2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.1u l=4u ng=1 m=1", "source": "XM11 o2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=1", "source": "XM12 o2 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.3u l=2u ng=1 m=4", "source": "XM13 out o2 vss vss sg13_lv_nmos w=4.3u l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.9u l=500n ng=1 m=16", "source": "XM14 out o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=16", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCa", "displayName": "Ca", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u", "source": "XCa s out cap_cmim w=25.767u l=25.767u", "pins": [ { "id": "p", "net": "s" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XM17", "displayName": "M17", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=4", "source": "XM17 s s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4", "pins": [ { "id": "d", "net": "s" }, { "id": "g", "net": "s" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM19", "displayName": "M19", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=4", "source": "XM19 x1 s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "s" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM22", "displayName": "M22", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=2", "source": "XM22 s vbc sm vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "s" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "sm" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM18", "displayName": "M18", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=3", "source": "XM18 sm vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=3", "pins": [ { "id": "d", "net": "sm" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM23", "displayName": "M23", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=2", "source": "XM23 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=8", "source": "XCf o1 vdd cap_cmim w=28.814u l=28.814u m=8", "pins": [ { "id": "p", "net": "o1" }, { "id": "n", "net": "vdd" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMT2", "displayName": "MT2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT2 s15 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "s15" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT3", "displayName": "MT3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT3 s16 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "s16" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRf", "displayName": "Rf", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=15.342u", "source": "XRf s15 s16 vss rhigh w=0.5u l=15.342u", "pins": [ { "id": "p", "net": "s15" }, { "id": "n", "net": "s16" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM15", "displayName": "M15", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM15 o2 inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "s15" }, { "id": "b", "net": "s15" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM24", "displayName": "M24", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=7", "source": "XM24 vss inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=7", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "s15" }, { "id": "b", "net": "s15" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM16", "displayName": "M16", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM16 d2 inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "s16" }, { "id": "b", "net": "s16" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM25", "displayName": "M25", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=7", "source": "XM25 vss inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=7", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "s16" }, { "id": "b", "net": "s16" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM20", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMT2", "pin": "g" }, { "device": "XMT3", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM20", "pin": "s" }, { "device": "XM20", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" }, { "device": "XM17", "pin": "s" }, { "device": "XM17", "pin": "b" }, { "device": "XM19", "pin": "s" }, { "device": "XM19", "pin": "b" }, { "device": "XCf", "pin": "n" }, { "device": "XMT2", "pin": "s" }, { "device": "XMT2", "pin": "b" }, { "device": "XMT3", "pin": "s" }, { "device": "XMT3", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XM20", "pin": "d" }, { "device": "XRb", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XM22", "pin": "g" }, { "device": "XM23", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRb", "pin": "n" }, { "device": "XM21", "pin": "d" }, { "device": "XM21", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XM18", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRb", "pin": "substrate" }, { "device": "XM21", "pin": "s" }, { "device": "XM21", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM22", "pin": "b" }, { "device": "XM18", "pin": "s" }, { "device": "XM18", "pin": "b" }, { "device": "XM23", "pin": "b" }, { "device": "XRf", "pin": "substrate" }, { "device": "XM24", "pin": "d" }, { "device": "XM25", "pin": "d" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" }, { "device": "XM23", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM16", "pin": "g" }, { "device": "XM25", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" }, { "device": "XM15", "pin": "g" }, { "device": "XM24", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM12", "pin": "g" }, { "device": "XM19", "pin": "d" }, { "device": "XM23", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM14", "pin": "g" }, { "device": "XCf", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XM10", "pin": "g" }, { "device": "XM11", "pin": "g" }, { "device": "XM16", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM13", "pin": "g" }, { "device": "XM15", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM13", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XCa", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "s", "ground": false, "terminals": [ { "device": "XCa", "pin": "p" }, { "device": "XM17", "pin": "d" }, { "device": "XM17", "pin": "g" }, { "device": "XM19", "pin": "g" }, { "device": "XM22", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "sm", "ground": false, "terminals": [ { "device": "XM22", "pin": "s" }, { "device": "XM18", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "s15", "ground": false, "terminals": [ { "device": "XMT2", "pin": "d" }, { "device": "XRf", "pin": "p" }, { "device": "XM15", "pin": "s" }, { "device": "XM15", "pin": "b" }, { "device": "XM24", "pin": "s" }, { "device": "XM24", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "s16", "ground": false, "terminals": [ { "device": "XMT3", "pin": "d" }, { "device": "XRf", "pin": "n" }, { "device": "XM16", "pin": "s" }, { "device": "XM16", "pin": "b" }, { "device": "XM25", "pin": "s" }, { "device": "XM25", "pin": "b" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota3dacfc" } }, { "id": "graph-6", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD} ac 1", "source": "Vdd vdd 0 dc {VDD} ac 1", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2.5u", "source": "Ib ib 0 2.5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota3dacfc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota3dacfc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota3dacfc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m", "source": "Vin inp 0 dc 400m", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota3dacfc", "name": "ota3dacfc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XM20 vbc ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=35.725u", "source": "XRb vbc vbn vss rhigh w=0.5u l=35.725u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM21", "displayName": "M21", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=1", "source": "XM21 vbn vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM1 f1 inn tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM2 f2 inp tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=5", "source": "XM3 f1 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=5", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=2", "source": "XM4 f2 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM5 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM6 o1 vbc f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=2", "source": "XM7 x1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=2", "source": "XM8 o1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.9u l=500n ng=1 m=1", "source": "XM9 d2 o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.1u l=4u ng=1 m=1", "source": "XM10 d2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.1u l=4u ng=1 m=1", "source": "XM11 o2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=1", "source": "XM12 o2 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.3u l=2u ng=1 m=4", "source": "XM13 out o2 vss vss sg13_lv_nmos w=4.3u l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.9u l=500n ng=1 m=16", "source": "XM14 out o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=16", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCa", "displayName": "Ca", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u", "source": "XCa s out cap_cmim w=25.767u l=25.767u", "pins": [ { "id": "p", "net": "s" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XM17", "displayName": "M17", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=4", "source": "XM17 s s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4", "pins": [ { "id": "d", "net": "s" }, { "id": "g", "net": "s" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM19", "displayName": "M19", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=4", "source": "XM19 x1 s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "s" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM22", "displayName": "M22", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=2", "source": "XM22 s vbc sm vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "s" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "sm" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM18", "displayName": "M18", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=3", "source": "XM18 sm vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=3", "pins": [ { "id": "d", "net": "sm" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM23", "displayName": "M23", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=2", "source": "XM23 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=8", "source": "XCf o1 vdd cap_cmim w=28.814u l=28.814u m=8", "pins": [ { "id": "p", "net": "o1" }, { "id": "n", "net": "vdd" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMT2", "displayName": "MT2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT2 s15 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "s15" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT3", "displayName": "MT3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT3 s16 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "s16" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRf", "displayName": "Rf", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=15.342u", "source": "XRf s15 s16 vss rhigh w=0.5u l=15.342u", "pins": [ { "id": "p", "net": "s15" }, { "id": "n", "net": "s16" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM15", "displayName": "M15", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM15 o2 inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "s15" }, { "id": "b", "net": "s15" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM24", "displayName": "M24", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=7", "source": "XM24 vss inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=7", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "s15" }, { "id": "b", "net": "s15" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM16", "displayName": "M16", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM16 d2 inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "s16" }, { "id": "b", "net": "s16" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM25", "displayName": "M25", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=7", "source": "XM25 vss inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=7", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "s16" }, { "id": "b", "net": "s16" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM20", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMT2", "pin": "g" }, { "device": "XMT3", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM20", "pin": "s" }, { "device": "XM20", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" }, { "device": "XM17", "pin": "s" }, { "device": "XM17", "pin": "b" }, { "device": "XM19", "pin": "s" }, { "device": "XM19", "pin": "b" }, { "device": "XCf", "pin": "n" }, { "device": "XMT2", "pin": "s" }, { "device": "XMT2", "pin": "b" }, { "device": "XMT3", "pin": "s" }, { "device": "XMT3", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XM20", "pin": "d" }, { "device": "XRb", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XM22", "pin": "g" }, { "device": "XM23", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRb", "pin": "n" }, { "device": "XM21", "pin": "d" }, { "device": "XM21", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XM18", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRb", "pin": "substrate" }, { "device": "XM21", "pin": "s" }, { "device": "XM21", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM22", "pin": "b" }, { "device": "XM18", "pin": "s" }, { "device": "XM18", "pin": "b" }, { "device": "XM23", "pin": "b" }, { "device": "XRf", "pin": "substrate" }, { "device": "XM24", "pin": "d" }, { "device": "XM25", "pin": "d" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" }, { "device": "XM23", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM16", "pin": "g" }, { "device": "XM25", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" }, { "device": "XM15", "pin": "g" }, { "device": "XM24", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM12", "pin": "g" }, { "device": "XM19", "pin": "d" }, { "device": "XM23", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM14", "pin": "g" }, { "device": "XCf", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XM10", "pin": "g" }, { "device": "XM11", "pin": "g" }, { "device": "XM16", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM13", "pin": "g" }, { "device": "XM15", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM13", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XCa", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "s", "ground": false, "terminals": [ { "device": "XCa", "pin": "p" }, { "device": "XM17", "pin": "d" }, { "device": "XM17", "pin": "g" }, { "device": "XM19", "pin": "g" }, { "device": "XM22", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "sm", "ground": false, "terminals": [ { "device": "XM22", "pin": "s" }, { "device": "XM18", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "s15", "ground": false, "terminals": [ { "device": "XMT2", "pin": "d" }, { "device": "XRf", "pin": "p" }, { "device": "XM15", "pin": "s" }, { "device": "XM15", "pin": "b" }, { "device": "XM24", "pin": "s" }, { "device": "XM24", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "s16", "ground": false, "terminals": [ { "device": "XMT3", "pin": "d" }, { "device": "XRf", "pin": "n" }, { "device": "XM16", "pin": "s" }, { "device": "XM16", "pin": "b" }, { "device": "XM25", "pin": "s" }, { "device": "XM25", "pin": "b" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota3dacfc" } }, { "id": "graph-7", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2.5u", "source": "Ib ib 0 2.5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota3dacfc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota3dacfc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota3dacfc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vsrc", "displayName": "Vsrc", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m", "source": "Vsrc src 0 dc 400m", "pins": [ { "id": "p", "net": "src" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Va", "displayName": "Va", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Va inp src dc 0 ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "src" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vb", "displayName": "Vb", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Vb inn out dc 0 ac 1", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vsrc", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Va", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "src", "ground": false, "terminals": [ { "device": "Vsrc", "pin": "p" }, { "device": "Va", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota3dacfc", "name": "ota3dacfc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XM20 vbc ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=35.725u", "source": "XRb vbc vbn vss rhigh w=0.5u l=35.725u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM21", "displayName": "M21", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=1", "source": "XM21 vbn vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM1 f1 inn tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM2 f2 inp tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=5", "source": "XM3 f1 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=5", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=2", "source": "XM4 f2 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM5 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM6 o1 vbc f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=2", "source": "XM7 x1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=2", "source": "XM8 o1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.9u l=500n ng=1 m=1", "source": "XM9 d2 o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.1u l=4u ng=1 m=1", "source": "XM10 d2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.1u l=4u ng=1 m=1", "source": "XM11 o2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=1", "source": "XM12 o2 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.3u l=2u ng=1 m=4", "source": "XM13 out o2 vss vss sg13_lv_nmos w=4.3u l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.9u l=500n ng=1 m=16", "source": "XM14 out o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=16", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCa", "displayName": "Ca", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u", "source": "XCa s out cap_cmim w=25.767u l=25.767u", "pins": [ { "id": "p", "net": "s" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XM17", "displayName": "M17", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=4", "source": "XM17 s s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4", "pins": [ { "id": "d", "net": "s" }, { "id": "g", "net": "s" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM19", "displayName": "M19", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=4", "source": "XM19 x1 s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "s" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM22", "displayName": "M22", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=2", "source": "XM22 s vbc sm vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "s" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "sm" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM18", "displayName": "M18", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=3", "source": "XM18 sm vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=3", "pins": [ { "id": "d", "net": "sm" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM23", "displayName": "M23", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=2", "source": "XM23 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=8", "source": "XCf o1 vdd cap_cmim w=28.814u l=28.814u m=8", "pins": [ { "id": "p", "net": "o1" }, { "id": "n", "net": "vdd" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMT2", "displayName": "MT2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT2 s15 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "s15" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT3", "displayName": "MT3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT3 s16 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "s16" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRf", "displayName": "Rf", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=15.342u", "source": "XRf s15 s16 vss rhigh w=0.5u l=15.342u", "pins": [ { "id": "p", "net": "s15" }, { "id": "n", "net": "s16" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM15", "displayName": "M15", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM15 o2 inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "s15" }, { "id": "b", "net": "s15" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM24", "displayName": "M24", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=7", "source": "XM24 vss inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=7", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "s15" }, { "id": "b", "net": "s15" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM16", "displayName": "M16", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM16 d2 inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "s16" }, { "id": "b", "net": "s16" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM25", "displayName": "M25", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=7", "source": "XM25 vss inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=7", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "s16" }, { "id": "b", "net": "s16" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM20", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMT2", "pin": "g" }, { "device": "XMT3", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM20", "pin": "s" }, { "device": "XM20", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" }, { "device": "XM17", "pin": "s" }, { "device": "XM17", "pin": "b" }, { "device": "XM19", "pin": "s" }, { "device": "XM19", "pin": "b" }, { "device": "XCf", "pin": "n" }, { "device": "XMT2", "pin": "s" }, { "device": "XMT2", "pin": "b" }, { "device": "XMT3", "pin": "s" }, { "device": "XMT3", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XM20", "pin": "d" }, { "device": "XRb", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XM22", "pin": "g" }, { "device": "XM23", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRb", "pin": "n" }, { "device": "XM21", "pin": "d" }, { "device": "XM21", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XM18", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRb", "pin": "substrate" }, { "device": "XM21", "pin": "s" }, { "device": "XM21", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM22", "pin": "b" }, { "device": "XM18", "pin": "s" }, { "device": "XM18", "pin": "b" }, { "device": "XM23", "pin": "b" }, { "device": "XRf", "pin": "substrate" }, { "device": "XM24", "pin": "d" }, { "device": "XM25", "pin": "d" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" }, { "device": "XM23", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM16", "pin": "g" }, { "device": "XM25", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" }, { "device": "XM15", "pin": "g" }, { "device": "XM24", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM12", "pin": "g" }, { "device": "XM19", "pin": "d" }, { "device": "XM23", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM14", "pin": "g" }, { "device": "XCf", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XM10", "pin": "g" }, { "device": "XM11", "pin": "g" }, { "device": "XM16", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM13", "pin": "g" }, { "device": "XM15", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM13", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XCa", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "s", "ground": false, "terminals": [ { "device": "XCa", "pin": "p" }, { "device": "XM17", "pin": "d" }, { "device": "XM17", "pin": "g" }, { "device": "XM19", "pin": "g" }, { "device": "XM22", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "sm", "ground": false, "terminals": [ { "device": "XM22", "pin": "s" }, { "device": "XM18", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "s15", "ground": false, "terminals": [ { "device": "XMT2", "pin": "d" }, { "device": "XRf", "pin": "p" }, { "device": "XM15", "pin": "s" }, { "device": "XM15", "pin": "b" }, { "device": "XM24", "pin": "s" }, { "device": "XM24", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "s16", "ground": false, "terminals": [ { "device": "XMT3", "pin": "d" }, { "device": "XRf", "pin": "n" }, { "device": "XM16", "pin": "s" }, { "device": "XM16", "pin": "b" }, { "device": "XM25", "pin": "s" }, { "device": "XM25", "pin": "b" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota3dacfc" } }, { "id": "graph-8", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2.5u", "source": "Ib ib 0 2.5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota3dacfc", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota3dacfc", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota3dacfc" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m ac 1", "source": "Vin inp 0 dc 400m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota3dacfc", "name": "ota3dacfc", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XM20 vbc ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=35.725u", "source": "XRb vbc vbn vss rhigh w=0.5u l=35.725u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM21", "displayName": "M21", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=1", "source": "XM21 vbn vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM1 f1 inn tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM2 f2 inp tail tail sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=5", "source": "XM3 f1 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=5", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=2", "source": "XM4 f2 vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM5 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=1", "source": "XM6 o1 vbc f2 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=2", "source": "XM7 x1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=2", "source": "XM8 o1 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=2", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.9u l=500n ng=1 m=1", "source": "XM9 d2 o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.1u l=4u ng=1 m=1", "source": "XM10 d2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.1u l=4u ng=1 m=1", "source": "XM11 o2 d2 vss vss sg13_lv_nmos w=4.1u l=4u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=1", "source": "XM12 o2 x1 vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.3u l=2u ng=1 m=4", "source": "XM13 out o2 vss vss sg13_lv_nmos w=4.3u l=2u ng=1 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1.9u l=500n ng=1 m=16", "source": "XM14 out o1 vdd vdd sg13_lv_pmos w=1.9u l=500n ng=1 m=16", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCa", "displayName": "Ca", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u", "source": "XCa s out cap_cmim w=25.767u l=25.767u", "pins": [ { "id": "p", "net": "s" }, { "id": "n", "net": "out" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XM17", "displayName": "M17", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=4", "source": "XM17 s s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4", "pins": [ { "id": "d", "net": "s" }, { "id": "g", "net": "s" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM19", "displayName": "M19", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=3u l=1.5u ng=1 m=4", "source": "XM19 x1 s vdd vdd sg13_lv_pmos w=3u l=1.5u ng=1 m=4", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "s" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM22", "displayName": "M22", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=2", "source": "XM22 s vbc sm vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "s" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "sm" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM18", "displayName": "M18", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=8u ng=2 m=3", "source": "XM18 sm vbn vss vss sg13_lv_nmos w=5.7u l=8u ng=2 m=3", "pins": [ { "id": "d", "net": "sm" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM23", "displayName": "M23", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4.9u l=1u ng=1 m=2", "source": "XM23 x1 vbc f1 vss sg13_lv_nmos w=4.9u l=1u ng=1 m=2", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCf", "displayName": "Cf", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=28.814u l=28.814u m=8", "source": "XCf o1 vdd cap_cmim w=28.814u l=28.814u m=8", "pins": [ { "id": "p", "net": "o1" }, { "id": "n", "net": "vdd" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XMT2", "displayName": "MT2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT2 s15 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "s15" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT3", "displayName": "MT3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XMT3 s16 ib vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "s16" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRf", "displayName": "Rf", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=15.342u", "source": "XRf s15 s16 vss rhigh w=0.5u l=15.342u", "pins": [ { "id": "p", "net": "s15" }, { "id": "n", "net": "s16" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM15", "displayName": "M15", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM15 o2 inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "s15" }, { "id": "b", "net": "s15" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM24", "displayName": "M24", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=7", "source": "XM24 vss inp s15 s15 sg13_lv_pmos w=8.9u l=1u ng=2 m=7", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "s15" }, { "id": "b", "net": "s15" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM16", "displayName": "M16", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=1", "source": "XM16 d2 inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "s16" }, { "id": "b", "net": "s16" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM25", "displayName": "M25", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.9u l=1u ng=2 m=7", "source": "XM25 vss inn s16 s16 sg13_lv_pmos w=8.9u l=1u ng=2 m=7", "pins": [ { "id": "d", "net": "vss" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "s16" }, { "id": "b", "net": "s16" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM20", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XMT2", "pin": "g" }, { "device": "XMT3", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM20", "pin": "s" }, { "device": "XM20", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" }, { "device": "XM17", "pin": "s" }, { "device": "XM17", "pin": "b" }, { "device": "XM19", "pin": "s" }, { "device": "XM19", "pin": "b" }, { "device": "XCf", "pin": "n" }, { "device": "XMT2", "pin": "s" }, { "device": "XMT2", "pin": "b" }, { "device": "XMT3", "pin": "s" }, { "device": "XMT3", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XM20", "pin": "d" }, { "device": "XRb", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XM22", "pin": "g" }, { "device": "XM23", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRb", "pin": "n" }, { "device": "XM21", "pin": "d" }, { "device": "XM21", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" }, { "device": "XM18", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRb", "pin": "substrate" }, { "device": "XM21", "pin": "s" }, { "device": "XM21", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XM22", "pin": "b" }, { "device": "XM18", "pin": "s" }, { "device": "XM18", "pin": "b" }, { "device": "XM23", "pin": "b" }, { "device": "XRf", "pin": "substrate" }, { "device": "XM24", "pin": "d" }, { "device": "XM25", "pin": "d" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" }, { "device": "XM23", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM16", "pin": "g" }, { "device": "XM25", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" }, { "device": "XM15", "pin": "g" }, { "device": "XM24", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM12", "pin": "g" }, { "device": "XM19", "pin": "d" }, { "device": "XM23", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XM14", "pin": "g" }, { "device": "XCf", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XM10", "pin": "g" }, { "device": "XM11", "pin": "g" }, { "device": "XM16", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM13", "pin": "g" }, { "device": "XM15", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM13", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XCa", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "s", "ground": false, "terminals": [ { "device": "XCa", "pin": "p" }, { "device": "XM17", "pin": "d" }, { "device": "XM17", "pin": "g" }, { "device": "XM19", "pin": "g" }, { "device": "XM22", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "sm", "ground": false, "terminals": [ { "device": "XM22", "pin": "s" }, { "device": "XM18", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "s15", "ground": false, "terminals": [ { "device": "XMT2", "pin": "d" }, { "device": "XRf", "pin": "p" }, { "device": "XM15", "pin": "s" }, { "device": "XM15", "pin": "b" }, { "device": "XM24", "pin": "s" }, { "device": "XM24", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "s16", "ground": false, "terminals": [ { "device": "XMT3", "pin": "d" }, { "device": "XRf", "pin": "n" }, { "device": "XM16", "pin": "s" }, { "device": "XM16", "pin": "b" }, { "device": "XM25", "pin": "s" }, { "device": "XM25", "pin": "b" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota3dacfc" } } ], "views": [ { "bench": "op", "source": { "recordField": "testbenches", "id": "op", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota3-dacfc/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Three-stage op amp, dual active-capacitive feedback", "instances": [] } ] }, "benchDiagram": { "graph": "graph-2", "svg": { "url": "/circuits/ota3-dacfc/op-bench.svg", "asset": "op-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota3-dacfc/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "open_loop", "source": { "recordField": "testbenches", "id": "open_loop", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota3-dacfc/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Three-stage op amp, dual active-capacitive feedback", "instances": [] } ] }, "benchDiagram": { "graph": "graph-4", "svg": { "url": "/circuits/ota3-dacfc/open_loop-bench.svg", "asset": "open_loop-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota3-dacfc/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "step", "source": { "recordField": "testbenches", "id": "step", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota3-dacfc/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Three-stage op amp, dual active-capacitive feedback", "instances": [] } ] }, "benchDiagram": { "graph": "graph-5", "svg": { "url": "/circuits/ota3-dacfc/step-bench.svg", "asset": "step-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota3-dacfc/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "psrr", "source": { "recordField": "testbenches", "id": "psrr", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota3-dacfc/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Three-stage op amp, dual active-capacitive feedback", "instances": [] } ] }, "benchDiagram": { "graph": "graph-6", "svg": { "url": "/circuits/ota3-dacfc/psrr-bench.svg", "asset": "psrr-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota3-dacfc/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "cmrr", "source": { "recordField": "testbenches", "id": "cmrr", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota3-dacfc/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Three-stage op amp, dual active-capacitive feedback", "instances": [] } ] }, "benchDiagram": { "graph": "graph-7", "svg": { "url": "/circuits/ota3-dacfc/cmrr-bench.svg", "asset": "cmrr-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota3-dacfc/op-block.svg", "asset": "op-block.svg" } } }, { "bench": "noise", "source": { "recordField": "testbenches", "id": "noise", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/ota3-dacfc/op-schematic.svg", "asset": "op-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Three-stage op amp, dual active-capacitive feedback", "instances": [] } ] }, "benchDiagram": { "graph": "graph-8", "svg": { "url": "/circuits/ota3-dacfc/noise-bench.svg", "asset": "noise-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/ota3-dacfc/op-block.svg", "asset": "op-block.svg" } } } ] } }