{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ota3-nmcnr", "name": "Three-stage op amp, nested Miller, nulling resistor", "group": "Op amps and OTAs", "subgroup": "Three-stage op amps", "title": "Three-stage op amp, nested Miller, nulling resistor", "summary": "This three-stage amplifier uses two nested compensation capacitors and a shared series resistor. The resistor corrects an unwanted fast signal path through the capacitors, improving stability. Its value must stay within a useful range: making it too large can destabilize an internal loop.", "reference": { "kind": "paper", "authors": "K. N. Leung, P. K. T. Mok", "title": "Analysis of multistage amplifier-frequency compensation", "year": 2001, "where": "IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 48(9):1041-1056", "doi": "10.1109/81.948432", "takes": "Nested Miller compensation with a nulling resistor (NMCNR): both Miller capacitors joined to the output through one resistor, the condition R > 1/g_m3 that puts the zeros in the left half-plane, and g_m2·R < 1 that keeps the non-dominant poles in the left half-plane. The core amplifier, its bias and every size are this library's, for SG13G2 at 1.2 V." }, "resources": { "record": "/circuits/ota3-nmcnr.json", "page": "/index.html#ota3-nmcnr", "achieved": "/achieved/ota3-nmcnr.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "inp", "kind": "input" }, { "name": "inn", "kind": "input" }, { "name": "out", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the reference current, drawn out of this pin" } ], "devices": [ { "name": "MB", "type": "pmos", "nodes": "ib ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "bias reference, diode-connected: takes Ib", "fingers": 2, "copies": 1 }, { "name": "M20", "type": "pmos", "nodes": "vbc ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "copies Ib into the NMOS bias branch", "fingers": 2, "copies": 1 }, { "name": "Rb", "type": "resistor", "nodes": "vbc vbn", "sizedBy": [ "Rb" ], "role": "lifts the cascode bias vbc to Ib·Rb above vbn" }, { "name": "M21", "type": "nmos", "nodes": "vbn vbn vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "NMOS bias diode: sets the sinks' gate vbn", "fingers": 1, "copies": 1 }, { "name": "MT", "type": "pmos", "nodes": "tail ib vdd vdd", "sizedBy": [ "Wp", "Lp", "Kt" ], "role": "tail current source: Kt copies of MB", "fingers": 2, "copies": 2 }, { "name": "M1", "type": "pmos", "nodes": "f1 inn tail tail", "sizedBy": [ "W1", "L1" ], "role": "input pair, inverting input; bulk on its source", "fingers": 4, "copies": 1 }, { "name": "M2", "type": "pmos", "nodes": "f2 inp tail tail", "sizedBy": [ "W1", "L1" ], "role": "input pair, non-inverting input; bulk on its source", "fingers": 4, "copies": 1 }, { "name": "M3", "type": "nmos", "nodes": "f1 vbn vss vss", "sizedBy": [ "Wn", "Ln", "Ks" ], "role": "folding sink: Ks copies of M21", "fingers": 1, "copies": 2 }, { "name": "M4", "type": "nmos", "nodes": "f2 vbn vss vss", "sizedBy": [ "Wn", "Ln", "Ks" ], "role": "folding sink: Ks copies of M21", "fingers": 1, "copies": 2 }, { "name": "M5", "type": "nmos", "nodes": "x1 vbc f1 vss", "sizedBy": [ "Wc", "Lc" ], "role": "cascode, mirror side", "fingers": 1, "copies": 1 }, { "name": "M6", "type": "nmos", "nodes": "o1 vbc f2 vss", "sizedBy": [ "Wc", "Lc" ], "role": "cascode, output side", "fingers": 1, "copies": 1 }, { "name": "M7", "type": "pmos", "nodes": "x1 x1 vdd vdd", "sizedBy": [ "Wm", "Lm" ], "role": "mirror load, diode-connected", "fingers": 2, "copies": 1 }, { "name": "M8", "type": "pmos", "nodes": "o1 x1 vdd vdd", "sizedBy": [ "Wm", "Lm" ], "role": "mirror load: the first stage's output o1", "fingers": 2, "copies": 1 }, { "name": "M9", "type": "pmos", "nodes": "d2 o1 vdd vdd", "sizedBy": [ "W2", "L2" ], "role": "second-stage input: turns o1 into a current", "fingers": 1, "copies": 1 }, { "name": "M10", "type": "nmos", "nodes": "d2 d2 vss vss", "sizedBy": [ "Wr", "Lr" ], "role": "second-stage mirror, diode-connected", "fingers": 2, "copies": 1 }, { "name": "M11", "type": "nmos", "nodes": "o2 d2 vss vss", "sizedBy": [ "Wr", "Lr" ], "role": "second-stage mirror: drives o2", "fingers": 2, "copies": 1 }, { "name": "M12", "type": "pmos", "nodes": "o2 ib vdd vdd", "sizedBy": [ "Wp", "Lp", "K2" ], "role": "second-stage current source: K2 copies of MB", "fingers": 2, "copies": 1 }, { "name": "M13", "type": "nmos", "nodes": "out o2 vss vss", "sizedBy": [ "W3", "L3", "N3" ], "role": "output device, common source on o2: N3 copies", "fingers": 2, "copies": 4 }, { "name": "M14", "type": "pmos", "nodes": "out ib vdd vdd", "sizedBy": [ "Wp", "Lp", "Kf", "K2" ], "role": "output current source: Kf*K2 copies of MB", "fingers": 2, "copies": 16 }, { "name": "Cm1", "type": "capacitor", "nodes": "o1 z", "sizedBy": [ "Cm1" ], "role": "outer Miller capacitor: sets the dominant pole and the unity-gain frequency" }, { "name": "Cm2", "type": "capacitor", "nodes": "o2 z", "sizedBy": [ "Cm2" ], "role": "inner Miller capacitor, around the output stage" }, { "name": "Rz", "type": "resistor", "nodes": "z out", "sizedBy": [ "Rz" ], "role": "nulling resistor, in series with both Miller capacitors" } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "The input pair: any difference between them is input offset." }, { "rule": "match", "of": [ "M3", "M4" ], "why": "The folding sinks: a mismatch unbalances the cascode currents and appears as offset." }, { "rule": "match", "of": [ "M7", "M8" ], "why": "The mirror load: a mismatch copies the wrong current to o1 and appears as offset." }, { "rule": "unit-copies", "of": [ "MB", "M20", "MT", "M12", "M14" ], "constraint": "MT = Kt copies of MB, M12 = K2 copies, M14 = Kf·K2 copies", "why": "Repeating the same unit geometry preserves the intended nominal ratio and avoids geometry-dependent systematic shifts. Random mismatch and unequal drain voltages still cause current-copy errors." }, { "rule": "ratio", "of": [ "M3", "M4", "MT" ], "constraint": "Ks > Kt/2", "why": "Each sink carries its input device's share of the tail and its cascode's current: the cascodes get (Ks − Kt/2)·Ib, which must stay positive, or a cascode turns off and the first stage loses its gain." }, { "rule": "bias", "of": [ "Rb", "M3", "M4" ], "constraint": "Ib·Rb ≈ V_DSAT(M3) + 0.1 V", "why": "The cascode gates sit Ib·Rb above the sinks' gates, so the sinks keep that much V_DS less the cascodes' body effect: enough to stay saturated at every corner, not so much that the cascodes lose theirs." }, { "rule": "match", "of": [ "M10", "M11" ], "why": "The second-stage mirror: a mismatch moves the balance between M11 and M12 and appears as offset." }, { "rule": "dominant-pole", "of": [ "Cm1", "M1", "M2" ], "constraint": "ω_u ≈ g_m1/C_m1", "why": "Cm1, multiplied by the gain of the last two stages, makes o1 the dominant pole: the angular unity-gain frequency is the input pair's g_m over Cm1." }, { "rule": "zero", "of": [ "Rz", "M13" ], "constraint": "R_z > 1/g_m13", "why": "Without Rz both Miller capacitors feed their nodes forward to the output: right-half-plane zeros. With Rz above 1/g_m13 both zeros move into the left half-plane, where they add phase." }, { "rule": "poles", "of": [ "Rz", "M9" ], "constraint": "g_m9·R_z < 1", "why": "Rz also multiplies the s² term of the non-dominant pole pair by (1 − g_m2·R_z): with the second stage's g_m too large for Rz that term turns negative and a non-dominant pole can enter the right half-plane. The second stage runs at one Ib to keep g_m9·Rz near 0.3." } ], "specs": [ { "key": "dc_gain_db", "label": "DC open-loop gain", "unit": "dB", "direction": "max", "constraint": ">= 100 dB", "min": 100, "max": null, "why": "About 100 dB open-loop gain contributes approximately 10 ppm finite-gain error to a unity-gain buffer. This is not total accuracy: offset, noise and other errors are separate, and gain varies with condition." }, { "key": "ugf_hz", "label": "Unity-gain frequency", "unit": "Hz", "direction": "max", "constraint": ">= 1500000 Hz", "min": 1500000, "max": null, "why": "A few MHz into the 10 pF load at tt; the limit holds at the slow, hot, low-supply corner, where the input pair's g_m is lowest." }, { "key": "pm_deg", "label": "Phase margin", "unit": "deg", "direction": "max", "constraint": ">= 60 deg", "min": 60, "max": null, "why": "A phase-margin target of 60° or more supports a well-damped unity-gain loop, but does not guarantee a ringing-free higher-order response. The separate step and gain-margin benches check additional behavior at the stated conditions." }, { "key": "gm_db", "label": "Gain margin", "unit": "dB", "direction": "max", "constraint": ">= 10 dB", "min": 10, "max": null, "why": "The margin the open-loop phase margin can hide: a three-stage amplifier's non-dominant pole pair can peak, and the gain margin is where that shows." }, { "key": "t_settle", "label": "Settling time, 1 %", "unit": "s", "direction": "min", "constraint": "<= 8e-7 s", "min": null, "max": 8e-7, "why": "The step bench can expose dynamics hidden by an open-loop margin. After the output change tracks 90–110 % of the commanded 0.2 V step, settling is measured within 1 % of that step amplitude around the final output; overshoot is checked separately. This is not a 1 % DC-accuracy limit." }, { "key": "overshoot_pct", "label": "Overshoot", "unit": "%", "direction": "min", "constraint": "<= 5 %", "min": null, "max": 5, "why": "A well-damped closed loop overshoots a few percent at most." }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 60 dB", "min": 60, "max": null, "why": "Supply ripple at 1 kHz reaching the buffer's output, as the rest of the library measures it." }, { "key": "cmrr_db", "label": "Common-mode rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 80 dB", "min": 80, "max": null, "why": "The folded-cascode first stage rejects a common-mode input at 1 kHz by this much or more." }, { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.000075 A", "min": null, "max": 0.000075, "why": "Low power is what these compensation schemes are for: the whole amplifier, bias included, stays under this." } ], "explanation": { "idea": "This three-stage amplifier uses two nested compensation capacitors and a shared series resistor. The resistor corrects an unwanted fast signal path through the capacitors, improving stability. Its value must stay within a useful range: making it too large can destabilize an internal loop.", "detail": "The three-stage op amp in its plain form - a class-A output, no feedforward - made stable by nested Miller capacitors that reach the output through one shared nulling resistor. Nested Miller alone leaves right-half-plane zeros, since each capacitor feeds its node forward to the output; Rz in series with both moves them into the left half-plane once it exceeds 1/g_m13, as long as g_m9·Rz stays below one.", "lesson": { "relation": 1, "symbols": "ω_u is angular unity-gain frequency in rad/s; f_u = ω_u/(2π) is frequency in Hz; g_m1 is the input transistor's transconductance in S; C_m1 is the main compensation capacitance in F.", "assumptions": "Small signals around the default bias point, with the intended dominant pole and the other internal poles above crossover. Device and load parasitics make the relation approximate.", "exercise": { "param": "Cm1", "value": 6e-12, "analysis": "open_loop", "expect": "Increasing the compensation capacitance should lower the unity-gain frequency. Compare the phase margin as well; a slower crossover does not by itself prove every internal loop is stable." }, "limits": "Provide the external bias current and use the specified load and common-mode level. Three gain stages contain interacting local loops: inspect gain margin and step settling as well as phase margin after changes." }, "path": [ { "part": "First stage", "devices": "M1, M2, MT, M3, M4, M5, M6, M7, M8", "does": "The PMOS pair M1/M2 on the tail MT folds into the sinks M3/M4 and the cascodes M5/M6; the mirror M7/M8 turns the two halves into one output, o1, which falls as inp rises." }, { "part": "Second stage", "devices": "M9, M10, M11, M12", "does": "M9 turns o1 into a current, the NMOS mirror M10/M11 copies it onto o2 against the source M12: a non-inverting stage, o2 rises with o1. It runs at one Ib, slow on purpose." }, { "part": "Output stage", "devices": "M13, M14", "does": "M13 on o2 sinks against M14, a current source of sixteen copies of MB: a class-A output with no feedforward path, inverting o2 onto out." }, { "part": "Compensation network", "devices": "Cm1, Cm2, Rz", "does": "Cm1 from o1 and Cm2 from o2 meet at z, and Rz joins z to out: the nulling resistor sits in series with both Miller capacitors." } ], "bias": "The testbench draws Ib (2.5 µA) out of the diode MB. MT is two copies of it, so each input device carries Ib; M20 feeds Ib through Rb (116 kΩ) into the NMOS diode M21, so the cascode gate vbc sits Ib·Rb above vbn and the folding nodes rest near 0.3 V; the sinks M3/M4 are two copies of M21 each, leaving Ib for each cascode. M12 is one copy of MB, so the second stage runs at Ib, and M14 is sixteen copies of MB: the output stage carries 40 µA.", "relations": [ { "what": "DC gain", "expr": "A_0 ≈ g_m1 R_o1 · g_m9 R_o2 · g_m13 R_o3", "note": "R_o1 is set mostly by the mirror M8, R_o2 and R_o3 by the NMOS M11 and M13, whose V_A is only 2-3 V: the reason those two are long." }, { "what": "Unity-gain frequency", "expr": "ω_u ≈ g_m1/C_m1", "note": "About 2.9 MHz with Cm1 at 3 pF." }, { "what": "Zeros", "expr": "1 + s [R_z (C_m1 + C_m2) − C_m2/g_m13] + s^2 C_m1 C_m2 (g_m13 R_z − 1)/(g_m9 g_m13)", "note": "Both terms turn positive, the zeros left-half-plane, once R_z > 1/g_m13 (about 1.7 kΩ)." }, { "what": "Non-dominant poles", "expr": "1 + s C_m2 (g_m13 − g_m9)/(g_m9 g_m13) + s^2 C_m2 C_L (1 − g_m9 R_z)/(g_m9 g_m13)", "note": "g_m9·R_z must stay well below one: the second stage runs at one Ib to keep it near 0.3." } ], "tradeoffs": [ "Rz: below 1/g_m13 the zeros stay right-half-plane; well above it g_m9·Rz nears one and a non-dominant pole can enter the right half-plane - the step oscillates behind a good open-loop margin.", "Cm2: larger raises the gain margin and slows the pole pair; smaller and the unity-gain step rings.", "Cm1: larger lowers ω_u and raises the phase margin.", "The second stage's current: more of it raises g_m9 and breaks g_m9·Rz < 1." ] }, "sizing": [ { "key": "Ib", "label": "Reference current", "unit": "A", "value": 0.0000025, "min": 5e-7, "max": 0.00002, "kind": "si" }, { "key": "Wp", "label": "W PMOS source unit (MB and its copies)", "unit": "m", "value": 0.0000054, "min": 5e-7, "max": 0.00005, "kind": "si" }, { "key": "Lp", "label": "L PMOS source unit", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "W1", "label": "W input pair (M1, M2)", "unit": "m", "value": 0.0000179, "min": 5e-7, "max": 0.0001, "kind": "si" }, { "key": "L1", "label": "L input pair", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Wn", "label": "W NMOS sink unit (M21 and its copies)", "unit": "m", "value": 0.0000014, "min": 3e-7, "max": 0.00005, "kind": "si" }, { "key": "Ln", "label": "L NMOS sink unit", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Rb", "label": "Cascode bias resistor", "unit": "Ω", "value": 116000, "min": 10000, "max": 500000, "kind": "si" }, { "key": "Wc", "label": "W cascode unit (M5, M6)", "unit": "m", "value": 0.0000032, "min": 3e-7, "max": 0.00005, "kind": "si" }, { "key": "Lc", "label": "L cascode unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Wm", "label": "W mirror load (M7, M8)", "unit": "m", "value": 0.0000081, "min": 5e-7, "max": 0.0001, "kind": "si" }, { "key": "Lm", "label": "L mirror load", "unit": "m", "value": 0.000003, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "W2", "label": "W second-stage PMOS unit (M9, M14)", "unit": "m", "value": 0.0000025, "min": 5e-7, "max": 0.0001, "kind": "si" }, { "key": "L2", "label": "L second-stage PMOS unit", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Wr", "label": "W second-stage mirror (M10, M11)", "unit": "m", "value": 0.0000054, "min": 3e-7, "max": 0.0001, "kind": "si" }, { "key": "Lr", "label": "L second-stage mirror", "unit": "m", "value": 0.000004, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "W3", "label": "W output NMOS unit (M13)", "unit": "m", "value": 0.0000057, "min": 3e-7, "max": 0.0001, "kind": "si" }, { "key": "L3", "label": "L output NMOS unit", "unit": "m", "value": 0.000002, "min": 1.3e-7, "max": 0.000008, "kind": "si" }, { "key": "Kt", "label": "Tail current, in Ib", "unit": "", "value": 2, "min": 1, "max": 16, "kind": "int" }, { "key": "Ks", "label": "Folding-sink current, in Ib", "unit": "", "value": 2, "min": 1, "max": 16, "kind": "int" }, { "key": "K2", "label": "Second-stage current, in unit copies", "unit": "", "value": 1, "min": 1, "max": 40, "kind": "int" }, { "key": "Kf", "label": "Output-stage current, in second-stage currents", "unit": "", "value": 16, "min": 1, "max": 40, "kind": "int" }, { "key": "N3", "label": "Output NMOS copies", "unit": "", "value": 4, "min": 1, "max": 40, "kind": "int" }, { "key": "Cm1", "label": "Outer Miller capacitor", "unit": "F", "value": 3e-12, "min": 3e-13, "max": 2e-11, "kind": "si" }, { "key": "Cm2", "label": "Inner Miller capacitor", "unit": "F", "value": 1.5e-12, "min": 1e-13, "max": 1e-11, "kind": "si" }, { "key": "Rz", "label": "Nulling resistor", "unit": "Ω", "value": 8000, "min": 0, "max": 50000, "kind": "si" }, { "key": "CL", "label": "Load capacitance", "unit": "F", "value": 1e-11, "min": 1e-12, "max": 1e-10, "kind": "si" }, { "key": "VCM", "label": "Input common mode", "unit": "V", "value": 0.4, "min": 0, "max": 0.6, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.", "measures": [], "metricKeys": [ "i_supply", "vout_dc", "vos" ], "acceptance": [ "i_supply" ], "acceptanceRules": [ { "key": "i_supply", "unit": "A", "min": null, "max": 0.000075, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Three-stage op amp, nested Miller, nulling resistor - operating point as a unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 2.5u\n.subckt ota3nmcnr inp inn out vdd vss ib\n* bias: Ib into the PMOS diode MB; M20 copies it through Rb into the NMOS diode M21, so vbc sits Ib*Rb above vbn\nXMB ib ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1\nXM20 vbc ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1\nXRb vbc vbn vss rhigh w=0.5u l=35.725u\nXM21 vbn vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=1\n* first stage: PMOS pair M1/M2 on tail MT, folded into sinks M3/M4 and cascodes M5/M6, mirror load M7/M8 - o1 falls as inp rises\nXMT tail ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=2\nXM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1\nXM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1\nXM3 f1 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2\nXM4 f2 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2\nXM5 x1 vbc f1 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1\nXM6 o1 vbc f2 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1\nXM7 x1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXM8 o1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\n* second stage: M9 into the NMOS mirror M10/M11, against the source M12 - o2 rises with o1\nXM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=500n ng=1 m=1\nXM10 d2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1\nXM11 o2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1\nXM12 o2 ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1\n* output stage: M13 on o2 against the current source M14 - class A, no feedforward\nXM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4\nXM14 out ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=16\n* nested Miller capacitors Cm1 (from o1) and Cm2 (from o2) meet at z; the nulling resistor Rz joins z to out\nXCm1 o1 z cap_cmim w=25.767u l=25.767u m=3\nXCm2 o2 z cap_cmim w=22.307u l=22.307u m=2\nXRz z out vss rppd w=0.5u l=15.478u\n.ends\nXdut inp inn out vdd 0 ib ota3nmcnr\nCl out 0 10p\nVin inp 0 dc 400m\n* the output drives the inverting input: a unity-gain buffer\nVfb inn out 0\n.op\n.end" }, { "id": "open_loop", "label": "Open-loop gain", "note": "Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.", "measures": [], "metricKeys": [ "dc_gain_db", "ugf_hz", "pm_deg", "gm_db" ], "acceptance": [ "dc_gain_db", "ugf_hz", "pm_deg", "gm_db" ], "acceptanceRules": [ { "key": "dc_gain_db", "unit": "dB", "min": 100, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "ugf_hz", "unit": "Hz", "min": 1500000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "pm_deg", "unit": "deg", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "gm_db", "unit": "dB", "min": 10, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Three-stage op amp, nested Miller, nulling resistor - open-loop gain and phase\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 2.5u\n.subckt ota3nmcnr inp inn out vdd vss ib\n* bias: Ib into the PMOS diode MB; M20 copies it through Rb into the NMOS diode M21, so vbc sits Ib*Rb above vbn\nXMB ib ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1\nXM20 vbc ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1\nXRb vbc vbn vss rhigh w=0.5u l=35.725u\nXM21 vbn vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=1\n* first stage: PMOS pair M1/M2 on tail MT, folded into sinks M3/M4 and cascodes M5/M6, mirror load M7/M8 - o1 falls as inp rises\nXMT tail ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=2\nXM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1\nXM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1\nXM3 f1 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2\nXM4 f2 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2\nXM5 x1 vbc f1 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1\nXM6 o1 vbc f2 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1\nXM7 x1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXM8 o1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\n* second stage: M9 into the NMOS mirror M10/M11, against the source M12 - o2 rises with o1\nXM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=500n ng=1 m=1\nXM10 d2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1\nXM11 o2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1\nXM12 o2 ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1\n* output stage: M13 on o2 against the current source M14 - class A, no feedforward\nXM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4\nXM14 out ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=16\n* nested Miller capacitors Cm1 (from o1) and Cm2 (from o2) meet at z; the nulling resistor Rz joins z to out\nXCm1 o1 z cap_cmim w=25.767u l=25.767u m=3\nXCm2 o2 z cap_cmim w=22.307u l=22.307u m=2\nXRz z out vss rppd w=0.5u l=15.478u\n.ends\nXdut inp inn out vdd 0 ib ota3nmcnr\nCl out 0 10p\nVin inp 0 dc 400m ac 1\n* the loop closed at DC and open at every frequency the sweep visits\nLfb out inn 1t\nCfb inn 0 1t\n.ac dec 25 0.1 10g\n.end" }, { "id": "step", "label": "Step response", "note": "A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.", "measures": [], "metricKeys": [ "sr", "t_settle", "overshoot_pct" ], "acceptance": [ "t_settle", "overshoot_pct" ], "acceptanceRules": [ { "key": "t_settle", "unit": "s", "min": null, "max": 8e-7, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "overshoot_pct", "unit": "%", "min": null, "max": 5, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Three-stage op amp, nested Miller, nulling resistor - step response of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 2.5u\n.subckt ota3nmcnr inp inn out vdd vss ib\n* bias: Ib into the PMOS diode MB; M20 copies it through Rb into the NMOS diode M21, so vbc sits Ib*Rb above vbn\nXMB ib ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1\nXM20 vbc ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1\nXRb vbc vbn vss rhigh w=0.5u l=35.725u\nXM21 vbn vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=1\n* first stage: PMOS pair M1/M2 on tail MT, folded into sinks M3/M4 and cascodes M5/M6, mirror load M7/M8 - o1 falls as inp rises\nXMT tail ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=2\nXM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1\nXM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1\nXM3 f1 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2\nXM4 f2 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2\nXM5 x1 vbc f1 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1\nXM6 o1 vbc f2 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1\nXM7 x1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXM8 o1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\n* second stage: M9 into the NMOS mirror M10/M11, against the source M12 - o2 rises with o1\nXM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=500n ng=1 m=1\nXM10 d2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1\nXM11 o2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1\nXM12 o2 ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1\n* output stage: M13 on o2 against the current source M14 - class A, no feedforward\nXM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4\nXM14 out ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=16\n* nested Miller capacitors Cm1 (from o1) and Cm2 (from o2) meet at z; the nulling resistor Rz joins z to out\nXCm1 o1 z cap_cmim w=25.767u l=25.767u m=3\nXCm2 o2 z cap_cmim w=22.307u l=22.307u m=2\nXRz z out vss rppd w=0.5u l=15.478u\n.ends\nXdut inp inn out vdd 0 ib ota3nmcnr\nCl out 0 10p\nVin inp 0 pulse(300m 500m 400n 1n 1n 2u 8u)\nVfb inn out 0\n.tran 1000p 4u\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.", "measures": [], "metricKeys": [ "psrr_db" ], "acceptance": [ "psrr_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 60, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Three-stage op amp, nested Miller, nulling resistor - supply rejection of the unity-gain buffer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD} ac 1\nIb ib 0 2.5u\n.subckt ota3nmcnr inp inn out vdd vss ib\n* bias: Ib into the PMOS diode MB; M20 copies it through Rb into the NMOS diode M21, so vbc sits Ib*Rb above vbn\nXMB ib ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1\nXM20 vbc ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1\nXRb vbc vbn vss rhigh w=0.5u l=35.725u\nXM21 vbn vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=1\n* first stage: PMOS pair M1/M2 on tail MT, folded into sinks M3/M4 and cascodes M5/M6, mirror load M7/M8 - o1 falls as inp rises\nXMT tail ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=2\nXM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1\nXM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1\nXM3 f1 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2\nXM4 f2 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2\nXM5 x1 vbc f1 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1\nXM6 o1 vbc f2 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1\nXM7 x1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXM8 o1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\n* second stage: M9 into the NMOS mirror M10/M11, against the source M12 - o2 rises with o1\nXM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=500n ng=1 m=1\nXM10 d2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1\nXM11 o2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1\nXM12 o2 ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1\n* output stage: M13 on o2 against the current source M14 - class A, no feedforward\nXM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4\nXM14 out ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=16\n* nested Miller capacitors Cm1 (from o1) and Cm2 (from o2) meet at z; the nulling resistor Rz joins z to out\nXCm1 o1 z cap_cmim w=25.767u l=25.767u m=3\nXCm2 o2 z cap_cmim w=22.307u l=22.307u m=2\nXRz z out vss rppd w=0.5u l=15.478u\n.ends\nXdut inp inn out vdd 0 ib ota3nmcnr\nCl out 0 10p\nVin inp 0 dc 400m\nVfb inn out 0\n.ac dec 25 1 100meg\n.end" }, { "id": "cmrr", "label": "Common-mode rejection", "note": "Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.", "measures": [], "metricKeys": [ "cmrr_db" ], "acceptance": [ "cmrr_db" ], "acceptanceRules": [ { "key": "cmrr_db", "unit": "dB", "min": 80, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Three-stage op amp, nested Miller, nulling resistor - common-mode rejection\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 2.5u\n.subckt ota3nmcnr inp inn out vdd vss ib\n* bias: Ib into the PMOS diode MB; M20 copies it through Rb into the NMOS diode M21, so vbc sits Ib*Rb above vbn\nXMB ib ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1\nXM20 vbc ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1\nXRb vbc vbn vss rhigh w=0.5u l=35.725u\nXM21 vbn vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=1\n* first stage: PMOS pair M1/M2 on tail MT, folded into sinks M3/M4 and cascodes M5/M6, mirror load M7/M8 - o1 falls as inp rises\nXMT tail ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=2\nXM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1\nXM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1\nXM3 f1 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2\nXM4 f2 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2\nXM5 x1 vbc f1 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1\nXM6 o1 vbc f2 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1\nXM7 x1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXM8 o1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\n* second stage: M9 into the NMOS mirror M10/M11, against the source M12 - o2 rises with o1\nXM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=500n ng=1 m=1\nXM10 d2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1\nXM11 o2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1\nXM12 o2 ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1\n* output stage: M13 on o2 against the current source M14 - class A, no feedforward\nXM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4\nXM14 out ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=16\n* nested Miller capacitors Cm1 (from o1) and Cm2 (from o2) meet at z; the nulling resistor Rz joins z to out\nXCm1 o1 z cap_cmim w=25.767u l=25.767u m=3\nXCm2 o2 z cap_cmim w=22.307u l=22.307u m=2\nXRz z out vss rppd w=0.5u l=15.478u\n.ends\nXdut inp inn out vdd 0 ib ota3nmcnr\nCl out 0 10p\nVsrc src 0 dc 400m\n* va on the non-inverting input, vb in the feedback path: both inputs move with the signal\nVa inp src dc 0 ac 1\nVb inn out dc 0 ac 1\n.ac dec 25 1 100meg\n.end" }, { "id": "noise", "label": "Noise", "note": "Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.", "measures": [], "metricKeys": [ "vn_1k", "vn_int" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Three-stage op amp, nested Miller, nulling resistor - input-referred noise\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 2.5u\n.subckt ota3nmcnr inp inn out vdd vss ib\n* bias: Ib into the PMOS diode MB; M20 copies it through Rb into the NMOS diode M21, so vbc sits Ib*Rb above vbn\nXMB ib ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1\nXM20 vbc ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1\nXRb vbc vbn vss rhigh w=0.5u l=35.725u\nXM21 vbn vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=1\n* first stage: PMOS pair M1/M2 on tail MT, folded into sinks M3/M4 and cascodes M5/M6, mirror load M7/M8 - o1 falls as inp rises\nXMT tail ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=2\nXM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1\nXM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1\nXM3 f1 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2\nXM4 f2 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2\nXM5 x1 vbc f1 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1\nXM6 o1 vbc f2 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1\nXM7 x1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\nXM8 o1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1\n* second stage: M9 into the NMOS mirror M10/M11, against the source M12 - o2 rises with o1\nXM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=500n ng=1 m=1\nXM10 d2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1\nXM11 o2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1\nXM12 o2 ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1\n* output stage: M13 on o2 against the current source M14 - class A, no feedforward\nXM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4\nXM14 out ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=16\n* nested Miller capacitors Cm1 (from o1) and Cm2 (from o2) meet at z; the nulling resistor Rz joins z to out\nXCm1 o1 z cap_cmim w=25.767u l=25.767u m=3\nXCm2 o2 z cap_cmim w=22.307u l=22.307u m=2\nXRz z out vss rppd w=0.5u l=15.478u\n.ends\nXdut inp inn out vdd 0 ib ota3nmcnr\nCl out 0 10p\nVin inp 0 dc 400m ac 1\nVfb inn out 0\n.control\nnoise v(out) Vin dec 20 1 1meg\nsetplot noise1\n* 20 points a decade from 1 Hz: point 60 is 1 kHz\nlet vn_1k = inoise_spectrum[60]\nprint vn_1k\nsetplot noise2\nprint inoise_total\n.endc\n.op\n.end" } ], "measurements": { "dc_gain_db": { "label": "DC open-loop gain", "unit": "dB", "spec": { "min": 100, "max": null } }, "ugf_hz": { "label": "Unity-gain frequency", "unit": "Hz", "spec": { "min": 1500000, "max": null } }, "pm_deg": { "label": "Phase margin", "unit": "deg", "spec": { "min": 60, "max": null } }, "gm_db": { "label": "Gain margin", "unit": "dB", "spec": { "min": 10, "max": null } }, "t_settle": { "label": "Settling time, 1 %", "unit": "s", "spec": { "min": null, "max": 8e-7 } }, "overshoot_pct": { "label": "Overshoot", "unit": "%", "spec": { "min": null, "max": 5 } }, "psrr_db": { "label": "Supply rejection at 1 kHz", "unit": "dB", "spec": { "min": 60, "max": null } }, "cmrr_db": { "label": "Common-mode rejection at 1 kHz", "unit": "dB", "spec": { "min": 80, "max": null } }, "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.000075 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "0e77ab05a12565b8c0c237b5ae2c2e05ea109cdf09449e2632160fd9840b63d5" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ota3-nmcnr.js", "sha256": "dca998a417538bf5401ba36ef291ebcfa94ada7a6af74fc7d2a9c4f1c015491e" }, "simulationFingerprints": { "op": "54710c580cdc4b6055d46e34276b93edbdd76963cac95a3d721848249a52b172", "open_loop": "1902515d746614ab774a0dd2fdd2f99ae9db5f759ef0f6613cfc9f1c9e46134f", "step": "bacd0586ed30f348acb8f3f1425ebe8aa3db2d50b0f9ab03a91e8ab0e98801da", "psrr": "8b02f05407719b94d63d9d5b5423d9e22113d6183012a794e0fa5fe1ba602e42", "cmrr": "ab57776a815588daa3c4bd8eaf02381b08fa6712b3a9d6990b139669925ee244", "noise": "6887c60f0ae15b583bd9cac91d0a9e73cc4f892d56f82ef3aa1c4c214385c4f3" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "0e6166fd905c26affb17c25558176358d4ed539e0824ebdaf4d438c719ee5fa0", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ota3-nmcnr", "parameters": { "Ib": 0.0000025, "Wp": 0.0000054, "Lp": 0.000002, "W1": 0.0000179, "L1": 0.000001, "Wn": 0.0000014, "Ln": 0.000002, "Rb": 116000, "Wc": 0.0000032, "Lc": 0.000001, "Wm": 0.0000081, "Lm": 0.000003, "W2": 0.0000025, "L2": 5e-7, "Wr": 0.0000054, "Lr": 0.000004, "W3": 0.0000057, "L3": 0.000002, "Kt": 2, "Ks": 2, "K2": 1, "Kf": 16, "N3": 4, "Cm1": 3e-12, "Cm2": 1.5e-12, "Rz": 8000, "CL": 1e-11, "VCM": 0.4 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ota3-nmcnr/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "ota3nmcnr", "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=1", "source": "XM20 vbc ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=35.725u", "source": "XRb vbc vbn vss rhigh w=0.5u l=35.725u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM21", "displayName": "M21", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.4u l=2u ng=1 m=1", "source": "XM21 vbn vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=17.9u l=1u ng=4 m=1", "source": "XM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=17.9u l=1u ng=4 m=1", "source": "XM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.4u l=2u ng=1 m=2", "source": "XM3 f1 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.4u l=2u ng=1 m=2", "source": "XM4 f2 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=1u ng=1 m=1", "source": "XM5 x1 vbc f1 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=1u ng=1 m=1", "source": "XM6 o1 vbc f2 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XM7 x1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XM8 o1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.5u l=500n ng=1 m=1", "source": "XM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.4u l=4u ng=2 m=1", "source": "XM10 d2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.4u l=4u ng=2 m=1", "source": "XM11 o2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=1", "source": "XM12 o2 ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=2u ng=2 m=4", "source": "XM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=16", "source": "XM14 out ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=16", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCm1", "displayName": "Cm1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCm1 o1 z cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "o1" }, { "id": "n", "net": "z" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCm2", "displayName": "Cm2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=22.307u l=22.307u m=2", "source": "XCm2 o2 z cap_cmim w=22.307u l=22.307u m=2", "pins": [ { "id": "p", "net": "o2" }, { "id": "n", "net": "z" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=15.478u", "source": "XRz z out vss rppd w=0.5u l=15.478u", "pins": [ { "id": "p", "net": "z" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM20", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM12", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM20", "pin": "s" }, { "device": "XM20", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XM20", "pin": "d" }, { "device": "XRb", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRb", "pin": "n" }, { "device": "XM21", "pin": "d" }, { "device": "XM21", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRb", "pin": "substrate" }, { "device": "XM21", "pin": "s" }, { "device": "XM21", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XCm1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XM10", "pin": "g" }, { "device": "XM11", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM13", "pin": "g" }, { "device": "XCm2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM13", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XRz", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "z", "ground": false, "terminals": [ { "device": "XCm1", "pin": "n" }, { "device": "XCm2", "pin": "n" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2.5u", "source": "Ib ib 0 2.5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota3nmcnr", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota3nmcnr", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota3nmcnr" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m", "source": "Vin inp 0 dc 400m", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota3nmcnr", "name": "ota3nmcnr", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=1", "source": "XM20 vbc ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=35.725u", "source": "XRb vbc vbn vss rhigh w=0.5u l=35.725u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM21", "displayName": "M21", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.4u l=2u ng=1 m=1", "source": "XM21 vbn vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=17.9u l=1u ng=4 m=1", "source": "XM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=17.9u l=1u ng=4 m=1", "source": "XM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.4u l=2u ng=1 m=2", "source": "XM3 f1 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.4u l=2u ng=1 m=2", "source": "XM4 f2 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=1u ng=1 m=1", "source": "XM5 x1 vbc f1 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=1u ng=1 m=1", "source": "XM6 o1 vbc f2 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XM7 x1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XM8 o1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.5u l=500n ng=1 m=1", "source": "XM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.4u l=4u ng=2 m=1", "source": "XM10 d2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.4u l=4u ng=2 m=1", "source": "XM11 o2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", 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"id": "p", "net": "z" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM20", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM12", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM20", "pin": "s" }, { "device": "XM20", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XM14", "pin": "s" }, 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"XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XCm1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XM10", "pin": "g" }, { "device": "XM11", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM13", "pin": "g" }, { "device": "XCm2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM13", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XRz", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "z", "ground": false, "terminals": [ { "device": "XCm1", "pin": "n" }, { "device": "XCm2", "pin": "n" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota3nmcnr" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Bias reference", "devices": [ { "scope": "dut", "device": "XMB" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "Copies Ib into the NMOS bias branch", "devices": [ { "scope": "dut", "device": "XM20" } ], "inferredStages": [ "bias" ] }, { "id": "block-3", "label": "Lifts the cascode bias vbc to Ib·Rb above vbn", "devices": [ { "scope": "dut", "device": "XRb" } ], "inferredStages": [ "bias" ] }, { "id": "block-4", "label": "NMOS bias diode: sets the sinks' gate vbn", "devices": [ { "scope": "dut", "device": "XM21" } ], "inferredStages": [ "bias" ] }, { "id": "block-5", "label": "Tail current source: Kt copies of MB", "devices": [ { "scope": "dut", "device": "XMT" } ], "inferredStages": [ 1 ] }, { "id": "block-6", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 1 ] }, { "id": "block-7", "label": "Folding sink: Ks copies of M21", "devices": [ { "scope": "dut", "device": "XM3" }, { "scope": "dut", "device": "XM4" } ], "inferredStages": [ 1 ] }, { "id": "block-8", "label": "Cascode", "devices": [ { "scope": "dut", "device": "XM5" }, { "scope": "dut", "device": "XM6" } ], "inferredStages": [ 2 ] }, { "id": "block-9", "label": "Mirror load", "devices": [ { "scope": "dut", "device": "XM7" } ], "inferredStages": [ 2 ] }, { "id": "block-10", "label": "Mirror load: the first stage's output o1", "devices": [ { "scope": "dut", "device": "XM8" } ], "inferredStages": [ 2 ] }, { "id": "block-11", "label": "Second-stage input: turns o1 into a current", "devices": [ { "scope": "dut", "device": "XM9" } ], "inferredStages": [ 3 ] }, { "id": "block-12", "label": "Second-stage mirror", "devices": [ { "scope": "dut", "device": "XM10" } ], "inferredStages": [ 3 ] }, { "id": "block-13", "label": "Second-stage mirror: drives o2", "devices": [ { "scope": "dut", "device": "XM11" } ], "inferredStages": [ 4 ] }, { "id": "block-14", "label": "Second-stage current source: K2 copies of MB", "devices": [ { "scope": "dut", "device": "XM12" } ], "inferredStages": [ 4 ] }, { "id": "block-15", "label": "Output device", "devices": [ { "scope": "dut", "device": "XM13" } ], "inferredStages": [ 5 ] }, { "id": "block-16", "label": "Output current source: Kf*K2 copies of MB", "devices": [ { "scope": "dut", "device": "XM14" } ], "inferredStages": [ 5 ] }, { "id": "block-17", "label": "Outer Miller capacitor: sets the dominant pole and the unity-gain frequency", "devices": [ { "scope": "dut", "device": "XCm1" } ], "inferredStages": [ "comp" ] }, { "id": "block-18", "label": "Inner Miller capacitor", "devices": [ { "scope": "dut", "device": "XCm2" } ], "inferredStages": [ "comp" ] }, { "id": "block-19", "label": "Nulling resistor", "devices": [ { "scope": "dut", "device": "XRz" } ], "inferredStages": [ "comp" ] } ], "edges": [ { "id": "net-1", "net": "ib", "nodes": [ "block-1", "block-2", "block-5", "block-14", "block-16" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "vbc", "nodes": [ "block-2", "block-3", "block-8" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "vbn", "nodes": [ "block-3", "block-4", "block-7" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "tail", "nodes": [ "block-5", "block-6" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "f1", "nodes": [ "block-6", "block-7", "block-8" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "f2", "nodes": [ "block-6", "block-7", "block-8" ], "direction": "undirected-shared-net" }, { "id": "net-7", "net": "x1", "nodes": [ "block-8", "block-9", "block-10" ], "direction": "undirected-shared-net" }, { "id": "net-8", "net": "o1", "nodes": [ "block-8", "block-10", "block-11", "block-17" ], "direction": "undirected-shared-net" }, { "id": "net-9", "net": "d2", "nodes": [ "block-11", "block-12", "block-13" ], "direction": "undirected-shared-net" }, { "id": "net-10", "net": "o2", "nodes": [ "block-13", "block-14", "block-15", "block-18" ], "direction": "undirected-shared-net" }, { "id": "net-11", "net": "out", "nodes": [ "block-15", "block-16", "block-19" ], "direction": "undirected-shared-net" }, { "id": "net-12", "net": "z", "nodes": [ "block-17", "block-18", "block-19" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2.5u", "source": "Ib ib 0 2.5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota3nmcnr", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota3nmcnr", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota3nmcnr" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m ac 1", "source": "Vin inp 0 dc 400m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Lfb", "displayName": "Lfb", "spiceType": "L", "model": null, "parametersOrValue": "1t", "source": "Lfb out inn 1t", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "inn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cfb", "displayName": "Cfb", "spiceType": "C", "model": null, "parametersOrValue": "1t", "source": "Cfb inn 0 1t", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" }, { "device": "Cfb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Lfb", "pin": "n" }, { "device": "Cfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Lfb", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota3nmcnr", "name": "ota3nmcnr", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=1", "source": "XM20 vbc ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=35.725u", "source": "XRb vbc vbn vss rhigh w=0.5u l=35.725u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM21", "displayName": "M21", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.4u l=2u ng=1 m=1", "source": "XM21 vbn vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS 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"source": "XM5 x1 vbc f1 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=1u ng=1 m=1", "source": "XM6 o1 vbc f2 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XM7 x1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XM8 o1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.5u l=500n ng=1 m=1", "source": "XM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.4u l=4u ng=2 m=1", "source": "XM10 d2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": 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w=22.307u l=22.307u m=2", "pins": [ { "id": "p", "net": "o2" }, { "id": "n", "net": "z" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=15.478u", "source": "XRz z out vss rppd w=0.5u l=15.478u", "pins": [ { "id": "p", "net": "z" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM20", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM12", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM20", "pin": "s" }, { "device": "XM20", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XM20", "pin": "d" }, { "device": "XRb", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRb", "pin": "n" }, { "device": "XM21", "pin": "d" }, { "device": "XM21", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRb", "pin": "substrate" }, { "device": "XM21", "pin": "s" }, { "device": "XM21", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XCm1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XM10", "pin": "g" }, { "device": "XM11", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM13", "pin": "g" }, { "device": "XCm2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM13", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XRz", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "z", "ground": false, "terminals": [ { "device": "XCm1", "pin": "n" }, { "device": "XCm2", "pin": "n" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota3nmcnr" } }, { "id": "graph-5", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2.5u", "source": "Ib ib 0 2.5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota3nmcnr", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota3nmcnr", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota3nmcnr" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "pulse(300m 500m 400n 1n 1n 2u 8u)", "source": "Vin inp 0 pulse(300m 500m 400n 1n 1n 2u 8u)", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota3nmcnr", "name": "ota3nmcnr", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=1", "source": "XM20 vbc ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=35.725u", "source": "XRb vbc vbn vss rhigh w=0.5u l=35.725u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM21", "displayName": "M21", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.4u l=2u ng=1 m=1", "source": "XM21 vbn vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": 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f1 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.4u l=2u ng=1 m=2", "source": "XM4 f2 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=1u ng=1 m=1", "source": "XM5 x1 vbc f1 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=1u ng=1 m=1", "source": "XM6 o1 vbc f2 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XM7 x1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XM8 o1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.5u l=500n ng=1 m=1", "source": "XM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.4u l=4u ng=2 m=1", "source": "XM10 d2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.4u l=4u ng=2 m=1", "source": "XM11 o2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=1", "source": "XM12 o2 ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=2u ng=2 m=4", "source": "XM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": 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}, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XM20", "pin": "d" }, { "device": "XRb", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRb", "pin": "n" }, { "device": "XM21", "pin": "d" }, { "device": "XM21", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRb", "pin": "substrate" }, { "device": "XM21", "pin": "s" }, { "device": "XM21", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": 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[] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XCm1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XM10", "pin": "g" }, { "device": "XM11", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM13", "pin": "g" }, { "device": "XCm2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM13", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XRz", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "z", "ground": false, "terminals": [ { "device": "XCm1", "pin": "n" }, { "device": "XCm2", "pin": "n" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota3nmcnr" } }, { "id": "graph-6", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD} ac 1", "source": "Vdd vdd 0 dc {VDD} ac 1", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2.5u", "source": "Ib ib 0 2.5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota3nmcnr", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota3nmcnr", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", 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"Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota3nmcnr", "name": "ota3nmcnr", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=1", "source": "XM20 vbc ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=35.725u", "source": "XRb vbc vbn vss rhigh w=0.5u l=35.725u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM21", "displayName": "M21", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.4u l=2u ng=1 m=1", "source": "XM21 vbn vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=17.9u l=1u ng=4 m=1", "source": "XM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=17.9u l=1u ng=4 m=1", "source": "XM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.4u l=2u ng=1 m=2", "source": "XM3 f1 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.4u l=2u ng=1 m=2", "source": "XM4 f2 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=1u ng=1 m=1", "source": "XM5 x1 vbc f1 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=1u ng=1 m=1", "source": "XM6 o1 vbc f2 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XM7 x1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XM8 o1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.5u l=500n ng=1 m=1", "source": "XM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.4u l=4u ng=2 m=1", "source": "XM10 d2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.4u l=4u ng=2 m=1", "source": "XM11 o2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=1", "source": "XM12 o2 ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=2u ng=2 m=4", "source": "XM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=16", "source": "XM14 out ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=16", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCm1", "displayName": "Cm1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCm1 o1 z cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "o1" }, { "id": "n", "net": "z" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCm2", "displayName": "Cm2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=22.307u l=22.307u m=2", "source": "XCm2 o2 z cap_cmim w=22.307u l=22.307u m=2", "pins": [ { "id": "p", "net": "o2" }, { "id": "n", "net": "z" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=15.478u", "source": "XRz z out vss rppd w=0.5u l=15.478u", "pins": [ { "id": "p", "net": "z" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM20", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM12", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM20", "pin": "s" }, { "device": "XM20", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XM20", "pin": "d" }, { "device": "XRb", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRb", "pin": "n" }, { "device": "XM21", "pin": "d" }, { "device": "XM21", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRb", "pin": "substrate" }, { "device": "XM21", "pin": "s" }, { "device": "XM21", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XCm1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XM10", "pin": "g" }, { "device": "XM11", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM13", "pin": "g" }, { "device": "XCm2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM13", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XRz", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "z", "ground": false, "terminals": [ { "device": "XCm1", "pin": "n" }, { "device": "XCm2", "pin": "n" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota3nmcnr" } }, { "id": "graph-7", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2.5u", "source": "Ib ib 0 2.5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota3nmcnr", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota3nmcnr", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota3nmcnr" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vsrc", "displayName": "Vsrc", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m", "source": "Vsrc src 0 dc 400m", "pins": [ { "id": "p", "net": "src" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Va", "displayName": "Va", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Va inp src dc 0 ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "src" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vb", "displayName": "Vb", "spiceType": "V", "model": null, "parametersOrValue": "dc 0 ac 1", "source": "Vb inn out dc 0 ac 1", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vsrc", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Va", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vb", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "src", "ground": false, "terminals": [ { "device": "Vsrc", "pin": "p" }, { "device": "Va", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ota3nmcnr", "name": "ota3nmcnr", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM20", "displayName": "M20", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=1", "source": "XM20 vbc ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "vbc" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XRb", "displayName": "Rb", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=35.725u", "source": "XRb vbc vbn vss rhigh w=0.5u l=35.725u", "pins": [ { "id": "p", "net": "vbc" }, { "id": "n", "net": "vbn" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM21", "displayName": "M21", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.4u l=2u ng=1 m=1", "source": "XM21 vbn vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vbn" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMT", "displayName": "MT", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=2", "source": "XMT tail ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=2", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=17.9u l=1u ng=4 m=1", "source": "XM1 f1 inn tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=17.9u l=1u ng=4 m=1", "source": "XM2 f2 inp tail tail sg13_lv_pmos w=17.9u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "tail" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.4u l=2u ng=1 m=2", "source": "XM3 f1 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2", "pins": [ { "id": "d", "net": "f1" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1.4u l=2u ng=1 m=2", "source": "XM4 f2 vbn vss vss sg13_lv_nmos w=1.4u l=2u ng=1 m=2", "pins": [ { "id": "d", "net": "f2" }, { "id": "g", "net": "vbn" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=1u ng=1 m=1", "source": "XM5 x1 vbc f1 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f1" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.2u l=1u ng=1 m=1", "source": "XM6 o1 vbc f2 vss sg13_lv_nmos w=3.2u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "vbc" }, { "id": "s", "net": "f2" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XM7 x1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "x1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8.1u l=3u ng=2 m=1", "source": "XM8 o1 x1 vdd vdd sg13_lv_pmos w=8.1u l=3u ng=2 m=1", "pins": [ { "id": "d", "net": "o1" }, { "id": "g", "net": "x1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2.5u l=500n ng=1 m=1", "source": "XM9 d2 o1 vdd vdd sg13_lv_pmos w=2.5u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "o1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.4u l=4u ng=2 m=1", "source": "XM10 d2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1", "pins": [ { "id": "d", "net": "d2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM11", "displayName": "M11", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.4u l=4u ng=2 m=1", "source": "XM11 o2 d2 vss vss sg13_lv_nmos w=5.4u l=4u ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "d2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM12", "displayName": "M12", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=1", "source": "XM12 o2 ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "o2" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM13", "displayName": "M13", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=5.7u l=2u ng=2 m=4", "source": "XM13 out o2 vss vss sg13_lv_nmos w=5.7u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "o2" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM14", "displayName": "M14", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=5.4u l=2u ng=2 m=16", "source": "XM14 out ib vdd vdd sg13_lv_pmos w=5.4u l=2u ng=2 m=16", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCm1", "displayName": "Cm1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCm1 o1 z cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "o1" }, { "id": "n", "net": "z" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCm2", "displayName": "Cm2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=22.307u l=22.307u m=2", "source": "XCm2 o2 z cap_cmim w=22.307u l=22.307u m=2", "pins": [ { "id": "p", "net": "o2" }, { "id": "n", "net": "z" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRz", "displayName": "Rz", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=15.478u", "source": "XRz z out vss rppd w=0.5u l=15.478u", "pins": [ { "id": "p", "net": "z" }, { "id": "n", "net": "out" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM20", "pin": "g" }, { "device": "XMT", "pin": "g" }, { "device": "XM12", "pin": "g" }, { "device": "XM14", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM20", "pin": "s" }, { "device": "XM20", "pin": "b" }, { "device": "XMT", "pin": "s" }, { "device": "XMT", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM12", "pin": "s" }, { "device": "XM12", "pin": "b" }, { "device": "XM14", "pin": "s" }, { "device": "XM14", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "vbc", "ground": false, "terminals": [ { "device": "XM20", "pin": "d" }, { "device": "XRb", "pin": "p" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vbn", "ground": false, "terminals": [ { "device": "XRb", "pin": "n" }, { "device": "XM21", "pin": "d" }, { "device": "XM21", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XRb", "pin": "substrate" }, { "device": "XM21", "pin": "s" }, { "device": "XM21", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" }, { "device": "XM11", "pin": "s" }, { "device": "XM11", "pin": "b" }, { "device": "XM13", "pin": "s" }, { "device": "XM13", "pin": "b" }, { "device": "XRz", "pin": "substrate" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMT", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "f1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM5", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "f2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM6", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "XM2", "pin": "g" } ], "ports": [ "inp" ], "voltageReferences": [] }, { "id": "x1", "ground": false, "terminals": [ { "device": "XM5", "pin": "d" }, { "device": "XM7", "pin": "d" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o1", "ground": false, "terminals": [ { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "XM9", "pin": "g" }, { "device": "XCm1", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "XM9", "pin": "d" }, { "device": "XM10", "pin": "d" }, { "device": "XM10", "pin": "g" }, { "device": "XM11", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "o2", "ground": false, "terminals": [ { "device": "XM11", "pin": "d" }, { "device": "XM12", "pin": "d" }, { "device": "XM13", "pin": "g" }, { "device": "XCm2", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM13", "pin": "d" }, { "device": "XM14", "pin": "d" }, { "device": "XRz", "pin": "n" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "z", "ground": false, "terminals": [ { "device": "XCm1", "pin": "n" }, { "device": "XCm2", "pin": "n" }, { "device": "XRz", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ota3nmcnr" } }, { "id": "graph-8", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "2.5u", "source": "Ib ib 0 2.5u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ota3nmcnr", "parametersOrValue": "", "source": "Xdut inp inn out vdd 0 ib ota3nmcnr", "pins": [ { "id": "inp", "net": "inp" }, { "id": "inn", "net": "inn" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ota3nmcnr" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "10p", "source": "Cl out 0 10p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 400m ac 1", "source": "Vin inp 0 dc 400m ac 1", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vfb", "displayName": "Vfb", "spiceType": "V", "model": null, "parametersOrValue": "0", "source": "Vfb inn out 0", "pins": [ { "id": "p", "net": "inn" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inp" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Xdut", "pin": "inn" }, { "device": "Vfb", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" }, { "device": "Vfb", "pin": "n" } ], "ports": [], "voltageReferences": [] } ] }, { "id": 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