{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ptat-2t", "name": "Two-transistor PTAT sensor with a drain shield", "group": "Mirrors, bias and references", "subgroup": "Temperature sensors", "title": "Two-transistor PTAT sensor with a drain shield", "summary": "Produces a small voltage that rises almost linearly with temperature. One NMOS supplies leakage current to a second; a third transistor shields the pair from the supply. It uses very little power, but supply changes can look like temperature changes, so it needs a regulated supply.", "reference": { "kind": "paper", "authors": "E. Vittoz, J. Fellrath", "title": "CMOS analog integrated circuits based on weak inversion operations", "year": 1977, "where": "IEEE Journal of Solid-State Circuits, 12(3):224-231", "doi": "10.1109/JSSC.1977.1050882", "takes": "The two-transistor cell and its result: a saturated transistor at V_GS = 0 feeding a non-saturated copy of itself in weak inversion gives V_out = U_T ln(1 + S1/S2), proportional to absolute temperature and independent of the current. The 3.3 V drain shield that keeps the thin-oxide cell from tunnelling, the ratio, the unit and the sizing are this library's." }, "resources": { "record": "/circuits/ptat-2t.json", "page": "/index.html#ptat-2t", "achieved": "/achieved/ptat-2t.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_hv_tt.spice", "url": "/sg13g2_hv_tt.spice", "sha256": "e9b858ad4f7bba550467f1eddb6ca496bcc5f4644474f41240d63927934928ad" }, { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_hv_tt.spice", "sg13g2_lv_tt.spice" ], "ports": [ { "name": "out", "kind": "output", "note": "the PTAT voltage: M1's source, M2's gate and drain" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" } ], "devices": [ { "name": "MS", "type": "nmos", "nodes": "vdd vdd x vss", "sizedBy": [ "WS", "LS" ], "role": "3.3 V; the drain shield, diode-connected: holds M1's drain about 0.65 V below the supply", "fingers": 1, "copies": 1 }, { "name": "M1", "type": "nmos", "nodes": "x out out vss", "sizedBy": [ "W", "L", "N1" ], "role": "N1 copies of the unit at V_GS = 0, saturated, one finger each: its leakage is the cell's current", "fingers": 1, "copies": 7 }, { "name": "M2", "type": "nmos", "nodes": "out out vss vss", "sizedBy": [ "W", "L", "N2" ], "role": "N2 copies of the unit, one finger each, diode-connected, below saturation: its V_DS is the output", "fingers": 1, "copies": 1 } ], "intent": [ { "rule": "ratio", "of": [ "M1", "M2" ], "constraint": "V_out = U_T ln(1 + N1/N2)", "why": "In weak inversion a transistor's current is its copies times exp((V_G - V_T0)/(n U_T)) times (exp(-V_S/U_T) - exp(-V_D/U_T)), voltages from the bulk. M1 and M2 share a gate voltage, the output: M1 with its source at V_out and its drain well above it, M2 with its source on ground and its drain at V_out. Equal currents leave N1 exp(-V_out/U_T) = N2 (1 - exp(-V_out/U_T)), so V_out = U_T ln(1 + N1/N2) - no n, no threshold, no current. N1/N2 = 7 gives U_T ln 8: 53.8 mV and 179 µV/°C ideally. The ratio is 7 rather than 3 because the supply's effect on V_out grows only as N1/(N1 + N2) while the slope grows as ln(1 + N1/N2): at 7 the supply error, read in degrees, is a fifth smaller." }, { "rule": "unit-copies", "of": [ "M1", "M2" ], "constraint": "one unit; N1 and N2 count it", "why": "The law needs the two thresholds equal, so both are copies of one unit, interleaved; a ratio drawn as two different widths or lengths would add the difference of their thresholds, and it moves with process: one length against another gave the output a corner spread of a third of itself." }, { "rule": "shield", "of": [ "MS", "M1" ], "constraint": "M1's gate-drain voltage ≈ V_DD - V_GS,MS - V_out ≈ 0.46 V", "why": "M1's gate is its source, the output, so its whole drain voltage sits across the thin gate oxide at the drain edge, and electrons tunnel through it into the output: at -40 °C, where M1's leakage is a few hundred picoamps, 20 pA of it with the supply on M1's drain. Draws that leak several times less than typical, or have a thinner oxide, then bow the output up by 15 to 60 °C at the cold end, and no unit shape removes it. MS, a diode-connected 3.3 V NMOS - thick oxide, negligible gate tunnelling at these voltages - takes about 0.65 V off: M1 sees 0.46 V, and its tunnelling falls tenfold. A 1.2 V shield drops only 0.2 V and halves it, which left draws bowing by 15 to 18 °C. MS's V_GS also grows with the cell's current at 125 °C, giving M1 less drain voltage when hot, which holds the hot end." }, { "rule": "unit-shape", "of": [ "M1", "M2" ], "constraint": "W = 10 µm in one finger, L = 0.5 µm", "why": "The cell runs on M1's leakage per micron against what the shield leaves of its tunnelling, and on M2 staying in weak inversion at 125 °C while carrying N1/N2 times M1's current density. IHP's model scales a finger's narrow-width effect by its own width, so one 10 µm finger leaks more per micron than the two 5 µm fingers the layout rule would draw: in Monte Carlo 5 µm fingers bowed up to 6.8 °C, one 10 µm finger 2.9 °C. The short 0.5 µm length has a halo-raised threshold that keeps the hot end in weak inversion; longer units bend more at 125 °C." }, { "rule": "supply", "of": [ "M1", "MS" ], "constraint": "V_DS(M1) = V_DD - V_GS,MS - V_out", "why": "MS's gate is the supply, so M1's drain still follows it volt for volt, and at 0.46 V M1's drain-induced barrier lowering is steeper than it would be at the full supply: V_out moves 4.9 mV over 1.08 to 1.32 V, read as 26 °C at 27 °C and 36 °C at 125 °C - about half as much again as unshielded. It is the price of the cold end; the cell wants a regulated supply." } ], "specs": [ { "key": "vout_27", "label": "Output at 27 °C", "unit": "V", "direction": "target", "constraint": ">= 0.064 V, <= 0.078 V", "min": 0.064, "max": 0.078, "why": "U_T ln 8 is 53.8 mV at 27 °C; M1's barrier lowering at 0.46 V of drain voltage adds about 17 mV, 71 mV in all. The window holds the corners (67 to 74 mV) and the pair's mismatch over 40 Monte Carlo draws (67 to 74 mV) with 3 mV to spare." }, { "key": "slope", "label": "Temperature slope", "unit": "µV/°C", "direction": "max", "constraint": ">= 165 µV/°C", "min": 165, "max": null, "why": "(k/q) ln 8 is 179 µV/°C; 185 µV/°C here, 176 to 199 over the corners and at least 183 in every draw." }, { "key": "nonlin", "label": "Nonlinearity, -40 to 125 °C", "unit": "°C", "direction": "min", "constraint": "<= 4 °C", "min": null, "max": 4, "why": "With M1's gate tunnelling taken off by the shield, the output stays within 1.6 °C of a straight line at the typical corner, 2.2 °C at the worst other corner and 2.9 °C in the worst of 40 Monte Carlo draws. Unshielded, draws that leaked several times less than typical bowed up by 15 to 60 °C at -40 °C." }, { "key": "line_temp", "label": "Supply error, 1.08 to 1.32 V", "unit": "°C", "direction": "min", "constraint": "<= 40 °C", "min": null, "max": 40, "why": "The cost of the shield: M1 now works at 0.46 V of drain voltage, where its barrier lowering is steeper, and the supply's changes still reach its drain one for one - 4.9 mV over 1.08 to 1.32 V, read as 26 °C at 27 °C and 36 °C at 125 °C (17 and 21 °C unshielded). The cell needs a regulated supply." }, { "key": "i_supply", "label": "Supply current at 27 °C", "unit": "A", "direction": "min", "constraint": "<= 4e-7 A", "min": null, "max": 4e-7, "why": "M1's leakage at V_GS = 0: 21 nA at 27 °C, 0.4 nA at -40 °C and 0.8 µA at 125 °C. A threshold 60 mV low moves it tenfold, so it spreads from 4 to 98 nA over the corners and up to 232 nA over 40 Monte Carlo draws; the limit is set from those draws." }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 10 dB", "min": 10, "max": null, "why": "Supply ripple reaches the output through M1's barrier lowering at low frequency and through the drain capacitances above: 34 dB at 1 kHz." }, { "key": "t_start", "label": "Start-up time, to 1 %", "unit": "s", "direction": "min", "constraint": "<= 0.00005 s", "min": null, "max": 0.00005, "why": "No state to stick in: M1 leaks from the moment the supply rises, charging the output in 10 µs at 27 °C and 35 µs at -40 °C." } ], "explanation": { "idea": "Produces a small voltage that rises almost linearly with temperature. One NMOS supplies leakage current to a second; a third transistor shields the pair from the supply. It uses very little power, but supply changes can look like temperature changes, so it needs a regulated supply.", "detail": "A compact temperature sensor: two copies of one NMOS unit and no bias, with a 3.3 V diode as a drain shield. M1 has its gate on its source, the output, so it passes only its weak-inversion leakage; M2, diode-connected, must carry that same current with only V_out across it, below saturation. In weak inversion a transistor's current is exponential in its source and drain voltages, so the balance settles at V_out ≈ U_T ln(1 + N1/N2): proportional to absolute temperature and independent of the current, the principle of 'CMOS analog integrated circuits based on weak inversion operations'. MS keeps 0.67 V of the supply off M1's thin gate oxide, whose tunnelling would otherwise feed the output at the cold end.", "lesson": { "relation": 0, "symbols": "V_out is output voltage; U_T = kT/q is thermal voltage with temperature T in kelvin; N1 and N2 are the numbers of identical NMOS units.", "assumptions": "Ideal matched units in weak inversion, common bulk and gate, M1 saturated and M2 not saturated. The real drain dependence adds an offset to this ideal PTAT law.", "exercise": { "param": "N1", "value": 10, "analysis": "temp", "expect": "More M1 units should raise the output voltage and its temperature slope. Compare the slope as well as the voltage at 27 °C." }, "limits": "Use a regulated supply and a very high-impedance readout. Device mismatch and drain dependence make this approximately linear, not an accurate absolute thermometer without calibration." }, "path": [ { "part": "Drain shield", "devices": "MS", "does": "A diode-connected 3.3 V NMOS, 1 by 1 µm, from the supply to M1's drain: it holds that drain 0.67 V below the supply, so M1's gate oxide sees 0.46 V instead of 1.13 V and tunnels more than ten times less; its own thick oxide has negligible gate tunnelling at these voltages." }, { "part": "Leakage source", "devices": "M1", "does": "N1 = 7 copies of a single 10 µm finger with the gate on the source: at V_GS = 0 it passes only its subthreshold current, 21 nA at 27 °C, and that current is the cell's." }, { "part": "Non-saturated diode", "devices": "M2", "does": "One copy, diode-connected: with only V_out, a few U_T, across it, its current carries the factor 1 − exp(−V_out/U_T), and V_out settles where that balances M1." }, { "part": "Matched units", "devices": "M1, M2", "does": "Both are copies of one 10 by 0.5 µm unit drawn as one finger, seven against one, so the common nominal threshold approximately cancels; mismatch and drain dependence remain." } ], "bias": "No bias circuit: the current is M1's leakage at V_GS = 0, 0.4 nA at −40 °C, 21 nA at 27 °C and 0.8 µA at 125 °C, and the ideal weak-inversion result is independent of it. Real drain effects and leakage still perturb V_out. The supply sits across MS and M1; MS takes 0.67 V of it.", "relations": [ { "what": "Output voltage", "expr": "V_out ≈ U_T ln(1 + N1/N2)", "note": "both in weak inversion, one threshold: U_T ln 8 = 53.8 mV at 27 °C; M1's barrier lowering at 0.46 V of drain voltage adds about 17 mV, 71.1 mV here" }, { "what": "Temperature slope", "expr": "dV_out/dT = (k/q) ln(1 + N1/N2)", "note": "179 µV/°C ideally, 185 µV/°C here; straight to 1.6 °C from −40 to 125 °C, and to 2.9 °C in the worst of 40 Monte Carlo draws" }, { "what": "Gate tunnelling", "expr": "I_g,M1 ∝ W_M1 J_EDT(V_DS,M1)", "note": "M1's gate current from its drain into the output: at −40 °C about 20 pA with the supply on its drain against a few hundred picoamps of leakage, about 1 pA at the shield's 0.46 V" }, { "what": "Cell current", "expr": "I ≈ N1 I_0 exp(−V_T0/(n U_T)) exp(−V_out (1 − 1/n)/U_T)", "note": "M1's leakage: a thousandfold over the range and tenfold for a threshold 60 mV low; the ideal output cancels this common current, but real-device effects remain" }, { "what": "Supply", "expr": "ΔV_out ≈ (N1/(N1 + N2)) σ ΔV_DD / n", "note": "σ, M1's drain-induced barrier lowering, steeper at 0.46 V: 4.9 mV over 1.08 to 1.32 V, read as 26 °C" } ], "tradeoffs": [ "N1 and N2: a larger N1/N2 raises V_out and its slope logarithmically and shrinks the supply error in degrees, but M2 then runs at N1/N2 times M1's current density and nears moderate inversion at 125 °C.", "WS and LS (the shield): a smaller shield drops more voltage, cutting M1's tunnelling further and, at 125 °C where the current is largest, its barrier lowering too, which holds the hot end; drop too much and the supply error grows and the hot end falls away. A 1.2 V shield drops too little: Monte Carlo draws still bowed by 15 to 18 °C.", "W (the unit, one finger): a wide single finger leaks more per micron than two narrow ones, which keeps M1's channel ahead of what tunnelling remains; 5 µm fingers bowed up to 6.8 °C in Monte Carlo draws, 10 µm ones 2.9 °C.", "L (the unit): short units have a halo-raised threshold that keeps the hot end in weak inversion; longer ones would cut the barrier lowering but bend at 125 °C." ] }, "sizing": [ { "key": "W", "label": "W unit (M1, M2), one finger", "unit": "m", "value": 0.00001, "min": 5e-7, "max": 0.00004, "kind": "si" }, { "key": "L", "label": "L unit", "unit": "m", "value": 5e-7, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "N1", "label": "M1, copies of the unit", "unit": "", "value": 7, "min": 1, "max": 40, "kind": "int" }, { "key": "N2", "label": "M2, copies of the unit", "unit": "", "value": 1, "min": 1, "max": 16, "kind": "int" }, { "key": "WS", "label": "W drain shield (MS)", "unit": "m", "value": 0.000001, "min": 3e-7, "max": 0.00002, "kind": "si" }, { "key": "LS", "label": "L drain shield", "unit": "m", "value": 0.000001, "min": 4.5e-7, "max": 0.00001, "kind": "si" } ], "testbenches": [ { "id": "temp", "label": "Against temperature", "note": "The output from -40 to 125 °C at the typical supply: its slope, how far it strays from a straight line, and where that line reaches zero - at -273 °C for an output proportional to absolute temperature.", "measures": [], "metricKeys": [ "vout_27", "slope", "nonlin", "t_zero", "i_supply" ], "acceptance": [ "vout_27", "slope", "nonlin", "i_supply" ], "acceptanceRules": [ { "key": "vout_27", "unit": "V", "min": 0.064, "max": 0.078, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "slope", "unit": "µV/°C", "min": 165, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "nonlin", "unit": "°C", "min": null, "max": 4, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "i_supply", "unit": "A", "min": null, "max": 4e-7, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_hv_tt.spice" ], "netlist": "* Two-transistor PTAT sensor - the output against temperature\n.include sg13g2_lv_tt.spice\n.include sg13g2_hv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n.subckt ptat2t out vdd vss\n* MS: the drain shield, gate on the supply: M1's drain sits a V_GS below it\nXMS vdd vdd x vss sg13_hv_nmos w=1u l=1u ng=1 m=1\n* M1: N1 copies at V_GS = 0, its leakage the cell's current\nXM1 x out out vss sg13_lv_nmos w=10u l=500n ng=1 m=7\n* M2: N2 copies, diode-connected, carrying it below saturation\nXM2 out out vss vss sg13_lv_nmos w=10u l=500n ng=1 m=1\n.ends\nXdut out vdd 0 ptat2t\n.dc temp -40 125 5\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc vout27 FIND v(out) AT=27\n.end" }, { "id": "line", "label": "Against the supply", "note": "The output over the rated supply, 1.08 to 1.32 V, and the temperature error that change would read as.", "measures": [], "metricKeys": [ "line_mv", "line_temp" ], "acceptance": [ "line_temp" ], "acceptanceRules": [ { "key": "line_temp", "unit": "°C", "min": null, "max": 40, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_hv_tt.spice" ], "netlist": "* Two-transistor PTAT sensor - the output against the supply\n.include sg13g2_lv_tt.spice\n.include sg13g2_hv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n.subckt ptat2t out vdd vss\n* MS: the drain shield, gate on the supply: M1's drain sits a V_GS below it\nXMS vdd vdd x vss sg13_hv_nmos w=1u l=1u ng=1 m=1\n* M1: N1 copies at V_GS = 0, its leakage the cell's current\nXM1 x out out vss sg13_lv_nmos w=10u l=500n ng=1 m=7\n* M2: N2 copies, diode-connected, carrying it below saturation\nXM2 out out vss vss sg13_lv_nmos w=10u l=500n ng=1 m=1\n.ends\nXdut out vdd 0 ptat2t\n.dc Vdd 1.08 1.32 0.01\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc vlo FIND v(out) AT=1.08\n.meas dc vhi FIND v(out) AT=1.32\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on V_DD, and how much of it reaches the output, from 1 Hz to 1 GHz.", "measures": [], "metricKeys": [ "psrr_db" ], "acceptance": [ "psrr_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 10, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_hv_tt.spice" ], "netlist": "* Two-transistor PTAT sensor - supply rejection\n.include sg13g2_lv_tt.spice\n.include sg13g2_hv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD} ac 1\n.subckt ptat2t out vdd vss\n* MS: the drain shield, gate on the supply: M1's drain sits a V_GS below it\nXMS vdd vdd x vss sg13_hv_nmos w=1u l=1u ng=1 m=1\n* M1: N1 copies at V_GS = 0, its leakage the cell's current\nXM1 x out out vss sg13_lv_nmos w=10u l=500n ng=1 m=7\n* M2: N2 copies, diode-connected, carrying it below saturation\nXM2 out out vss vss sg13_lv_nmos w=10u l=500n ng=1 m=1\n.ends\nXdut out vdd 0 ptat2t\n.ac dec 20 1 1g\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas ac vdb_1k FIND vdb(out) AT=1k\n.end" }, { "id": "startup", "label": "Power-up", "note": "The supply ramps from 0 to V_DD in 10.0 µs: how long the output takes to come within 1 % of its operating point, and whether it gets there.", "measures": [], "metricKeys": [ "t_start" ], "acceptance": [ "t_start" ], "acceptanceRules": [ { "key": "t_start", "unit": "s", "min": null, "max": 0.00005, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_hv_tt.spice" ], "netlist": "* Two-transistor PTAT sensor - the supply ramping up from zero\n.include sg13g2_lv_tt.spice\n.include sg13g2_hv_tt.spice\n.param VDD=1.2\nVdd vdd 0 pwl(0 0 10u {VDD})\n.subckt ptat2t out vdd vss\n* MS: the drain shield, gate on the supply: M1's drain sits a V_GS below it\nXMS vdd vdd x vss sg13_hv_nmos w=1u l=1u ng=1 m=1\n* M1: N1 copies at V_GS = 0, its leakage the cell's current\nXM1 x out out vss sg13_lv_nmos w=10u l=500n ng=1 m=7\n* M2: N2 copies, diode-connected, carrying it below saturation\nXM2 out out vss vss sg13_lv_nmos w=10u l=500n ng=1 m=1\n.ends\nXdut out vdd 0 ptat2t\n.tran 50n 100u\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas tran vend FIND v(out) AT=100u\n.end" } ], "measurements": { "vout_27": { "label": "Output at 27 °C", "unit": "V", "spec": { "min": 0.064, "max": 0.078 } }, "slope": { "label": "Temperature slope", "unit": "µV/°C", "spec": { "min": 165, "max": null } }, "nonlin": { "label": "Nonlinearity, -40 to 125 °C", "unit": "°C", "spec": { "min": null, "max": 4 } }, "line_temp": { "label": "Supply error, 1.08 to 1.32 V", "unit": "°C", "spec": { "min": null, "max": 40 } }, "i_supply": { "label": "Supply current at 27 °C", "unit": "A", "spec": { "min": null, "max": 4e-7 } }, "psrr_db": { "label": "Supply rejection at 1 kHz", "unit": "dB", "spec": { "min": 10, "max": null } }, "t_start": { "label": "Start-up time, to 1 %", "unit": "s", "spec": { "min": null, "max": 0.00005 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "331286af7ff5645952e726ddfd3494e6a1cf0be61a9e8e136c8bca35b82bb0af" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ptat-2t.js", "sha256": "5c29137d451096610601cd4714400430263891f71963e717dbe9a135d3a73cf6" }, "simulationFingerprints": { "temp": "1955885728b9c38d9aee422d126291bc9d3496df40f46b78c1d23d45a7621df0", "line": "a975ea85b8548457d4747cdac34c5701d2eea39f4702fe00b647b7dd95f87717", "psrr": "6dc5a81e7e38464dcc53ebf731aba6c92bbf863927c9e94c3389b6d75088979d", "startup": "e33a82cd052f41fdc929286532b3f1e670a571cc6deaef6e176f67de7b399b71" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "ec1d086c2c9da12f7018cf8ea3d7f988020655b1ba67bc81910a40b58a787952", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ptat-2t", "parameters": { "W": 0.00001, "L": 5e-7, "N1": 7, "N2": 1, "WS": 0.000001, "LS": 0.000001 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ptat-2t/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "ptat2t", "ports": [ { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" } ], "definitions": [], "devices": [ { "id": "XMS", "displayName": "MS", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=1u l=1u ng=1 m=1", "source": "XMS vdd vdd x vss sg13_hv_nmos w=1u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vdd" }, { "id": "g", "net": "vdd" }, { "id": "s", "net": "x" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=500n ng=1 m=7", "source": "XM1 x out out vss sg13_lv_nmos w=10u l=500n ng=1 m=7", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "out" }, { "id": "s", "net": "out" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=500n ng=1 m=1", "source": "XM2 out out vss vss sg13_lv_nmos w=10u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "out" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "XMS", "pin": "d" }, { "device": "XMS", "pin": "g" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMS", "pin": "s" }, { "device": "XM1", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMS", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "d" }, { "device": "XM2", "pin": "g" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ptat2t", "parametersOrValue": "", "source": "Xdut out vdd 0 ptat2t", "pins": [ { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ptat2t" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ptat2t", "name": "ptat2t", "ports": [ { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" } ], "definitions": [], "devices": [ { "id": "XMS", "displayName": "MS", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=1u l=1u ng=1 m=1", "source": "XMS vdd vdd x vss sg13_hv_nmos w=1u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vdd" }, { "id": "g", "net": "vdd" }, { "id": "s", "net": "x" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=500n ng=1 m=7", "source": "XM1 x out out vss sg13_lv_nmos w=10u l=500n ng=1 m=7", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "out" }, { "id": "s", "net": "out" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=500n ng=1 m=1", "source": "XM2 out out vss vss sg13_lv_nmos w=10u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "out" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "XMS", "pin": "d" }, { "device": "XMS", "pin": "g" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMS", "pin": "s" }, { "device": "XM1", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMS", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "d" }, { "device": "XM2", "pin": "g" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ptat2t" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "3.3 V; the drain shield", "devices": [ { "scope": "dut", "device": "XMS" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "N1 copies of the unit at V_GS = 0", "devices": [ { "scope": "dut", "device": "XM1" } ], "inferredStages": [ "bias" ] }, { "id": "block-3", "label": "N2 copies of the unit", "devices": [ { "scope": "dut", "device": "XM2" } ], "inferredStages": [ "bias" ] } ], "edges": [ { "id": "net-1", "net": "x", "nodes": [ "block-1", "block-2" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "out", "nodes": [ "block-2", "block-3" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD} ac 1", "source": "Vdd vdd 0 dc {VDD} ac 1", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ptat2t", "parametersOrValue": "", "source": "Xdut out vdd 0 ptat2t", "pins": [ { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ptat2t" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ptat2t", "name": "ptat2t", "ports": [ { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" } ], "definitions": [], "devices": [ { "id": "XMS", "displayName": "MS", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=1u l=1u ng=1 m=1", "source": "XMS vdd vdd x vss sg13_hv_nmos w=1u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "vdd" }, { "id": "g", "net": "vdd" }, { "id": "s", "net": "x" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=500n ng=1 m=7", "source": "XM1 x out out vss sg13_lv_nmos w=10u l=500n ng=1 m=7", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "out" }, { "id": "s", "net": "out" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=500n ng=1 m=1", "source": "XM2 out out vss vss sg13_lv_nmos w=10u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "out" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "XMS", "pin": "d" }, { "device": "XMS", "pin": "g" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XMS", "pin": "s" }, { "device": "XM1", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMS", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "d" }, { "device": "XM2", "pin": "g" } ], "ports": [ "out" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ptat2t" } }, { "id": "graph-5", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. 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