{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ptat-4t", "name": "Resistorless four-transistor PTAT cell", "group": "Mirrors, bias and references", "subgroup": "Temperature sensors", "title": "Resistorless four-transistor PTAT cell", "summary": "Produces a temperature-dependent voltage without a resistor. Two mirrors force differently sized NMOS branches to carry the same current, making one device's drain voltage the output; a fifth transistor speeds start-up. Low current saves power but makes loading important.", "reference": { "kind": "paper", "authors": "E. Vittoz, J. Fellrath", "title": "CMOS analog integrated circuits based on weak inversion operations", "year": 1977, "where": "IEEE Journal of Solid-State Circuits, 12(3):224-231", "doi": "10.1109/JSSC.1977.1050882", "takes": "The principle: a transistor in weak inversion below saturation, made to carry the current of a saturated one at the same gate voltage, settles at a drain voltage that is U_T times a logarithm of their size ratio - proportional to absolute temperature and independent of the current. The four-transistor cell that applies it is credited to the paper; the 3.3 V devices that keep it in weak inversion from -40 to 125 °C at a 1.2 V supply, the start-up device and the sizing are this library's." }, "resources": { "record": "/circuits/ptat-4t.json", "page": "/index.html#ptat-4t", "achieved": "/achieved/ptat-4t.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_hv_tt.spice", "url": "/sg13g2_hv_tt.spice", "sha256": "e9b858ad4f7bba550467f1eddb6ca496bcc5f4644474f41240d63927934928ad" }, { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_hv_tt.spice", "sg13g2_lv_tt.spice" ], "ports": [ { "name": "out", "kind": "output", "note": "the PTAT voltage: MN1's drain" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" } ], "devices": [ { "name": "MP1", "type": "pmos", "nodes": "out out vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "3.3 V; diode across the supply less V_out: sets the loop current", "fingers": 1, "copies": 1 }, { "name": "MP2", "type": "pmos", "nodes": "g out vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "3.3 V; copies MP1's current into MN2", "fingers": 1, "copies": 1 }, { "name": "MN2", "type": "nmos", "nodes": "g g vss vss", "sizedBy": [ "Wn", "Ln", "N2" ], "role": "3.3 V; N2 copies of the unit, diode-connected, saturated: sets the pair's gate voltage", "fingers": 4, "copies": 4 }, { "name": "MN1", "type": "nmos", "nodes": "out g vss vss", "sizedBy": [ "Wn", "Ln", "N1" ], "role": "3.3 V; N1 copies of the unit below saturation: its drain voltage is the output", "fingers": 4, "copies": 6 }, { "name": "MS1", "type": "nmos", "nodes": "vdd out g vss", "sizedBy": [], "role": "start-up, 0.5 by 2 µm: feeds g while out is high, off once the loop runs", "fingers": 1, "copies": 1 } ], "intent": [ { "rule": "ratio", "of": [ "MN1", "MN2" ], "constraint": "V_out = U_T ln(N1/(N1 - N2)), N1 > N2", "why": "In weak inversion a transistor's current is its copies times exp(V_GS/(nU_T)) times (1 - exp(-V_DS/U_T)). MN2, saturated, has the last factor at 1; MN1, with the same gate voltage and N1/N2 times the copies, must carry the same current, so its factor is N2/N1: V_out = U_T ln(N1/(N1 - N2)). Neither the current, nor n, nor the threshold appears - the output is proportional to absolute temperature. N1/N2 = 3/2 gives U_T ln 3: 28.4 mV and 94.7 µV/°C. A ratio nearer one gives more, but a threshold mismatch between the two reaches the output multiplied by N2/(N1 - N2)/n - about 1.5 at 3/2 - and more as the ratio closes." }, { "rule": "unit-copies", "of": [ "MN1", "MN2" ], "constraint": "one unit; N1 and N2 are counts of it", "why": "The ratio is a count of identical copies, laid out interleaved, so that it holds whatever the unit's absolute threshold and whatever the process corner: at the tested process corners, with nominal supply and at 27 °C, the output stays close to 28.2 mV." }, { "rule": "weak-inversion", "of": [ "MN1", "MN2", "MP1" ], "constraint": "MN2 at about 2.5 nA per unit W/L; V_GS(MN2) > 5 U_T at 125 °C", "why": "The law holds only in weak inversion, and only while MN2 stays saturated - its V_DS is its own V_GS, which must exceed about 5 U_T, 0.17 V at 125 °C. MP1 is long and narrow, 0.5 by 40 µm, for about 50 nA per branch, and MN2 is four wide units, so it runs at about 2.5 nA per unit W/L, deep in weak inversion. Doubling the current per square moves the output by less than a millivolt; at 50 times it the pair is in moderate inversion and the output follows the current, and with it the supply." }, { "rule": "thick-oxide", "of": [ "MN1", "MN2", "MP1", "MP2" ], "constraint": "3.3 V devices at a 1.2 V supply", "why": "A 1.2 V NMOS in weak inversion needs less V_GS at 125 °C than the 5 U_T that keeps MN2 saturated - at 125 °C it leaks tens of nanoamps per square at V_GS = 0 - so with core devices the output collapses at the hot end and swings 50 °C of reading with the supply. The 3.3 V NMOS's higher threshold holds MN2's V_GS between 0.51 and 0.25 V from -40 to 125 °C at the same 2.5 nA per unit W/L. MP1 sits across V_DD - V_out, 1.17 V; the 3.3 V PMOS's higher threshold keeps its overdrive, and so MP2's saturation voltage, well below the 0.7 to 0.95 V that MP2 has, and makes 50 nA a reasonable size. Nothing here sees more than 1.32 V; the thick oxide is chosen for its threshold and its negligible gate leakage, not its voltage." }, { "rule": "start-up", "of": [ "MS1", "MN2", "MN1" ], "constraint": "V_GS(MS1) = V_out - V_g < -0.2 V once running", "why": "The loop has no second DC solution, but it has a very slow way out of the one it powers up in: as the supply rises MP1 pulls out up behind it, g stays near ground, and the loop current starts from picoamps charging the two NMOS gates, about 2 pF - many milliseconds. MS1, gate on out and source on g, feeds g while out sits high; MN2 turns that current into gate voltage, MN1 pulls out down and the loop takes over. Running, out is 22 to 37 mV and g 0.25 to 0.55 V, so MS1 sits at V_GS below -0.2 V; its leakage at 125 °C moves the output by 0.02 mV at the typical corner and costs about half a degree of straightness at the fast one. A wider MS1 starts faster at -40 °C but leaks more at 125 °C: 1 by 1 µm doubles that cost." }, { "rule": "match", "of": [ "MP1", "MP2" ], "constraint": "one copy each, interleaved", "why": "MP2's copy of MP1 goes into the ratio: a copy error ε moves the output by about U_T ε N2/(N1 - N2). The two see different drain voltages, V_out and MN2's V_GS, so both are long, for a small output conductance." } ], "specs": [ { "key": "vout_27", "label": "Output at 27 °C", "unit": "V", "direction": "target", "constraint": ">= 0.025 V, <= 0.031 V", "min": 0.025, "max": 0.031, "why": "U_T ln(N1/(N1 - N2)) is 28.4 mV at 27 °C with N1/N2 = 3/2; the window leaves room for the pair's mismatch, which reaches the output about one and a half times over (see ratio)." }, { "key": "slope", "label": "Temperature slope", "unit": "µV/°C", "direction": "max", "constraint": ">= 80 µV/°C", "min": 80, "max": null, "why": "(k/q) ln 3 is 94.7 µV/°C; the pair's small leftover drain dependence takes a few per cent of it." }, { "key": "nonlin", "label": "Nonlinearity, -40 to 125 °C", "unit": "°C", "direction": "min", "constraint": "<= 1.5 °C", "min": null, "max": 1.5, "why": "Weak inversion holds from -40 to 125 °C: a third of a degree from a straight line, under a degree at every corner. The start-up device's leakage at 125 °C and the pair's mismatch account for the rest of the allowance." }, { "key": "line_temp", "label": "Supply error, 1.08 to 1.32 V", "unit": "°C", "direction": "min", "constraint": "<= 6 °C", "min": null, "max": 6, "why": "In weak inversion the output does not depend on the loop current, which the supply moves by about half over 1.08 to 1.32 V; what remains is MN2's drain dependence, largest at -40 °C." }, { "key": "i_supply", "label": "Supply current at 27 °C", "unit": "A", "direction": "min", "constraint": "<= 2e-7 A", "min": null, "max": 2e-7, "why": "Two branches of about 50 nA: MP1 is long and narrow so the pair stays deep in weak inversion." }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 20 dB", "min": 20, "max": null, "why": "The output is a node of a few hundred kilohms, loaded by the devices' capacitance: the ripple it passes rises with frequency." }, { "key": "t_start", "label": "Start-up time, to 1 %", "unit": "s", "direction": "min", "constraint": "<= 0.00025 s", "min": null, "max": 0.00025, "why": "The loop starts from the leakage of its own devices; MS1 hurries it, to tens of microseconds at 27 °C and about 150 µs at -40 °C, where every current in it is smallest." } ], "explanation": { "idea": "Produces a temperature-dependent voltage without a resistor. Two mirrors force differently sized NMOS branches to carry the same current, making one device's drain voltage the output; a fifth transistor speeds start-up. Low current saves power but makes loading important.", "detail": "Four transistors and no resistor give a voltage proportional to absolute temperature. MP1, diode-connected across nearly the whole supply, sets a loop current; MP2 copies it into MN2, whose gate voltage MN1 shares. MN1 has N1 copies of the NMOS unit against MN2's N2, so in saturation it would carry N1/N2 times the current; held to the same current, it drops out of saturation, and in weak inversion its drain voltage, the output, settles where 1 − exp(−V_out/U_T) = N2/N1: V_out ≈ U_T ln(N1/(N1 − N2)), largely independent of current while those conditions hold.", "lesson": { "relation": 0, "symbols": "V_out is output voltage; U_T = kT/q is thermal voltage with T in kelvin; N1 and N2 count identical NMOS units, with N1 greater than N2.", "assumptions": "Both NMOS branches are in weak inversion with equal currents; MN2 is saturated and MN1 is not. Matched thresholds and negligible drain dependence are assumed.", "exercise": { "param": "N1", "value": 8, "analysis": "temp", "expect": "Increasing N1 while keeping N2 fixed should lower the output voltage and temperature slope. Bringing their ratio closer to one does the opposite but increases mismatch sensitivity." }, "limits": "Keep integer N1 > N2 >= 1 and load the output lightly; invalid count combinations are rejected. Four devices form the sensing core; a fifth is included for start-up." }, "path": [ { "part": "Loop current", "devices": "MP1, MP2", "does": "MP1, long and narrow, sits across V_DD − V_out and sets about 50 nA; MP2 copies it into g." }, { "part": "Diode", "devices": "MN2", "does": "N2 = 4 copies of the 20 by 4 µm unit, diode-connected and saturated. At about 50 nA, the normalized current I/[N2·(Wn/Ln)] is 2.5 nA; g is about 0.42 V at 27 °C." }, { "part": "Output device", "devices": "MN1", "does": "N1 = 6 copies at MN2's gate voltage: it can carry MN2's current only below saturation, and its drain voltage, 28.1 mV at 27 °C, is V_out." }, { "part": "Start-up", "devices": "MS1", "does": "Gate on out, source on g: while the supply comes up out sits high and MS1 feeds g; once the loop runs its gate is 0.4 V below its source and it is off." } ], "bias": "Nothing but MP1 sets the current: its square law across V_DD − V_out, about 50 nA per branch, moving by half over 1.08 to 1.32 V - whose effect on V_out is much smaller because the ideal weak-inversion law cancels common current. All four are 3.3 V devices at a 1.2 V supply, for their threshold; MS1 is a 1.2 V device.", "relations": [ { "what": "Output voltage", "expr": "V_out ≈ U_T ln(N1/(N1 − N2))", "note": "U_T ln 3 = 28.4 mV at 27 °C for N1/N2 = 3/2; about 28.2 mV here; compare tested corner and mismatch results separately" }, { "what": "Temperature slope", "expr": "dV_out/dT = (k/q) ln(N1/(N1 − N2))", "note": "94.7 µV/°C ideally, 88 µV/°C here; about 0.36 °C from a fitted straight line from −40 to 125 °C" }, { "what": "MN2 saturated", "expr": "V_GS,MN2 > 5 U_T", "note": "0.17 V at 125 °C: why the pair is 3.3 V devices - their V_GS stays between 0.51 and 0.25 V over the range at about 2.5 nA per unit W/L, where a 1.2 V device's would fall below 0.1 V" }, { "what": "Mismatch", "expr": "ΔV_out ≈ (N2/(N1 − N2)) ΔV_T/n", "note": "the price of a ratio near one: N2/(N1 − N2) is 2 at 3/2, so the pair's threshold mismatch reaches the output about one and a half times over" } ], "tradeoffs": [ "N1 and N2: a ratio nearer one gives a larger V_out and slope, but multiplies the pair's mismatch by N2/(N1 − N2); 2 gives 17.9 mV with half the sensitivity.", "Wp and Lp (MP1, MP2): more current speeds start-up and cuts the start-up device's relative leakage, but moves the pair towards moderate inversion, where V_out follows the current and so the supply.", "Wn and Ln (the NMOS unit): larger units run the pair deeper in weak inversion and match better, at the cost of the gate capacitance MS1 must charge at power-up." ] }, "sizing": [ { "key": "Wn", "label": "W NMOS unit (MN1, MN2)", "unit": "m", "value": 0.00002, "min": 0.000001, "max": 0.00005, "kind": "si" }, { "key": "Ln", "label": "L NMOS unit", "unit": "m", "value": 0.000004, "min": 5e-7, "max": 0.00002, "kind": "si" }, { "key": "N2", "label": "MN2, copies of the unit", "unit": "", "value": 4, "min": 1, "max": 16, "kind": "int" }, { "key": "N1", "label": "MN1, copies of the unit", "unit": "", "value": 6, "min": 2, "max": 32, "kind": "int" }, { "key": "Wp", "label": "W PMOS (MP1, MP2)", "unit": "m", "value": 5e-7, "min": 3e-7, "max": 0.00001, "kind": "si" }, { "key": "Lp", "label": "L PMOS", "unit": "m", "value": 0.00004, "min": 0.000001, "max": 0.0001, "kind": "si" } ], "testbenches": [ { "id": "temp", "label": "Against temperature", "note": "The output from -40 to 125 °C at the typical supply: its slope, how far it strays from a straight line, and where that line reaches zero - at -273 °C for an output proportional to absolute temperature.", "measures": [], "metricKeys": [ "vout_27", "slope", "nonlin", "t_zero", "i_supply" ], "acceptance": [ "vout_27", "slope", "nonlin", "i_supply" ], "acceptanceRules": [ { "key": "vout_27", "unit": "V", "min": 0.025, "max": 0.031, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "slope", "unit": "µV/°C", "min": 80, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "nonlin", "unit": "°C", "min": null, "max": 1.5, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "i_supply", "unit": "A", "min": null, "max": 2e-7, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_hv_tt.spice" ], "netlist": "* Resistorless four-transistor PTAT cell - the output against temperature\n.include sg13g2_lv_tt.spice\n.include sg13g2_hv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n.subckt ptat4t out vdd vss\n* the loop current: MP1 across nearly the whole supply, and its copy MP2\nXMP1 out out vdd vdd sg13_hv_pmos w=500n l=40u ng=1 m=1\nXMP2 g out vdd vdd sg13_hv_pmos w=500n l=40u ng=1 m=1\n* MN2 (N2 copies) takes the copy and sets the gate voltage it shares with MN1\n* (N1 copies); MN1 carries the same current only below saturation\nXMN2 g g vss vss sg13_hv_nmos w=20u l=4u ng=4 m=4\nXMN1 out g vss vss sg13_hv_nmos w=20u l=4u ng=4 m=6\n* start-up: while out sits high MS1 feeds g; running, its gate is below its source\nXMS1 vdd out g vss sg13_lv_nmos w=500n l=2u ng=1 m=1\n.ends\nXdut out vdd 0 ptat4t\n.dc temp -40 125 5\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc vout27 FIND v(out) AT=27\n.end" }, { "id": "line", "label": "Against the supply", "note": "The output over the rated supply, 1.08 to 1.32 V, and the temperature error that change would read as.", "measures": [], "metricKeys": [ "line_mv", "line_temp" ], "acceptance": [ "line_temp" ], "acceptanceRules": [ { "key": "line_temp", "unit": "°C", "min": null, "max": 6, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_hv_tt.spice" ], "netlist": "* Resistorless four-transistor PTAT cell - the output against the supply\n.include sg13g2_lv_tt.spice\n.include sg13g2_hv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n.subckt ptat4t out vdd vss\n* the loop current: MP1 across nearly the whole supply, and its copy MP2\nXMP1 out out vdd vdd sg13_hv_pmos w=500n l=40u ng=1 m=1\nXMP2 g out vdd vdd sg13_hv_pmos w=500n l=40u ng=1 m=1\n* MN2 (N2 copies) takes the copy and sets the gate voltage it shares with MN1\n* (N1 copies); MN1 carries the same current only below saturation\nXMN2 g g vss vss sg13_hv_nmos w=20u l=4u ng=4 m=4\nXMN1 out g vss vss sg13_hv_nmos w=20u l=4u ng=4 m=6\n* start-up: while out sits high MS1 feeds g; running, its gate is below its source\nXMS1 vdd out g vss sg13_lv_nmos w=500n l=2u ng=1 m=1\n.ends\nXdut out vdd 0 ptat4t\n.dc Vdd 1.08 1.32 0.01\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc vlo FIND v(out) AT=1.08\n.meas dc vhi FIND v(out) AT=1.32\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on V_DD, and how much of it reaches the output, from 1 Hz to 1 GHz.", "measures": [], "metricKeys": [ "psrr_db" ], "acceptance": [ "psrr_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 20, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_hv_tt.spice" ], "netlist": "* Resistorless four-transistor PTAT cell - supply rejection\n.include sg13g2_lv_tt.spice\n.include sg13g2_hv_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD} ac 1\n.subckt ptat4t out vdd vss\n* the loop current: MP1 across nearly the whole supply, and its copy MP2\nXMP1 out out vdd vdd sg13_hv_pmos w=500n l=40u ng=1 m=1\nXMP2 g out vdd vdd sg13_hv_pmos w=500n l=40u ng=1 m=1\n* MN2 (N2 copies) takes the copy and sets the gate voltage it shares with MN1\n* (N1 copies); MN1 carries the same current only below saturation\nXMN2 g g vss vss sg13_hv_nmos w=20u l=4u ng=4 m=4\nXMN1 out g vss vss sg13_hv_nmos w=20u l=4u ng=4 m=6\n* start-up: while out sits high MS1 feeds g; running, its gate is below its source\nXMS1 vdd out g vss sg13_lv_nmos w=500n l=2u ng=1 m=1\n.ends\nXdut out vdd 0 ptat4t\n.ac dec 20 1 1g\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas ac vdb_1k FIND vdb(out) AT=1k\n.end" }, { "id": "startup", "label": "Power-up", "note": "The supply ramps from 0 to V_DD in 10.0 µs: how long the output takes to come within 1 % of its operating point, and whether it gets there.", "measures": [], "metricKeys": [ "t_start" ], "acceptance": [ "t_start" ], "acceptanceRules": [ { "key": "t_start", "unit": "s", "min": null, "max": 0.00025, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_hv_tt.spice" ], "netlist": "* Resistorless four-transistor PTAT cell - the supply ramping up from zero\n.include sg13g2_lv_tt.spice\n.include sg13g2_hv_tt.spice\n.param VDD=1.2\nVdd vdd 0 pwl(0 0 10u {VDD})\n.subckt ptat4t out vdd vss\n* the loop current: MP1 across nearly the whole supply, and its copy MP2\nXMP1 out out vdd vdd sg13_hv_pmos w=500n l=40u ng=1 m=1\nXMP2 g out vdd vdd sg13_hv_pmos w=500n l=40u ng=1 m=1\n* MN2 (N2 copies) takes the copy and sets the gate voltage it shares with MN1\n* (N1 copies); MN1 carries the same current only below saturation\nXMN2 g g vss vss sg13_hv_nmos w=20u l=4u ng=4 m=4\nXMN1 out g vss vss sg13_hv_nmos w=20u l=4u ng=4 m=6\n* start-up: while out sits high MS1 feeds g; running, its gate is below its source\nXMS1 vdd out g vss sg13_lv_nmos w=500n l=2u ng=1 m=1\n.ends\nXdut out vdd 0 ptat4t\n.tran 500n 1m\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas tran vend FIND v(out) AT=1m\n.end" } ], "measurements": { "vout_27": { "label": "Output at 27 °C", "unit": "V", "spec": { "min": 0.025, "max": 0.031 } }, "slope": { "label": "Temperature slope", "unit": "µV/°C", "spec": { "min": 80, "max": null } }, "nonlin": { "label": "Nonlinearity, -40 to 125 °C", "unit": "°C", "spec": { "min": null, "max": 1.5 } }, "line_temp": { "label": "Supply error, 1.08 to 1.32 V", "unit": "°C", "spec": { "min": null, "max": 6 } }, "i_supply": { "label": "Supply current at 27 °C", "unit": "A", "spec": { "min": null, "max": 2e-7 } }, "psrr_db": { "label": "Supply rejection at 1 kHz", "unit": "dB", "spec": { "min": 20, "max": null } }, "t_start": { "label": "Start-up time, to 1 %", "unit": "s", "spec": { "min": null, "max": 0.00025 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "aef6fd148f2b6f99d4fcb4940cbfb80f0ce1e33a55a0f2a2a1850a37203220c9" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ptat-4t.js", "sha256": "f495ff251b8d4ea61570595b9186baa991692911a416229d8320569e750a9554" }, "simulationFingerprints": { "temp": "31e0b77fae1e6ca8aac43c45d43dc1ebca5def375a0d983f18c4601348a6f337", "line": "09afe0556d74d2a2a6abab687a826254ff6b4c1555d69ad994b5a8521d46ef7d", "psrr": "4cf7f4dbeae61baa85f26e4d7b9e7af0a3d96a83eb15b435c2ba862b56bba70e", "startup": "9a79f0ea31537cc26a86a149df6c5217b6cb0e8d37d4430fed5765d6b1432b56" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "da1aa2046000e6065661d17df0ceb99d7087e75a1b64e0f44aa227740f45c0e3", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ptat-4t", "parameters": { "Wn": 0.00002, "Ln": 0.000004, "N2": 4, "N1": 6, "Wp": 5e-7, "Lp": 0.00004 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ptat-4t/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "ptat4t", "ports": [ { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" } ], "definitions": [], "devices": [ { "id": "XMP1", "displayName": "MP1", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=500n l=40u ng=1 m=1", "source": "XMP1 out out vdd vdd sg13_hv_pmos w=500n l=40u ng=1 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "out" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP2", "displayName": "MP2", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=500n l=40u ng=1 m=1", "source": "XMP2 g out vdd vdd sg13_hv_pmos w=500n l=40u ng=1 m=1", "pins": [ { "id": "d", "net": "g" }, { "id": "g", "net": "out" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=20u l=4u ng=4 m=4", "source": "XMN2 g g vss vss sg13_hv_nmos w=20u l=4u ng=4 m=4", "pins": [ { "id": "d", "net": "g" }, { "id": "g", "net": "g" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN1", "displayName": "MN1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=20u l=4u ng=4 m=6", "source": "XMN1 out g vss vss sg13_hv_nmos w=20u l=4u ng=4 m=6", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "g" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS1", "displayName": "MS1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=2u ng=1 m=1", "source": "XMS1 vdd out g vss sg13_lv_nmos w=500n l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vdd" }, { "id": "g", "net": "out" }, { "id": "s", "net": "g" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "out", "ground": false, "terminals": [ { "device": "XMP1", "pin": "d" }, { "device": "XMP1", "pin": "g" }, { "device": "XMP2", "pin": "g" }, { "device": "XMN1", "pin": "d" }, { "device": "XMS1", "pin": "g" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMP1", "pin": "s" }, { "device": "XMP1", "pin": "b" }, { "device": "XMP2", "pin": "s" }, { "device": "XMP2", "pin": "b" }, { "device": "XMS1", "pin": "d" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "g", "ground": false, "terminals": [ { "device": "XMP2", "pin": "d" }, { "device": "XMN2", "pin": "d" }, { "device": "XMN2", "pin": "g" }, { "device": "XMN1", "pin": "g" }, { "device": "XMS1", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XMN1", "pin": "s" }, { "device": "XMN1", "pin": "b" }, { "device": "XMS1", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ptat4t", "parametersOrValue": "", "source": "Xdut out vdd 0 ptat4t", "pins": [ { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ptat4t" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ptat4t", "name": "ptat4t", "ports": [ { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" } ], "definitions": [], "devices": [ { "id": "XMP1", "displayName": "MP1", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=500n l=40u ng=1 m=1", "source": "XMP1 out out vdd vdd sg13_hv_pmos w=500n l=40u ng=1 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "out" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMP2", "displayName": "MP2", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=500n l=40u ng=1 m=1", "source": "XMP2 g out vdd vdd sg13_hv_pmos w=500n l=40u ng=1 m=1", "pins": [ { "id": "d", "net": "g" }, { "id": "g", "net": "out" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN2", "displayName": "MN2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=20u l=4u ng=4 m=4", "source": "XMN2 g g vss vss sg13_hv_nmos w=20u l=4u ng=4 m=4", "pins": [ { "id": "d", "net": "g" }, { "id": "g", "net": "g" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMN1", "displayName": "MN1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=20u l=4u ng=4 m=6", "source": "XMN1 out g vss vss sg13_hv_nmos w=20u l=4u ng=4 m=6", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "g" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS1", "displayName": "MS1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=2u ng=1 m=1", "source": "XMS1 vdd out g vss sg13_lv_nmos w=500n l=2u ng=1 m=1", "pins": [ { "id": "d", "net": "vdd" }, { "id": "g", "net": "out" }, { "id": "s", "net": "g" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "out", "ground": false, "terminals": [ { "device": "XMP1", "pin": "d" }, { "device": "XMP1", "pin": "g" }, { "device": "XMP2", "pin": "g" }, { "device": "XMN1", "pin": "d" }, { "device": "XMS1", "pin": "g" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMP1", "pin": "s" }, { "device": "XMP1", "pin": "b" }, { "device": "XMP2", "pin": "s" }, { "device": "XMP2", "pin": "b" }, { "device": "XMS1", "pin": "d" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "g", "ground": false, "terminals": [ { "device": "XMP2", "pin": "d" }, { "device": "XMN2", "pin": "d" }, { "device": "XMN2", "pin": "g" }, { "device": "XMN1", "pin": "g" }, { "device": "XMS1", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XMN2", "pin": "s" }, { "device": "XMN2", "pin": "b" }, { "device": "XMN1", "pin": "s" }, { "device": "XMN1", "pin": "b" }, { "device": "XMS1", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ptat4t" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. 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