{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "ptat-self-biased", "name": "Self-biased PTAT generator", "group": "Mirrors, bias and references", "subgroup": "Temperature sensors", "title": "Self-biased PTAT generator", "summary": "Generates a voltage that rises almost linearly with temperature. A current mirror forces two differently sized NMOS branches to carry the same current, creating a temperature-dependent voltage across a resistor. A start-up circuit gets the loop running; matching and operating region limit accuracy.", "reference": { "kind": "book", "authors": "B. Razavi", "title": "Design of Analog CMOS Integrated Circuits", "edition": "2nd", "publisher": "McGraw-Hill", "year": 2016, "where": "Ch. 12 'Bandgap References': Sec. 12.4 'PTAT Current Generation' (p. 523), with Sec. 12.2 'Supply-Independent Biasing' (p. 509) and Sec. 12.5 'Constant-Gm Biasing' (p. 524)", "takes": "The topology - a diode-connected NMOS and a wider one with a resistor in its source, forced to one current by a PMOS mirror - its PTAT result, and the start-up the zero-current state needs. Weak inversion with both bulks on ground, which makes the result U_T ln K with no slope factor in it, the 3.3 V pair and the sizing are this library's." }, "resources": { "record": "/circuits/ptat-self-biased.json", "page": "/index.html#ptat-self-biased", "achieved": "/achieved/ptat-self-biased.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_hv_tt.spice", "url": "/sg13g2_hv_tt.spice", "sha256": "e9b858ad4f7bba550467f1eddb6ca496bcc5f4644474f41240d63927934928ad" }, { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_hv_tt.spice", "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "out", "kind": "output", "note": "the PTAT voltage across R1, M2's source" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" } ], "devices": [ { "name": "M1", "type": "nmos", "nodes": "g g vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "3.3 V; the diode: one unit", "fingers": 4, "copies": 1 }, { "name": "M2", "type": "nmos", "nodes": "d g out vss", "sizedBy": [ "Wn", "Ln", "K" ], "role": "3.3 V; K copies of M1's unit, R1 in its source, bulk on ground", "fingers": 4, "copies": 16 }, { "name": "R1", "type": "resistor", "nodes": "out vss", "sizedBy": [ "R" ], "role": "carries the PTAT voltage; sets only the current" }, { "name": "M4", "type": "pmos", "nodes": "d d vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "the mirror's diode, on M2's drain", "fingers": 1, "copies": 1 }, { "name": "M3", "type": "pmos", "nodes": "g d vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "copies M2's current into M1", "fingers": 1, "copies": 1 }, { "name": "MS1", "type": "nmos", "nodes": "d su g vss", "sizedBy": [], "role": "start-up, 1 by 1 µm: pulls d down into g while the loop is off", "fingers": 1, "copies": 1 }, { "name": "MS2", "type": "nmos", "nodes": "su g vss vss", "sizedBy": [ "Wn", "Ln" ], "role": "start-up, 3.3 V, two copies of M1's unit: holds su low once M1 carries a fifth of its current", "fingers": 4, "copies": 2 }, { "name": "MS3", "type": "pmos", "nodes": "su vss vdd vdd", "sizedBy": [], "role": "start-up, 3.3 V, 0.3 by 40 µm: a weak pull-up on su", "fingers": 1, "copies": 1 } ], "intent": [ { "rule": "ptat", "of": [ "M1", "M2", "R1" ], "constraint": "V_R1 = U_T ln K; I = U_T ln K / R1", "why": "In weak inversion a transistor's current is exp((V_G - V_T0)/(n U_T)) times exp(-V_S/U_T), voltages from its bulk. M1 and M2 share a gate and a bulk; M2 is K copies with its source V_R1 above ground; equal currents leave K exp(-V_R1/U_T) = 1. So V_R1 = U_T ln K: 71.7 mV at 27 °C for K = 16, rising 239 µV/°C, with no threshold, slope factor n or R1 in this weak-inversion approximation. R1 sets only the current, 100 nA per branch at 720 kΩ." }, { "rule": "bulk", "of": [ "M2" ], "constraint": "bulk on ground, not on its source", "why": "Tied to its source, M2 would lose its body effect and the result would become n U_T ln K - larger, but carrying n, which moves with process and temperature, and needing an isolated p-well under M2. With the bulk on ground, n cancels between the gate and the source terms and nothing but U_T is left. No special well is needed." }, { "rule": "weak-inversion", "of": [ "M1", "M2", "R1" ], "constraint": "M1 at about 10 nA per square", "why": "The law needs both in weak inversion over the whole range. M1, the denser of the two, is one 20 by 2 µm unit at 100 nA: 10 nA per square at 27 °C. Denser - a smaller R1, a smaller unit - and the pair moves towards the strong-inversion beta multiplier, whose voltage follows mobility and R1 instead of U_T." }, { "rule": "thick-oxide", "of": [ "M1", "M2" ], "constraint": "3.3 V devices at a 1.2 V supply", "why": "M2's drain follows the supply (it hangs one V_SG below it) and M1's does not. With 1.2 V devices that asymmetry costs dearly: in weak inversion their drain dependence moves V_R1 by about 20 mV per volt of drain even 8 µm long, and the output reads 15 °C of error over 1.08 to 1.32 V and bows by 3 °C. The 3.3 V NMOS barely feels its drain there: 2 °C over the same supply range, and a third of a degree of bow. Nothing in the cell sees more than 1.32 V." }, { "rule": "unit-copies", "of": [ "M1", "M2", "M3", "M4" ], "constraint": "K is a count of M1's unit; M3 and M4 one PMOS unit", "why": "The law needs K to be the ratio of two identical devices' sizes, so M2 is K copies of M1's unit, interleaved around it; a copy error ε in M3 and M4 moves V_R1 by U_T ε." }, { "rule": "start-up", "of": [ "MS1", "MS2", "MS3", "M1" ], "constraint": "MS2 = two copies of M1's unit; MS1 off once running", "why": "Zero current satisfies the loop as well, and so, nearly, does a trickle: at a few nanoamps M1's gate already sits at 0.2 to 0.35 V. While MS2 is off, MS3 pulls su up and MS1 pulls M4's gate down into g, which drives both branches. MS2 is two copies of M1's own 3.3 V unit, so it switches at M1's gate voltage: it takes su away only once M1 carries more than a fifth of its running current, MS3's 37 nA over its two copies. A 1.2 V MS2, a threshold 0.3 V lower, let go at the trickle, and the loop then crawled out on its own - 30 to 165 µs, in one Monte Carlo draw not within 200 µs. Running, MS2 holds su at 6 mV and MS1's gate sits half a volt below its source. MS3 is a 3.3 V PMOS, long and narrow, so that holding su low costs about 40 nA." } ], "specs": [ { "key": "vout_27", "label": "Output at 27 °C", "unit": "V", "direction": "target", "constraint": ">= 0.068 V, <= 0.079 V", "min": 0.068, "max": 0.079, "why": "U_T ln 16 is 71.7 mV at 27 °C; the pair's small drain dependence adds about 1.5 mV. The window is for the mismatch of M1 against M2." }, { "key": "slope", "label": "Temperature slope", "unit": "µV/°C", "direction": "max", "constraint": ">= 230 µV/°C", "min": 230, "max": null, "why": "(k/q) ln 16 is 239 µV/°C, and the cell gives 246: the law holds to 3 %." }, { "key": "nonlin", "label": "Nonlinearity, -40 to 125 °C", "unit": "°C", "direction": "min", "constraint": "<= 1 °C", "min": null, "max": 1, "why": "Weak inversion holds over the whole range, M1 at about 10 nA per square: a few tenths of a degree from a straight line." }, { "key": "line_temp", "label": "Supply error, 1.08 to 1.32 V", "unit": "°C", "direction": "min", "constraint": "<= 4 °C", "min": null, "max": 4, "why": "M2's drain follows the supply through M4's V_SG, M3's drain does not move; the 3.3 V pair's small drain dependence keeps that to about 0.5 mV, 2 °C." }, { "key": "i_supply", "label": "Supply current at 27 °C", "unit": "A", "direction": "min", "constraint": "<= 4e-7 A", "min": null, "max": 4e-7, "why": "Two branches of U_T ln K / R1, 100 nA each at 27 °C, and the start-up's pull-up, about 40 nA." }, { "key": "psrr_db", "label": "Supply rejection at 1 kHz", "unit": "dB", "direction": "max", "constraint": ">= 30 dB", "min": 30, "max": null, "why": "The loop sets V_R1 whatever the supply; a ripple reaches it through the drain dependence left and, at high frequency, M2's drain capacitance." }, { "key": "t_start", "label": "Start-up time, to 1 %", "unit": "s", "direction": "min", "constraint": "<= 0.000025 s", "min": null, "max": 0.000025, "why": "The start-up circuit holds the loop until it runs: 11.5 µs from the start of a 10 µs supply ramp, 10 to 13 µs at every corner and in every one of 40 Monte Carlo draws." } ], "explanation": { "idea": "Generates a voltage that rises almost linearly with temperature. A current mirror forces two differently sized NMOS branches to carry the same current, creating a temperature-dependent voltage across a resistor. A start-up circuit gets the loop running; matching and operating region limit accuracy.", "detail": "The self-biased loop of a supply-independent bias, run in weak inversion to give a voltage proportional to absolute temperature. M1 is diode-connected; M2, K copies of it, shares its gate with R1 in its source; the mirror M3–M4 forces both to one current. In weak inversion M2 would carry K times M1's current at the same gate voltage, so the voltage across R1 rises until exp(−V_R1/U_T) takes back the factor K: V_R1 ≈ U_T ln K in the weak-inversion approximation; R1 mainly sets current. With both bulks grounded, the common slope factor cancels in this approximation.", "lesson": { "relation": 1, "symbols": "V_R1 is the output across R1; U_T = kT/q is thermal voltage with T in kelvin; K is the number of M2 unit devices relative to M1.", "assumptions": "Matched weak-inversion NMOS devices sharing a gate and grounded bulk, equal branch currents, and negligible drain dependence. The cancellation of the slope factor is approximate.", "exercise": { "param": "K", "value": 8, "analysis": "temp", "expect": "Halving K should lower the output and its temperature slope. The change follows ln K, so it is not a factor of two." }, "limits": "The resistor sets current and helps keep the devices in weak inversion. The output must be lightly loaded, and the start-up circuit must remain connected." }, "path": [ { "part": "Start-up", "devices": "MS1, MS2, MS3", "does": "Until M1 carries a fifth of its current, MS2 - two copies of M1's own 3.3 V unit - is off and MS3 pulls su up; MS1 then pulls d down into g and drives both branches. Once M1 runs, MS2 holds su at 6 mV and MS1 is off." }, { "part": "Diode", "devices": "M1", "does": "One 20 by 2 µm unit of the 3.3 V NMOS, diode-connected at about 100 nA: 10 nA per square, weak inversion; its gate voltage g is shared with M2." }, { "part": "Degenerated copies", "devices": "M2, R1", "does": "K = 16 copies with R1 in their source: to carry M1's current they need V_R1 ≈ U_T ln K less gate-source voltage, and that voltage across R1 is the output." }, { "part": "Mirror", "devices": "M3, M4", "does": "M4, diode-connected on M2's drain d, and M3 copying it into M1 make the two currents equal and close the loop." } ], "bias": "Self-biased: the loop settles at the one non-zero current I = U_T ln K / R1, about 100 nA per branch at 27 °C with R1 = 720 kΩ, rising with temperature; the start-up's pull-up MS3 adds about 40 nA. The 1.2 V supply reaches the pair only through M2's drain, one V_SG of M4 below it.", "relations": [ { "what": "Loop condition", "expr": "I_M2/I_M1 = K exp(−V_R1/U_T) = 1", "note": "weak inversion, both bulks on ground: the gate terms cancel and only the source term is left" }, { "what": "Output voltage", "expr": "V_R1 ≈ U_T ln K", "note": "71.7 mV at 27 °C for K = 16; 73.3 mV here, the pair's small drain dependence adding the rest" }, { "what": "Temperature slope", "expr": "dV_R1/dT = (k/q) ln K", "note": "239 µV/°C ideally; about 247 µV/°C here, with 0.38 °C nonlinearity from −40 to 125 °C" }, { "what": "Current", "expr": "I = U_T ln K / R1", "note": "R1 mainly sets current while both devices remain in weak inversion; its value and temperature coefficient can affect real-device departures" }, { "what": "Start-up release", "expr": "2 I_M1(V_g) > I_MS3", "note": "MS2 takes su away once M1 carries more than half of MS3's 37 nA; a 1.2 V MS2 let go at a trickle of a few nanoamps, where g already sits at 0.2 to 0.35 V, and the loop crawled out on its own for up to 165 µs" }, { "what": "Bulk tied to the source instead", "expr": "V_R1 = n U_T ln K", "note": "larger, but carrying n, which moves with process and temperature, and needing an isolated p-well" } ], "tradeoffs": [ "K (copies of the unit in M2): V_R1 and its slope grow as ln K; area grows as K.", "R1: a larger R1 lowers the current and deepens weak inversion, at the cost of a longer resistor; too small an R1 moves the pair towards the strong-inversion beta multiplier, whose voltage follows mobility.", "Wn and Ln (the NMOS unit, also MS2's): wider units run at a lower current density, deeper in weak inversion; the 3.3 V device is chosen because its drain dependence is small - 1.2 V devices would read 15 °C of error over the supply range.", "MS2 (two copies of M1's unit): matched to M1 it releases the start-up at a fixed fraction of M1's current at every corner, in 10 to 13 µs; smaller copies hold su against MS3 with too little margin, and lose it at cold corners.", "Wp and Lp (the mirror): longer devices copy more exactly across the different drain voltages of M3 and M4." ] }, "sizing": [ { "key": "Wn", "label": "W NMOS unit (M1, M2)", "unit": "m", "value": 0.00002, "min": 0.000001, "max": 0.00005, "kind": "si" }, { "key": "Ln", "label": "L NMOS unit", "unit": "m", "value": 0.000002, "min": 5e-7, "max": 0.00001, "kind": "si" }, { "key": "K", "label": "M2, copies of the unit", "unit": "", "value": 16, "min": 2, "max": 32, "kind": "int" }, { "key": "R", "label": "R1", "unit": "Ω", "value": 720000, "min": 100000, "max": 2000000, "kind": "si" }, { "key": "Wp", "label": "W PMOS (M3, M4)", "unit": "m", "value": 0.000001, "min": 3e-7, "max": 0.00001, "kind": "si" }, { "key": "Lp", "label": "L PMOS", "unit": "m", "value": 0.000008, "min": 5e-7, "max": 0.00002, "kind": "si" } ], "testbenches": [ { "id": "temp", "label": "Against temperature", "note": "The output from -40 to 125 °C at the typical supply: its slope, how far it strays from a straight line, and where that line reaches zero - at -273 °C for an output proportional to absolute temperature.", "measures": [], "metricKeys": [ "vout_27", "slope", "nonlin", "t_zero", "i_supply" ], "acceptance": [ "vout_27", "slope", "nonlin", "i_supply" ], "acceptanceRules": [ { "key": "vout_27", "unit": "V", "min": 0.068, "max": 0.079, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "slope", "unit": "µV/°C", "min": 230, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "nonlin", "unit": "°C", "min": null, "max": 1, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "i_supply", "unit": "A", "min": null, "max": 4e-7, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Self-biased PTAT generator - the output against temperature\n.include sg13g2_lv_tt.spice\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n.subckt ptatsb out vdd vss\n* the pair, 3.3 V devices: M1 diode-connected, M2 K copies with R1 in its source\nXM1 g g vss vss sg13_hv_nmos w=20u l=2u ng=4 m=1\nXM2 d g out vss sg13_hv_nmos w=20u l=2u ng=4 m=16\nXR1 out vss vss rhigh w=0.5u l=222.254u\n* the mirror: M4 takes M2's current, M3 copies it into M1\nXM4 d d vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1\nXM3 g d vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1\n* start-up: until M1 carries a fifth of its current MS2 (a copy of M1's 3.3 V\n* unit) is off, MS3 pulls su up and MS1 pulls d down into g; once the loop\n* runs MS2 holds su near ground\nXMS3 su vss vdd vdd sg13_hv_pmos w=300n l=40u ng=1 m=1\nXMS2 su g vss vss sg13_hv_nmos w=20u l=2u ng=4 m=2\nXMS1 d su g vss sg13_lv_nmos w=1u l=1u ng=1 m=1\n.ends\nXdut out vdd 0 ptatsb\n.dc temp -40 125 5\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc vout27 FIND v(out) AT=27\n.end" }, { "id": "line", "label": "Against the supply", "note": "The output over the rated supply, 1.08 to 1.32 V, and the temperature error that change would read as.", "measures": [], "metricKeys": [ "line_mv", "line_temp" ], "acceptance": [ "line_temp" ], "acceptanceRules": [ { "key": "line_temp", "unit": "°C", "min": null, "max": 4, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Self-biased PTAT generator - the output against the supply\n.include sg13g2_lv_tt.spice\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\n.subckt ptatsb out vdd vss\n* the pair, 3.3 V devices: M1 diode-connected, M2 K copies with R1 in its source\nXM1 g g vss vss sg13_hv_nmos w=20u l=2u ng=4 m=1\nXM2 d g out vss sg13_hv_nmos w=20u l=2u ng=4 m=16\nXR1 out vss vss rhigh w=0.5u l=222.254u\n* the mirror: M4 takes M2's current, M3 copies it into M1\nXM4 d d vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1\nXM3 g d vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1\n* start-up: until M1 carries a fifth of its current MS2 (a copy of M1's 3.3 V\n* unit) is off, MS3 pulls su up and MS1 pulls d down into g; once the loop\n* runs MS2 holds su near ground\nXMS3 su vss vdd vdd sg13_hv_pmos w=300n l=40u ng=1 m=1\nXMS2 su g vss vss sg13_hv_nmos w=20u l=2u ng=4 m=2\nXMS1 d su g vss sg13_lv_nmos w=1u l=1u ng=1 m=1\n.ends\nXdut out vdd 0 ptatsb\n.dc Vdd 1.08 1.32 0.01\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc vlo FIND v(out) AT=1.08\n.meas dc vhi FIND v(out) AT=1.32\n.end" }, { "id": "psrr", "label": "Supply rejection", "note": "A ripple on V_DD, and how much of it reaches the output, from 1 Hz to 1 GHz.", "measures": [], "metricKeys": [ "psrr_db" ], "acceptance": [ "psrr_db" ], "acceptanceRules": [ { "key": "psrr_db", "unit": "dB", "min": 30, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Self-biased PTAT generator - supply rejection\n.include sg13g2_lv_tt.spice\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD} ac 1\n.subckt ptatsb out vdd vss\n* the pair, 3.3 V devices: M1 diode-connected, M2 K copies with R1 in its source\nXM1 g g vss vss sg13_hv_nmos w=20u l=2u ng=4 m=1\nXM2 d g out vss sg13_hv_nmos w=20u l=2u ng=4 m=16\nXR1 out vss vss rhigh w=0.5u l=222.254u\n* the mirror: M4 takes M2's current, M3 copies it into M1\nXM4 d d vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1\nXM3 g d vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1\n* start-up: until M1 carries a fifth of its current MS2 (a copy of M1's 3.3 V\n* unit) is off, MS3 pulls su up and MS1 pulls d down into g; once the loop\n* runs MS2 holds su near ground\nXMS3 su vss vdd vdd sg13_hv_pmos w=300n l=40u ng=1 m=1\nXMS2 su g vss vss sg13_hv_nmos w=20u l=2u ng=4 m=2\nXMS1 d su g vss sg13_lv_nmos w=1u l=1u ng=1 m=1\n.ends\nXdut out vdd 0 ptatsb\n.ac dec 20 1 1g\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas ac vdb_1k FIND vdb(out) AT=1k\n.end" }, { "id": "startup", "label": "Power-up", "note": "The supply ramps from 0 to V_DD in 10.0 µs: how long the output takes to come within 1 % of its operating point, and whether it gets there.", "measures": [], "metricKeys": [ "t_start" ], "acceptance": [ "t_start" ], "acceptanceRules": [ { "key": "t_start", "unit": "s", "min": null, "max": 0.000025, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_hv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Self-biased PTAT generator - the supply ramping up from zero\n.include sg13g2_lv_tt.spice\n.include sg13g2_hv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 pwl(0 0 10u {VDD})\n.subckt ptatsb out vdd vss\n* the pair, 3.3 V devices: M1 diode-connected, M2 K copies with R1 in its source\nXM1 g g vss vss sg13_hv_nmos w=20u l=2u ng=4 m=1\nXM2 d g out vss sg13_hv_nmos w=20u l=2u ng=4 m=16\nXR1 out vss vss rhigh w=0.5u l=222.254u\n* the mirror: M4 takes M2's current, M3 copies it into M1\nXM4 d d vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1\nXM3 g d vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1\n* start-up: until M1 carries a fifth of its current MS2 (a copy of M1's 3.3 V\n* unit) is off, MS3 pulls su up and MS1 pulls d down into g; once the loop\n* runs MS2 holds su near ground\nXMS3 su vss vdd vdd sg13_hv_pmos w=300n l=40u ng=1 m=1\nXMS2 su g vss vss sg13_hv_nmos w=20u l=2u ng=4 m=2\nXMS1 d su g vss sg13_lv_nmos w=1u l=1u ng=1 m=1\n.ends\nXdut out vdd 0 ptatsb\n.tran 100n 200u\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas tran vend FIND v(out) AT=200u\n.end" } ], "measurements": { "vout_27": { "label": "Output at 27 °C", "unit": "V", "spec": { "min": 0.068, "max": 0.079 } }, "slope": { "label": "Temperature slope", "unit": "µV/°C", "spec": { "min": 230, "max": null } }, "nonlin": { "label": "Nonlinearity, -40 to 125 °C", "unit": "°C", "spec": { "min": null, "max": 1 } }, "line_temp": { "label": "Supply error, 1.08 to 1.32 V", "unit": "°C", "spec": { "min": null, "max": 4 } }, "i_supply": { "label": "Supply current at 27 °C", "unit": "A", "spec": { "min": null, "max": 4e-7 } }, "psrr_db": { "label": "Supply rejection at 1 kHz", "unit": "dB", "spec": { "min": 30, "max": null } }, "t_start": { "label": "Start-up time, to 1 %", "unit": "s", "spec": { "min": null, "max": 0.000025 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "199b4b809a09cd5cd0f8bfac57f91846fc62e6250e43444f7d2b5bcd3c6f5037" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/ptat-self-biased.js", "sha256": "a77efbacaa9f47f19c8927bad91017d2f73bd20b7e35d11de76ea7b0b811e403" }, "simulationFingerprints": { "temp": "1ac4ef21a607907865ce3c6ed84a6473a0efc917ca0d9c8db57be78633202b37", "line": "d69a0f9157d095a534071728c7b451f3ce03a0b49663a0bbc4077f62ad1d31ef", "psrr": "335441a234421f8fa7e9018bca02e786611fb56439fbab9c4bf2fc15a224b824", "startup": "7b09e828ab9c7fab3a7ec1e0fbbf5f52f14eefc6aa62309e492b79263c01fa6c" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "04f375aaa441ef55a7d9f1107f5e68a07cf5004d9b91b67221b3b0ef0e319cb9", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "ptat-self-biased", "parameters": { "Wn": 0.00002, "Ln": 0.000002, "K": 16, "R": 720000, "Wp": 0.000001, "Lp": 0.000008 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/ptat-self-biased/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "ptatsb", "ports": [ { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" } ], "definitions": [], "devices": [ { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM1 g g vss vss sg13_hv_nmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "g" }, { "id": "g", "net": "g" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=20u l=2u ng=4 m=16", "source": "XM2 d g out vss sg13_hv_nmos w=20u l=2u ng=4 m=16", "pins": [ { "id": "d", "net": "d" }, { "id": "g", "net": "g" }, { "id": "s", "net": "out" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=222.254u", "source": "XR1 out vss vss rhigh w=0.5u l=222.254u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=8u ng=1 m=1", "source": "XM4 d d vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1", "pins": [ { "id": "d", "net": "d" }, { "id": "g", "net": "d" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=8u ng=1 m=1", "source": "XM3 g d vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1", "pins": [ { "id": "d", "net": "g" }, { "id": "g", "net": "d" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS3", "displayName": "MS3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=300n l=40u ng=1 m=1", "source": "XMS3 su vss vdd vdd sg13_hv_pmos w=300n l=40u ng=1 m=1", "pins": [ { "id": "d", "net": "su" }, { "id": "g", "net": "vss" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS2", "displayName": "MS2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=20u l=2u ng=4 m=2", "source": "XMS2 su g vss vss sg13_hv_nmos w=20u l=2u ng=4 m=2", "pins": [ { "id": "d", "net": "su" }, { "id": "g", "net": "g" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS1", "displayName": "MS1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=1u ng=1 m=1", "source": "XMS1 d su g vss sg13_lv_nmos w=1u l=1u ng=1 m=1", "pins": [ { "id": "d", "net": "d" }, { "id": "g", "net": "su" }, { "id": "s", "net": "g" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" } ], "nets": [ { "id": "g", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM1", "pin": "g" }, { "device": "XM2", "pin": "g" }, { "device": "XM3", "pin": "d" }, { "device": "XMS2", "pin": "g" }, { "device": "XMS1", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM1", "pin": "s" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XR1", "pin": "n" }, { "device": "XR1", "pin": "substrate" }, { "device": "XMS3", "pin": "g" }, { "device": "XMS2", "pin": "s" }, { "device": "XMS2", "pin": "b" }, { "device": "XMS1", "pin": "b" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "d", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM4", "pin": "g" }, { "device": "XM3", "pin": "g" }, { "device": "XMS1", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM2", "pin": "s" }, { "device": "XR1", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XMS3", "pin": "s" }, { "device": "XMS3", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "su", "ground": false, "terminals": [ { "device": "XMS3", "pin": "d" }, { "device": "XMS2", "pin": "d" }, { "device": "XMS1", "pin": "g" } ], "ports": [], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ptatsb", "parametersOrValue": "", "source": "Xdut out vdd 0 ptatsb", "pins": [ { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ptatsb" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Xdut", "pin": "vss" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ptatsb", "name": "ptatsb", "ports": [ { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" } ], "definitions": [], "devices": [ { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=20u l=2u ng=4 m=1", "source": "XM1 g g vss vss sg13_hv_nmos w=20u l=2u ng=4 m=1", "pins": [ { "id": "d", "net": "g" }, { "id": "g", "net": "g" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=20u l=2u ng=4 m=16", "source": "XM2 d g out vss sg13_hv_nmos w=20u l=2u ng=4 m=16", "pins": [ { "id": "d", "net": "d" }, { "id": "g", "net": "g" }, { "id": "s", "net": "out" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XR1", "displayName": "R1", "spiceType": "X", "model": "rhigh", "parametersOrValue": "w=0.5u l=222.254u", "source": "XR1 out vss vss rhigh w=0.5u l=222.254u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" }, { "id": "substrate", "net": "vss" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=8u ng=1 m=1", "source": "XM4 d d vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1", "pins": [ { "id": "d", "net": "d" }, { "id": "g", "net": "d" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=8u ng=1 m=1", "source": "XM3 g d vdd vdd sg13_lv_pmos w=1u l=8u ng=1 m=1", "pins": [ { "id": "d", "net": "g" }, { "id": "g", "net": "d" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS3", "displayName": "MS3", "spiceType": "X", "model": "sg13_hv_pmos", "parametersOrValue": "w=300n l=40u ng=1 m=1", "source": "XMS3 su vss vdd vdd sg13_hv_pmos w=300n l=40u ng=1 m=1", "pins": [ { "id": "d", "net": "su" }, { "id": "g", "net": "vss" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS2", "displayName": "MS2", "spiceType": "X", "model": "sg13_hv_nmos", "parametersOrValue": "w=20u l=2u ng=4 m=2", "source": "XMS2 su g vss vss sg13_hv_nmos w=20u l=2u ng=4 m=2", "pins": [ { "id": "d", "net": "su" }, { "id": "g", "net": "g" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMS1", "displayName": "MS1", "spiceType": "X", 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