{
  "schema": "aisic.circuit/1",
  "entryType": "library-block",
  "domain": "analog",
  "id": "rc-lowpass",
  "name": "RC low-pass",
  "group": "Passives and trimming",
  "subgroup": "Filters",
  "title": "RC low-pass",
  "summary": "A resistor and capacitor pass slow changes and reduce fast ones. Their product sets the ideal cutoff frequency. The physical models show how parasitics and manufacturing variation move that cutoff; the tight implementation target applies only at the stated nominal condition.",
  "reference": {
    "kind": "book",
    "authors": "A. S. Sedra and K. C. Smith",
    "title": "Microelectronic Circuits",
    "edition": "7th ed.",
    "publisher": "Oxford University Press",
    "year": 2015,
    "where": "single-time-constant networks - the low-pass STC response",
    "takes": "The closed-form corner f = 1/(2*pi*R*C), which is what the measured corner is compared against."
  },
  "resources": {
    "record": "/circuits/rc-lowpass.json",
    "page": "/index.html#rc-lowpass",
    "achieved": "/achieved/rc-lowpass.json",
    "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.",
    "modelCards": [
      {
        "name": "sg13g2_passive_tt.spice",
        "url": "/sg13g2_passive_tt.spice",
        "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc"
      }
    ],
    "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.",
    "schema": "/schemas/circuit.schema.json"
  },
  "specificationPolicy": {
    "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.",
    "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.",
    "scopes": {
      "nominal": {
        "corner": "tt",
        "temp": 27,
        "vdd": 1,
        "temperatureUnit": "degC",
        "supplyMeaning": "scale of the bench's nominal supply"
      }
    },
    "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim."
  },
  "corners": {
    "cards": "a deck's sg13g2_<family>_tt.spice (family lv, hv, passive, hbt) becomes sg13g2_<family>_<corner>.spice",
    "process": [
      "tt",
      "ss",
      "ff",
      "sf",
      "fs"
    ],
    "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise",
    "temperatures": [
      -40,
      27,
      125
    ],
    "supplyScale": [
      0.9,
      1,
      1.1
    ],
    "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it",
    "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw",
    "sets": {
      "essential": [
        {
          "corner": "tt",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "ss",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "ff",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "sf",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "fs",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "tt",
          "temp": -40,
          "vdd": 1
        },
        {
          "corner": "tt",
          "temp": 125,
          "vdd": 1
        },
        {
          "corner": "tt",
          "temp": 27,
          "vdd": 0.9
        },
        {
          "corner": "tt",
          "temp": 27,
          "vdd": 1.1
        },
        {
          "corner": "ss",
          "temp": 125,
          "vdd": 0.9
        },
        {
          "corner": "ff",
          "temp": -40,
          "vdd": 1.1
        }
      ],
      "full": "all 45 combinations"
    },
    "montecarlo": {
      "cards": {
        "mc": "process and mismatch",
        "mcmm": "mismatch only",
        "mcproc": "process only"
      },
      "seed": "draw k adds .options seed=k, so draws are reproducible"
    }
  },
  "technology": {
    "id": "sg13g2",
    "name": "IHP SG13G2",
    "node": "130 nm",
    "corner": "tt",
    "vdd": 1.2,
    "lmin": 1.3e-7,
    "wmin": 1.5e-7,
    "models": "sg13g2_lv_tt.spice",
    "devices": {
      "nmos": "sg13_lv_nmos",
      "pmos": "sg13_lv_pmos",
      "resistor": "rppd, rhigh",
      "capacitor": "cap_cmim"
    },
    "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.",
    "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF."
  },
  "implementation": {
    "kind": "physical-device-reference",
    "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.",
    "evidence": "schematic-simulation",
    "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.",
    "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.",
    "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification."
  },
  "cards": [
    "sg13g2_passive_tt.spice"
  ],
  "ports": [
    {
      "name": "in",
      "kind": "input"
    },
    {
      "name": "out",
      "kind": "output"
    },
    {
      "name": "0",
      "kind": "ground"
    }
  ],
  "devices": [
    {
      "name": "R1",
      "type": "resistor",
      "nodes": "in out",
      "sizedBy": [
        "R"
      ],
      "role": "series element"
    },
    {
      "name": "C1",
      "type": "capacitor",
      "nodes": "out 0",
      "sizedBy": [
        "C"
      ],
      "role": "shunt element"
    }
  ],
  "intent": [
    {
      "rule": "closed-form",
      "of": [
        "R1",
        "C1"
      ],
      "constraint": "f_-3dB = 1/(2*pi*R*C)",
      "why": "The formula is the ideal nominal reference, checked at TT and 27 °C. The physical resistor and capacitor vary systematically with process and temperature as well as randomly with mismatch. Keep the simple untrimmed topology; characterize that spread instead of interpreting a nominal target as an all-condition guarantee."
    }
  ],
  "specs": [
    {
      "key": "f3db",
      "label": "Corner frequency",
      "unit": "Hz",
      "direction": "target"
    },
    {
      "key": "err",
      "label": "Nominal pole deviation",
      "unit": "%",
      "direction": "min",
      "constraint": "< 2 % at TT, 27 °C",
      "scope": "nominal",
      "why": "A nominal implementation check against 1/(2πRC), not an absolute-accuracy guarantee over PVT or mismatch. Other conditions retain their measured deviations as characterization; precision applications need process-appropriate trimming, calibration or another topology."
    }
  ],
  "explanation": {
    "idea": "This filter passes slow changes and reduces fast changes. The resistor limits how quickly the capacitor can charge, so the output changes more slowly than the input. Increasing either resistance or capacitance lowers the cutoff frequency.",
    "detail": "The capacitor's impedance falls as frequency rises, so the resistor and capacitor form a frequency-dependent voltage divider. The ideal response has one pole, approaches a 20 dB-per-decade roll-off and tends toward −90° phase. Physical passive models add variation and parasitics to that ideal response.",
    "lesson": {
      "relation": 1,
      "symbols": "f_c is cutoff frequency in hertz, R is resistance in ohms and C is capacitance in farads. At this frequency the ideal output amplitude is 1/√2 of its low-frequency value, about −3 dB.",
      "assumptions": "Ideal linear resistor and capacitor, negligible source resistance and negligible output loading. Physical-device parasitics and variation shift the measured cutoff.",
      "exercise": {
        "param": "C",
        "value": 3.183e-12,
        "analysis": "ac",
        "expect": "Doubling C should approximately halve the cutoff frequency. Compare the measured cutoff with the ideal formula."
      },
      "limits": "The <2% deviation target applies only at nominal TT, 27 °C and the bench conditions. PVT and Monte Carlo characterize variation; this untrimmed filter does not promise 2% accuracy across manufacturing."
    },
    "path": [
      {
        "part": "Series resistor",
        "devices": "R1",
        "does": "High-resistance poly, 100 kΩ by default, lets a current (v_in − v_out)/R into the output node, limiting how fast C1 can follow the input."
      },
      {
        "part": "Shunt capacitor",
        "devices": "C1",
        "does": "MIM capacitance, 1.5915 pF by default as two squares in parallel, integrates that current; its impedance 1/(ωC) falls with frequency, so fast signals are shorted to ground."
      }
    ],
    "bias": "No transistor bias is needed. The bench linearizes the physical passive models about the source's 0 V DC level; their parasitics and voltage/temperature coefficients are part of the small-signal response. The bench drives a 1 V AC source and sweeps three decades either side of the corner.",
    "relations": [
      {
        "what": "Transfer",
        "expr": "H(jω) = 1/(1 + jω·R·C)",
        "note": "a divider of R and the capacitor's impedance 1/(jωC)"
      },
      {
        "what": "Corner",
        "expr": "f_c = 1/(2π·R·C)",
        "note": "where |H| = 1/√2 (−3 dB) and the phase is −45°: 1 MHz at the defaults"
      },
      {
        "what": "Roll-off",
        "expr": "|H| ≈ f_c/f for f ≫ f_c",
        "note": "20 dB per decade, the phase approaching −90°"
      },
      {
        "what": "Time constant",
        "expr": "τ = R·C",
        "note": "159 ns at the defaults; an ideal step response reaches 63 % of its final change after one time constant"
      },
      {
        "what": "Output noise",
        "expr": "v_n^2 = kT/C",
        "note": "R's thermal noise integrated over the pole: independent of R"
      }
    ],
    "tradeoffs": [
      "R: raising it lowers the corner without more capacitor area, but adds poly length and noise density 4kTR; the integrated noise stays kT/C.",
      "C: raising it lowers both the corner and the integrated noise kT/C, but the MIM area grows in proportion.",
      "R and C: scaling R up and C down together keeps the corner but raises the output impedance and the integrated noise kT/C.",
      "Process portability: retain the RC relation and loading/noise intent, then choose practical resistor geometry and capacitor area from the new process. Recheck sheet-resistance spread, capacitance density, voltage and temperature coefficients, parasitics and matching; copying these dimensions does not preserve the corner.",
      "Absolute accuracy: increasing device area can reduce mismatch but does not cancel systematic process spread. A precision absolute pole needs trimming, calibration or compensation, which would be a separate design with its own area and power costs."
    ]
  },
  "sizing": [
    {
      "key": "R",
      "label": "R",
      "unit": "Ω",
      "value": 100000,
      "min": 1000,
      "max": 1000000,
      "kind": "si"
    },
    {
      "key": "C",
      "label": "C",
      "unit": "F",
      "value": 1.5915e-12,
      "min": 1e-14,
      "max": 2e-11,
      "kind": "si"
    }
  ],
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    {
      "id": "ac",
      "label": "Frequency response",
      "note": "<2% is a nominal TT, 27 °C implementation target. PVT and Monte Carlo show physical pole variation, not yield against this nominal target.",
      "measures": [
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        "err"
      ],
      "metricKeys": [
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        "err"
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          "unit": "%",
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          "classification": "nominal-simulation-target",
          "conditions": {
            "corner": "tt",
            "temp": 27,
            "vdd": 1
          },
          "outsideScope": "characterization; the measurement must still be present, unique and finite"
        }
      ],
      "cards": [
        "sg13g2_passive_tt.spice"
      ],
      "netlist": "* RC low-pass - one pole, in closed form\n.include sg13g2_passive_tt.spice\nV1 in 0 dc 0 ac 1\nXR1 in out 0 rhigh w=0.5u l=30.784u\nXC1 out 0 cap_cmim w=22.979u l=22.979u m=2\n.ac dec 40 1.00003k 1.00003g\n* Measured by this deck, so a local ngspice run reports the same figures:\n* A passive divider starts at 0 dB, so -3 dB is an absolute level here and\n* the corner can be measured in the deck. An amplifier's corner sits 3 dB\n* below ITS gain, which .meas cannot take as a threshold.\n.meas ac f3db WHEN vdb(out)=-3 FALL=1\n.end"
    }
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            "url": "/circuits/rc-lowpass/ac-schematic.svg",
            "asset": "ac-schematic.svg"
          },
          "drawingCheck": {
            "method": "checkSchematic",
            "problems": []
          },
          "sheets": [
            {
              "name": "RC low-pass",
              "instances": []
            }
          ]
        },
        "benchDiagram": {
          "graph": "graph-2",
          "svg": {
            "url": "/circuits/rc-lowpass/ac-bench.svg",
            "asset": "ac-bench.svg"
          }
        },
        "blockDiagram": {
          "graph": "graph-3",
          "electricalGraph": "graph-1",
          "svg": {
            "url": "/circuits/rc-lowpass/ac-block.svg",
            "asset": "ac-block.svg"
          }
        }
      }
    ]
  }
}