{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "sample-hold", "name": "Sample and hold", "group": "Switches and sampling", "subgroup": "Sample and hold", "title": "Sample and hold", "summary": "This circuit captures a voltage on a capacitor. While the switch is on, the capacitor follows the input; when the switch opens, it holds the sample. A larger capacitor reduces noise and switching error but takes longer to charge.", "reference": { "kind": "book", "authors": "B. Razavi", "title": "Design of Analog CMOS Integrated Circuits", "edition": "2nd ed.", "publisher": "McGraw-Hill", "year": 2017, "where": "Switched-Capacitor Circuits - the MOS sampling switch, charge injection and clock feedthrough", "takes": "The two non-idealities this bench measures, and the transmission gate as the standard answer to the first of them." }, "resources": { "record": "/circuits/sample-hold.json", "page": "/index.html#sample-hold", "achieved": "/achieved/sample-hold.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "in", "kind": "input" }, { "name": "out", "kind": "output", "note": "the hold node" }, { "name": "clk", "kind": "clock", "note": "high tracks, low holds; the clock high level is supplied externally" }, { "name": "clkb", "kind": "clock", "note": "transmission-gate option only: externally supplied complement of clk for M2; no inverter is included in the core" }, { "name": "vdd", "kind": "supply", "note": "PMOS well connection in the transmission-gate option only; the clock high level is supplied externally, not generated by this pin" }, { "name": "0", "kind": "ground", "note": "NMOS substrate and hold-capacitor return" } ], "devices": [ { "name": "M1", "type": "nmos", "nodes": "in clk out 0", "sizedBy": [ "W", "L" ], "role": "sampling switch", "fingers": 1, "copies": 1 }, { "name": "M2", "type": "pmos", "nodes": "in clkb out vdd", "sizedBy": [ "Wp", "L" ], "role": "switch complement, transmission-gate option only" }, { "name": "Ch", "type": "capacitor", "nodes": "out 0", "sizedBy": [ "Ch" ], "role": "hold capacitor" } ], "intent": [ { "rule": "conduction-range", "of": [ "M1" ], "constraint": "an NMOS stops conducting within V_th of the supply", "why": "This is the reason a transmission gate exists. With an NMOS alone the tracking error runs away at the top of the input range; the PMOS takes over exactly where the NMOS gives up." }, { "rule": "trade", "of": [ "M1", "Ch" ], "constraint": "pedestal ~ W*L*C_ox*V / (2*C_h)", "why": "Charge injection scales with switch area and inversely with the hold capacitor, so it cannot be fixed by making the switch faster - only by making it smaller or the capacitor bigger, and both cost you elsewhere." }, { "rule": "trade", "of": [ "Ch" ], "constraint": "kT/C noise against acquisition time", "why": "A bigger hold capacitor cuts sampling noise and the pedestal, and lengthens acquisition through the switch's on-resistance. That is the whole sizing problem for a sampler." } ], "specs": [ { "key": "tacq", "label": "Acquisition time", "unit": "s", "direction": "min" }, { "key": "err", "label": "Tracking error", "unit": "V", "direction": "min" }, { "key": "pedestal", "label": "Hold pedestal", "unit": "V", "direction": "min" }, { "key": "droop", "label": "Droop", "unit": "V", "direction": "min" } ], "explanation": { "idea": "This circuit captures a voltage on a capacitor. While the switch is on, the capacitor follows the input; when the switch opens, it holds the sample. A larger capacitor reduces noise and switching error but takes longer to charge.", "detail": "Takes a snapshot of a voltage: while clk is high the switch M1 joins the input to the hold capacitor Ch, which follows it through the switch's on-resistance, and when clk falls Ch keeps the last value. Opening is not clean: part of the channel charge, and the clock step coupled through the gate overlap, land on Ch as a pedestal. An NMOS alone loses strong conduction within a threshold of V_DD; the transmission-gate option adds M2, on clkb, to improve tracking at the top of the range. Leakage and the following stage can change the held voltage.", "lesson": { "relation": 1, "symbols": "τ is the tracking time constant; R_on is the switch on-resistance at the input level; C_h is the hold capacitance.", "assumptions": "The simple RC estimate assumes nearly constant switch resistance, a low-impedance input source and negligible additional load capacitance. Several time constants are needed for accurate acquisition.", "exercise": { "param": "Ch", "value": 4e-13, "analysis": "tran", "expect": "Doubling the hold capacitance should slow acquisition and reduce the voltage step when the switch opens. Compare acquisition time and hold pedestal; the theoretical noise reduction is not measured by this transient." }, "limits": "The clock and input source are ideal in the bench. The transmission-gate option needs an external complementary clock and PMOS well supply. Real input resistance, clock skew, leakage and the following stage change settling and hold accuracy; changing controls is not new qualification. Acquisition is timed from the clock reaching full high until it starts falling, and requires remaining within 1 mV over the rest of that tracking interval; a later crossing in hold is not acquisition." }, "path": [ { "part": "Track", "devices": "M1, M2, Ch", "does": "With clk high, M1 (and M2 on clkb, if chosen) conducts; Ch charges towards v_in with τ = R_on·C_h, and the bench counts acquisition to within 1 mV." }, { "part": "Turn-off", "devices": "M1, M2", "does": "As clk falls the channel empties: about half its charge lands on Ch, and the gate overlap couples the clock step in, a pedestal negative for the NMOS." }, { "part": "Hold", "devices": "Ch", "does": "With the switch off, Ch keeps the sample; leakage through the off switch and its junctions droops it at I_leak/C_h." } ], "bias": "Nothing is biased: the clock, 0 to 1.2 V, rising at 1 ns and falling about 5 ns later, is the switch's gate drive, and V_in (0.4 V by default) comes from an ideal source. The gate overdrive V_DD − V_in − V_th therefore sets the NMOS's R_on and channel charge. Ground is the hold-capacitor and NMOS-body return. The transmission-gate option also needs an externally supplied clkb complement and vdd for the PMOS well; no on-core clock inverter is included.", "relations": [ { "what": "On-resistance", "expr": "R_on ≈ 1/(µ_n·C_ox·(W/L)·(V_DD − V_in − V_th))", "note": "grows without bound as V_in nears V_DD − V_th; M2 covers that end" }, { "what": "Tracking", "expr": "τ = R_on·C_h", "note": "the bench starts Ch at 0 V and counts acquisition to within 1 mV of V_in" }, { "what": "Charge-injection pedestal", "expr": "ΔV ≈ −W·L·C_ox·(V_DD − V_in − V_th)/(2·C_h)", "note": "about half of M1's channel charge; M2's holes, in the transmission gate, partly cancel it" }, { "what": "Clock feedthrough", "expr": "ΔV ≈ −V_DD·C_ov/(C_ov + C_h)", "note": "the gate–source overlap couples the falling clock onto Ch" }, { "what": "Sampled noise", "expr": "v_n^2 = kT/C_h", "note": "independent of R_on: the noise power halves only when C_h doubles" } ], "tradeoffs": [ "C_hold: a larger capacitor cuts kT/C noise, the pedestal and droop, but lengthens acquisition through the same R_on.", "W NMOS: a wider switch lowers R_on and acquisition time, but injects more channel charge and couples more clock, so the pedestal grows in proportion.", "L: a longer switch only adds R_on and channel charge; minimum length gives the best speed for a given pedestal.", "Switch: the transmission gate tracks up to V_DD, M2 taking over where M1 cuts off, and its opposite charge partly cancels M1's; it needs clkb." ] }, "sizing": [ { "key": "sw", "label": "Switch", "unit": "", "value": "nmos", "kind": "choice", "choices": [ [ "nmos", "NMOS only" ], [ "tg", "Transmission gate" ] ] }, { "key": "W", "label": "W NMOS", "unit": "m", "value": 0.000004, "min": 1.5e-7, "max": 0.00005, "kind": "si" }, { "key": "Wp", "label": "W PMOS", "unit": "m", "value": 0.000008, "min": 1.5e-7, "max": 0.0001, "kind": "si" }, { "key": "L", "label": "L", "unit": "m", "value": 1.3e-7, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "Ch", "label": "C_hold", "unit": "F", "value": 2e-13, "min": 1e-14, "max": 1e-11, "kind": "si" }, { "key": "Vin", "label": "V_in", "unit": "V", "value": 0.4, "min": 0.05, "max": 1.15, "kind": "si" } ], "testbenches": [ { "id": "tran", "label": "One sample", "note": "", "measures": [ "tacq", "err", "pedestal", "droop" ], "metricKeys": [ "tacq", "vtrack", "err", "pedestal", "droop" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Sample and hold - NMOS switch\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n* the supply, which the clock - the switch's gate drive - swings to\n.param VDD=1.2\nVdd vdd 0 {VDD}\nVin in 0 400m\n* track while the clock is high, hold when it falls\nVclk clk 0 pulse(0 {VDD} 1n 100p 100p 5n 80n)\nXM1 in clk out 0 sg13_lv_nmos w=4u l=130n ng=1 m=1\nXCh out 0 cap_cmim w=11.494u l=11.494u\n.ic v(out)=0\n.tran 10p 20n uic\n.end" }, { "id": "sweep", "label": "Across the input range", "note": "Eleven runs.", "measures": [ "err", "pedestal", "tacq" ], "metricKeys": [ "err_max", "ped_max", "vin_max" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Sample and hold - NMOS switch\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n* the supply, which the clock - the switch's gate drive - swings to\n.param VDD=1.2\nVdd vdd 0 {VDD}\nVin in 0 600m\n* track while the clock is high, hold when it falls\nVclk clk 0 pulse(0 {VDD} 1n 100p 100p 5n 80n)\nXM1 in clk out 0 sg13_lv_nmos w=4u l=130n ng=1 m=1\nXCh out 0 cap_cmim w=11.494u l=11.494u\n.ic v(out)=0\n.tran 10p 20n uic\n.end" } ], "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "7bb3c438bddeaf73ff6efb824ef37eae7fd7ea3f288c5176ae0d85ac7bf26428" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/sample-hold.js", "sha256": "d7c46827ee281aa72bd10dc2915456780dab9446262e8839cf882bebaf58a88b" }, "simulationFingerprints": { "tran": "94de0e96c394ffa86765e3608cb1292270183f422528bef4ebde5f9312333bff", "sweep": "ad0d7588eb00acbc2eb4368867b742ebaa60cf0091300cffaa059ae657cad352" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "4e642ec54ce33c251bc0549121e595cc6eb0099e40bc5d53bb0144d7eba0188d", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "sample-hold", "parameters": { "sw": "nmos", "W": 0.000004, "Wp": 0.000008, "L": 1.3e-7, "Ch": 2e-13, "Vin": 0.4 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [ { "key": "sw", "selected": "nmos", "choices": [ { "value": "nmos", "label": "NMOS only" }, { "value": "tg", "label": "Transmission gate" } ] } ], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/sample-hold/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "top", "ports": [ { "name": "in", "net": "in", "kind": "input" }, { "name": "clk", "net": "clk", "kind": "clock" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "gnd", "net": "0", "kind": "ground" } ], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XM1 in clk out 0 sg13_lv_nmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "in" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "out" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCh", "displayName": "Ch", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XCh out 0 cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "in", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" } ], "ports": [ "in" ], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM1", "pin": "s" }, { "device": "XCh", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "XM1", "pin": "b" }, { "device": "XCh", "pin": "n" } ], "ports": [ "gnd" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "{VDD}", "source": "Vdd vdd 0 {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "400m", "source": "Vin in 0 400m", "pins": [ { "id": "p", "net": "in" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclk", "displayName": "Vclk", "spiceType": "V", "model": null, "parametersOrValue": "pulse(0 {VDD} 1n 100p 100p 5n 80n)", "source": "Vclk clk 0 pulse(0 {VDD} 1n 100p 100p 5n 80n)", "pins": [ { "id": "p", "net": "clk" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XM1 in clk out 0 sg13_lv_nmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "in" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "out" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCh", "displayName": "Ch", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=11.494u l=11.494u", "source": "XCh out 0 cap_cmim w=11.494u l=11.494u", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vin", "pin": "n" }, { "device": "Vclk", "pin": "n" }, { "device": "XM1", "pin": "b" }, { "device": "XCh", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "in", "ground": false, "terminals": [ { "device": "Vin", "pin": "p" }, { "device": "XM1", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "Vclk", "pin": "p" }, { "device": "XM1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM1", "pin": "s" }, { "device": "XCh", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "top-level-device-set", "scope": "top", "devices": [ "XM1", "XCh" ] } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Sampling switch", "devices": [ { "scope": "dut", "device": "XM1" } ], "inferredStages": [ 1 ] }, { "id": "block-2", "label": "Hold capacitor", "devices": [ { "scope": "dut", "device": "XCh" } ], "inferredStages": [ "bias" ] } ], "edges": [ { "id": "net-1", "net": "out", "nodes": [ "block-1", "block-2" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "in", "net": "in", "kind": "input" }, { "name": "clk", "net": "clk", "kind": "clock" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "gnd", "net": "0", "kind": "ground" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. 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