{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "mixed-signal", "id": "sar-adc", "name": "SAR ADC", "group": "Data converters", "subgroup": "ADCs", "title": "SAR ADC", "summary": "This ADC converts a sampled voltage into a binary number. A capacitor DAC tries one bit at a time, and a comparator keeps or clears each trial. More bits give finer voltage steps but require more clock cycles and better matching.", "reference": { "kind": "paper", "authors": "J. L. McCreary and P. R. Gray", "title": "All-MOS charge redistribution analog-to-digital conversion techniques - Part I", "publisher": "IEEE Journal of Solid-State Circuits, vol. SC-10, no. 6", "year": 1975, "where": "the binary-weighted charge-redistribution array and its sample / redistribute sequence", "takes": "The array, its sample-then-redistribute sequence, and the charge-conservation result every trial is checked against: v(top) = V_cm - V_in + V_ref*code/2^N." }, "resources": { "record": "/circuits/sar-adc.json", "page": "/index.html#sar-adc", "achieved": "/achieved/sar-adc.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" }, { "name": "sg13g2_stdcell.spice", "url": "/sg13g2_stdcell.spice", "sha256": "cfd805c964d3238b3342b5b1432522c3cf614d167b848d540a1499d1253ef3d4" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice", "sg13g2_stdcell.spice" ], "ports": [ { "name": "vin", "kind": "input", "note": "the input, sampled onto the bottom plates" }, { "name": "vcm", "kind": "bias", "note": "the top plate's level while sampling, and the comparator's reference" }, { "name": "vref", "kind": "bias", "note": "what the bit drivers switch the bottom plates to: the full scale" }, { "name": "ib", "kind": "bias", "note": "20 uA into the preamplifier's bias mirror" }, { "name": "clk", "kind": "clock", "note": "high: the comparator precharges; each rising edge ends a trial" }, { "name": "samp", "kind": "clock", "note": "high: track the input; its falling edge samples it" }, { "name": "d0..dN-1", "kind": "output", "note": "the result, valid once eoc rises" }, { "name": "eoc", "kind": "output", "note": "end of conversion" }, { "name": "vdd", "kind": "supply" } ], "devices": [ { "name": "C0..CN-1", "type": "capacitor", "sizedBy": [ "Cu", "bits", "mismatch", "seed" ], "role": "binary-weighted MIM array, C_k = 2^k * C_u" }, { "name": "Ct", "type": "capacitor", "sizedBy": [ "Cu" ], "role": "termination, making the total 2^N * C_u" }, { "name": "St", "type": "switch", "sizedBy": [ "Wsw" ], "role": "top plate onto vcm while sampling; opens first (transmission gate)" }, { "name": "Si0..SiN-1", "type": "switch", "sizedBy": [ "Wsw" ], "role": "each bottom plate onto vin while sampling" }, { "name": "Sd0..SdN-1", "type": "switch", "sizedBy": [ "Wsw" ], "role": "each bottom plate onto its bit driver while converting; wider for a bigger capacitor" }, { "name": "Sit", "type": "switch", "sizedBy": [ "Wsw" ], "role": "the termination's bottom plate onto vin while sampling, Sgt to ground after" }, { "name": "B0..BN-1", "type": "logic", "role": "bit drivers, supplied from vref, their drive scaled with the capacitor: buf_1 up to four unit cells, buf_2 at eight, then an inv_2 into one inv_4 per sixteen" }, { "name": "P1", "type": "nmos", "role": "preamplifier pair (with P2), 16/1 um, loaded by R1..R4", "fingers": 4, "copies": 1 }, { "name": "R1..R4", "type": "resistor", "role": "the preamplifier's loads, 15 kOhm p+ poly units, two in series a side: R1 and R3 on pn, R2 and R4 on pp" }, { "name": "Pbt", "type": "nmos", "role": "preamplifier tail, 20 uA mirrored from Pbd and pin ib", "fingers": 2, "copies": 1 }, { "name": "M1..M10", "type": "nmos", "role": "StrongARM latch: input pair M1-M2, cross-coupled M3-M6, precharge M7-M10, clocked tail Mt" }, { "name": "Ls", "type": "logic", "role": "NOR latch (with Lr) holding the decision, behind the buffers Ikn and Ikp" }, { "name": "T0..TN-1", "type": "logic", "role": "the token chain: flip-flops passing one bit's turn down the register" }, { "name": "F0..FN-1", "type": "logic", "role": "the bit registers: flip-flops loading the decision through the muxes K0..KN-1; the ORs O0..ON-1 put a bit on the array during its trial" } ], "intent": [ { "rule": "bottom-plate-sampling", "of": [ "St", "Si0..SiN-1" ], "constraint": "the top plate is let go two gate delays before the bottom plates", "why": "With the top plate already floating, the charge on it is fixed; the bottom-plate switches that open after it inject their channel charge into nodes the drivers are about to drive, so it never reaches the top plate. Opened together, that charge depends on the input and becomes a gain error." }, { "rule": "msb-first", "of": [ "T0..TN-1", "F0..FN-1" ], "constraint": "the MSB's token and register are set while sampling", "why": "The MSB trial is already on the array when the bottom plates leave vin. The ideal top-plate level is V_cm + V_ref/2 - V_in; top-plate parasitics attenuate its displacement from V_cm, and switching adds transient errors. With the stated input range and common-mode constraint, this preset avoids the large negative excursion of an all-zero start, whose ideal level is V_cm - V_in. A sufficiently negative plate turns the top-plate switch's NMOS back on and drains sampled charge: 300 fC, thirteen LSBs, at a 1.2 V input in the all-zero-start probe, which converted to 51 instead of 63." }, { "rule": "top-plate-in-rails", "of": [ "vcm" ], "constraint": "V_ref/2 <= V_cm <= V_DD - V_ref/2", "why": "Every trial leaves the top plate within V_ref/2 of V_cm; far enough outside the rails the top-plate switch conducts, as above. While the plates switch it overshoots a little further - at 6 bits to -2 mV at a 1.2 V input and 1.21 V at 0 V, at 8 bits to -22 mV and 1.32 V - well short of the threshold at which either half of the switch turns back on. The switches' gates are driven hard for that: on a slow sampling edge the MSB's plate moves while the others are still loosely held." }, { "rule": "precharge-while-sampling", "of": [ "M1..M10" ], "constraint": "clk is high (precharge) while samp is", "why": "The top plate is sampled with the comparator in the state it is in before every decision, so the gate charge on the top plate is the same at sampling as at each comparison. Behind the preamplifier the latch's state hardly reaches the top plate - sampling it decided moves no trial by 0.1 mV - but with the latch on the top plate directly, the decided state shifts every trial by 7 mV." }, { "rule": "kickback-isolation", "of": [ "P1", "M1..M10" ], "constraint": "a preamplifier between the top plate and the latch", "why": "The latch's regeneration kicks charge back into its inputs. On V_cm, a stiff reference, that does nothing; on the floating top plate it moves the top plate 7-23 mV just as the decision is made, and a 1.06 V input converts to 57 instead of 56. The preamplifier's resistive outputs take the kick, both alike; about 5 mV of it still reaches the top plate as the latch fires, and moves the code transitions by under 1 mV." }, { "rule": "symmetric-latch-load", "of": [ "Ls" ], "constraint": "outp and outn each drive one identical inverter", "why": "A NAND latch on them directly loads the two sides differently depending on what it holds, and the comparator favours its previous answer by 1.3 mV, even behind the preamplifier - a quarter of an LSB at 8 bits. With the inverters it stays within 0.1 mV." }, { "rule": "driver-scaling", "of": [ "B0..BN-1", "Sd0..SdN-1" ], "constraint": "drive and switch width in proportion to the capacitor: one time constant for every bit", "why": "Each bottom plate must settle to a fraction of an LSB in the half clock before its decision, and the plates must move together. Put every bit of an 8-bit array on the same buf_2 and switch and neither holds: the MSB trial is decided 25 mV (5 LSB) short of where it settles, so 0.3 V converts to 63 instead of 64, and at full scale the small plates, falling before the MSB's rises, drag the top plate to -0.40 V, where the top-plate switch starts to leak. At the default 6 bits the same drivers still settle, and their -0.25 V dip leaks nothing: the scaling is what lets the resolution go up." }, { "rule": "comparator-offset", "of": [ "P1", "R1..R4", "M1..M10" ], "constraint": "offset sigma about 2 mV: a tenth of an LSB at 6 bits", "why": "The comparator's offset moves every code boundary alike - an offset error, not DNL - but by a different amount on every die, and an input closer than that to a boundary converts to the next code. With 4/0.5 um inputs and 20 kOhm loads of high-resistance poly its sigma was 5.2 mV - 3.7 mV from the pair, 2.5 mV from the loads, 2.7 mV from the latch behind a gain of 2.8 - and 0.758 V, 8 mV above a boundary, converted to 39 in 3 of 20 Monte Carlo draws. With 16/1 um inputs, p+ poly loads and a gain of 5 it is 2.0 mV (1.3, 0.2 and 1.8 mV), and all 20 draws give 40. The array adds 0.2 mV." }, { "rule": "matching-limited", "of": [ "C0..CN-1" ], "constraint": "resolution is set by unit-capacitor matching", "why": "The comparator only ever answers yes or no, so every code boundary is a capacitor ratio, shifted by the comparator's offset alike. The array's DNL and INL under mismatch are on the charge-redistribution DAC page." } ], "specs": [ { "key": "bits", "label": "Resolution", "unit": "bit", "direction": "max" }, { "key": "error", "label": "Quantisation error", "unit": "V", "direction": "min", "constraint": "within 1 LSB" }, { "key": "tconv", "label": "Nominal conversion interval", "unit": "s", "direction": "min", "constraint": "N clock cycles after sampling; calculated, not a measured EOC delay" }, { "key": "energy", "label": "Energy per conversion", "unit": "J", "direction": "min" } ], "explanation": { "idea": "This ADC converts a sampled voltage into a binary number. A capacitor DAC tries one bit at a time, and a comparator keeps or clears each trial. More bits give finer voltage steps but require more clock cycles and better matching.", "detail": "Converts one sampled voltage into an N-bit code by binary search, one comparison per clock. The input is stored as charge on a binary-weighted capacitor array whose common top plate is then left floating. Moving the bottom plates between ground and V_ref redistributes that charge. Ideally, the top plate lands at V_cm − V_in + V_ref·code/2^N; top-plate parasitics reduce the excursion from V_cm. The comparator asks whether that is below V_cm, meaning the trial code is still below the input, and the register keeps or drops each bit, most significant bit first.", "lesson": { "relation": 1, "symbols": "LSB is one ideal code step in volts; V_ref is the reference voltage; N is the number of bits.", "assumptions": "The LSB relation describes an ideal binary DAC with settled, matched capacitor ratios. It does not include comparator offset, parasitic gain error or incomplete settling.", "exercise": { "param": "bits", "value": 7, "analysis": "convert", "expect": "The ideal voltage step halves and the scheduled conversion needs one more clock cycle. Compare the reported error in volts and in LSB; finer nominal resolution does not guarantee better accuracy." }, "limits": "Supply bias, V_ref, V_cm, sampling and conversion clocks externally. This bench converts one input value; it does not establish full-code linearity, physical noise or maximum sample rate. Recheck timing and matching after changing the resolution." }, "path": [ { "part": "Sample", "devices": "St, Si0..SiN-1, Sit", "does": "While samp is high, St holds the top plate at V_cm and every bottom plate sits on V_in; St opens two gate delays before the others (bottom-plate sampling)." }, { "part": "MSB trial", "devices": "Sd0..SdN-1, B0..BN-1, Sgt", "does": "The bottom plates leave V_in for their drivers, Ct's for ground. With the MSB preset, an ideal array puts the top plate at V_cm + V_ref/2 − V_in. Physical top-plate capacitance attenuates its displacement from V_cm; switching adds further error." }, { "part": "Compare", "devices": "P1, P2, R1..R4, Mt, M1..M10, Ls, Lr", "does": "While clk is low, the preamplifier, a gain of about 5, and the StrongARM latch decide whether V_cm is above the top plate, meaning keep the bit; the NOR latch holds the answer." }, { "part": "Register", "devices": "T0..TN-1, K0..KN-1, F0..FN-1, O0..ON-1", "does": "Each rising clk edge stores the decision in that bit's flip-flop and passes the token down; the OR gates put the next trial on the array beside the kept bits." }, { "part": "End of conversion", "devices": "Tend", "does": "N rising edges after sampling the token reaches Tend and eoc rises; the top plate then sits within one LSB below V_cm, and d0..dN-1 hold the code." } ], "bias": "Pbt mirrors into the preamplifier's tail the 20 µA the bench drives into pin ib through Pbd; each input device takes 10 µA through 30 kΩ of p+ poly, R1 and R3 or R2 and R4, which holds the latch's inputs near 0.9 V. The latch draws charge only as it decides. V_ref sets the full scale and supplies the bit drivers, V_cm is both the top plate's sampling level and the comparator's reference, and samp and clk, 100 MHz by default, set the timing.", "relations": [ { "what": "Top plate in each trial", "expr": "v_top ≈ V_cm + α·(V_ref·code/2^N − V_in)", "note": "α is the array capacitance divided by total top-plate capacitance, about 0.94 here; α = 1 gives the ideal equation. Charge injection and comparator kickback add further errors. A trial bit is kept when v_top < V_cm." }, { "what": "LSB", "expr": "LSB = V_ref/2^N", "note": "18.75 mV with V_ref = 1.2 V at 6 bits; the selected conversion is checked against the published ±1 LSB requirement. This single input point does not establish full-code ADC linearity." }, { "what": "Conversion time", "expr": "t_conv = N·T_clk", "note": "nominal timing calculation: one trial per clock after sampling, 60 ns at 6 bits and 100 MHz; this number is not a measured EOC delay" }, { "what": "Bottom-plate settling", "expr": "T_clk/2 ≥ τ·ln(2^(N+1))", "note": "settle to half an LSB before the latch fires; drivers and switches scale with C_k so τ is shared" }, { "what": "Comparator offset", "expr": "σ_os^2 ≈ σ_P^2 + σ_R^2 + (σ_L/A_p)^2", "note": "The preamplifier pair, loads and latch contribute input-referred mismatch; their uncorrelated variances add approximately. Comparator offset shifts code boundaries. The ideal sampled rms noise √[kT/(2^N·C_u)] is about 57 µV at the defaults; this is a calculation, not a transient-noise measurement." } ], "tradeoffs": [ "Resolution: each extra bit halves the LSB, doubles the array and its switching energy, adds a clock cycle, and asks more of the capacitor matching.", "C_unit: a larger unit lowers kT/C noise but raises the energy per conversion and slows each bit's settling through the same drivers.", "Clock: faster shortens the N-cycle conversion, but each half period must still settle the bottom plates and let the latch resolve the closest trial.", "Switch nMOS width: wider switches track and settle faster but add channel charge and capacitance; bottom-plate sampling leaves only St's input-independent charge, an offset." ] }, "sizing": [ { "key": "bits", "label": "Resolution", "unit": "bit", "value": 6, "min": 3, "max": 8, "kind": "int" }, { "key": "Cu", "label": "C_unit", "unit": "F", "value": 2e-14, "min": 1e-14, "max": 1e-13, "kind": "si" }, { "key": "mismatch", "label": "Unit-cap σ", "unit": "%", "value": 0, "min": 0, "max": 10, "kind": "si" }, { "key": "seed", "label": "Mismatch seed", "unit": "", "value": 1, "min": 1, "max": 999, "kind": "int" }, { "key": "vref", "label": "V_ref", "unit": "V", "value": 1.2, "min": 0.8, "max": 1.2, "kind": "si" }, { "key": "vcm", "label": "V_cm", "unit": "V", "value": 0.6, "min": 0.4, "max": 0.8, "kind": "si" }, { "key": "vin", "label": "V_in", "unit": "V", "value": 0.758, "min": 0, "max": 1.2, "kind": "si" }, { "key": "fclk", "label": "Clock", "unit": "Hz", "value": 100000000, "min": 20000000, "max": 200000000, "kind": "si" }, { "key": "Wsw", "label": "Switch nMOS width", "unit": "m", "value": 0.000004, "min": 1.5e-7, "max": 0.00002, "kind": "si" } ], "testbenches": [ { "id": "convert", "label": "Conversion", "note": "One conversion with every device simulated: about 10 s in the browser.", "measures": [ "error", "tconv", "energy" ], "metricKeys": [ "code", "error", "error_lsb", "tconv", "energy", "closest" ], "acceptance": [ "error_lsb" ], "acceptanceRules": [ { "key": "error_lsb", "unit": "LSB", "min": -1, "max": 1, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice", "sg13g2_stdcell.spice" ], "netlist": "* 6-bit SAR ADC, transistor level: one conversion of 758mV\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.include sg13g2_stdcell.spice\n.subckt sar_cmp inp inn clk ib dec vdd\n* -- preamplifier: a resistively loaded pair between the top plate and the\n* latch. The latch's kickback lands on its two outputs alike, where on the\n* floating top plate it would move the decision by 7-23 mV. Its tail\n* mirrors the bias current the testbench gives on pin ib.\n* Its offset is the converter's: 16/1 um inputs (1.3 mV sigma, where 4/0.5 um\n* gave 3.7 mV) and loads of p+ poly, two 15 kOhm units a side in series\n* (0.2 mV; 20 kOhm of high-resistance poly, 3 um^2 of it, gave 2.5 mV). The\n* 30 kOhm loads give a gain of 5, which divides the latch's own offset.\nXPbd ib ib 0 0 sg13_lv_nmos w=6.6u l=1u ng=2 m=1\nXPbt ptail ib 0 0 sg13_lv_nmos w=6.6u l=1u ng=2 m=1\nXP1 pn inp ptail 0 sg13_lv_nmos w=16u l=1u ng=4 m=1\nXP2 pp inn ptail 0 sg13_lv_nmos w=16u l=1u ng=4 m=1\nXR1 vdd rn 0 rppd w=0.5u l=29.263u\nXR3 rn pn 0 rppd w=0.5u l=29.263u\nXR2 vdd rp 0 rppd w=0.5u l=29.263u\nXR4 rp pp 0 rppd w=0.5u l=29.263u\n* -- StrongARM latch: precharged while clk is high, deciding while it is low.\n* pp rises above pn when inp > inn, which drops outn.\nXIck clkb clk vdd 0 sg13g2_inv_2\nXMt ctail clkb 0 0 sg13_lv_nmos w=4u l=130n ng=1 m=1\nXM1 dip pp ctail 0 sg13_lv_nmos w=8u l=130n ng=2 m=1\nXM2 din pn ctail 0 sg13_lv_nmos w=8u l=130n ng=2 m=1\nXM3 outn outp dip 0 sg13_lv_nmos w=2u l=130n ng=1 m=1\nXM4 outp outn din 0 sg13_lv_nmos w=2u l=130n ng=1 m=1\nXM5 outn outp vdd vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\nXM6 outp outn vdd vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\nXM7 outn clkb vdd vdd sg13_lv_pmos w=1u l=130n ng=1 m=1\nXM8 outp clkb vdd vdd sg13_lv_pmos w=1u l=130n ng=1 m=1\nXM9 dip clkb vdd vdd sg13_lv_pmos w=1u l=130n ng=1 m=1\nXM10 din clkb vdd vdd sg13_lv_pmos w=1u l=130n ng=1 m=1\n* -- the decision, held through the next precharge. Identical inverters load\n* outp and outn the same whatever the latch holds; a latch on them directly\n* makes the comparator favour its last answer by 1.3 mV.\nXIkn keep outn vdd 0 sg13g2_inv_1\nXIkp rej outp vdd 0 sg13g2_inv_1\nXLs dec rej decb vdd 0 sg13g2_nor2_1\nXLr decb keep dec vdd 0 sg13g2_nor2_1\n.ends sar_cmp\n\n.subckt sar_logic clk conv dec b5 b4 b3 b2 b1 b0 d5 d4 d3 d2 d1 d0 eoc vdd\n* Each bit's flip-flop loads the decision through a mux on the edge that ends\n* its trial, and holds it otherwise. The MSB's are set while conv is low, so\n* the MSB trial is already on the array when the bottom plates leave vin:\n* starting from all zero would take the top plate to vcm - vin, below ground\n* for vin > vcm. The library's flip-flops only reset, so each of those two\n* holds its bit's complement - reset is then 1 on Q_N - and is fed an\n* inverted D: vdd for the token, which is 0 once passed on.\nXT5 tq5 t5 clk vdd conv vdd 0 sg13g2_dfrbp_1\nXT4 t4 clk t5 conv vdd 0 sg13g2_dfrbpq_1\nXT3 t3 clk t4 conv vdd 0 sg13g2_dfrbpq_1\nXT2 t2 clk t3 conv vdd 0 sg13g2_dfrbpq_1\nXT1 t1 clk t2 conv vdd 0 sg13g2_dfrbpq_1\nXT0 t0 clk t1 conv vdd 0 sg13g2_dfrbpq_1\nXTend eoc clk t0 conv vdd 0 sg13g2_dfrbpq_1\nXK5 nxt5 d5 dec t5 vdd 0 sg13g2_mux2_1\nXK4 nxt4 d4 dec t4 vdd 0 sg13g2_mux2_1\nXK3 nxt3 d3 dec t3 vdd 0 sg13g2_mux2_1\nXK2 nxt2 d2 dec t2 vdd 0 sg13g2_mux2_1\nXK1 nxt1 d1 dec t1 vdd 0 sg13g2_mux2_1\nXK0 nxt0 d0 dec t0 vdd 0 sg13g2_mux2_1\nXFi5 nxtb5 nxt5 vdd 0 sg13g2_inv_1\nXF5 dq5 d5 clk nxtb5 conv vdd 0 sg13g2_dfrbp_1\nXF4 d4 clk nxt4 conv vdd 0 sg13g2_dfrbpq_1\nXF3 d3 clk nxt3 conv vdd 0 sg13g2_dfrbpq_1\nXF2 d2 clk nxt2 conv vdd 0 sg13g2_dfrbpq_1\nXF1 d1 clk nxt1 conv vdd 0 sg13g2_dfrbpq_1\nXF0 d0 clk nxt0 conv vdd 0 sg13g2_dfrbpq_1\nXO5 b5 t5 d5 vdd 0 sg13g2_or2_1\nXO4 b4 t4 d4 vdd 0 sg13g2_or2_1\nXO3 b3 t3 d3 vdd 0 sg13g2_or2_1\nXO2 b2 t2 d2 vdd 0 sg13g2_or2_1\nXO1 b1 t1 d1 vdd 0 sg13g2_or2_1\nXO0 b0 t0 d0 vdd 0 sg13g2_or2_1\n.ends sar_logic\n\n.subckt sar_adc vin vcm vref ib clk samp d5 d4 d3 d2 d1 d0 eoc vdd\n* -- timing. samp high tracks the input. The top-plate switch opens on samp\n* itself; the bottom plates and the register follow sampd, two gate delays\n* later, so the charge is fixed while the top plate floats and the bottom\n* plates' own switches can inject nothing into it (bottom-plate sampling).\n* sampd and sampdn drive the gate of every bottom-plate switch, so they are\n* strong: on a slow edge the MSB's plate starts moving while the others are\n* still loosely held, they ride up with the top plate, and it overshot to\n* 1.32 V at a 0 V input with buf_2 and inv_4; with these, 1.21 V.\nXIs sampn samp vdd 0 sg13g2_inv_2\nXId1 sd1 samp vdd 0 sg13g2_buf_1\nXId2 sampd sd1 vdd 0 sg13g2_buf_8\nXId3 sampdn sampd vdd 0 sg13g2_inv_8\n* -- the array. While sampling, every bottom plate is on vin and the top\n* plate on vcm; then each bottom plate goes to its bit driver, which swings\n* between ground and vref. The termination capacitor goes to ground.\nXC0 bp0 top cap_cmim w=3.599u l=3.599u\nXSi0n vin sampd bp0 0 sg13_lv_nmos w=4u l=130n ng=1 m=1\nXSi0p vin sampdn bp0 vdd sg13_lv_pmos w=8u l=130n ng=2 m=1\nXSd0n drv0 sampdn bp0 0 sg13_lv_nmos w=4u l=130n ng=1 m=1\nXSd0p drv0 sampd bp0 vdd sg13_lv_pmos w=8u l=130n ng=2 m=1\nXB0 drv0 b0 vref 0 sg13g2_buf_1\nXC1 bp1 top cap_cmim w=5.111u l=5.111u\nXSi1n vin sampd bp1 0 sg13_lv_nmos w=4u l=130n ng=1 m=1\nXSi1p vin sampdn bp1 vdd sg13_lv_pmos w=8u l=130n ng=2 m=1\nXSd1n drv1 sampdn bp1 0 sg13_lv_nmos w=4u l=130n ng=1 m=1\nXSd1p drv1 sampd bp1 vdd sg13_lv_pmos w=8u l=130n ng=2 m=1\nXB1 drv1 b1 vref 0 sg13g2_buf_1\nXC2 bp2 top cap_cmim w=7.25u l=7.25u\nXSi2n vin sampd bp2 0 sg13_lv_nmos w=4u l=130n ng=1 m=1\nXSi2p vin sampdn bp2 vdd sg13_lv_pmos w=8u l=130n ng=2 m=1\nXSd2n drv2 sampdn bp2 0 sg13_lv_nmos w=4u l=130n ng=1 m=1\nXSd2p drv2 sampd bp2 vdd sg13_lv_pmos w=8u l=130n ng=2 m=1\nXB2 drv2 b2 vref 0 sg13g2_buf_1\nXC3 bp3 top cap_cmim w=10.275u l=10.275u\nXSi3n vin sampd bp3 0 sg13_lv_nmos w=4u l=130n ng=1 m=1\nXSi3p vin sampdn bp3 vdd sg13_lv_pmos w=8u l=130n ng=2 m=1\nXSd3n drv3 sampdn bp3 0 sg13_lv_nmos w=8u l=130n ng=2 m=1\nXSd3p drv3 sampd bp3 vdd sg13_lv_pmos w=16u l=130n ng=4 m=1\nXB3 drv3 b3 vref 0 sg13g2_buf_2\nXC4 bp4 top cap_cmim w=14.553u l=14.553u\nXSi4n vin sampd bp4 0 sg13_lv_nmos w=4u l=130n ng=1 m=1\nXSi4p vin sampdn bp4 vdd sg13_lv_pmos w=8u l=130n ng=2 m=1\nXSd4n drv4 sampdn bp4 0 sg13_lv_nmos w=16u l=130n ng=4 m=1\nXSd4p drv4 sampd bp4 vdd sg13_lv_pmos w=32u l=130n ng=8 m=1\nXB4a drvn4 b4 vref 0 sg13g2_inv_2\nXB4b drv4 drvn4 vref 0 sg13g2_inv_4\nXC5 bp5 top cap_cmim w=20.603u l=20.603u\nXSi5n vin sampd bp5 0 sg13_lv_nmos w=4u l=130n ng=1 m=1\nXSi5p vin sampdn bp5 vdd sg13_lv_pmos w=8u l=130n ng=2 m=1\nXSd5n drv5 sampdn bp5 0 sg13_lv_nmos w=32u l=130n ng=8 m=1\nXSd5p drv5 sampd bp5 vdd sg13_lv_pmos w=64u l=130n ng=14 m=1\nXB5a drvn5 b5 vref 0 sg13g2_inv_2\nXB5b0 drv5 drvn5 vref 0 sg13g2_inv_4\nXB5b1 drv5 drvn5 vref 0 sg13g2_inv_4\nXCt bpt top cap_cmim w=3.599u l=3.599u\nXSitn vin sampd bpt 0 sg13_lv_nmos w=4u l=130n ng=1 m=1\nXSitp vin sampdn bpt vdd sg13_lv_pmos w=8u l=130n ng=2 m=1\nXSgt bpt sampdn 0 0 sg13_lv_nmos w=4u l=130n ng=1 m=1\nXStn top samp vcm 0 sg13_lv_nmos w=4u l=130n ng=1 m=1\nXStp top sampn vcm vdd sg13_lv_pmos w=8u l=130n ng=2 m=1\n* -- the comparator decides whether vcm > top: keep the bit\nXcmp vcm top clk ib dec vdd sar_cmp\nXsar clk sampdn dec b5 b4 b3 b2 b1 b0 d5 d4 d3 d2 d1 d0 eoc vdd sar_logic\n.ends sar_adc\n* the testbench: supply, references, the input, the preamplifier's bias, the clock\nVdd vdd 0 1.2\nVref vref 0 1.2\nVcm vcm 0 600m\nVin vin 0 758m\nIb vdd ib 20u\nVs samp 0 pwl(0 1.2 3n 1.2 3.05n 0)\nVclk clk 0 pulse(1.2 0 10n 50p 50p 4.95n 10n)\nXadc vin vcm vref ib clk samp d5 d4 d3 d2 d1 d0 eoc vdd sar_adc\n* What the page reads, and nothing else: every PSP transistor adds three\n* internal nodes, and saving all of them is 2,200 vectors to hand back.\n.save v(samp) v(clk) v(xadc.top) v(xadc.dec) v(d0) v(xadc.b0) v(d1) v(xadc.b1) v(d2) v(xadc.b2) v(d3) v(xadc.b3) v(d4) v(xadc.b4) v(d5) v(xadc.b5) v(eoc) v(vdd) i(vdd) i(vref) i(vcm)\n* A 250 ps step: the solver still places its own points on every edge, and\n* the top plate at each decision comes out within 0.1 mV of a 100 ps run, in\n* 60 % of the time - several hundred PSP transistors make every point dear.\n.tran 250p 70n\n.end" } ], "measurements": { "error_lsb": { "label": "Quantisation error in LSB", "unit": "LSB", "spec": { "min": -1, "max": 1 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "5dae21347b575b7ffaf9bdbdf1729e16a453fc04ddcee4008c7cd12ae7454f4d" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/sar-adc.js", "sha256": "21a3797892d11a15c7f9d4b4883418bb3fe59a5ee8e17310ed37d36307a817ef" }, "simulationFingerprints": { "convert": "9ffcf3bd0407ba079cac1902541e22ba6ecca637dd6cccb714277ac762a77567" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "3ec9beda19bba3970ccae7a7b029bc7583bcbc96e8f7d1d05e2ebbc6eb7a31cb", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "sar-adc", "parameters": { "bits": 6, "Cu": 2e-14, "mismatch": 0, "seed": 1, "vref": 1.2, "vcm": 0.6, "vin": 0.758, "fclk": 100000000, "Wsw": 0.000004 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/sar-adc/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [], "scopes": [ { "id": "dut", "name": "sar_adc", "ports": [ { "name": "vin", "net": "vin", "kind": "input" }, { "name": "vcm", "net": "vcm", "kind": "bias" }, { "name": "vref", "net": "vref", "kind": "bias" }, { "name": "ib", "net": "ib", "kind": "bias" }, { "name": "clk", "net": "clk", "kind": "clock" }, { "name": "samp", "net": "samp", "kind": "clock" }, { "name": "d5", "net": "d5", "kind": "output" }, { "name": "d4", "net": "d4", "kind": "output" }, { "name": "d3", "net": "d3", "kind": "output" }, { "name": "d2", "net": "d2", "kind": "output" }, { "name": "d1", "net": "d1", "kind": "output" }, { "name": "d0", "net": "d0", "kind": "output" }, { "name": "eoc", "net": "eoc", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" } ], "definitions": [], "devices": [ { "id": "XIs", "displayName": "Is", "spiceType": "X", "model": "sg13g2_inv_2", "parametersOrValue": "", "source": "XIs sampn samp vdd 0 sg13g2_inv_2", "pins": [ { "id": "Y", "net": "sampn" }, { "id": "A", "net": "samp" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XId1", "displayName": "Id1", "spiceType": "X", "model": "sg13g2_buf_1", "parametersOrValue": "", "source": "XId1 sd1 samp vdd 0 sg13g2_buf_1", "pins": [ { "id": "X", "net": "sd1" }, { "id": "A", "net": "samp" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XId2", "displayName": "Id2", "spiceType": "X", "model": "sg13g2_buf_8", "parametersOrValue": "", "source": "XId2 sampd sd1 vdd 0 sg13g2_buf_8", "pins": [ { "id": "X", "net": "sampd" }, { "id": "A", "net": "sd1" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XId3", "displayName": "Id3", "spiceType": "X", "model": "sg13g2_inv_8", "parametersOrValue": "", "source": "XId3 sampdn sampd vdd 0 sg13g2_inv_8", "pins": [ { "id": "Y", "net": "sampdn" }, { "id": "A", "net": "sampd" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XC0", "displayName": "C0", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=3.599u l=3.599u", "source": "XC0 bp0 top cap_cmim w=3.599u l=3.599u", "pins": [ { "id": "p", "net": "bp0" }, { "id": "n", "net": "top" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XSi0n", "displayName": "Si0n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSi0n vin sampd bp0 0 sg13_lv_nmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "sampd" }, { "id": "s", "net": "bp0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSi0p", "displayName": "Si0p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XSi0p vin sampdn bp0 vdd sg13_lv_pmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "sampdn" }, { "id": "s", "net": "bp0" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSd0n", "displayName": "Sd0n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSd0n drv0 sampdn bp0 0 sg13_lv_nmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "drv0" }, { "id": "g", "net": "sampdn" }, { "id": "s", "net": "bp0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSd0p", "displayName": "Sd0p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XSd0p drv0 sampd bp0 vdd sg13_lv_pmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "drv0" }, { "id": "g", "net": "sampd" }, { "id": "s", "net": "bp0" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XB0", "displayName": "B0", "spiceType": "X", "model": "sg13g2_buf_1", "parametersOrValue": "", "source": "XB0 drv0 b0 vref 0 sg13g2_buf_1", "pins": [ { "id": "X", "net": "drv0" }, { "id": "A", "net": "b0" }, { "id": "VDD", "net": "vref" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XC1", "displayName": "C1", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=5.111u l=5.111u", "source": "XC1 bp1 top cap_cmim w=5.111u l=5.111u", "pins": [ { "id": "p", "net": "bp1" }, { "id": "n", "net": "top" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XSi1n", "displayName": "Si1n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSi1n vin sampd bp1 0 sg13_lv_nmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "sampd" }, { "id": "s", "net": "bp1" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSi1p", "displayName": "Si1p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XSi1p vin sampdn bp1 vdd sg13_lv_pmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "sampdn" }, { "id": "s", "net": "bp1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSd1n", "displayName": "Sd1n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSd1n drv1 sampdn bp1 0 sg13_lv_nmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "drv1" }, { "id": "g", "net": "sampdn" }, { "id": "s", "net": "bp1" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSd1p", "displayName": "Sd1p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XSd1p drv1 sampd bp1 vdd sg13_lv_pmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "drv1" }, { "id": "g", "net": "sampd" }, { "id": "s", "net": "bp1" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XB1", "displayName": "B1", "spiceType": "X", "model": "sg13g2_buf_1", "parametersOrValue": "", "source": "XB1 drv1 b1 vref 0 sg13g2_buf_1", "pins": [ { "id": "X", "net": "drv1" }, { "id": "A", "net": "b1" }, { "id": "VDD", "net": "vref" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XC2", "displayName": "C2", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=7.25u l=7.25u", "source": "XC2 bp2 top cap_cmim w=7.25u l=7.25u", "pins": [ { "id": "p", "net": "bp2" }, { "id": "n", "net": "top" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XSi2n", "displayName": "Si2n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSi2n vin sampd bp2 0 sg13_lv_nmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "sampd" }, { "id": "s", "net": "bp2" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSi2p", "displayName": "Si2p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XSi2p vin sampdn bp2 vdd sg13_lv_pmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "sampdn" }, { "id": "s", "net": "bp2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSd2n", "displayName": "Sd2n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSd2n drv2 sampdn bp2 0 sg13_lv_nmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "drv2" }, { "id": "g", "net": "sampdn" }, { "id": "s", "net": "bp2" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSd2p", "displayName": "Sd2p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XSd2p drv2 sampd bp2 vdd sg13_lv_pmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "drv2" }, { "id": "g", "net": "sampd" }, { "id": "s", "net": "bp2" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XB2", "displayName": "B2", "spiceType": "X", "model": "sg13g2_buf_1", "parametersOrValue": "", "source": "XB2 drv2 b2 vref 0 sg13g2_buf_1", "pins": [ { "id": "X", "net": "drv2" }, { "id": "A", "net": "b2" }, { "id": "VDD", "net": "vref" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XC3", "displayName": "C3", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=10.275u l=10.275u", "source": "XC3 bp3 top cap_cmim w=10.275u l=10.275u", "pins": [ { "id": "p", "net": "bp3" }, { "id": "n", "net": "top" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XSi3n", "displayName": "Si3n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSi3n vin sampd bp3 0 sg13_lv_nmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "sampd" }, { "id": "s", "net": "bp3" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSi3p", "displayName": "Si3p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XSi3p vin sampdn bp3 vdd sg13_lv_pmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "sampdn" }, { "id": "s", "net": "bp3" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSd3n", "displayName": "Sd3n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XSd3n drv3 sampdn bp3 0 sg13_lv_nmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "drv3" }, { "id": "g", "net": "sampdn" }, { "id": "s", "net": "bp3" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSd3p", "displayName": "Sd3p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=16u l=130n ng=4 m=1", "source": "XSd3p drv3 sampd bp3 vdd sg13_lv_pmos w=16u l=130n ng=4 m=1", "pins": [ { "id": "d", "net": "drv3" }, { "id": "g", "net": "sampd" }, { "id": "s", "net": "bp3" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XB3", "displayName": "B3", "spiceType": "X", "model": "sg13g2_buf_2", "parametersOrValue": "", "source": "XB3 drv3 b3 vref 0 sg13g2_buf_2", "pins": [ { "id": "X", "net": "drv3" }, { "id": "A", "net": "b3" }, { "id": "VDD", "net": "vref" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XC4", "displayName": "C4", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=14.553u l=14.553u", "source": "XC4 bp4 top cap_cmim w=14.553u l=14.553u", "pins": [ { "id": "p", "net": "bp4" }, { "id": "n", "net": "top" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XSi4n", "displayName": "Si4n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSi4n vin sampd bp4 0 sg13_lv_nmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "sampd" }, { "id": "s", "net": "bp4" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSi4p", "displayName": "Si4p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XSi4p vin sampdn bp4 vdd sg13_lv_pmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "sampdn" }, { "id": "s", "net": "bp4" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSd4n", "displayName": "Sd4n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=16u l=130n ng=4 m=1", "source": "XSd4n drv4 sampdn bp4 0 sg13_lv_nmos w=16u l=130n ng=4 m=1", "pins": [ { "id": "d", "net": "drv4" }, { "id": "g", "net": "sampdn" }, { "id": "s", "net": "bp4" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSd4p", "displayName": "Sd4p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=32u l=130n ng=8 m=1", "source": "XSd4p drv4 sampd bp4 vdd sg13_lv_pmos w=32u l=130n ng=8 m=1", "pins": [ { "id": "d", "net": "drv4" }, { "id": "g", "net": "sampd" }, { "id": "s", "net": "bp4" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XB4a", "displayName": "B4a", "spiceType": "X", "model": "sg13g2_inv_2", "parametersOrValue": "", "source": "XB4a drvn4 b4 vref 0 sg13g2_inv_2", "pins": [ { "id": "Y", "net": "drvn4" }, { "id": "A", "net": "b4" }, { "id": "VDD", "net": "vref" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XB4b", "displayName": "B4b", "spiceType": "X", "model": "sg13g2_inv_4", "parametersOrValue": "", "source": "XB4b drv4 drvn4 vref 0 sg13g2_inv_4", "pins": [ { "id": "Y", "net": "drv4" }, { "id": "A", "net": "drvn4" }, { "id": "VDD", "net": "vref" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XC5", "displayName": "C5", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=20.603u l=20.603u", "source": "XC5 bp5 top cap_cmim w=20.603u l=20.603u", "pins": [ { "id": "p", "net": "bp5" }, { "id": "n", "net": "top" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XSi5n", "displayName": "Si5n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSi5n vin sampd bp5 0 sg13_lv_nmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "sampd" }, { "id": "s", "net": "bp5" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSi5p", "displayName": "Si5p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XSi5p vin sampdn bp5 vdd sg13_lv_pmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "sampdn" }, { "id": "s", "net": "bp5" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSd5n", "displayName": "Sd5n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=32u l=130n ng=8 m=1", "source": "XSd5n drv5 sampdn bp5 0 sg13_lv_nmos w=32u l=130n ng=8 m=1", "pins": [ { "id": "d", "net": "drv5" }, { "id": "g", "net": "sampdn" }, { "id": "s", "net": "bp5" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSd5p", "displayName": "Sd5p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=64u l=130n ng=14 m=1", "source": "XSd5p drv5 sampd bp5 vdd sg13_lv_pmos w=64u l=130n ng=14 m=1", "pins": [ { "id": "d", "net": "drv5" }, { "id": "g", "net": "sampd" }, { "id": "s", "net": "bp5" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XB5a", "displayName": "B5a", "spiceType": "X", "model": "sg13g2_inv_2", "parametersOrValue": "", "source": "XB5a drvn5 b5 vref 0 sg13g2_inv_2", "pins": [ { "id": "Y", "net": "drvn5" }, { "id": "A", "net": "b5" }, { "id": "VDD", "net": "vref" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XB5b0", "displayName": "B5b0", "spiceType": "X", "model": "sg13g2_inv_4", "parametersOrValue": "", "source": "XB5b0 drv5 drvn5 vref 0 sg13g2_inv_4", "pins": [ { "id": "Y", "net": "drv5" }, { "id": "A", "net": "drvn5" }, { "id": "VDD", "net": "vref" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XB5b1", "displayName": "B5b1", "spiceType": "X", "model": "sg13g2_inv_4", "parametersOrValue": "", "source": "XB5b1 drv5 drvn5 vref 0 sg13g2_inv_4", "pins": [ { "id": "Y", "net": "drv5" }, { "id": "A", "net": "drvn5" }, { "id": "VDD", "net": "vref" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XCt", "displayName": "Ct", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=3.599u l=3.599u", "source": "XCt bpt top cap_cmim w=3.599u l=3.599u", "pins": [ { "id": "p", "net": "bpt" }, { "id": "n", "net": "top" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XSitn", "displayName": "Sitn", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSitn vin sampd bpt 0 sg13_lv_nmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "sampd" }, { "id": "s", "net": "bpt" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSitp", "displayName": "Sitp", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XSitp vin sampdn bpt vdd sg13_lv_pmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "sampdn" }, { "id": "s", "net": "bpt" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSgt", "displayName": "Sgt", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSgt bpt sampdn 0 0 sg13_lv_nmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "bpt" }, { "id": "g", "net": "sampdn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XStn", "displayName": "Stn", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XStn top samp vcm 0 sg13_lv_nmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "top" }, { "id": "g", "net": "samp" }, { "id": "s", "net": "vcm" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XStp", "displayName": "Stp", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XStp top sampn vcm vdd sg13_lv_pmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "top" }, { "id": "g", "net": "sampn" }, { "id": "s", "net": "vcm" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "Xcmp", "displayName": "Xcmp", "spiceType": "X", "model": "sar_cmp", "parametersOrValue": "", "source": "Xcmp vcm top clk ib dec vdd sar_cmp", "pins": [ { "id": "inp", "net": "vcm" }, { "id": "inn", "net": "top" }, { "id": "clk", "net": "clk" }, { "id": "ib", "net": "ib" }, { "id": "dec", "net": "dec" }, { "id": "vdd", "net": "vdd" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/sar_cmp" }, { "id": "Xsar", "displayName": "Xsar", "spiceType": "X", "model": "sar_logic", "parametersOrValue": "", "source": "Xsar clk sampdn dec b5 b4 b3 b2 b1 b0 d5 d4 d3 d2 d1 d0 eoc vdd sar_logic", "pins": [ { "id": "clk", "net": "clk" }, { "id": "conv", "net": "sampdn" }, { "id": "dec", "net": "dec" }, { "id": "b5", "net": "b5" }, { "id": "b4", "net": "b4" }, { "id": "b3", "net": "b3" }, { "id": "b2", "net": "b2" }, { "id": "b1", "net": "b1" }, { "id": "b0", "net": "b0" }, { "id": "d5", "net": "d5" }, { "id": "d4", "net": "d4" }, { "id": "d3", "net": "d3" }, { "id": "d2", "net": "d2" }, { "id": "d1", "net": "d1" }, { "id": "d0", "net": "d0" }, { "id": "eoc", "net": "eoc" }, { "id": "vdd", "net": "vdd" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/sar_logic" } ], "nets": [ { "id": "sampn", "ground": false, "terminals": [ { "device": "XIs", "pin": "Y" }, { "device": "XStp", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "samp", "ground": false, "terminals": [ { "device": "XIs", "pin": "A" }, { "device": "XId1", "pin": "A" }, { "device": "XStn", "pin": "g" } ], "ports": [ "samp" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XIs", "pin": "VDD" }, { "device": "XId1", "pin": "VDD" }, { "device": "XId2", "pin": "VDD" }, { "device": "XId3", "pin": "VDD" }, { "device": "XSi0p", "pin": "b" }, { "device": "XSd0p", "pin": "b" }, { "device": "XSi1p", "pin": "b" }, { "device": "XSd1p", "pin": "b" }, { "device": "XSi2p", "pin": "b" }, { "device": "XSd2p", "pin": "b" }, { "device": "XSi3p", "pin": "b" }, { "device": "XSd3p", "pin": "b" }, { "device": "XSi4p", "pin": "b" }, { "device": "XSd4p", "pin": "b" }, { "device": "XSi5p", "pin": "b" }, { "device": "XSd5p", "pin": "b" }, { "device": "XSitp", "pin": "b" }, { "device": "XStp", "pin": "b" }, { "device": "Xcmp", "pin": "vdd" }, { "device": "Xsar", "pin": "vdd" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "XIs", "pin": "VSS" }, { "device": "XId1", "pin": "VSS" }, { "device": "XId2", "pin": "VSS" }, { "device": "XId3", "pin": "VSS" }, { "device": "XSi0n", "pin": "b" }, { "device": "XSd0n", "pin": "b" }, { "device": "XB0", "pin": "VSS" }, { "device": "XSi1n", "pin": "b" }, { "device": "XSd1n", "pin": "b" }, { "device": "XB1", "pin": "VSS" }, { "device": "XSi2n", "pin": "b" }, { "device": "XSd2n", "pin": "b" }, { "device": "XB2", "pin": "VSS" }, { "device": "XSi3n", "pin": "b" }, { "device": "XSd3n", "pin": "b" }, { "device": "XB3", "pin": "VSS" }, { "device": "XSi4n", "pin": "b" }, { "device": "XSd4n", "pin": "b" }, { "device": "XB4a", "pin": "VSS" }, { "device": "XB4b", "pin": "VSS" }, { "device": "XSi5n", "pin": "b" }, { "device": "XSd5n", "pin": "b" }, { "device": "XB5a", "pin": "VSS" }, { "device": "XB5b0", "pin": "VSS" }, { "device": "XB5b1", "pin": "VSS" }, { "device": "XSitn", "pin": "b" }, { "device": "XSgt", "pin": "s" }, { "device": "XSgt", "pin": "b" }, { "device": "XStn", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "sd1", "ground": false, "terminals": [ { "device": "XId1", "pin": "X" }, { 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}, { "id": "nxtb5", "ground": false, "terminals": [ { "device": "XFi5", "pin": "Y" }, { "device": "XF5", "pin": "D" } ], "ports": [], "voltageReferences": [] }, { "id": "dq5", "ground": false, "terminals": [ { "device": "XF5", "pin": "Q" } ], "ports": [], "voltageReferences": [] }, { "id": "b5", "ground": false, "terminals": [ { "device": "XO5", "pin": "X" } ], "ports": [ "b5" ], "voltageReferences": [] }, { "id": "b4", "ground": false, "terminals": [ { "device": "XO4", "pin": "X" } ], "ports": [ "b4" ], "voltageReferences": [] }, { "id": "b3", "ground": false, "terminals": [ { "device": "XO3", "pin": "X" } ], "ports": [ "b3" ], "voltageReferences": [] }, { "id": "b2", "ground": false, "terminals": [ { "device": "XO2", "pin": "X" } ], "ports": [ "b2" ], "voltageReferences": [] }, { "id": "b1", "ground": false, "terminals": [ { "device": "XO1", "pin": "X" } ], "ports": [ "b1" ], "voltageReferences": [] }, { "id": "b0", "ground": false, "terminals": [ { "device": "XO0", "pin": "X" } ], "ports": [ "b0" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "1.2", "source": "Vdd vdd 0 1.2", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vref", "displayName": "Vref", "spiceType": "V", "model": null, "parametersOrValue": "1.2", "source": "Vref vref 0 1.2", "pins": [ { "id": "p", "net": "vref" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vcm", "displayName": "Vcm", "spiceType": "V", "model": null, "parametersOrValue": "600m", "source": "Vcm vcm 0 600m", "pins": [ { "id": "p", "net": "vcm" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "758m", "source": "Vin vin 0 758m", "pins": [ { "id": "p", "net": "vin" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "20u", "source": "Ib vdd ib 20u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "ib" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vs", "displayName": "Vs", "spiceType": "V", "model": null, "parametersOrValue": "pwl(0 1.2 3n 1.2 3.05n 0)", "source": "Vs samp 0 pwl(0 1.2 3n 1.2 3.05n 0)", "pins": [ { "id": "p", "net": "samp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclk", "displayName": "Vclk", "spiceType": "V", "model": null, "parametersOrValue": "pulse(1.2 0 10n 50p 50p 4.95n 10n)", "source": "Vclk clk 0 pulse(1.2 0 10n 50p 50p 4.95n 10n)", "pins": [ { "id": "p", "net": "clk" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xadc", "displayName": "Xadc", "spiceType": "X", "model": "sar_adc", "parametersOrValue": "", "source": "Xadc vin vcm vref ib clk samp d5 d4 d3 d2 d1 d0 eoc vdd sar_adc", "pins": [ { "id": "vin", "net": "vin" }, { "id": "vcm", "net": "vcm" }, { "id": "vref", "net": "vref" }, { "id": "ib", "net": "ib" }, { "id": "clk", "net": "clk" }, { "id": "samp", "net": "samp" }, { "id": "d5", "net": "d5" }, { "id": "d4", "net": "d4" }, { "id": "d3", "net": "d3" }, { "id": "d2", "net": "d2" }, { "id": "d1", "net": "d1" }, { "id": "d0", "net": "d0" }, { "id": "eoc", "net": "eoc" }, { "id": "vdd", "net": "vdd" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/sar_adc" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ib", "pin": "p" }, { "device": "Xadc", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vref", "pin": "n" }, { "device": "Vcm", "pin": "n" }, { "device": "Vin", "pin": "n" }, { "device": "Vs", "pin": "n" }, { "device": "Vclk", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vref", "ground": false, "terminals": [ { "device": "Vref", "pin": "p" }, { "device": "Xadc", "pin": "vref" } ], "ports": [], "voltageReferences": [] }, { "id": "vcm", "ground": false, "terminals": [ { "device": "Vcm", "pin": "p" }, { "device": "Xadc", "pin": "vcm" } ], "ports": [], "voltageReferences": [] }, { "id": "vin", "ground": false, "terminals": [ { "device": "Vin", "pin": "p" }, { "device": "Xadc", "pin": "vin" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "Xadc", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "samp", "ground": false, "terminals": [ { "device": "Vs", "pin": "p" }, { "device": "Xadc", "pin": "samp" } ], "ports": [], "voltageReferences": [] }, { "id": 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"cap_cmim", "parametersOrValue": "w=3.599u l=3.599u", "source": "XCt bpt top cap_cmim w=3.599u l=3.599u", "pins": [ { "id": "p", "net": "bpt" }, { "id": "n", "net": "top" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XSitn", "displayName": "Sitn", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSitn vin sampd bpt 0 sg13_lv_nmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "sampd" }, { "id": "s", "net": "bpt" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSitp", "displayName": "Sitp", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XSitp vin sampdn bpt vdd sg13_lv_pmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "sampdn" }, { "id": "s", "net": "bpt" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSgt", "displayName": "Sgt", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XSgt bpt sampdn 0 0 sg13_lv_nmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "bpt" }, { "id": "g", "net": "sampdn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XStn", "displayName": "Stn", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XStn top samp vcm 0 sg13_lv_nmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "top" }, { "id": "g", "net": "samp" }, { "id": "s", "net": "vcm" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XStp", "displayName": "Stp", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XStp top sampn vcm vdd sg13_lv_pmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "top" }, { "id": "g", "net": "sampn" }, { "id": "s", "net": "vcm" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "Xcmp", "displayName": "Xcmp", "spiceType": "X", "model": "sar_cmp", "parametersOrValue": "", "source": "Xcmp vcm top clk ib dec vdd sar_cmp", "pins": [ { "id": "inp", "net": "vcm" }, { "id": "inn", "net": "top" }, { "id": "clk", "net": "clk" }, { "id": "ib", "net": "ib" }, { "id": "dec", "net": "dec" }, { "id": "vdd", "net": "vdd" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/sar_cmp" }, { "id": "Xsar", "displayName": "Xsar", "spiceType": "X", "model": "sar_logic", "parametersOrValue": "", "source": "Xsar clk sampdn dec b5 b4 b3 b2 b1 b0 d5 d4 d3 d2 d1 d0 eoc vdd sar_logic", "pins": [ { "id": "clk", "net": "clk" }, { "id": "conv", "net": "sampdn" }, { "id": "dec", "net": "dec" }, { "id": "b5", "net": "b5" }, { "id": "b4", "net": "b4" }, { "id": "b3", "net": "b3" }, { "id": "b2", "net": "b2" }, { "id": "b1", "net": "b1" }, { "id": "b0", "net": "b0" }, { "id": "d5", "net": "d5" }, { "id": "d4", "net": "d4" }, { "id": "d3", "net": "d3" }, { "id": "d2", "net": "d2" }, { "id": "d1", "net": "d1" }, { "id": "d0", "net": "d0" }, { "id": "eoc", "net": "eoc" }, { "id": "vdd", "net": "vdd" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/sar_logic" } ], "nets": [ { "id": "sampn", "ground": false, "terminals": [ { "device": "XIs", "pin": "Y" }, { "device": "XStp", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "samp", "ground": false, "terminals": [ { "device": "XIs", "pin": "A" }, { "device": "XId1", "pin": "A" }, { "device": "XStn", "pin": "g" } ], "ports": [ "samp" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XIs", "pin": "VDD" }, { "device": "XId1", "pin": "VDD" }, { "device": "XId2", "pin": "VDD" }, { "device": "XId3", "pin": "VDD" }, { "device": "XSi0p", "pin": "b" }, { "device": "XSd0p", "pin": "b" }, { "device": "XSi1p", "pin": "b" }, { "device": "XSd1p", "pin": "b" }, { "device": "XSi2p", "pin": "b" }, { "device": "XSd2p", "pin": "b" }, { "device": "XSi3p", "pin": "b" }, { "device": "XSd3p", "pin": "b" }, { "device": "XSi4p", "pin": "b" }, { "device": "XSd4p", "pin": "b" }, { "device": "XSi5p", "pin": "b" }, { "device": "XSd5p", "pin": "b" }, { "device": "XSitp", "pin": "b" }, { "device": "XStp", "pin": "b" }, { "device": "Xcmp", "pin": "vdd" }, { "device": "Xsar", "pin": "vdd" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "XIs", "pin": "VSS" }, { "device": "XId1", "pin": "VSS" }, { "device": "XId2", "pin": "VSS" }, { "device": "XId3", "pin": "VSS" }, { "device": "XSi0n", "pin": "b" }, { "device": "XSd0n", "pin": "b" }, { "device": "XB0", "pin": "VSS" }, { "device": "XSi1n", "pin": "b" }, { "device": "XSd1n", "pin": "b" }, { "device": "XB1", "pin": "VSS" }, { "device": "XSi2n", "pin": "b" }, { "device": "XSd2n", "pin": "b" }, { "device": "XB2", "pin": "VSS" }, { "device": "XSi3n", "pin": "b" }, { "device": "XSd3n", "pin": "b" }, { "device": "XB3", "pin": "VSS" }, { "device": "XSi4n", "pin": "b" }, { "device": "XSd4n", "pin": "b" }, { "device": "XB4a", "pin": "VSS" }, { "device": "XB4b", "pin": "VSS" }, { "device": "XSi5n", "pin": "b" }, { "device": "XSd5n", "pin": "b" }, { "device": "XB5a", "pin": "VSS" }, { "device": "XB5b0", "pin": "VSS" }, { "device": "XB5b1", "pin": "VSS" }, { "device": "XSitn", "pin": "b" }, { "device": "XSgt", "pin": "s" }, { "device": "XSgt", "pin": "b" }, { "device": "XStn", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "sd1", "ground": false, "terminals": [ { "device": "XId1", "pin": "X" }, { "device": "XId2", "pin": "A" } ], "ports": [], "voltageReferences": [] }, { "id": "sampd", "ground": false, "terminals": [ { "device": "XId2", "pin": "X" }, { "device": "XId3", "pin": "A" }, { "device": "XSi0n", "pin": "g" }, { "device": "XSd0p", "pin": "g" }, { "device": "XSi1n", "pin": "g" }, { "device": "XSd1p", "pin": "g" }, { "device": "XSi2n", "pin": "g" }, { "device": "XSd2p", "pin": "g" }, { "device": "XSi3n", "pin": "g" }, { "device": "XSd3p", "pin": "g" }, { "device": "XSi4n", "pin": "g" }, { "device": "XSd4p", "pin": "g" }, { "device": "XSi5n", "pin": "g" }, { "device": "XSd5p", "pin": "g" }, { "device": "XSitn", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "sampdn", "ground": false, "terminals": [ { "device": "XId3", "pin": "Y" }, { "device": "XSi0p", "pin": "g" }, { "device": "XSd0n", "pin": "g" }, { "device": "XSi1p", "pin": "g" }, { "device": "XSd1n", "pin": "g" }, { "device": "XSi2p", "pin": "g" }, { "device": "XSd2n", "pin": "g" }, { "device": "XSi3p", "pin": "g" }, { "device": "XSd3n", "pin": "g" }, { "device": "XSi4p", "pin": "g" }, { "device": "XSd4n", "pin": "g" }, { "device": "XSi5p", "pin": "g" }, { "device": "XSd5n", "pin": "g" }, { "device": "XSitp", "pin": "g" }, { "device": "XSgt", "pin": "g" }, { "device": "Xsar", "pin": "conv" } ], "ports": [], "voltageReferences": [] }, { "id": "bp0", "ground": false, "terminals": [ { "device": "XC0", "pin": "p" }, { "device": "XSi0n", "pin": "s" }, { "device": "XSi0p", "pin": "s" }, { "device": "XSd0n", "pin": "s" }, { "device": "XSd0p", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "top", "ground": false, "terminals": [ { "device": "XC0", "pin": "n" }, { "device": "XC1", "pin": "n" }, { "device": "XC2", "pin": "n" }, { "device": "XC3", "pin": "n" }, { "device": "XC4", "pin": "n" }, { "device": "XC5", "pin": "n" }, { "device": "XCt", "pin": "n" }, { "device": "XStn", "pin": "d" }, { "device": "XStp", "pin": "d" }, { "device": "Xcmp", "pin": "inn" } ], "ports": [], "voltageReferences": [] }, { "id": "vin", "ground": false, "terminals": [ { "device": "XSi0n", "pin": "d" }, { "device": "XSi0p", "pin": "d" }, { "device": "XSi1n", "pin": "d" }, { "device": "XSi1p", "pin": "d" }, { "device": "XSi2n", "pin": "d" }, { "device": "XSi2p", "pin": "d" }, { "device": "XSi3n", "pin": "d" }, { "device": "XSi3p", "pin": "d" }, { "device": "XSi4n", "pin": "d" }, { "device": "XSi4p", "pin": "d" }, { "device": "XSi5n", "pin": "d" }, { "device": "XSi5p", "pin": "d" }, { "device": "XSitn", "pin": "d" }, { "device": "XSitp", "pin": "d" } ], "ports": [ "vin" ], "voltageReferences": [] }, { "id": "drv0", "ground": false, "terminals": [ { "device": "XSd0n", "pin": "d" }, { "device": "XSd0p", "pin": "d" }, { "device": "XB0", "pin": "X" } ], "ports": [], "voltageReferences": [] }, { "id": "b0", "ground": false, "terminals": [ { "device": "XB0", "pin": "A" }, { "device": "Xsar", "pin": "b0" } ], "ports": [], "voltageReferences": [] }, { "id": "vref", "ground": false, "terminals": [ { "device": "XB0", "pin": "VDD" }, { "device": "XB1", "pin": "VDD" }, { "device": "XB2", "pin": "VDD" }, { "device": "XB3", "pin": "VDD" }, { "device": "XB4a", "pin": "VDD" }, { "device": "XB4b", "pin": "VDD" }, { "device": "XB5a", "pin": "VDD" }, { "device": "XB5b0", "pin": "VDD" }, { "device": "XB5b1", "pin": "VDD" } ], "ports": [ "vref" ], "voltageReferences": [] }, { "id": "bp1", "ground": false, "terminals": [ { "device": "XC1", "pin": "p" }, { "device": "XSi1n", "pin": "s" }, { "device": "XSi1p", "pin": "s" }, { "device": "XSd1n", "pin": "s" }, { "device": "XSd1p", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "drv1", "ground": false, "terminals": [ { "device": "XSd1n", "pin": "d" }, { "device": "XSd1p", "pin": "d" }, { "device": "XB1", "pin": "X" } ], "ports": [], "voltageReferences": [] }, { "id": "b1", "ground": false, "terminals": [ { "device": "XB1", "pin": "A" }, { "device": "Xsar", "pin": "b1" } ], "ports": [], "voltageReferences": [] }, { "id": "bp2", "ground": false, "terminals": [ { "device": "XC2", "pin": "p" }, { "device": "XSi2n", "pin": "s" }, { "device": "XSi2p", "pin": "s" }, { "device": "XSd2n", "pin": "s" }, { "device": "XSd2p", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "drv2", "ground": false, "terminals": [ { "device": "XSd2n", "pin": "d" }, { "device": "XSd2p", "pin": "d" }, { "device": "XB2", "pin": "X" } ], "ports": [], "voltageReferences": [] }, { "id": "b2", "ground": false, "terminals": [ { "device": "XB2", "pin": "A" }, { "device": "Xsar", "pin": "b2" } ], "ports": [], "voltageReferences": [] }, { "id": "bp3", "ground": false, "terminals": [ { "device": "XC3", "pin": "p" }, { "device": "XSi3n", "pin": "s" }, { "device": "XSi3p", "pin": "s" }, { "device": "XSd3n", "pin": "s" }, { "device": "XSd3p", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "drv3", "ground": false, "terminals": [ { "device": "XSd3n", "pin": "d" }, { "device": "XSd3p", "pin": "d" }, { "device": "XB3", "pin": "X" } ], "ports": [], "voltageReferences": [] }, { "id": "b3", "ground": false, "terminals": [ { "device": "XB3", "pin": "A" }, { "device": "Xsar", "pin": "b3" } ], "ports": [], "voltageReferences": [] }, { "id": "bp4", "ground": false, "terminals": [ { "device": "XC4", "pin": "p" }, { "device": "XSi4n", "pin": "s" }, { "device": "XSi4p", "pin": "s" }, { "device": "XSd4n", "pin": "s" }, { "device": "XSd4p", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "drv4", "ground": false, "terminals": [ { "device": "XSd4n", "pin": "d" }, { "device": "XSd4p", "pin": "d" }, { "device": "XB4b", "pin": "Y" } ], "ports": [], "voltageReferences": [] }, { "id": "drvn4", "ground": false, "terminals": [ { "device": "XB4a", "pin": "Y" }, { "device": "XB4b", "pin": "A" } ], "ports": [], "voltageReferences": [] }, { "id": "b4", "ground": false, "terminals": [ { "device": "XB4a", "pin": "A" }, { "device": "Xsar", "pin": "b4" } ], "ports": [], "voltageReferences": [] }, { "id": "bp5", "ground": false, "terminals": [ { "device": "XC5", "pin": "p" }, { "device": "XSi5n", "pin": "s" }, { "device": "XSi5p", "pin": "s" }, { "device": "XSd5n", "pin": "s" }, { "device": "XSd5p", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "drv5", "ground": false, "terminals": [ { "device": "XSd5n", "pin": "d" }, { "device": "XSd5p", "pin": "d" }, { "device": "XB5b0", "pin": "Y" }, { "device": "XB5b1", "pin": "Y" } ], "ports": [], "voltageReferences": [] }, { "id": "drvn5", "ground": false, "terminals": [ { "device": "XB5a", "pin": "Y" }, { "device": "XB5b0", "pin": "A" }, { "device": "XB5b1", "pin": "A" } ], "ports": [], "voltageReferences": [] }, { "id": "b5", "ground": false, "terminals": [ { "device": "XB5a", "pin": "A" }, { "device": "Xsar", "pin": "b5" } ], "ports": [], "voltageReferences": [] }, { "id": "bpt", "ground": false, "terminals": [ { "device": "XCt", "pin": "p" }, { "device": "XSitn", "pin": "s" }, { "device": "XSitp", "pin": "s" }, { "device": "XSgt", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "vcm", "ground": false, "terminals": [ { "device": "XStn", "pin": "s" }, { "device": "XStp", "pin": "s" }, { "device": "Xcmp", "pin": "inp" } ], "ports": [ "vcm" ], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "Xcmp", "pin": "clk" }, { "device": "Xsar", "pin": "clk" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Xcmp", "pin": "ib" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "dec", "ground": false, "terminals": [ { "device": "Xcmp", "pin": "dec" }, { "device": "Xsar", "pin": "dec" } ], "ports": [], "voltageReferences": [] }, { "id": "d5", "ground": false, "terminals": [ { "device": "Xsar", "pin": "d5" } ], "ports": [ "d5" ], "voltageReferences": [] }, { "id": "d4", "ground": false, "terminals": [ { "device": "Xsar", "pin": "d4" } ], "ports": [ "d4" ], "voltageReferences": [] }, { "id": "d3", "ground": false, "terminals": [ { "device": "Xsar", "pin": "d3" } ], "ports": [ "d3" ], "voltageReferences": [] }, { "id": "d2", "ground": false, "terminals": [ { "device": "Xsar", "pin": "d2" } ], "ports": [ "d2" ], "voltageReferences": [] }, { "id": "d1", "ground": false, "terminals": [ { "device": "Xsar", "pin": "d1" } ], "ports": [ "d1" ], "voltageReferences": [] }, { "id": "d0", "ground": false, "terminals": [ { "device": "Xsar", "pin": "d0" } ], "ports": [ "d0" ], "voltageReferences": [] }, { "id": "eoc", "ground": false, "terminals": [ { "device": "Xsar", "pin": "eoc" } ], "ports": [ "eoc" ], "voltageReferences": [] } ] }, { "id": "subckt/sar_cmp", "name": "sar_cmp", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "clk", "net": "clk" }, { "name": "ib", "net": "ib" }, { "name": "dec", "net": "dec" }, { "name": "vdd", "net": "vdd" } ], "definitions": [], "devices": [ { "id": "XPbd", "displayName": "Pbd", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=6.6u l=1u ng=2 m=1", "source": "XPbd ib ib 0 0 sg13_lv_nmos w=6.6u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XPbt", "displayName": "Pbt", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=6.6u l=1u ng=2 m=1", "source": "XPbt ptail ib 0 0 sg13_lv_nmos w=6.6u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ptail" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XP1", "displayName": "P1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=16u l=1u ng=4 m=1", "source": "XP1 pn inp ptail 0 sg13_lv_nmos w=16u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "pn" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "ptail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XP2", "displayName": "P2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=16u l=1u ng=4 m=1", "source": "XP2 pp inn ptail 0 sg13_lv_nmos w=16u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "pp" }, { "id": "g", "net": "inn" }, { "id": "s", "net": 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