{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "mixed-signal", "id": "sar-monotonic", "name": "SAR ADC, monotonic switching", "group": "Data converters", "subgroup": "ADCs", "title": "SAR ADC, monotonic switching", "summary": "This ADC converts the difference between two sampled voltages into a binary number. It decides the first bit directly, then lowers one capacitor plate per decision. This saves capacitor area and switching energy, but the comparator must keep working as its inputs approach ground.", "reference": { "kind": "paper", "authors": "C.-C. Liu, S.-J. Chang, G.-Y. Huang and Y.-Z. Lin", "title": "A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure", "publisher": "IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740", "year": 2010, "where": "the monotonic switching procedure: top-plate sampling, the MSB decided without switching, one side switched down per bit", "takes": "The procedure, the halved array, the falling common mode and what it asks of the comparator, and the switching-energy argument." }, "resources": { "record": "/circuits/sar-monotonic.json", "page": "/index.html#sar-monotonic", "achieved": "/achieved/sar-monotonic.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" }, { "name": "sg13g2_stdcell.spice", "url": "/sg13g2_stdcell.spice", "sha256": "cfd805c964d3238b3342b5b1432522c3cf614d167b848d540a1499d1253ef3d4" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice", "sg13g2_stdcell.spice" ], "ports": [ { "name": "vip", "kind": "input", "polarity": "+", "note": "sampled onto the P array's top plate" }, { "name": "vin", "kind": "input", "polarity": "-", "note": "sampled onto the N array's top plate" }, { "name": "vref", "kind": "bias", "note": "the level every bottom plate starts on, and the drivers' supply" }, { "name": "ib", "kind": "bias", "note": "the bench sinks 20 uA from it: the preamplifier's bias" }, { "name": "clk", "kind": "clock", "note": "high: the comparator precharges; each rising edge ends a trial" }, { "name": "samp", "kind": "clock", "note": "high: the top plates track the inputs; its falling edge samples them" }, { "name": "d0..dN-1", "kind": "output", "note": "the result, valid once eoc rises" }, { "name": "eoc", "kind": "output", "note": "end of conversion" }, { "name": "vdd", "kind": "supply" } ], "devices": [ { "name": "CP0..CPN-2", "type": "capacitor", "sizedBy": [ "Cu", "bits" ], "role": "the P array, CP_k = 2^k C_u, on the top plate topp" }, { "name": "CN0..CNN-2", "type": "capacitor", "sizedBy": [ "Cu", "bits" ], "role": "the N array, the same, on topn" }, { "name": "CPt", "type": "capacitor", "sizedBy": [ "Cu" ], "role": "one more unit on each side (with CNt), on ground: 2^(N-1) units a side" }, { "name": "Sp", "type": "switch", "sizedBy": [ "Wsw" ], "role": "vip onto topp while sampling (with Sn for vin): transmission gates" }, { "name": "LP0..LPN-2", "type": "logic", "role": "P side: capacitor k to ground once bit k+1 is decided 1" }, { "name": "LN0..LNN-2", "type": "logic", "role": "N side: capacitor k to ground once bit k+1 is decided 0 (s_k says it is decided)" }, { "name": "DP0..DPN-2", "type": "logic", "role": "bottom-plate drivers, supplied from vref, their drive in proportion to the capacitor (with DN)" }, { "name": "P1", "type": "pmos", "role": "preamplifier pair (with P2), 4/0.5 um, loaded by 20 kOhm to ground (R1..R4); tail Pbt mirrors pin ib", "fingers": 1, "copies": 1 }, { "name": "R1..R4", "type": "resistor", "role": "the preamplifier's loads, 10 kOhm p+ poly units, two in series a side: R1 and R3 on pn, R2 and R4 on pp" }, { "name": "M1..M10", "type": "pmos", "role": "StrongARM latch with a PMOS input pair, the SAR page's turned over: input pair M1-M2 (16/0.26 um), cross-coupled M3-M6, reset to ground M7-M10, clocked tail Mt" }, { "name": "Ls", "type": "logic", "role": "NOR latch (with Lr) holding the decision, behind the buffers Ikn and Ikp" }, { "name": "T0..TN-2", "type": "logic", "role": "the thermometer s_k: a 1 shifted down one bit per clock, which stays" }, { "name": "F0..FN-1", "type": "logic", "role": "the bit registers, loading the decision through the muxes K0..KN-1 in their turn t_k (H0..HN-1)" } ], "intent": [ { "rule": "msb-without-switching", "of": [ "CP0..CPN-2", "CN0..CNN-2" ], "constraint": "N bits from N - 1 capacitors a side, 2^(N-1) units", "why": "The first comparison is made on the sampled inputs as they are, before any bottom plate moves, so the arrays only have to make the remaining N - 1 steps: 2^(N-1) units a side, half the array of a converter that has to switch its MSB to try it." }, { "rule": "monotonic", "of": [ "LP0..LPN-2", "LN0..LNN-2", "DP0..DPN-2" ], "constraint": "one capacitor per decision, the higher side's, from V_ref to ground", "why": "Every step pulls one top plate down and none up, so no charge is pushed back into V_ref: the arrays draw only for the capacitors still on V_ref under the plate that fell. For V_id = -0.5 V at 6 bits that is 457 fJ by the decisions, 513 fJ measured with the drivers' own. Liu et al. count 81 % less switching energy than the conventional procedure, averaged over the codes of their 10-bit converter." }, { "rule": "falling-common-mode", "of": [ "P1", "M1..M10" ], "constraint": "the comparator decides at any common mode from V_cm to ground", "why": "With one side moving at a time, the top plates' common mode falls every step: from 0.60 V to 28 mV over the 6-bit conversion of -0.5 V, to 7 mV at 8 bits. An NMOS pair there would be off, so the preamplifier is a PMOS pair - which at 0.6 V, the first comparison, has little headroom for its tail, on a slow cold corner none, and its outputs sink towards ground. The latch after it therefore has a PMOS input pair too, deciding from any level between ground and 0.4 V, where 20 kOhm loads keep the preamplifier's outputs. The SAR page's NMOS latch, which wants 0.5 V or more, left that first comparison undecided on slow corners: at ss, 27 °C, V_id = 30 mV converted to 31 instead of 32, and at ss, -40 °C with the supply 10 % low every V_id tried up to 70 mV did." }, { "rule": "top-plate-parasitics", "of": [ "P1", "Sp" ], "constraint": "top-plate capacitance small against 2^(N-1) C_u", "why": "The inputs are sampled on the top plates, so whatever capacitance hangs there - the preamplifier's input devices, the switches - takes a share of every step: the first is 587 mV rather than 600 mV at 6 bits, a gain error of 2 %: near full scale most of an LSB, and +-1.0 V convert to 59 and 4 instead of 58 and 5. With 8 um preamplifier inputs and 2 um switches it was 574 mV, and -0.5 V converted to 17 instead of 18. At 8 bits the arrays are four times larger and the first step is 597 mV." }, { "rule": "driver-scaling", "of": [ "DP0..DPN-2" ], "constraint": "drive in proportion to the capacitor", "why": "Each bottom plate must settle in the half clock before the next decision. At 8 bits the largest capacitor is 64 units: on one buf_1 its top plate was still 88 mV from where it settles when the comparator fired, and one trial compared 348 mV against 347 mV. Driven as on the SAR page, it settles within a tenth of a period." }, { "rule": "thermometer-register", "of": [ "T0..TN-2", "LN0..LNN-2" ], "constraint": "s_k: bit k's trial has begun", "why": "An N-side driver must move once its bit is decided 0 - and a decided 0 looks, in its register, just like a bit not yet decided. The thermometer s_k, a 1 that stays once it has arrived, says that bit k+1 is decided, for the same flip-flop per bit a one-hot token would cost." } ], "specs": [ { "key": "error", "label": "Quantisation error", "unit": "V", "direction": "min" }, { "key": "tconv", "label": "Nominal conversion interval", "unit": "s", "direction": "min" }, { "key": "energy", "label": "Energy from V_ref per conversion", "unit": "J", "direction": "min" } ], "explanation": { "idea": "This ADC converts the difference between two sampled voltages into a binary number. It decides the first bit directly, then lowers one capacitor plate per decision. This saves capacitor area and switching energy, but the comparator must keep working as its inputs approach ground.", "detail": "Converts a differential input, V_ip − V_in, into N bits with one-way capacitor switching. Both inputs are sampled on the top plates of two binary arrays whose switched bottom plates start on V_ref; the most significant bit is decided on the samples as they are, and each later decision pulls one capacitor of the higher side from V_ref to ground, moving that plate down by approximately V_ref·C_k/C_side. The ideal top plates only fall during conversion, avoiding charge returned to V_ref by upward steps. N bits need N − 1 switched capacitor weights per side, plus a termination capacitor.", "lesson": { "relation": 0, "symbols": "LSB is one ideal differential-input voltage step; V_ref is the reference voltage; N is the number of bits. The ideal differential range spans −V_ref to +V_ref.", "assumptions": "The binary capacitor ratios are exact and settle before every decision. Both physical input voltages must also stay within the switch and comparator operating ranges; the ideal differential span alone does not guarantee this.", "exercise": { "param": "bits", "value": 7, "analysis": "convert", "expect": "The ideal differential voltage step halves and the schedule adds one clock cycle. Inspect the top-plate common-mode fall and the reported conversion error, rather than assuming the extra bit is accurate." }, "limits": "External bias, reference, sampling and conversion clocks are required. Top-plate parasitics alter the gain, and the comparator must work throughout the falling common-mode trajectory. The single-input bench is characterization, not a full-code linearity or maximum-rate guarantee." }, "path": [ { "part": "Sample", "devices": "Sp, Sn, CP0..CPN-2, CN0..CNN-2, CPt, CNt", "does": "While samp is high, transmission gates put vip on topp and vin on topn with every switched bottom plate on V_ref; samp's fall leaves both top plates floating." }, { "part": "MSB without switching", "devices": "Xcmp", "does": "The first comparison is made on the sampled inputs directly: topp above topn is a 1 for the MSB, and no capacitor has moved yet." }, { "part": "One side down", "devices": "LP0..LPN-2, LN0..LNN-2, DP0..DPN-2, DN0..DNN-2", "does": "After bit k+1, capacitor k of the higher side (P after a 1, N after a 0) drops from V_ref to ground, pulling that top plate down." }, { "part": "Comparator", "devices": "Pbt, P1, P2, R1..R4, Mt, M1..M10, Ls, Lr", "does": "A PMOS preamplifier, 20 kΩ loads to ground, works down to inputs at ground; a StrongARM with a PMOS input pair decides from its outputs, below 0.4 V; the NOR latch holds each answer." }, { "part": "Register", "devices": "T0..TN-2, H0..HN-1, K0..KN-1, F0..FN-1", "does": "A 1 shifts down the thermometer s_k each clock and stays, marking decided bits; each flip-flop loads the decision on the edge ending its turn." } ], "bias": "Pbt mirrors into the preamplifier's tail the 20 µA the bench sinks from pin ib through Pbd, and 20 kΩ loads to ground keep its outputs below 0.4 V, where the latch's PMOS inputs work at every corner - even when, with the top plates at 0.6 V, the tail has almost no headroom. V_ref is where every switched bottom plate starts and the drivers' supply; samp's falling edge samples, and clk, 100 MHz by default, paces one decision per period.", "relations": [ { "what": "LSB", "expr": "LSB = 2·V_ref/2^N", "note": "the differential range is ±V_ref: 37.5 mV at 6 bits and 1.2 V" }, { "what": "Step after bit k+1", "expr": "ΔV_top = V_ref·2^k/2^(N−1)", "note": "on the higher side only: V_ref/2 first, V_ref/4 next; top-plate parasitics shrink each alike" }, { "what": "Array per side", "expr": "C_side = 2^(N−1)·C_u", "note": "half the conventional array, because the MSB is decided before anything switches" }, { "what": "Common-mode fall", "expr": "ΔV_cm ≈ −(V_ref/2)·(1 − 2^(1−N))", "note": "each step moves one side, so the common mode falls half as far: 0.6 V to near ground by default" }, { "what": "Nominal conversion interval", "expr": "t_conv = N·T_clk", "note": "one scheduled decision per clock after sampling: 60 ns at 6 bits and 100 MHz; calculated from timing, not a measured EOC delay" } ], "tradeoffs": [ "Resolution: each extra bit halves the LSB, doubles both arrays, adds a clock cycle and ends the conversion with the common mode nearer ground.", "C_unit: a larger unit lowers kT/C noise and dilutes the top-plate parasitic, shrinking the gain error, but raises switching energy and settling time.", "Sampling switch nMOS width: wider gates track faster, but their channel charge lands on the sampled top plates and their capacitance shrinks every step alike.", "Clock: faster shortens the N-cycle conversion, but each half period must settle the switched plate and let the latch decide at a falling common mode." ] }, "sizing": [ { "key": "bits", "label": "Resolution", "unit": "bit", "value": 6, "min": 3, "max": 8, "kind": "int" }, { "key": "Cu", "label": "C_unit", "unit": "F", "value": 2e-14, "min": 1e-14, "max": 1e-13, "kind": "si" }, { "key": "vid", "label": "V_id = V_ip - V_in", "unit": "V", "value": 0.31, "min": -1.2, "max": 1.2, "kind": "si" }, { "key": "vcm", "label": "Input common mode", "unit": "V", "value": 0.6, "min": 0.3, "max": 0.9, "kind": "si" }, { "key": "vref", "label": "V_ref", "unit": "V", "value": 1.2, "min": 0.8, "max": 1.2, "kind": "si" }, { "key": "fclk", "label": "Clock", "unit": "Hz", "value": 100000000, "min": 20000000, "max": 200000000, "kind": "si" }, { "key": "Wsw", "label": "Sampling switch nMOS width", "unit": "m", "value": 0.000001, "min": 1.5e-7, "max": 0.00001, "kind": "si" } ], "testbenches": [ { "id": "convert", "label": "Conversion", "note": "One conversion with every device simulated: about 10 s in the browser at 6 bits.", "measures": [ "error", "tconv", "energy" ], "metricKeys": [ "code", "error", "tconv", "energy_ref", "energy_supply", "first_step" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice", "sg13g2_stdcell.spice" ], "netlist": "* 6-bit monotonic-switching SAR ADC, transistor level: one conversion of V_id = 310mV\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.include sg13g2_stdcell.spice\n.subckt msar_cmp inp inn clk ib dec vdd\n* -- preamplifier: a PMOS pair, working down to inputs at ground, loaded by\n* resistors to ground. With its inputs at 0.6 V, the first comparison, its\n* tail has little headroom - on a slow cold corner none - and its outputs\n* fall towards ground; as the top plates reach ground it has all 20 uA.\nXPbd ib ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXPbt ptail ib vdd vdd sg13_lv_pmos w=8u l=1u ng=2 m=1\nXP1 pn inp ptail vdd sg13_lv_pmos w=4u l=500n ng=1 m=1\nXP2 pp inn ptail vdd sg13_lv_pmos w=4u l=500n ng=1 m=1\n* 20 kOhm a side, two 10 kOhm p+ poly units in series, keep the outputs below\n* 0.4 V whatever the inputs do: 10 uA each at balance, 20 uA at most\nXR1 pn rn 0 rppd w=0.5u l=19.417u\nXR3 rn 0 0 rppd w=0.5u l=19.417u\nXR2 pp rp 0 rppd w=0.5u l=19.417u\nXR4 rp 0 0 rppd w=0.5u l=19.417u\n* -- StrongARM latch with a PMOS input pair - the SAR page's, turned over:\n* outputs held at ground while clk is high, deciding while it is low. inp\n* above inn starves P1, so pn falls below pp, M1 takes more current than M2,\n* and outp rises. Its inputs decide from any level between ground and 0.4 V,\n* where the loads keep the preamplifier's outputs; the SAR page's NMOS pair\n* needs 0.5 V or more, and left the first comparison undecided on slow corners.\nXIck clkd clk vdd 0 sg13g2_buf_2\nXMt ctail clkd vdd vdd sg13_lv_pmos w=8u l=130n ng=2 m=1\nXM1 dip pn ctail vdd sg13_lv_pmos w=16u l=260n ng=4 m=1\nXM2 din pp ctail vdd sg13_lv_pmos w=16u l=260n ng=4 m=1\nXM3 outp outn dip vdd sg13_lv_pmos w=8u l=130n ng=2 m=1\nXM4 outn outp din vdd sg13_lv_pmos w=8u l=130n ng=2 m=1\nXM5 outp outn 0 0 sg13_lv_nmos w=2u l=130n ng=1 m=1\nXM6 outn outp 0 0 sg13_lv_nmos w=2u l=130n ng=1 m=1\nXM7 outp clkd 0 0 sg13_lv_nmos w=1u l=130n ng=1 m=1\nXM8 outn clkd 0 0 sg13_lv_nmos w=1u l=130n ng=1 m=1\nXM9 dip clkd 0 0 sg13_lv_nmos w=1u l=130n ng=1 m=1\nXM10 din clkd 0 0 sg13_lv_nmos w=1u l=130n ng=1 m=1\n* -- the decision, held through the next precharge\nXIkp keep outp vdd 0 sg13g2_buf_1\nXIkn rej outn vdd 0 sg13g2_buf_1\nXLs dec rej decb vdd 0 sg13g2_nor2_1\nXLr decb keep dec vdd 0 sg13g2_nor2_1\n.ends msar_cmp\n\n.subckt msar_logic clk conv dec d5 d4 d3 d2 d1 d0 s5 s4 s3 s2 s1 s0 eoc vdd\n* the MSB's trial begins as sampling ends\nXTs s5 conv vdd 0 sg13g2_buf_1\nXT4 s4 clk s5 conv vdd 0 sg13g2_dfrbpq_1\nXT3 s3 clk s4 conv vdd 0 sg13g2_dfrbpq_1\nXT2 s2 clk s3 conv vdd 0 sg13g2_dfrbpq_1\nXT1 s1 clk s2 conv vdd 0 sg13g2_dfrbpq_1\nXT0 s0 clk s1 conv vdd 0 sg13g2_dfrbpq_1\nXTend eoc clk s0 conv vdd 0 sg13g2_dfrbpq_1\nXH5 t5 s4 s5 vdd 0 sg13g2_nor2b_1\nXK5 nd5 d5 dec t5 vdd 0 sg13g2_mux2_1\nXF5 d5 clk nd5 conv vdd 0 sg13g2_dfrbpq_1\nXH4 t4 s3 s4 vdd 0 sg13g2_nor2b_1\nXK4 nd4 d4 dec t4 vdd 0 sg13g2_mux2_1\nXF4 d4 clk nd4 conv vdd 0 sg13g2_dfrbpq_1\nXH3 t3 s2 s3 vdd 0 sg13g2_nor2b_1\nXK3 nd3 d3 dec t3 vdd 0 sg13g2_mux2_1\nXF3 d3 clk nd3 conv vdd 0 sg13g2_dfrbpq_1\nXH2 t2 s1 s2 vdd 0 sg13g2_nor2b_1\nXK2 nd2 d2 dec t2 vdd 0 sg13g2_mux2_1\nXF2 d2 clk nd2 conv vdd 0 sg13g2_dfrbpq_1\nXH1 t1 s0 s1 vdd 0 sg13g2_nor2b_1\nXK1 nd1 d1 dec t1 vdd 0 sg13g2_mux2_1\nXF1 d1 clk nd1 conv vdd 0 sg13g2_dfrbpq_1\nXH0 t0 eoc s0 vdd 0 sg13g2_nor2b_1\nXK0 nd0 d0 dec t0 vdd 0 sg13g2_mux2_1\nXF0 d0 clk nd0 conv vdd 0 sg13g2_dfrbpq_1\n.ends msar_logic\n\n.subckt msar_adc vip vin vref ib clk samp d5 d4 d3 d2 d1 d0 eoc vdd\n* -- sampling: the top plates follow the inputs while samp is high\nXIs sampn samp vdd 0 sg13g2_inv_2\nXSpn vip samp topp 0 sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSpp vip sampn topp vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\nXSnn vin samp topn 0 sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSnp vin sampn topn vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\n* -- the arrays, P and N. Each bottom plate sits on vref until its bit is\n* decided, then the P side's goes to ground on a 1, the N side's on a 0. The\n* drivers are supplied from vref, their drive in proportion to the capacitor.\nXCP0 topp bp0 cap_cmim w=3.599u l=3.599u\nXCN0 topn bn0 cap_cmim w=3.599u l=3.599u\nXLP0 cp0 d1 vdd 0 sg13g2_inv_1\nXLN0 cn0 d1 s0 vdd 0 sg13g2_nand2b_1\nXDP0 bp0 cp0 vref 0 sg13g2_buf_1\nXDN0 bn0 cn0 vref 0 sg13g2_buf_1\nXCP1 topp bp1 cap_cmim w=5.111u l=5.111u\nXCN1 topn bn1 cap_cmim w=5.111u l=5.111u\nXLP1 cp1 d2 vdd 0 sg13g2_inv_1\nXLN1 cn1 d2 s1 vdd 0 sg13g2_nand2b_1\nXDP1 bp1 cp1 vref 0 sg13g2_buf_1\nXDN1 bn1 cn1 vref 0 sg13g2_buf_1\nXCP2 topp bp2 cap_cmim w=7.25u l=7.25u\nXCN2 topn bn2 cap_cmim w=7.25u l=7.25u\nXLP2 cp2 d3 vdd 0 sg13g2_inv_1\nXLN2 cn2 d3 s2 vdd 0 sg13g2_nand2b_1\nXDP2 bp2 cp2 vref 0 sg13g2_buf_1\nXDN2 bn2 cn2 vref 0 sg13g2_buf_1\nXCP3 topp bp3 cap_cmim w=10.275u l=10.275u\nXCN3 topn bn3 cap_cmim w=10.275u l=10.275u\nXLP3 cp3 d4 vdd 0 sg13g2_inv_1\nXLN3 cn3 d4 s3 vdd 0 sg13g2_nand2b_1\nXDP3 bp3 cp3 vref 0 sg13g2_buf_2\nXDN3 bn3 cn3 vref 0 sg13g2_buf_2\nXCP4 topp bp4 cap_cmim w=14.553u l=14.553u\nXCN4 topn bn4 cap_cmim w=14.553u l=14.553u\nXLP4 cp4 d5 vdd 0 sg13g2_inv_1\nXLN4 cn4 d5 s4 vdd 0 sg13g2_nand2b_1\nXDP4a bp4x cp4 vref 0 sg13g2_inv_2\nXDP4b bp4 bp4x vref 0 sg13g2_inv_4\nXDN4a bn4x cn4 vref 0 sg13g2_inv_2\nXDN4b bn4 bn4x vref 0 sg13g2_inv_4\n* one more unit on each side, on ground: each array is 2^(N-1) units\nXCPt topp 0 cap_cmim w=3.599u l=3.599u\nXCNt topn 0 cap_cmim w=3.599u l=3.599u\n* -- the comparator decides whether topp > topn: a 1\nXcmp topp topn clk ib dec vdd msar_cmp\nXsar clk sampn dec d5 d4 d3 d2 d1 d0 s5 s4 s3 s2 s1 s0 eoc vdd msar_logic\n.ends msar_adc\n* the testbench: supply, reference, the two inputs, the preamplifier's bias, the clock\nVdd vdd 0 1.2\nVref vref 0 1.2\nVip vip 0 755m\nVin vin 0 445m\nIb ib 0 20u\nVs samp 0 pwl(0 1.2 3n 1.2 3.05n 0)\nVclk clk 0 pulse(1.2 0 10n 50p 50p 4.95n 10n)\nXadc vip vin vref ib clk samp d5 d4 d3 d2 d1 d0 eoc vdd msar_adc\n.save v(samp) v(clk) v(xadc.topp) v(xadc.topn) v(xadc.dec) v(d0) v(d1) v(d2) v(d3) v(d4) v(d5) v(eoc) v(vdd) i(vdd) i(vref)\n.tran 250p 70n\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas tran vtop_p FIND v(xadc.topp) AT=5n\n.meas tran vtop_n FIND v(xadc.topn) AT=5n\n.end" } ], "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "5cfc8be214c5f43d461f51654eb94406102be9535ac7f7a113a0edbb16d11482" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/sar-monotonic.js", "sha256": "e068891330429f34e1bfd0923e7d42ff3fb60946c2743edd22fc46835c2f9e3d" }, "simulationFingerprints": { "convert": "61da9478964c4a41968f923ea7eb8c295ad22d9c0059c8136407aacc4ab08225" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "36960d3b00374a724861533b47882dfe4e83ad1e821d948176d420d571fc5ab0", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "sar-monotonic", "parameters": { "bits": 6, "Cu": 2e-14, "vid": 0.31, "vcm": 0.6, "vref": 1.2, "fclk": 100000000, "Wsw": 0.000001 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/sar-monotonic/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [], "scopes": [ { "id": "dut", "name": "msar_adc", "ports": [ { "name": "vip", "net": "vip", "kind": "input" }, { "name": "vin", "net": "vin", "kind": "input" }, { "name": "vref", "net": "vref", "kind": "bias" }, { "name": "ib", "net": "ib", "kind": "bias" }, { "name": "clk", "net": "clk", "kind": "clock" }, { "name": "samp", "net": "samp", "kind": "clock" }, { "name": "d5", "net": "d5", "kind": "output" }, { "name": "d4", "net": "d4", "kind": "output" }, { "name": "d3", "net": "d3", "kind": "output" }, { "name": "d2", "net": "d2", "kind": "output" }, { "name": "d1", "net": "d1", "kind": "output" }, { "name": "d0", "net": "d0", "kind": "output" }, { "name": "eoc", "net": "eoc", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" } ], "definitions": [], "devices": [ { "id": "XIs", "displayName": "Is", "spiceType": "X", "model": "sg13g2_inv_2", "parametersOrValue": "", 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l=19.417u", "source": "XR4 rp 0 0 rppd w=0.5u l=19.417u", "pins": [ { "id": "p", "net": "rp" }, { "id": "n", "net": "0" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XIck", "displayName": "Ick", "spiceType": "X", "model": "sg13g2_buf_2", "parametersOrValue": "", "source": "XIck clkd clk vdd 0 sg13g2_buf_2", "pins": [ { "id": "X", "net": "clkd" }, { "id": "A", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMt", "displayName": "Mt", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XMt ctail clkd vdd vdd sg13_lv_pmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "ctail" }, { "id": "g", "net": "clkd" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=16u l=260n ng=4 m=1", "source": "XM1 dip pn ctail vdd sg13_lv_pmos w=16u l=260n ng=4 m=1", "pins": [ { "id": "d", "net": "dip" }, { "id": "g", "net": "pn" }, { "id": "s", "net": "ctail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=16u l=260n ng=4 m=1", "source": "XM2 din pp ctail vdd sg13_lv_pmos w=16u l=260n ng=4 m=1", "pins": [ { "id": "d", "net": "din" }, { "id": "g", "net": "pp" }, { "id": "s", "net": "ctail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XM3 outp outn dip vdd sg13_lv_pmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "outn" }, { "id": "s", "net": "dip" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XM4 outn outp din vdd sg13_lv_pmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "outp" }, { "id": "s", "net": "din" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XM5 outp outn 0 0 sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "outn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XM6 outn outp 0 0 sg13_lv_nmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", 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"pinMeaning": "IHP standard-cell declared terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XPbd", "pin": "d" }, { "device": "XPbd", "pin": "g" }, { "device": "XPbt", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XPbd", "pin": "s" }, { "device": "XPbd", "pin": "b" }, { "device": "XPbt", "pin": "s" }, { "device": "XPbt", "pin": "b" }, { "device": "XP1", "pin": "b" }, { "device": "XP2", "pin": "b" }, { "device": "XIck", "pin": "VDD" }, { "device": "XMt", "pin": "s" }, { "device": "XMt", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "b" }, { "device": "XIkp", "pin": "VDD" }, { "device": "XIkn", "pin": "VDD" }, { "device": "XLs", "pin": "VDD" }, { "device": "XLr", "pin": "VDD" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "ptail", "ground": false, "terminals": [ { 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"s5" }, { "id": "A", "net": "conv" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XT4", "displayName": "T4", "spiceType": "X", "model": "sg13g2_dfrbpq_1", "parametersOrValue": "", "source": "XT4 s4 clk s5 conv vdd 0 sg13g2_dfrbpq_1", "pins": [ { "id": "Q", "net": "s4" }, { "id": "CLK", "net": "clk" }, { "id": "D", "net": "s5" }, { "id": "RESET_B", "net": "conv" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XT3", "displayName": "T3", "spiceType": "X", "model": "sg13g2_dfrbpq_1", "parametersOrValue": "", "source": "XT3 s3 clk s4 conv vdd 0 sg13g2_dfrbpq_1", "pins": [ { "id": "Q", "net": "s3" }, { "id": "CLK", "net": "clk" }, { "id": "D", "net": "s4" }, { "id": "RESET_B", "net": "conv" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { 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"net": "vref" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XCPt", "displayName": "CPt", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=3.599u l=3.599u", "source": "XCPt topp 0 cap_cmim w=3.599u l=3.599u", "pins": [ { "id": "p", "net": "topp" }, { "id": "n", "net": "0" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XCNt", "displayName": "CNt", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=3.599u l=3.599u", "source": "XCNt topn 0 cap_cmim w=3.599u l=3.599u", "pins": [ { "id": "p", "net": "topn" }, { "id": "n", "net": "0" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "Xcmp", "displayName": "Xcmp", "spiceType": "X", "model": "msar_cmp", "parametersOrValue": "", "source": "Xcmp topp topn clk ib dec vdd msar_cmp", "pins": [ { "id": "inp", "net": "topp" }, { "id": "inn", "net": "topn" }, { "id": "clk", "net": "clk" }, { "id": "ib", "net": "ib" }, { "id": "dec", "net": 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"terminals": [ { "device": "Xcmp", "pin": "clk" }, { "device": "Xsar", "pin": "clk" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Xcmp", "pin": "ib" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "dec", "ground": false, "terminals": [ { "device": "Xcmp", "pin": "dec" }, { "device": "Xsar", "pin": "dec" } ], "ports": [], "voltageReferences": [] }, { "id": "d0", "ground": false, "terminals": [ { "device": "Xsar", "pin": "d0" } ], "ports": [ "d0" ], "voltageReferences": [] }, { "id": "s5", "ground": false, "terminals": [ { "device": "Xsar", "pin": "s5" } ], "ports": [], "voltageReferences": [] }, { "id": "eoc", "ground": false, "terminals": [ { "device": "Xsar", "pin": "eoc" } ], "ports": [ "eoc" ], "voltageReferences": [] } ] }, { "id": "subckt/msar_cmp", "name": "msar_cmp", "ports": [ { "name": "inp", "net": "inp" }, { "name": "inn", "net": "inn" }, { "name": "clk", "net": "clk" }, { "name": "ib", "net": "ib" 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[ { "id": "X", "net": "clkd" }, { "id": "A", "net": "clk" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMt", "displayName": "Mt", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XMt ctail clkd vdd vdd sg13_lv_pmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "ctail" }, { "id": "g", "net": "clkd" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=16u l=260n ng=4 m=1", "source": "XM1 dip pn ctail vdd sg13_lv_pmos w=16u l=260n ng=4 m=1", "pins": [ { "id": "d", "net": "dip" }, { "id": "g", "net": "pn" }, { "id": "s", "net": "ctail" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": 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