{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "mixed-signal", "id": "sigma-delta", "name": "Sigma-delta modulator (first order)", "group": "Data converters", "subgroup": "ADCs", "title": "Sigma-delta modulator (first order)", "summary": "This modulator represents a slowly changing voltage as a stream of ones and zeros. Feedback makes the fraction of ones follow the input while moving much of the quantisation error to high frequencies. A separate digital filter is needed to produce lower-rate, multi-bit samples.", "reference": { "kind": "book", "authors": "S. Pavan, R. Schreier and G. C. Temes", "title": "Understanding Delta-Sigma Data Converters", "edition": "2nd ed.", "publisher": "Wiley-IEEE Press", "year": 2017, "where": "The first-order modulator - its loop, noise shaping and tones - and its discrete-time and continuous-time loop filters", "takes": "The loop, the result that the density of ones follows the input, the 20 dB/decade shaping of the quantisation noise, and the two ways of building the integrator.", "also": [ { "authors": "T. Chan Carusone, D. A. Johns and K. W. Martin", "title": "Analog Integrated Circuit Design", "edition": "2nd ed.", "year": 2012, "where": "Oversampling converters - first-order modulators and the switched-capacitor integrator" } ] }, "resources": { "record": "/circuits/sigma-delta.json", "page": "/index.html#sigma-delta", "achieved": "/achieved/sigma-delta.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" }, { "name": "sg13g2_stdcell.spice", "url": "/sg13g2_stdcell.spice", "sha256": "cfd805c964d3238b3342b5b1432522c3cf614d167b848d540a1499d1253ef3d4" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice", "sg13g2_stdcell.spice" ], "ports": [ { "name": "vin", "kind": "input" }, { "name": "vcm", "kind": "bias", "note": "the middle of the range, V_DD/2 (the bench derives it from the supply): the integrator's reference" }, { "name": "bn", "kind": "bias", "note": "the amplifiers' bias: the bench gives a current into Mb" }, { "name": "p1", "kind": "clock", "note": "discrete time: phase 1, sampling (p1b its complement)" }, { "name": "p1b", "kind": "clock", "note": "discrete time: externally supplied complement of p1; also clocks the decision flip-flop" }, { "name": "p2", "kind": "clock", "note": "discrete time: phase 2, integrating (p2b its complement)" }, { "name": "p2b", "kind": "clock", "note": "discrete time: externally supplied complement of p2" }, { "name": "clk", "kind": "clock", "note": "continuous time: the flip-flop's clock" }, { "name": "rst", "kind": "clock", "note": "high through the first period: C_i shorted (rstb clears the flip-flop)" }, { "name": "rstb", "kind": "clock", "note": "externally supplied complement of rst: active-low flip-flop reset and integrator reset-switch control" }, { "name": "q", "kind": "output", "note": "the bitstream" }, { "name": "vdd", "kind": "supply" }, { "name": "0", "kind": "ground" } ], "devices": [ { "name": "S1n", "type": "nmos", "sizedBy": [ "topology" ], "role": "discrete time: the input switch (with S1p)", "fingers": 1, "copies": 1 }, { "name": "S1p", "type": "pmos", "sizedBy": [ "topology" ], "role": "discrete time: the input switch (with S1n)", "fingers": 1, "copies": 1 }, { "name": "S2n", "type": "nmos", "sizedBy": [ "topology" ], "role": "discrete time: C_s's right plate to vcm in phase 1", "fingers": 1, "copies": 1 }, { "name": "S2p", "type": "pmos", "sizedBy": [ "topology" ], "role": "discrete time: C_s's right plate to vcm in phase 1", "fingers": 1, "copies": 1 }, { "name": "S4n", "type": "nmos", "sizedBy": [ "topology" ], "role": "discrete time: C_s's right plate to the summing node in phase 2", "fingers": 1, "copies": 1 }, { "name": "S4p", "type": "pmos", "sizedBy": [ "topology" ], "role": "discrete time: C_s's right plate to the summing node in phase 2", "fingers": 1, "copies": 1 }, { "name": "CS", "type": "capacitor", "sizedBy": [ "Cs", "topology" ], "role": "discrete time: the sampling capacitor" }, { "name": "GP", "type": "logic", "sizedBy": [ "topology" ], "role": "discrete time: turns MDP on in phase 2 when q = 1" }, { "name": "GN", "type": "logic", "sizedBy": [ "topology" ], "role": "discrete time: turns MDN on in phase 2 when q = 0" }, { "name": "MDP", "type": "pmos", "sizedBy": [ "topology" ], "role": "discrete time: the DAC's upper level, vdd", "fingers": 1, "copies": 1 }, { "name": "MDN", "type": "nmos", "sizedBy": [ "topology" ], "role": "discrete time: the DAC's lower level, ground", "fingers": 1, "copies": 1 }, { "name": "RIN", "type": "resistor", "sizedBy": [ "R", "topology" ], "role": "continuous time: the input into the summing node" }, { "name": "RDAC", "type": "resistor", "sizedBy": [ "R", "topology" ], "role": "continuous time: the DAC into the summing node" }, { "name": "GD", "type": "logic", "sizedBy": [ "topology" ], "role": "continuous time: the DAC, q's complement" }, { "name": "CI", "type": "capacitor", "sizedBy": [ "Ci" ], "role": "the integrating capacitor" }, { "name": "SRn", "type": "nmos", "sizedBy": [], "role": "shorts C_i through the first period (with SRp)", "fingers": 1, "copies": 1 }, { "name": "SRp", "type": "pmos", "sizedBy": [], "role": "shorts C_i through the first period (with SRn)", "fingers": 1, "copies": 1 }, { "name": "Mb", "type": "nmos", "sizedBy": [ "Ib" ], "role": "the bias diode, four 10/2 um units taking Ib: every current source is copies of that unit", "fingers": 2, "copies": 4 }, { "name": "Mt", "type": "nmos", "sizedBy": [ "Ib" ], "role": "the integrator amplifier's tail, four units: Ib", "fingers": 2, "copies": 4 }, { "name": "M1", "type": "nmos", "sizedBy": [], "role": "the integrator amplifier's input, on the summing node", "fingers": 4, "copies": 1 }, { "name": "M2", "type": "nmos", "sizedBy": [], "role": "the integrator amplifier's input, on vcm", "fingers": 4, "copies": 1 }, { "name": "M3", "type": "pmos", "sizedBy": [], "role": "first-stage load, diode side", "fingers": 4, "copies": 1 }, { "name": "M4", "type": "pmos", "sizedBy": [], "role": "first-stage load", "fingers": 4, "copies": 1 }, { "name": "M5", "type": "pmos", "sizedBy": [], "role": "second stage, eight copies of M3", "fingers": 4, "copies": 8 }, { "name": "M6", "type": "nmos", "sizedBy": [ "Ib" ], "role": "second-stage current sink, sixteen units: four times Ib", "fingers": 2, "copies": 16 }, { "name": "CC", "type": "capacitor", "sizedBy": [], "role": "Miller compensation" }, { "name": "RZ", "type": "resistor", "sizedBy": [], "role": "nulling resistor" }, { "name": "MQT", "type": "nmos", "sizedBy": [ "Ib" ], "role": "the comparator's tail, one unit: a quarter of Ib", "fingers": 2, "copies": 1 }, { "name": "MQ1", "type": "nmos", "sizedBy": [], "role": "comparator input, diode side", "fingers": 1, "copies": 1 }, { "name": "MQ2", "type": "nmos", "sizedBy": [], "role": "comparator input, output side", "fingers": 1, "copies": 1 }, { "name": "MQ3", "type": "pmos", "sizedBy": [], "role": "comparator load, diode side", "fingers": 1, "copies": 1 }, { "name": "MQ4", "type": "pmos", "sizedBy": [], "role": "comparator load", "fingers": 1, "copies": 1 }, { "name": "IQ", "type": "logic", "sizedBy": [], "role": "squares the comparator's output" }, { "name": "FQ", "type": "logic", "sizedBy": [], "role": "the flip-flop: one decision per clock, held for the DAC" } ], "intent": [ { "rule": "loop-average", "of": [ "CI", "FQ", "MDP", "MDN", "RDAC" ], "constraint": "ideal long-run density = V_in / V_DD", "why": "A bounded ideal integrator requires the input and feedback to balance on average. With the intended DAC levels and V_cm = V_DD/2, both versions therefore approach density V_in/V_DD: 0.45 V at 1.2 V corresponds to 24 ones per 64 bits. Counting N bits gives voltage increments V_DD/N, not guaranteed accuracy: the finite window retains a state-dependent error, and circuit nonidealities add errors." }, { "rule": "integrator-step", "of": [ "CS", "CI", "RIN" ], "constraint": "C_s/C_i = T/(R C_i) = 1/4", "why": "The ideal discrete-time change is +(C_s/C_i)(V_in - V_DD q). With V_cm = V_DD/2, the continuous-time change over a held-bit period is approximately -(T/(R C_i))(V_in - V_DD q): its complemented DAC and reversed comparator polarity preserve negative feedback. Both gain magnitudes are 1/4 here. At 0.45 V, the discrete-time steps are +112.5 mV for q = 0 and -187.5 mV for q = 1; continuous time reverses those signs. Real operation also needs amplifier headroom, bandwidth and settling." }, { "rule": "settling", "of": [ "M1", "M2", "M5", "M6", "CC", "RZ" ], "constraint": "settled within half a clock period", "why": "In discrete time the amplifier has phase 2, 9 ns, to take C_s's charge, and must then hold through phase 1. At 80 µA with C_c = 0.5 pF it moves under 2 mV over the last 2 ns of phase 2 and under 1.5 mV through phase 1; hot and slow with the supply 10 % low, 6 and 2 mV, where with its tail in triode it moved 15 and 12 mV. At 40 µA with 1 pF it was still drifting 20 mV through the phase in which it should hold." }, { "rule": "bias-headroom", "of": [ "Mb", "Mt", "M6", "MQT", "M1", "M2" ], "constraint": "every current source saturated: 20 uA per 10/2 um unit", "why": "The first stage stacks M3's V_SG, M1 and Mt from V_DD to ground with its inputs at vcm, 0.6 V, so Mt has vcm - V_GS1 to work in. One 5/2 um unit carrying all 80 µA needed 0.36 V of it: Mt ran in triode at 64 µA and the comparator's tail at 53 µA, their currents set by what the inputs left them rather than by the mirror. Four units for Mb and Mt, sixteen for M6 and one, a quarter of Ib, for the comparator, with 20/1 um inputs and loads, leave Mt 0.10 V and MQT 0.06 V above saturation, and every current source still saturated hot and slow with the supply 10 % low." }, { "rule": "non-overlap", "of": [ "S1n", "S1p", "S2n", "S2p", "S4n", "S4p" ], "constraint": "phases 1 and 2 never both high", "why": "With phase 1 and phase 2 closed at once, C_s would join V_in to the summing node directly and charge would be lost. The bench leaves 1 ns between them." }, { "rule": "dt-or-ct", "of": [ "RIN", "RDAC", "S1n", "CS" ], "why": "Discrete time samples at S1, so out-of-band signals can alias and may need an input filter. Its ideal step uses the capacitor ratio C_s/C_i. Continuous time filters the input before the flip-flop samples; this provides some inherent anti-alias attenuation, not immunity to aliasing or overload. Its step depends on the absolute R C_i product, whose process variation needs checking, and DAC pulse timing makes clock jitter important. With equal resistors, the continuous-time loop balances average V_dac = 2 V_cm - V_in; density V_in/V_DD therefore needs V_cm = V_DD/2. The ideal discrete-time charge difference cancels V_cm, but the switches and amplifier must still remain within their operating ranges." }, { "rule": "quantiser", "of": [ "MQ1", "MQ2", "IQ", "FQ" ], "why": "Feedback makes a one-bit decision useful without a precision multi-bit quantiser. In a linearised loop model, small errors added at the quantiser are suppressed at low frequencies. This does not make arbitrary comparator errors harmless: offset can shift the integrator's operating range, and insufficient gain or settling can cause late or incorrect decisions. The comparator must deliver a valid logic level before the flip-flop samples, and the flip-flop holds that decision for the DAC." } ], "specs": [ { "key": "density", "label": "Density of ones against V_in / V_DD", "unit": "", "direction": "target" }, { "key": "sqnr", "label": "Estimated in-band signal-to-residual ratio", "unit": "dB", "direction": "max" }, { "key": "swing", "label": "Integrator swing", "unit": "V", "direction": "min" } ], "explanation": { "idea": "This modulator represents a slowly changing voltage as a stream of ones and zeros. Feedback makes the fraction of ones follow the input while moving much of the quantisation error to high frequencies. A separate digital filter is needed to produce lower-rate, multi-bit samples.", "detail": "Turns a slowly varying input into a stream of one-bit decisions whose long-term density of ones approaches V_in/V_DD. An integrator accumulates the difference between the input and a one-bit DAC, and a comparator on the integrator's output picks the next decision each clock. The discrete-time DAC feeds back V_DD or ground directly; the continuous-time circuit uses the complemented bit and V_cm = V_DD/2. The integrator stays bounded only when average feedback balances the input. In the ideal first-order model, quantisation error is differentiated, reducing its low-frequency content. A digital decimation filter averages sampled bits, not the analog area of their voltage pulses.", "lesson": { "relation": 0, "symbols": "n_1 is the number of one bits; N is the number of sampled bits; V_in is the input voltage; V_DD is the supply and feedback scale.", "assumptions": "The input is constant during counting, the loop has settled and remains bounded, and the feedback levels are ground and supply. The continuous-time version also needs V_cm = V_DD/2. Finite counts approximate the long-term density.", "exercise": { "param": "vin", "value": 0.6, "analysis": "dc", "expect": "The fraction of one bits should move towards one half at the nominal 1.2 V supply. Compare V_DD times the sampled-bit density with the input, rather than the analog pulse-voltage average." }, "limits": "External clocks, reset, bias and V_cm generation are required. The 128-sample spectrum is an estimated signal-to-residual ratio including deterministic errors, not isolated quantisation noise or complete physical-noise characterization. A production converter also needs a digital filter and a wider input, settling and aliasing study." }, "path": [ { "part": "Sample (phase 1)", "devices": "S1n, S1p, S2n, S2p, CS", "does": "In phase 1, S1 puts V_in on C_s's left plate and S2 holds the right one at V_cm, storing C_s·(V_in − V_cm)." }, { "part": "DAC and transfer (phase 2)", "devices": "GP, GN, MDP, MDN, S4n, S4p", "does": "In phase 2 MDP or MDN puts the left plate at vdd (q = 1) or ground, S4 joins the right to sum, and C_s·(V_in − V_dac) moves into C_i." }, { "part": "Integrator", "devices": "M1, M2, M3, M4, M5, M6, CC, RZ, CI", "does": "M1–M6 form a two-stage Miller amplifier (CC, RZ) that holds sum at V_cm, so each period steps v_o by (C_s/C_i)·(V_in − V_dac); it must settle within phase 2." }, { "part": "Quantiser", "devices": "MQT, MQ1, MQ2, MQ3, MQ4, IQ, FQ", "does": "MQ1–MQ4 compare v_o with V_cm, IQ squares the result, and FQ, clocked as phase 1 ends, holds q for the DAC: q = 1 when v_o is above V_cm." }, { "part": "Continuous-time option", "devices": "RIN, RDAC, GD", "does": "With Loop filter at continuous time, RIN and RDAC feed V_in and GD's complement of q into sum all the time; the comparator's inputs swap, and FQ samples on clk." }, { "part": "Reset", "devices": "SRn, SRp", "does": "SRn and SRp short C_i through the first period, so each run starts with v_o at V_cm, while rstb holds FQ cleared." } ], "bias": "Ib, 80 µA by default, flows into Mb, four 10/2 µm units; the integrator's tail Mt, four units, copies it, its second stage M6, sixteen units, four times over, and the comparator's tail MQT, one unit, a quarter of it, all saturated. V_cm, V_DD/2 from the bench, is the integrator's reference and the comparator's threshold. The period is 20 ns: two non-overlapping 9 ns phases in discrete time, one flip-flop edge in continuous time.", "relations": [ { "what": "Density of ones", "expr": "n_1/N ≈ V_in/V_DD", "note": "for a settled, bounded loop and a constant input; finite counts only approximate the long-term balance. At the nominal default, 24 ones in 64 represent 0.45 V." }, { "what": "Integrator step", "expr": "Δv_o = (C_s/C_i)·(V_in − V_DD·q)", "note": "discrete time, assuming ideal charge transfer and settling. In continuous time, dv_o/dt = −(V_in − V_DD·q)/(R·C_i) when V_cm = V_DD/2; the comparator polarity reverses too. C_s/C_i and T/(R·C_i) are both 1/4 by default." }, { "what": "Noise transfer", "expr": "NTF(z) = 1 − z^(−1)", "note": "the normalized ideal first-order model: the input passes delayed and low-frequency quantisation error is differentiated, rising approximately 20 dB per decade. This is a teaching model, not an extracted transfer function of either transistor circuit." }, { "what": "In-band quantisation noise", "expr": "P_q ≈ (Δ^2/12)·(π^2/3)·OSR^(−3)", "note": "ideal additive-white-quantisation-error approximation, with Δ = V_DD and OSR the sampling rate divided by twice the signal bandwidth; each doubling of OSR predicts about 9 dB. A real first-order bitstream can contain tones, so the finite-record result need not follow this exactly." }, { "what": "Averaging", "expr": "δV = V_DD/N", "note": "spacing of the values available from an N-bit count; this is not a guarantee of total input accuracy or effective resolution" } ], "tradeoffs": [ "C_s (discrete time): a larger C_s lowers kT/C noise and enlarges each step C_s/C_i, but loads the amplifier, which must still settle within phase 2.", "C_i: a larger C_i shrinks the integrator's swing and keeps the amplifier linear, at the cost of area and a smaller signal at the comparator.", "Amplifier bias: more current settles C_s's charge sooner in phase 2 but needs more V_DS for the tail below inputs at V_cm; less saves power until the integrator is still drifting when the comparator decides.", "Loop filter: discrete time rests on C_s/C_i and needs input anti-alias filtering. Continuous-time integration attenuates some out-of-band input before sampling, but does not guarantee enough alias rejection; its dynamics depend on R·C_i and DAC timing.", "Integration: the bench supplies p1/p1b and p2/p2b in discrete time, clk in continuous time, and rst/rstb in both. A physical implementation needs the appropriate clock, non-overlap and reset generation, plus bias and V_cm circuits; their nonideal behavior is not established by ideal bench sources." ] }, "sizing": [ { "key": "topology", "label": "Loop filter", "unit": "", "value": "dt", "kind": "choice", "choices": [ [ "dt", "discrete time (switched capacitors)" ], [ "ct", "continuous time (resistors)" ] ] }, { "key": "vin", "label": "V_in (the DC bench)", "unit": "V", "value": 0.45, "min": 0.05, "max": 1.15, "kind": "si" }, { "key": "amp", "label": "Sine amplitude (the spectrum bench)", "unit": "V", "value": 0.4, "min": 0.05, "max": 0.55, "kind": "si" }, { "key": "Cs", "label": "C_s (discrete time)", "unit": "F", "value": 2.5e-13, "min": 5e-14, "max": 1e-12, "kind": "si" }, { "key": "R", "label": "R (continuous time)", "unit": "Ω", "value": 80000, "min": 20000, "max": 400000, "kind": "si" }, { "key": "Ci", "label": "C_i", "unit": "F", "value": 1e-12, "min": 2e-13, "max": 5e-12, "kind": "si" }, { "key": "Ib", "label": "Amplifier bias", "unit": "A", "value": 0.00008, "min": 0.00001, "max": 0.0002, "kind": "si" } ], "testbenches": [ { "id": "dc", "label": "A DC input", "note": "64 clock periods with every transistor simulated: 10-15 s in the browser.", "measures": [ "density", "swing" ], "metricKeys": [ "density", "estimate", "swing" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice", "sg13g2_stdcell.spice" ], "netlist": "* First-order sigma-delta modulator, discrete time - a DC input for 64 clocks\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.include sg13g2_stdcell.spice\nVdd vdd 0 1.2\n* vcm is half the supply, as a divider on chip would make it: the continuous-\n* time loop balances where its DAC averages 2 vcm - vin, so its density of\n* ones is vin / V_DD only while vcm = V_DD / 2\nEcm vcm 0 vdd 0 0.5\nIb vdd bn 80u\nVin vin 0 450m\n* two phases that never overlap: 1 in the first half of each period, 2 in the second\nVp1 p1 0 PULSE(0 1.2 0 200p 200p 9n 20n)\nVp1b p1b 0 PULSE(1.2 0 0 200p 200p 9n 20n)\nVp2 p2 0 PULSE(0 1.2 10n 200p 200p 9n 20n)\nVp2b p2b 0 PULSE(1.2 0 10n 200p 200p 9n 20n)\n* reset through the first period: C_i shorted, the flip-flop cleared\nVrst rst 0 PWL(0 1.2 18n 1.2 20n 0)\nVrstb rstb 0 PWL(0 0 18n 0 20n 1.2)\n* the loop filter, discrete time: C_s takes vin - vcm in phase 1 and puts\n* vin - v_dac into C_i in phase 2; the switches are transmission gates\nXS1n vin p1 l 0 sg13_lv_nmos w=1u l=130n ng=1 m=1\nXS1p vin p1b l vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\nXS2n r p1 vcm 0 sg13_lv_nmos w=1u l=130n ng=1 m=1\nXS2p r p1b vcm vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\nXS4n r p2 sum 0 sg13_lv_nmos w=1u l=130n ng=1 m=1\nXS4p r p2b sum vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\nXCS l r cap_cmim w=12.857u l=12.857u\n* the DAC: in phase 2 the left plate goes to vdd when q = 1, to ground when q = 0\nXGP dp p2 q vdd 0 sg13g2_nand2_1\nXGN dn p2b q vdd 0 sg13g2_nor2_1\nXMDP l dp vdd vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\nXMDN l dn 0 0 sg13_lv_nmos w=1u l=130n ng=1 m=1\n* the integrator: a two-stage amplifier with C_i from its output back to sum,\n* shorted through the first clock period so every run starts from vcm\nXCI sum vo cap_cmim w=25.767u l=25.767u\nXSRn sum rst vo 0 sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSRp sum rstb vo vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\n* Mb is four bias units taking Ib; Mt copies it to the tail, M6 (sixteen\n* units) four times over to the second stage, MQT (one) a quarter of it to\n* the comparator. At 20 uA a unit they stay saturated - Mt with 0.1 V to\n* spare with vcm on the inputs - where one 5/2 um unit at the whole 80 uA\n* needed 0.36 V and Mt ran in triode at 64 uA, the comparator's tail at 53.\nXMb bn bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=4\nXMt tail bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=4\nXM1 n1 sum tail 0 sg13_lv_nmos w=20u l=1u ng=4 m=1\nXM2 n2 vcm tail 0 sg13_lv_nmos w=20u l=1u ng=4 m=1\nXM3 n1 n1 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM4 n2 n1 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM5 vo n2 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=8\nXM6 vo bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=16\nXCC n2 nz cap_cmim w=18.204u l=18.204u\nXRZ nz vo 0 rppd w=0.5u l=2.678u\n* the quantiser: a comparator between vo and vcm, squared by an inverter, and a\n* flip-flop that takes the decision on the clock's rising edge\nXMQT qs bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=1\nXMQ1 qx vcm qs 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXMQ2 qo vo qs 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXMQ3 qx qx vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXMQ4 qo qx vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXIQ qd qo vdd 0 sg13g2_inv_1\nXFQ q p1b qd rstb vdd 0 sg13g2_dfrbpq_1\n.save v(vin) v(vo) v(q) v(sum) v(vdd) i(vdd)\n.tran 250p 1.3u\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas tran qavg AVG v(q) FROM=30n TO=1.29u\n.end" }, { "id": "sine", "label": "A sine, and its spectrum", "note": "128 clock periods with every transistor simulated: 15-20 s in the browser.", "measures": [ "sqnr" ], "metricKeys": [ "sqnr_osr4", "sqnr_osr8" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice", "sg13g2_stdcell.spice" ], "netlist": "* First-order sigma-delta modulator, discrete time - a sine for 128 clocks\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.include sg13g2_stdcell.spice\nVdd vdd 0 1.2\n* vcm is half the supply, as a divider on chip would make it: the continuous-\n* time loop balances where its DAC averages 2 vcm - vin, so its density of\n* ones is vin / V_DD only while vcm = V_DD / 2\nEcm vcm 0 vdd 0 0.5\nIb vdd bn 80u\nVin vin vcm SIN(0 400m 1.17188meg 20n)\n* two phases that never overlap: 1 in the first half of each period, 2 in the second\nVp1 p1 0 PULSE(0 1.2 0 200p 200p 9n 20n)\nVp1b p1b 0 PULSE(1.2 0 0 200p 200p 9n 20n)\nVp2 p2 0 PULSE(0 1.2 10n 200p 200p 9n 20n)\nVp2b p2b 0 PULSE(1.2 0 10n 200p 200p 9n 20n)\n* reset through the first period: C_i shorted, the flip-flop cleared\nVrst rst 0 PWL(0 1.2 18n 1.2 20n 0)\nVrstb rstb 0 PWL(0 0 18n 0 20n 1.2)\n* the loop filter, discrete time: C_s takes vin - vcm in phase 1 and puts\n* vin - v_dac into C_i in phase 2; the switches are transmission gates\nXS1n vin p1 l 0 sg13_lv_nmos w=1u l=130n ng=1 m=1\nXS1p vin p1b l vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\nXS2n r p1 vcm 0 sg13_lv_nmos w=1u l=130n ng=1 m=1\nXS2p r p1b vcm vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\nXS4n r p2 sum 0 sg13_lv_nmos w=1u l=130n ng=1 m=1\nXS4p r p2b sum vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\nXCS l r cap_cmim w=12.857u l=12.857u\n* the DAC: in phase 2 the left plate goes to vdd when q = 1, to ground when q = 0\nXGP dp p2 q vdd 0 sg13g2_nand2_1\nXGN dn p2b q vdd 0 sg13g2_nor2_1\nXMDP l dp vdd vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\nXMDN l dn 0 0 sg13_lv_nmos w=1u l=130n ng=1 m=1\n* the integrator: a two-stage amplifier with C_i from its output back to sum,\n* shorted through the first clock period so every run starts from vcm\nXCI sum vo cap_cmim w=25.767u l=25.767u\nXSRn sum rst vo 0 sg13_lv_nmos w=1u l=130n ng=1 m=1\nXSRp sum rstb vo vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\n* Mb is four bias units taking Ib; Mt copies it to the tail, M6 (sixteen\n* units) four times over to the second stage, MQT (one) a quarter of it to\n* the comparator. At 20 uA a unit they stay saturated - Mt with 0.1 V to\n* spare with vcm on the inputs - where one 5/2 um unit at the whole 80 uA\n* needed 0.36 V and Mt ran in triode at 64 uA, the comparator's tail at 53.\nXMb bn bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=4\nXMt tail bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=4\nXM1 n1 sum tail 0 sg13_lv_nmos w=20u l=1u ng=4 m=1\nXM2 n2 vcm tail 0 sg13_lv_nmos w=20u l=1u ng=4 m=1\nXM3 n1 n1 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM4 n2 n1 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=1\nXM5 vo n2 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=8\nXM6 vo bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=16\nXCC n2 nz cap_cmim w=18.204u l=18.204u\nXRZ nz vo 0 rppd w=0.5u l=2.678u\n* the quantiser: a comparator between vo and vcm, squared by an inverter, and a\n* flip-flop that takes the decision on the clock's rising edge\nXMQT qs bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=1\nXMQ1 qx vcm qs 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXMQ2 qo vo qs 0 sg13_lv_nmos w=4u l=500n ng=1 m=1\nXMQ3 qx qx vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXMQ4 qo qx vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1\nXIQ qd qo vdd 0 sg13g2_inv_1\nXFQ q p1b qd rstb vdd 0 sg13g2_dfrbpq_1\n.save v(vin) v(vo) v(q) v(sum) v(vdd) i(vdd)\n.tran 250p 2.58u\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas tran qavg AVG v(q) FROM=30n TO=2.57u\n.end" } ], "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "1108eb16c4dfb9aee2f36189aebbc30b48a7f67a8701c11fe5e84870cd412af4" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/sigma-delta.js", "sha256": "365169aa066285809a70fbf515055cd2962d58294ce1bf79429b3f1faa6c0046" }, "simulationFingerprints": { "dc": "909fd7856e5870284e05a270635117ae4960191b9b40430e7e26bbab61e5d434", "sine": "6ef0f3542cbb56eb2df3cc24471e93c3b147f43213c92e177c55051d2a45318c" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "b5776f3f7e718f147c0370538e281897a4fb9b4ba2477294d89649cebbd1a4e3", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "sigma-delta", "parameters": { "topology": "dt", "vin": 0.45, "amp": 0.4, "Cs": 2.5e-13, "R": 80000, "Ci": 1e-12, "Ib": 0.00008 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [ { "key": "topology", "selected": "dt", "choices": [ { "value": "dt", "label": "discrete time (switched capacitors)" }, { "value": "ct", "label": "continuous time (resistors)" } ] } ], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/sigma-delta/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [], "scopes": [ { "id": "dut", "name": "top", "ports": [ { "name": "vin", "net": "vin", "kind": "input" }, { "name": "p1", "net": "p1", "kind": "clock" }, { "name": "gnd", "net": "0", "kind": "ground" }, { "name": "p1b", "net": "p1b", "kind": "clock" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vcm", "net": "vcm", "kind": "bias" }, { "name": "p2", "net": "p2", "kind": "clock" }, { "name": "p2b", "net": "p2b", "kind": "clock" }, { "name": "q", "net": "q", "kind": "output" }, { "name": "rst", "net": "rst", "kind": "clock" }, { "name": "rstb", "net": "rstb", "kind": "clock" }, { "name": "bn", "net": "bn", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XS1n", "displayName": "S1n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XS1n vin p1 l 0 sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "p1" }, { "id": "s", "net": "l" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS1p", "displayName": "S1p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS1p vin p1b l vdd sg13_lv_pmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "p1b" }, { "id": "s", "net": "l" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS2n", "displayName": "S2n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XS2n r p1 vcm 0 sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "r" }, { "id": "g", "net": "p1" }, { "id": "s", "net": "vcm" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS2p", "displayName": "S2p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS2p r p1b vcm vdd sg13_lv_pmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "r" }, { "id": "g", "net": "p1b" }, { "id": "s", "net": "vcm" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS4n", "displayName": "S4n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XS4n r p2 sum 0 sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "r" }, { "id": "g", "net": "p2" }, { "id": "s", "net": "sum" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS4p", "displayName": "S4p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS4p r p2b sum vdd sg13_lv_pmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "r" }, { "id": "g", "net": "p2b" }, { "id": "s", "net": "sum" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCS", "displayName": "CS", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=12.857u l=12.857u", "source": "XCS l r cap_cmim w=12.857u l=12.857u", "pins": [ { "id": "p", "net": "l" }, { "id": "n", "net": "r" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XGP", "displayName": "GP", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XGP dp p2 q vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "dp" }, { "id": "A", "net": "p2" }, { "id": "B", "net": "q" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XGN", "displayName": "GN", "spiceType": "X", "model": "sg13g2_nor2_1", "parametersOrValue": "", "source": "XGN dn p2b q vdd 0 sg13g2_nor2_1", "pins": [ { "id": "Y", "net": "dn" }, { "id": "A", "net": "p2b" }, { "id": "B", "net": "q" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMDP", "displayName": "MDP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XMDP l dp vdd vdd sg13_lv_pmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "l" }, { "id": "g", "net": "dp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMDN", "displayName": "MDN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XMDN l dn 0 0 sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "l" }, { "id": "g", "net": "dn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCI", "displayName": "CI", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u", "source": "XCI sum vo cap_cmim w=25.767u l=25.767u", "pins": [ { "id": "p", "net": "sum" }, { "id": "n", "net": "vo" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XSRn", "displayName": "SRn", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSRn sum rst vo 0 sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "sum" }, { "id": "g", "net": "rst" }, { "id": "s", "net": "vo" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSRp", "displayName": "SRp", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSRp sum rstb vo vdd sg13_lv_pmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "sum" }, { "id": "g", "net": "rstb" }, { "id": "s", "net": "vo" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMb", "displayName": "Mb", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XMb bn bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "bn" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMt", "displayName": "Mt", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XMt tail bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM1 n1 sum tail 0 sg13_lv_nmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n1" }, { "id": "g", "net": "sum" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM2 n2 vcm tail 0 sg13_lv_nmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n2" }, { "id": "g", "net": "vcm" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM3 n1 n1 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n1" }, { "id": "g", "net": "n1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM4 n2 n1 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n2" }, { "id": "g", "net": "n1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=8", "source": "XM5 vo n2 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=8", "pins": [ { "id": "d", "net": "vo" }, { "id": "g", "net": "n2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=16", "source": "XM6 vo bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=16", "pins": [ { "id": "d", "net": "vo" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC", "displayName": "CC", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=18.204u l=18.204u", "source": "XCC n2 nz cap_cmim w=18.204u l=18.204u", "pins": [ { "id": "p", "net": "n2" }, { "id": "n", "net": "nz" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ", "displayName": "RZ", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=2.678u", "source": "XRZ nz vo 0 rppd w=0.5u l=2.678u", "pins": [ { "id": "p", "net": "nz" }, { "id": "n", "net": "vo" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMQT", "displayName": "MQT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMQT qs bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "qs" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMQ1", "displayName": "MQ1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMQ1 qx vcm qs 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "qx" }, { "id": "g", "net": "vcm" }, { "id": "s", "net": "qs" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMQ2", "displayName": "MQ2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMQ2 qo vo qs 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "qo" }, { "id": "g", "net": "vo" }, { "id": "s", "net": "qs" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMQ3", "displayName": "MQ3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMQ3 qx qx vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "qx" }, { "id": "g", "net": "qx" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMQ4", "displayName": "MQ4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMQ4 qo qx vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "qo" }, { "id": "g", "net": "qx" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XIQ", "displayName": "IQ", "spiceType": "X", "model": "sg13g2_inv_1", "parametersOrValue": "", "source": "XIQ qd qo vdd 0 sg13g2_inv_1", "pins": [ { "id": "Y", "net": "qd" }, { "id": "A", "net": "qo" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XFQ", "displayName": "FQ", "spiceType": "X", "model": "sg13g2_dfrbpq_1", "parametersOrValue": "", "source": "XFQ q p1b qd rstb vdd 0 sg13g2_dfrbpq_1", "pins": [ { "id": "Q", "net": "q" }, { "id": "CLK", "net": "p1b" }, { "id": "D", "net": "qd" }, { "id": "RESET_B", "net": "rstb" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" } ], "nets": [ { "id": "vin", "ground": false, "terminals": [ { "device": "XS1n", "pin": "d" }, { "device": "XS1p", "pin": "d" } ], "ports": [ "vin" ], "voltageReferences": [] }, { "id": "p1", "ground": false, "terminals": [ { "device": "XS1n", "pin": "g" }, { "device": "XS2n", "pin": "g" } ], "ports": [ "p1" ], "voltageReferences": [] }, { "id": "l", "ground": false, "terminals": [ { "device": "XS1n", "pin": "s" }, { "device": "XS1p", "pin": "s" }, { "device": "XCS", "pin": "p" }, { "device": "XMDP", "pin": "d" }, { "device": "XMDN", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "XS1n", "pin": "b" }, { "device": "XS2n", "pin": "b" }, { "device": "XS4n", "pin": "b" }, { "device": "XGP", "pin": "VSS" }, { "device": "XGN", "pin": "VSS" }, { "device": "XMDN", "pin": "s" }, { "device": "XMDN", "pin": "b" }, { "device": "XSRn", "pin": "b" }, { "device": "XMb", "pin": "s" }, { "device": "XMb", "pin": "b" }, { "device": "XMt", "pin": "s" }, { "device": "XMt", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XRZ", "pin": "substrate" }, { "device": "XMQT", "pin": "s" }, { "device": "XMQT", "pin": "b" }, { "device": "XMQ1", "pin": "b" }, { "device": "XMQ2", "pin": "b" }, { "device": "XIQ", "pin": "VSS" }, { "device": "XFQ", "pin": "VSS" } ], "ports": [ "gnd" ], "voltageReferences": [] }, { "id": "p1b", "ground": false, "terminals": [ { "device": "XS1p", "pin": "g" }, { "device": "XS2p", "pin": "g" }, { "device": "XFQ", "pin": "CLK" } ], "ports": [ "p1b" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XS1p", "pin": "b" }, { "device": "XS2p", "pin": "b" }, { "device": "XS4p", "pin": "b" }, { "device": "XGP", "pin": "VDD" }, { "device": "XGN", "pin": "VDD" }, { "device": "XMDP", "pin": "s" }, { "device": "XMDP", "pin": "b" }, { "device": "XSRp", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XMQ3", "pin": "s" }, { "device": "XMQ3", "pin": "b" }, { "device": "XMQ4", "pin": "s" }, { "device": "XMQ4", "pin": "b" }, { "device": "XIQ", "pin": "VDD" }, { "device": "XFQ", "pin": "VDD" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "r", "ground": false, "terminals": [ { "device": "XS2n", "pin": "d" }, { "device": "XS2p", "pin": "d" }, { "device": "XS4n", "pin": "d" }, { "device": "XS4p", "pin": "d" }, { "device": "XCS", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "vcm", "ground": false, "terminals": [ { "device": "XS2n", "pin": "s" }, { "device": "XS2p", "pin": "s" }, { "device": "XM2", "pin": "g" }, { "device": "XMQ1", "pin": "g" } ], "ports": [ "vcm" ], "voltageReferences": [] }, { "id": "p2", "ground": false, "terminals": [ { "device": "XS4n", "pin": "g" }, { "device": "XGP", "pin": "A" } ], "ports": [ "p2" ], "voltageReferences": [] }, { "id": "sum", "ground": false, "terminals": [ { "device": "XS4n", "pin": "s" }, { "device": "XS4p", "pin": "s" }, { "device": "XCI", "pin": "p" }, { "device": "XSRn", "pin": "d" }, { "device": "XSRp", "pin": "d" }, { "device": "XM1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "p2b", "ground": false, "terminals": [ { "device": "XS4p", "pin": "g" }, { "device": "XGN", "pin": "A" } ], "ports": [ "p2b" ], "voltageReferences": [] }, { "id": "dp", "ground": false, "terminals": [ { "device": "XGP", "pin": "Y" }, { "device": "XMDP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "q", "ground": false, "terminals": [ { "device": "XGP", "pin": "B" }, { "device": "XGN", "pin": "B" }, { "device": "XFQ", "pin": "Q" } ], "ports": [ "q" ], "voltageReferences": [] }, { "id": "dn", "ground": false, "terminals": [ { "device": "XGN", "pin": "Y" }, { "device": "XMDN", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vo", "ground": false, "terminals": [ { "device": "XCI", "pin": "n" }, { "device": "XSRn", "pin": "s" }, { "device": "XSRp", "pin": "s" }, { "device": "XM5", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XRZ", "pin": "n" }, { "device": "XMQ2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rst", "ground": false, "terminals": [ { "device": "XSRn", "pin": "g" } ], "ports": [ "rst" ], "voltageReferences": [] }, { "id": "rstb", "ground": false, "terminals": [ { "device": "XSRp", "pin": "g" }, { "device": "XFQ", "pin": "RESET_B" } ], "ports": [ "rstb" ], "voltageReferences": [] }, { "id": "bn", "ground": false, "terminals": [ { "device": "XMb", "pin": "d" }, { "device": "XMb", "pin": "g" }, { "device": "XMt", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XMQT", "pin": "g" } ], "ports": [ "bn" ], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMt", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "n1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "n2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XCC", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "nz", "ground": false, "terminals": [ { "device": "XCC", "pin": "n" }, { "device": "XRZ", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "qs", "ground": false, "terminals": [ { "device": "XMQT", "pin": "d" }, { "device": "XMQ1", "pin": "s" }, { "device": "XMQ2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "qx", "ground": false, "terminals": [ { "device": "XMQ1", "pin": "d" }, { "device": "XMQ3", "pin": "d" }, { "device": "XMQ3", "pin": "g" }, { "device": "XMQ4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "qo", "ground": false, "terminals": [ { "device": "XMQ2", "pin": "d" }, { "device": "XMQ4", "pin": "d" }, { "device": "XIQ", "pin": "A" } ], "ports": [], "voltageReferences": [] }, { "id": "qd", "ground": false, "terminals": [ { "device": "XIQ", "pin": "Y" }, { "device": "XFQ", "pin": "D" } ], "ports": [], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "1.2", "source": "Vdd vdd 0 1.2", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ecm", "displayName": "Ecm", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Ecm vcm 0 vdd 0 0.5", "pins": [ { "id": "p", "net": "vcm" }, { "id": "n", "net": "0" }, { "id": "cp", "net": "vdd" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "80u", "source": "Ib vdd bn 80u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "bn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "450m", "source": "Vin vin 0 450m", "pins": [ { "id": "p", "net": "vin" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vp1", "displayName": "Vp1", "spiceType": "V", "model": null, "parametersOrValue": "PULSE(0 1.2 0 200p 200p 9n 20n)", "source": "Vp1 p1 0 PULSE(0 1.2 0 200p 200p 9n 20n)", "pins": [ { "id": "p", "net": "p1" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vp1b", "displayName": "Vp1b", "spiceType": "V", "model": null, "parametersOrValue": "PULSE(1.2 0 0 200p 200p 9n 20n)", "source": "Vp1b p1b 0 PULSE(1.2 0 0 200p 200p 9n 20n)", "pins": [ { "id": "p", "net": "p1b" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vp2", "displayName": "Vp2", "spiceType": "V", "model": null, "parametersOrValue": "PULSE(0 1.2 10n 200p 200p 9n 20n)", "source": "Vp2 p2 0 PULSE(0 1.2 10n 200p 200p 9n 20n)", "pins": [ { "id": "p", "net": "p2" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vp2b", "displayName": "Vp2b", "spiceType": "V", "model": null, "parametersOrValue": "PULSE(1.2 0 10n 200p 200p 9n 20n)", "source": "Vp2b p2b 0 PULSE(1.2 0 10n 200p 200p 9n 20n)", "pins": [ { "id": "p", "net": "p2b" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vrst", "displayName": "Vrst", "spiceType": "V", "model": null, "parametersOrValue": "PWL(0 1.2 18n 1.2 20n 0)", "source": "Vrst rst 0 PWL(0 1.2 18n 1.2 20n 0)", "pins": [ { "id": "p", "net": "rst" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vrstb", "displayName": "Vrstb", "spiceType": "V", "model": null, "parametersOrValue": "PWL(0 0 18n 0 20n 1.2)", "source": "Vrstb rstb 0 PWL(0 0 18n 0 20n 1.2)", "pins": [ { "id": "p", "net": "rstb" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "XS1n", "displayName": "S1n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XS1n vin p1 l 0 sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "p1" }, { "id": "s", "net": "l" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS1p", "displayName": "S1p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS1p vin p1b l vdd sg13_lv_pmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "p1b" }, { "id": "s", "net": "l" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS2n", "displayName": "S2n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XS2n r p1 vcm 0 sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "r" }, { "id": "g", "net": "p1" }, { "id": "s", "net": "vcm" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS2p", "displayName": "S2p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS2p r p1b vcm vdd sg13_lv_pmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "r" }, { "id": "g", "net": "p1b" }, { "id": "s", "net": "vcm" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS4n", "displayName": "S4n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XS4n r p2 sum 0 sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "r" }, { "id": "g", "net": "p2" }, { "id": "s", "net": "sum" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS4p", "displayName": "S4p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS4p r p2b sum vdd sg13_lv_pmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "r" }, { "id": "g", "net": "p2b" }, { "id": "s", "net": "sum" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCS", "displayName": "CS", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=12.857u l=12.857u", "source": "XCS l r cap_cmim w=12.857u l=12.857u", "pins": [ { "id": "p", "net": "l" }, { "id": "n", "net": "r" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XGP", "displayName": "GP", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XGP dp p2 q vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "dp" }, { "id": "A", "net": "p2" }, { "id": "B", "net": "q" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XGN", "displayName": "GN", "spiceType": "X", "model": "sg13g2_nor2_1", "parametersOrValue": "", "source": "XGN dn p2b q vdd 0 sg13g2_nor2_1", "pins": [ { "id": "Y", "net": "dn" }, { "id": "A", "net": "p2b" }, { "id": "B", "net": "q" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMDP", "displayName": "MDP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XMDP l dp vdd vdd sg13_lv_pmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "l" }, { "id": "g", "net": "dp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMDN", "displayName": "MDN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XMDN l dn 0 0 sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "l" }, { "id": "g", "net": "dn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCI", "displayName": "CI", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u", "source": "XCI sum vo cap_cmim w=25.767u l=25.767u", "pins": [ { "id": "p", "net": "sum" }, { "id": "n", "net": "vo" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XSRn", "displayName": "SRn", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSRn sum rst vo 0 sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "sum" }, { "id": "g", "net": "rst" }, { "id": "s", "net": "vo" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSRp", "displayName": "SRp", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSRp sum rstb vo vdd sg13_lv_pmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "sum" }, { "id": "g", "net": "rstb" }, { "id": "s", "net": "vo" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMb", "displayName": "Mb", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XMb bn bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "bn" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMt", "displayName": "Mt", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XMt tail bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM1 n1 sum tail 0 sg13_lv_nmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n1" }, { "id": "g", "net": "sum" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM2 n2 vcm tail 0 sg13_lv_nmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n2" }, { "id": "g", "net": "vcm" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM3 n1 n1 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n1" }, { "id": "g", "net": "n1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM4 n2 n1 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n2" }, { "id": "g", "net": "n1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=8", "source": "XM5 vo n2 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=8", "pins": [ { "id": "d", "net": "vo" }, { "id": "g", "net": "n2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=16", "source": "XM6 vo bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=16", "pins": [ { "id": "d", "net": "vo" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC", "displayName": "CC", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=18.204u l=18.204u", "source": "XCC n2 nz cap_cmim w=18.204u l=18.204u", "pins": [ { "id": "p", "net": "n2" }, { "id": "n", "net": "nz" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ", "displayName": "RZ", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=2.678u", "source": "XRZ nz vo 0 rppd w=0.5u l=2.678u", "pins": [ { "id": "p", "net": "nz" }, { "id": "n", "net": "vo" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMQT", "displayName": "MQT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMQT qs bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "qs" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMQ1", "displayName": "MQ1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMQ1 qx vcm qs 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "qx" }, { "id": "g", "net": "vcm" }, { "id": "s", "net": "qs" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMQ2", "displayName": "MQ2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMQ2 qo vo qs 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "qo" }, { "id": "g", "net": "vo" }, { "id": "s", "net": "qs" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMQ3", "displayName": "MQ3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMQ3 qx qx vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "qx" }, { "id": "g", "net": "qx" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMQ4", "displayName": "MQ4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMQ4 qo qx vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "qo" }, { "id": "g", "net": "qx" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XIQ", "displayName": "IQ", "spiceType": "X", "model": "sg13g2_inv_1", "parametersOrValue": "", "source": "XIQ qd qo vdd 0 sg13g2_inv_1", "pins": [ { "id": "Y", "net": "qd" }, { "id": "A", "net": "qo" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XFQ", "displayName": "FQ", "spiceType": "X", "model": "sg13g2_dfrbpq_1", "parametersOrValue": "", "source": "XFQ q p1b qd rstb vdd 0 sg13g2_dfrbpq_1", "pins": [ { "id": "Q", "net": "q" }, { "id": "CLK", "net": "p1b" }, { "id": "D", "net": "qd" }, { "id": "RESET_B", "net": "rstb" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ecm", "pin": "cp" }, { "device": "Ib", "pin": "p" }, { "device": "XS1p", "pin": "b" }, { "device": "XS2p", "pin": "b" }, { "device": "XS4p", "pin": "b" }, { "device": "XGP", "pin": "VDD" }, { "device": "XGN", "pin": "VDD" }, { "device": "XMDP", "pin": "s" }, { "device": "XMDP", "pin": "b" }, { "device": "XSRp", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XMQ3", "pin": "s" }, { "device": "XMQ3", "pin": "b" }, { "device": "XMQ4", "pin": "s" }, { "device": "XMQ4", "pin": "b" }, { "device": "XIQ", "pin": "VDD" }, { "device": "XFQ", "pin": "VDD" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ecm", "pin": "n" }, { "device": "Ecm", "pin": "cn" }, { "device": "Vin", "pin": "n" }, { "device": "Vp1", "pin": "n" }, { "device": "Vp1b", "pin": "n" }, { "device": "Vp2", "pin": "n" }, { "device": "Vp2b", "pin": "n" }, { "device": "Vrst", "pin": "n" }, { "device": "Vrstb", "pin": "n" }, { "device": "XS1n", "pin": "b" }, { "device": "XS2n", "pin": "b" }, { "device": "XS4n", "pin": "b" }, { "device": "XGP", "pin": "VSS" }, { "device": "XGN", "pin": "VSS" }, { "device": "XMDN", "pin": "s" }, { "device": "XMDN", "pin": "b" }, { "device": "XSRn", "pin": "b" }, { "device": "XMb", "pin": "s" }, { "device": "XMb", "pin": "b" }, { "device": "XMt", "pin": "s" }, { "device": "XMt", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XRZ", "pin": "substrate" }, { "device": "XMQT", "pin": "s" }, { "device": "XMQT", "pin": "b" }, { "device": "XMQ1", "pin": "b" }, { "device": "XMQ2", "pin": "b" }, { "device": "XIQ", "pin": "VSS" }, { "device": "XFQ", "pin": "VSS" } ], "ports": [], "voltageReferences": [] }, { "id": "vcm", "ground": false, "terminals": [ { "device": "Ecm", "pin": "p" }, { "device": "XS2n", "pin": "s" }, { "device": "XS2p", "pin": "s" }, { "device": "XM2", "pin": "g" }, { "device": "XMQ1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "bn", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "XMb", "pin": "d" }, { "device": "XMb", "pin": "g" }, { "device": "XMt", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XMQT", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vin", "ground": false, "terminals": [ { "device": "Vin", "pin": "p" }, { "device": "XS1n", "pin": "d" }, { "device": "XS1p", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "p1", "ground": false, "terminals": [ { "device": "Vp1", "pin": "p" }, { "device": "XS1n", "pin": "g" }, { "device": "XS2n", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "p1b", "ground": false, "terminals": [ { "device": "Vp1b", "pin": "p" }, { "device": "XS1p", "pin": "g" }, { "device": "XS2p", "pin": "g" }, { "device": "XFQ", "pin": "CLK" } ], "ports": [], "voltageReferences": [] }, { "id": "p2", "ground": false, "terminals": [ { "device": "Vp2", "pin": "p" }, { "device": "XS4n", "pin": "g" }, { "device": "XGP", "pin": "A" } ], "ports": [], "voltageReferences": [] }, { "id": "p2b", "ground": false, "terminals": [ { "device": "Vp2b", "pin": "p" }, { "device": "XS4p", "pin": "g" }, { "device": "XGN", "pin": "A" } ], "ports": [], "voltageReferences": [] }, { "id": "rst", "ground": false, "terminals": [ { "device": "Vrst", "pin": "p" }, { "device": "XSRn", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rstb", "ground": false, "terminals": [ { "device": "Vrstb", "pin": "p" }, { "device": "XSRp", "pin": "g" }, { "device": "XFQ", "pin": "RESET_B" } ], "ports": [], "voltageReferences": [] }, { "id": "l", "ground": false, "terminals": [ { "device": "XS1n", "pin": "s" }, { "device": "XS1p", "pin": "s" }, { "device": "XCS", "pin": "p" }, { "device": "XMDP", "pin": "d" }, { "device": "XMDN", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "r", "ground": false, "terminals": [ { "device": "XS2n", "pin": "d" }, { "device": "XS2p", "pin": "d" }, { "device": "XS4n", "pin": "d" }, { "device": "XS4p", "pin": "d" }, { "device": "XCS", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "sum", "ground": false, "terminals": [ { "device": "XS4n", "pin": "s" }, { "device": "XS4p", "pin": "s" }, { "device": "XCI", "pin": "p" }, { "device": "XSRn", "pin": "d" }, { "device": "XSRp", "pin": "d" }, { "device": "XM1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "dp", "ground": false, "terminals": [ { "device": "XGP", "pin": "Y" }, { "device": "XMDP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "q", "ground": false, "terminals": [ { "device": "XGP", "pin": "B" }, { "device": "XGN", "pin": "B" }, { "device": "XFQ", "pin": "Q" } ], "ports": [], "voltageReferences": [] }, { "id": "dn", "ground": false, "terminals": [ { "device": "XGN", "pin": "Y" }, { "device": "XMDN", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vo", "ground": false, "terminals": [ { "device": "XCI", "pin": "n" }, { "device": "XSRn", "pin": "s" }, { "device": "XSRp", "pin": "s" }, { "device": "XM5", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XRZ", "pin": "n" }, { "device": "XMQ2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMt", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "n1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "n2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XCC", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "nz", "ground": false, "terminals": [ { "device": "XCC", "pin": "n" }, { "device": "XRZ", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "qs", "ground": false, "terminals": [ { "device": "XMQT", "pin": "d" }, { "device": "XMQ1", "pin": "s" }, { "device": "XMQ2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "qx", "ground": false, "terminals": [ { "device": "XMQ1", "pin": "d" }, { "device": "XMQ3", "pin": "d" }, { "device": "XMQ3", "pin": "g" }, { "device": "XMQ4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "qo", "ground": false, "terminals": [ { "device": "XMQ2", "pin": "d" }, { "device": "XMQ4", "pin": "d" }, { "device": "XIQ", "pin": "A" } ], "ports": [], "voltageReferences": [] }, { "id": "qd", "ground": false, "terminals": [ { "device": "XIQ", "pin": "Y" }, { "device": "XFQ", "pin": "D" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "top-level-device-set", "scope": "top", "devices": [ "XS1n", "XS1p", "XS2n", "XS2p", "XS4n", "XS4p", "XCS", "XGP", "XGN", "XMDP", "XMDN", "XCI", "XSRn", "XSRp", "XMb", "XMt", "XM1", "XM2", "XM3", "XM4", "XM5", "XM6", "XCC", "XRZ", "XMQT", "XMQ1", "XMQ2", "XMQ3", "XMQ4", "XIQ", "XFQ" ] } }, { "id": "graph-3", "kind": "functional-graph", "classification": "explicit-normalized-sigma-delta-loop", "topology": "dt", "boundary": "Normalized functional signs, not transistor wiring. CT uses an inverting integrator, reversed comparator and complementary physical DAC; normalization assumes vcm=VDD/2. The multi-bit decimator is not implemented.", "electricalScope": "dut", "nodes": [ { "id": "integrator", "devices": [ { "scope": "dut", "device": "XCI" }, { "scope": "dut", "device": "XSRn" }, { "scope": "dut", "device": "XSRp" }, { "scope": "dut", "device": "XMt" }, { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" }, { "scope": "dut", "device": "XM3" }, { "scope": "dut", "device": "XM4" }, { "scope": "dut", "device": "XM5" }, { "scope": "dut", "device": "XM6" }, { "scope": "dut", "device": "XCC" }, { "scope": "dut", "device": "XRZ" }, { "scope": "dut", "device": "XCS" }, { "scope": "dut", "device": "XS1n" }, { "scope": "dut", "device": "XS1p" }, { "scope": "dut", "device": "XS2n" }, { "scope": "dut", "device": "XS2p" }, { "scope": "dut", "device": "XS4n" }, { "scope": "dut", "device": "XS4p" } ] }, { "id": "quantizer", "devices": [ { "scope": "dut", "device": "XMQT" }, { "scope": "dut", "device": "XMQ1" }, { "scope": "dut", "device": "XMQ2" }, { "scope": "dut", "device": "XMQ3" }, { "scope": "dut", "device": "XMQ4" }, { "scope": "dut", "device": "XIQ" } ] }, { "id": "register", "devices": [ { "scope": "dut", "device": "XFQ" } ] }, { "id": "dac", "devices": [ { "scope": "dut", "device": "XGP" }, { "scope": "dut", "device": "XGN" }, { "scope": "dut", "device": "XMDP" }, { "scope": "dut", "device": "XMDN" } ] }, { "id": "bias", "devices": [ { "scope": "dut", "device": "XMb" } ] }, { "id": "input", "devices": [], "virtual": true }, { "id": "subtract", "devices": [], "virtual": true }, { "id": "output", "devices": [], "virtual": true }, { "id": "clock", "devices": [], "virtual": true }, { "id": "reset", "devices": [], "virtual": true } ], "edges": [ { "id": "input", "from": "input", "to": "subtract", "label": "vin", "sign": "positive" }, { "id": "error", "from": "subtract", "to": "integrator", "label": "vin − q·VDD" }, { "id": "state", "from": "integrator", "to": "quantizer", "label": "vo − vcm" }, { "id": "decision", "from": "quantizer", "to": "register", "label": "qd", "net": "qd" }, { "id": "bitstream", "from": "register", "to": "output", "label": "q", "net": "q" }, { "id": "held-bit", "from": "register", "to": "dac", "label": "held q", "net": "q" }, { "id": "feedback", "from": "dac", "to": "subtract", "label": "q·VDD", "sign": "negative" }, { "id": "clock", "from": "clock", "to": "register", "label": "p1b", "net": "p1b" }, { "id": "reset", "from": "reset", "to": "register", "label": "rstb", "net": "rstb" }, { "id": "bias-integrator", "from": "bias", "to": "integrator", "label": "bias", "net": "bn" }, { "id": "bias-quantizer", "from": "bias", "to": "quantizer", "label": "bias", "net": "bn" } ], "stateDefinition": "vo − vcm", "feedback": { "from": "register", "via": "dac", "to": "subtract", "sign": "negative" }, "controls": { "clock": "p1b", "reset": "rstb" }, "coverage": "Every DUT device is assigned once by sigmaDeltaDiagramModel. Required CI/summing, amplifier, quantizer-polarity, register and DAC terminal connections and device functions are checked against the selected supported topology; this is a structural guard, not a dynamic-stability proof." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "1.2", "source": "Vdd vdd 0 1.2", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ecm", "displayName": "Ecm", "spiceType": "E", "model": null, "parametersOrValue": "0.5", "source": "Ecm vcm 0 vdd 0 0.5", "pins": [ { "id": "p", "net": "vcm" }, { "id": "n", "net": "0" }, { "id": "cp", "net": "vdd" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "80u", "source": "Ib vdd bn 80u", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "bn" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "SIN(0 400m 1.17188meg 20n)", "source": "Vin vin vcm SIN(0 400m 1.17188meg 20n)", "pins": [ { "id": "p", "net": "vin" }, { "id": "n", "net": "vcm" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vp1", "displayName": "Vp1", "spiceType": "V", "model": null, "parametersOrValue": "PULSE(0 1.2 0 200p 200p 9n 20n)", "source": "Vp1 p1 0 PULSE(0 1.2 0 200p 200p 9n 20n)", "pins": [ { "id": "p", "net": "p1" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vp1b", "displayName": "Vp1b", "spiceType": "V", "model": null, "parametersOrValue": "PULSE(1.2 0 0 200p 200p 9n 20n)", "source": "Vp1b p1b 0 PULSE(1.2 0 0 200p 200p 9n 20n)", "pins": [ { "id": "p", "net": "p1b" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vp2", "displayName": "Vp2", "spiceType": "V", "model": null, "parametersOrValue": "PULSE(0 1.2 10n 200p 200p 9n 20n)", "source": "Vp2 p2 0 PULSE(0 1.2 10n 200p 200p 9n 20n)", "pins": [ { "id": "p", "net": "p2" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vp2b", "displayName": "Vp2b", "spiceType": "V", "model": null, "parametersOrValue": "PULSE(1.2 0 10n 200p 200p 9n 20n)", "source": "Vp2b p2b 0 PULSE(1.2 0 10n 200p 200p 9n 20n)", "pins": [ { "id": "p", "net": "p2b" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vrst", "displayName": "Vrst", "spiceType": "V", "model": null, "parametersOrValue": "PWL(0 1.2 18n 1.2 20n 0)", "source": "Vrst rst 0 PWL(0 1.2 18n 1.2 20n 0)", "pins": [ { "id": "p", "net": "rst" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vrstb", "displayName": "Vrstb", "spiceType": "V", "model": null, "parametersOrValue": "PWL(0 0 18n 0 20n 1.2)", "source": "Vrstb rstb 0 PWL(0 0 18n 0 20n 1.2)", "pins": [ { "id": "p", "net": "rstb" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "XS1n", "displayName": "S1n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XS1n vin p1 l 0 sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "p1" }, { "id": "s", "net": "l" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS1p", "displayName": "S1p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS1p vin p1b l vdd sg13_lv_pmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "vin" }, { "id": "g", "net": "p1b" }, { "id": "s", "net": "l" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS2n", "displayName": "S2n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XS2n r p1 vcm 0 sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "r" }, { "id": "g", "net": "p1" }, { "id": "s", "net": "vcm" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS2p", "displayName": "S2p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS2p r p1b vcm vdd sg13_lv_pmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "r" }, { "id": "g", "net": "p1b" }, { "id": "s", "net": "vcm" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS4n", "displayName": "S4n", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XS4n r p2 sum 0 sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "r" }, { "id": "g", "net": "p2" }, { "id": "s", "net": "sum" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XS4p", "displayName": "S4p", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XS4p r p2b sum vdd sg13_lv_pmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "r" }, { "id": "g", "net": "p2b" }, { "id": "s", "net": "sum" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCS", "displayName": "CS", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=12.857u l=12.857u", "source": "XCS l r cap_cmim w=12.857u l=12.857u", "pins": [ { "id": "p", "net": "l" }, { "id": "n", "net": "r" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XGP", "displayName": "GP", "spiceType": "X", "model": "sg13g2_nand2_1", "parametersOrValue": "", "source": "XGP dp p2 q vdd 0 sg13g2_nand2_1", "pins": [ { "id": "Y", "net": "dp" }, { "id": "A", "net": "p2" }, { "id": "B", "net": "q" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XGN", "displayName": "GN", "spiceType": "X", "model": "sg13g2_nor2_1", "parametersOrValue": "", "source": "XGN dn p2b q vdd 0 sg13g2_nor2_1", "pins": [ { "id": "Y", "net": "dn" }, { "id": "A", "net": "p2b" }, { "id": "B", "net": "q" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XMDP", "displayName": "MDP", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XMDP l dp vdd vdd sg13_lv_pmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "l" }, { "id": "g", "net": "dp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMDN", "displayName": "MDN", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XMDN l dn 0 0 sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "l" }, { "id": "g", "net": "dn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCI", "displayName": "CI", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u", "source": "XCI sum vo cap_cmim w=25.767u l=25.767u", "pins": [ { "id": "p", "net": "sum" }, { "id": "n", "net": "vo" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XSRn", "displayName": "SRn", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XSRn sum rst vo 0 sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "sum" }, { "id": "g", "net": "rst" }, { "id": "s", "net": "vo" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XSRp", "displayName": "SRp", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XSRp sum rstb vo vdd sg13_lv_pmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "sum" }, { "id": "g", "net": "rstb" }, { "id": "s", "net": "vo" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMb", "displayName": "Mb", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XMb bn bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "bn" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMt", "displayName": "Mt", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=4", "source": "XMt tail bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=4", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM1 n1 sum tail 0 sg13_lv_nmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n1" }, { "id": "g", "net": "sum" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM2 n2 vcm tail 0 sg13_lv_nmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n2" }, { "id": "g", "net": "vcm" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM3 n1 n1 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n1" }, { "id": "g", "net": "n1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=1", "source": "XM4 n2 n1 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "n2" }, { "id": "g", "net": "n1" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=20u l=1u ng=4 m=8", "source": "XM5 vo n2 vdd vdd sg13_lv_pmos w=20u l=1u ng=4 m=8", "pins": [ { "id": "d", "net": "vo" }, { "id": "g", "net": "n2" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=16", "source": "XM6 vo bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=16", "pins": [ { "id": "d", "net": "vo" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCC", "displayName": "CC", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=18.204u l=18.204u", "source": "XCC n2 nz cap_cmim w=18.204u l=18.204u", "pins": [ { "id": "p", "net": "n2" }, { "id": "n", "net": "nz" } ], "pinMeaning": "IHP MIM model terminal order" }, { "id": "XRZ", "displayName": "RZ", "spiceType": "X", "model": "rppd", "parametersOrValue": "w=0.5u l=2.678u", "source": "XRZ nz vo 0 rppd w=0.5u l=2.678u", "pins": [ { "id": "p", "net": "nz" }, { "id": "n", "net": "vo" }, { "id": "substrate", "net": "0" } ], "pinMeaning": "IHP resistor model terminal order" }, { "id": "XMQT", "displayName": "MQT", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=10u l=2u ng=2 m=1", "source": "XMQT qs bn 0 0 sg13_lv_nmos w=10u l=2u ng=2 m=1", "pins": [ { "id": "d", "net": "qs" }, { "id": "g", "net": "bn" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMQ1", "displayName": "MQ1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMQ1 qx vcm qs 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "qx" }, { "id": "g", "net": "vcm" }, { "id": "s", "net": "qs" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMQ2", "displayName": "MQ2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=500n ng=1 m=1", "source": "XMQ2 qo vo qs 0 sg13_lv_nmos w=4u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "qo" }, { "id": "g", "net": "vo" }, { "id": "s", "net": "qs" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMQ3", "displayName": "MQ3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMQ3 qx qx vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "qx" }, { "id": "g", "net": "qx" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMQ4", "displayName": "MQ4", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=500n ng=1 m=1", "source": "XMQ4 qo qx vdd vdd sg13_lv_pmos w=2u l=500n ng=1 m=1", "pins": [ { "id": "d", "net": "qo" }, { "id": "g", "net": "qx" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XIQ", "displayName": "IQ", "spiceType": "X", "model": "sg13g2_inv_1", "parametersOrValue": "", "source": "XIQ qd qo vdd 0 sg13g2_inv_1", "pins": [ { "id": "Y", "net": "qd" }, { "id": "A", "net": "qo" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" }, { "id": "XFQ", "displayName": "FQ", "spiceType": "X", "model": "sg13g2_dfrbpq_1", "parametersOrValue": "", "source": "XFQ q p1b qd rstb vdd 0 sg13g2_dfrbpq_1", "pins": [ { "id": "Q", "net": "q" }, { "id": "CLK", "net": "p1b" }, { "id": "D", "net": "qd" }, { "id": "RESET_B", "net": "rstb" }, { "id": "VDD", "net": "vdd" }, { "id": "VSS", "net": "0" } ], "pinMeaning": "IHP standard-cell declared terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Ecm", "pin": "cp" }, { "device": "Ib", "pin": "p" }, { "device": "XS1p", "pin": "b" }, { "device": "XS2p", "pin": "b" }, { "device": "XS4p", "pin": "b" }, { "device": "XGP", "pin": "VDD" }, { "device": "XGN", "pin": "VDD" }, { "device": "XMDP", "pin": "s" }, { "device": "XMDP", "pin": "b" }, { "device": "XSRp", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "s" }, { "device": "XM4", "pin": "b" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XMQ3", "pin": "s" }, { "device": "XMQ3", "pin": "b" }, { "device": "XMQ4", "pin": "s" }, { "device": "XMQ4", "pin": "b" }, { "device": "XIQ", "pin": "VDD" }, { "device": "XFQ", "pin": "VDD" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ecm", "pin": "n" }, { "device": "Ecm", "pin": "cn" }, { "device": "Vp1", "pin": "n" }, { "device": "Vp1b", "pin": "n" }, { "device": "Vp2", "pin": "n" }, { "device": "Vp2b", "pin": "n" }, { "device": "Vrst", "pin": "n" }, { "device": "Vrstb", "pin": "n" }, { "device": "XS1n", "pin": "b" }, { "device": "XS2n", "pin": "b" }, { "device": "XS4n", "pin": "b" }, { "device": "XGP", "pin": "VSS" }, { "device": "XGN", "pin": "VSS" }, { "device": "XMDN", "pin": "s" }, { "device": "XMDN", "pin": "b" }, { "device": "XSRn", "pin": "b" }, { "device": "XMb", "pin": "s" }, { "device": "XMb", "pin": "b" }, { "device": "XMt", "pin": "s" }, { "device": "XMt", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XRZ", "pin": "substrate" }, { "device": "XMQT", "pin": "s" }, { "device": "XMQT", "pin": "b" }, { "device": "XMQ1", "pin": "b" }, { "device": "XMQ2", "pin": "b" }, { "device": "XIQ", "pin": "VSS" }, { "device": "XFQ", "pin": "VSS" } ], "ports": [], "voltageReferences": [] }, { "id": "vcm", "ground": false, "terminals": [ { "device": "Ecm", "pin": "p" }, { "device": "Vin", "pin": "n" }, { "device": "XS2n", "pin": "s" }, { "device": "XS2p", "pin": "s" }, { "device": "XM2", "pin": "g" }, { "device": "XMQ1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "bn", "ground": false, "terminals": [ { "device": "Ib", "pin": "n" }, { "device": "XMb", "pin": "d" }, { "device": "XMb", "pin": "g" }, { "device": "XMt", "pin": "g" }, { "device": "XM6", "pin": "g" }, { "device": "XMQT", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vin", "ground": false, "terminals": [ { "device": "Vin", "pin": "p" }, { "device": "XS1n", "pin": "d" }, { "device": "XS1p", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "p1", "ground": false, "terminals": [ { "device": "Vp1", "pin": "p" }, { "device": "XS1n", "pin": "g" }, { "device": "XS2n", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "p1b", "ground": false, "terminals": [ { "device": "Vp1b", "pin": "p" }, { "device": "XS1p", "pin": "g" }, { "device": "XS2p", "pin": "g" }, { "device": "XFQ", "pin": "CLK" } ], "ports": [], "voltageReferences": [] }, { "id": "p2", "ground": false, "terminals": [ { "device": "Vp2", "pin": "p" }, { "device": "XS4n", "pin": "g" }, { "device": "XGP", "pin": "A" } ], "ports": [], "voltageReferences": [] }, { "id": "p2b", "ground": false, "terminals": [ { "device": "Vp2b", "pin": "p" }, { "device": "XS4p", "pin": "g" }, { "device": "XGN", "pin": "A" } ], "ports": [], "voltageReferences": [] }, { "id": "rst", "ground": false, "terminals": [ { "device": "Vrst", "pin": "p" }, { "device": "XSRn", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "rstb", "ground": false, "terminals": [ { "device": "Vrstb", "pin": "p" }, { "device": "XSRp", "pin": "g" }, { "device": "XFQ", "pin": "RESET_B" } ], "ports": [], "voltageReferences": [] }, { "id": "l", "ground": false, "terminals": [ { "device": "XS1n", "pin": "s" }, { "device": "XS1p", "pin": "s" }, { "device": "XCS", "pin": "p" }, { "device": "XMDP", "pin": "d" }, { "device": "XMDN", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "r", "ground": false, "terminals": [ { "device": "XS2n", "pin": "d" }, { "device": "XS2p", "pin": "d" }, { "device": "XS4n", "pin": "d" }, { "device": "XS4p", "pin": "d" }, { "device": "XCS", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "sum", "ground": false, "terminals": [ { "device": "XS4n", "pin": "s" }, { "device": "XS4p", "pin": "s" }, { "device": "XCI", "pin": "p" }, { "device": "XSRn", "pin": "d" }, { "device": "XSRp", "pin": "d" }, { "device": "XM1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "dp", "ground": false, "terminals": [ { "device": "XGP", "pin": "Y" }, { "device": "XMDP", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "q", "ground": false, "terminals": [ { "device": "XGP", "pin": "B" }, { "device": "XGN", "pin": "B" }, { "device": "XFQ", "pin": "Q" } ], "ports": [], "voltageReferences": [] }, { "id": "dn", "ground": false, "terminals": [ { "device": "XGN", "pin": "Y" }, { "device": "XMDN", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "vo", "ground": false, "terminals": [ { "device": "XCI", "pin": "n" }, { "device": "XSRn", "pin": "s" }, { "device": "XSRp", "pin": "s" }, { "device": "XM5", "pin": "d" }, { "device": "XM6", "pin": "d" }, { "device": "XRZ", "pin": "n" }, { "device": "XMQ2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMt", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "n1", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "d" }, { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "n2", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XCC", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "nz", "ground": false, "terminals": [ { "device": "XCC", "pin": "n" }, { "device": "XRZ", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "qs", "ground": false, "terminals": [ { "device": "XMQT", "pin": "d" }, { "device": "XMQ1", "pin": "s" }, { "device": "XMQ2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "qx", "ground": false, "terminals": [ { "device": "XMQ1", "pin": "d" }, { "device": "XMQ3", "pin": "d" }, { "device": "XMQ3", "pin": "g" }, { "device": "XMQ4", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "qo", "ground": false, "terminals": [ { "device": "XMQ2", "pin": "d" }, { "device": "XMQ4", "pin": "d" }, { "device": "XIQ", "pin": "A" } ], "ports": [], "voltageReferences": [] }, { "id": "qd", "ground": false, "terminals": [ { "device": "XIQ", "pin": "Y" }, { "device": "XFQ", "pin": "D" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "top-level-device-set", "scope": "top", "devices": [ "XS1n", "XS1p", "XS2n", "XS2p", "XS4n", "XS4p", "XCS", "XGP", "XGN", "XMDP", "XMDN", "XCI", "XSRn", "XSRp", "XMb", "XMt", "XM1", "XM2", "XM3", "XM4", "XM5", "XM6", "XCC", "XRZ", "XMQT", "XMQ1", "XMQ2", "XMQ3", "XMQ4", "XIQ", "XFQ" ] } } ], "views": [ { "bench": "dc", "source": { "recordField": "testbenches", "id": "dc", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/sigma-delta/dc-schematic.svg", "asset": "dc-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Sigma-delta modulator (first order)", "instances": [] } ] }, "benchDiagram": { "graph": "graph-2", "svg": { "url": "/circuits/sigma-delta/dc-bench.svg", "asset": "dc-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/sigma-delta/dc-block.svg", "asset": "dc-block.svg" } } }, { "bench": "sine", "source": { "recordField": "testbenches", "id": "sine", "field": "netlist" }, "schematic": { "graph": "graph-1", "svg": { "url": "/circuits/sigma-delta/dc-schematic.svg", "asset": "dc-schematic.svg" }, "drawingCheck": { "method": "checkSchematic", "problems": [] }, "sheets": [ { "name": "Sigma-delta modulator (first order)", "instances": [] } ] }, "benchDiagram": { "graph": "graph-4", "svg": { "url": "/circuits/sigma-delta/sine-bench.svg", "asset": "sine-bench.svg" } }, "blockDiagram": { "graph": "graph-3", "electricalGraph": "graph-1", "svg": { "url": "/circuits/sigma-delta/dc-block.svg", "asset": "dc-block.svg" } } } ] } }