{
  "schema": "aisic.circuit/1",
  "entryType": "library-block",
  "domain": "analog",
  "id": "source-follower",
  "name": "Source follower",
  "group": "Amplifier stages",
  "subgroup": "Followers",
  "title": "Source follower",
  "summary": "A voltage buffer whose output follows the input at a lower voltage. The bias current sets its operating point, while the body connection changes its gain and voltage shift. Compare the two body connections to see why practical followers fall short of unity gain.",
  "reference": {
    "kind": "book",
    "authors": "B. Razavi",
    "title": "Design of Analog CMOS Integrated Circuits",
    "edition": "2nd ed.",
    "publisher": "McGraw-Hill",
    "year": 2017,
    "where": "Single-Stage Amplifiers - the source follower, and the body effect's contribution to its gain",
    "takes": "The source-follower topology and its small-signal gain. Body transconductance and the output conductances of both the follower and its bias sink reduce the gain; the bulk-connection option isolates the body-effect contribution."
  },
  "resources": {
    "record": "/circuits/source-follower.json",
    "page": "/index.html#source-follower",
    "achieved": "/achieved/source-follower.json",
    "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.",
    "modelCards": [
      {
        "name": "sg13g2_lv_tt.spice",
        "url": "/sg13g2_lv_tt.spice",
        "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a"
      }
    ],
    "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.",
    "schema": "/schemas/circuit.schema.json"
  },
  "specificationPolicy": {
    "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.",
    "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.",
    "scopes": {
      "nominal": {
        "corner": "tt",
        "temp": 27,
        "vdd": 1,
        "temperatureUnit": "degC",
        "supplyMeaning": "scale of the bench's nominal supply"
      }
    },
    "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim."
  },
  "corners": {
    "cards": "a deck's sg13g2_<family>_tt.spice (family lv, hv, passive, hbt) becomes sg13g2_<family>_<corner>.spice",
    "process": [
      "tt",
      "ss",
      "ff",
      "sf",
      "fs"
    ],
    "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise",
    "temperatures": [
      -40,
      27,
      125
    ],
    "supplyScale": [
      0.9,
      1,
      1.1
    ],
    "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it",
    "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw",
    "sets": {
      "essential": [
        {
          "corner": "tt",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "ss",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "ff",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "sf",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "fs",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "tt",
          "temp": -40,
          "vdd": 1
        },
        {
          "corner": "tt",
          "temp": 125,
          "vdd": 1
        },
        {
          "corner": "tt",
          "temp": 27,
          "vdd": 0.9
        },
        {
          "corner": "tt",
          "temp": 27,
          "vdd": 1.1
        },
        {
          "corner": "ss",
          "temp": 125,
          "vdd": 0.9
        },
        {
          "corner": "ff",
          "temp": -40,
          "vdd": 1.1
        }
      ],
      "full": "all 45 combinations"
    },
    "montecarlo": {
      "cards": {
        "mc": "process and mismatch",
        "mcmm": "mismatch only",
        "mcproc": "process only"
      },
      "seed": "draw k adds .options seed=k, so draws are reproducible"
    }
  },
  "technology": {
    "id": "sg13g2",
    "name": "IHP SG13G2",
    "node": "130 nm",
    "corner": "tt",
    "vdd": 1.2,
    "lmin": 1.3e-7,
    "wmin": 1.5e-7,
    "models": "sg13g2_lv_tt.spice",
    "devices": {
      "nmos": "sg13_lv_nmos",
      "pmos": "sg13_lv_pmos",
      "resistor": "rppd, rhigh",
      "capacitor": "cap_cmim"
    },
    "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.",
    "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF."
  },
  "implementation": {
    "kind": "physical-device-reference",
    "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.",
    "evidence": "schematic-simulation",
    "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.",
    "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.",
    "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification."
  },
  "cards": [
    "sg13g2_lv_tt.spice"
  ],
  "ports": [
    {
      "name": "in",
      "kind": "input"
    },
    {
      "name": "out",
      "kind": "output"
    },
    {
      "name": "bn",
      "kind": "bias"
    },
    {
      "name": "vdd",
      "kind": "supply"
    },
    {
      "name": "0",
      "kind": "ground",
      "note": "bias-sink/reference return and the default NMOS substrate connection"
    }
  ],
  "devices": [
    {
      "name": "M1",
      "type": "nmos",
      "nodes": "vdd in out <bulk>",
      "sizedBy": [
        "W",
        "L",
        "bulk"
      ],
      "role": "follower",
      "fingers": 4,
      "copies": 1
    },
    {
      "name": "Mb",
      "type": "nmos",
      "nodes": "out bn 0 0",
      "sizedBy": [
        "Wb",
        "Lb"
      ],
      "role": "bias sink",
      "fingers": 2,
      "copies": 1
    },
    {
      "name": "Mr",
      "type": "nmos",
      "nodes": "bn bn 0 0",
      "sizedBy": [
        "Wb",
        "Lb"
      ],
      "role": "bias mirror, diode-connected",
      "fingers": 2,
      "copies": 1
    }
  ],
  "intent": [
    {
      "rule": "bulk-connection",
      "of": [
        "M1"
      ],
      "constraint": "bulk to ground unless the process offers a private well",
      "why": "With the bulk grounded, V_SB rises with the output and takes the threshold with it, so the level shift grows across the range and the gain falls. Tying bulk to source removes it but needs an isolated well - in SG13G2 a p-well of its own, cut off from the substrate by the n-buried layer (nBuLay) beneath it and an n-well ring around it. The plain sg13_lv_nmos used here shares the grounded substrate."
    },
    {
      "rule": "region",
      "of": [
        "M1",
        "Mb"
      ],
      "constraint": "both in saturation across the output range",
      "why": "The follower's output range is bounded below by the sink's saturation voltage - below it Mb leaves saturation and stops copying the reference - and above by the input minus V_GS."
    }
  ],
  "specs": [
    {
      "key": "av",
      "label": "Small-signal gain",
      "unit": "V/V",
      "direction": "target",
      "constraint": "< 1 by construction"
    },
    {
      "key": "shift",
      "label": "Level shift",
      "unit": "V",
      "direction": "min"
    }
  ],
  "explanation": {
    "idea": "This buffer makes its output follow the input, but at a lower voltage. It can drive a load more strongly than a high-resistance signal source. The transistor's body connection changes the voltage shift and makes the gain slightly less than one.",
    "detail": "The bias sink keeps M1's current approximately constant, so its source tracks its gate one V_GS lower. With the bulk grounded, the rising source voltage raises the threshold through body effect. Both transistors' finite output resistances also reduce the gain.",
    "lesson": {
      "relation": 0,
      "symbols": "A_v is voltage gain in V/V; g_m1 is gate transconductance and g_mb1 body transconductance, in siemens. r_o1 and r_ob are the follower and bias-sink output resistances in ohms.",
      "assumptions": "Low-frequency, unloaded small-signal model with fixed bias-gate voltage and both devices in saturation. Tying the body to the source removes the g_mb1 term.",
      "exercise": {
        "param": "bulk",
        "value": "src",
        "analysis": "dc",
        "expect": "Removing body effect should move the slope closer to one and make the voltage shift flatter. This option also changes the physical isolation requirement."
      },
      "limits": "The bench supplies the bias current. A body-to-source connection needs a suitable isolated well; it is not a free wiring change to a shared-substrate transistor."
    },
    "path": [
      {
        "part": "Follower",
        "devices": "M1",
        "does": "Drain on vdd, gate on in, source on out: with its current fixed, its V_GS barely changes, so the source follows the gate one V_GS lower."
      },
      {
        "part": "Bias sink",
        "devices": "Mr, Mb",
        "does": "Mr, diode-connected, takes the testbench's I_bias; Mb copies it from out to ground as the follower's current."
      }
    ],
    "bias": "Mb copies I_bias (20 µA by default) from Mr and so fixes M1's current; the output sits V_GS1 below the input, and V_GS1 grows with the output when the bulk is grounded. The ground port returns the bias reference and sink; it is also the input device's default bulk connection.",
    "relations": [
      {
        "what": "Small-signal gain",
        "expr": "A_v ≈ g_m1 / (g_m1 + g_mb1 + 1/r_o1 + 1/r_ob)",
        "note": "below one by construction; with the bulk on its source g_mb1 drops out. The bench checks gain below 0 dB at its stated 1.0 V input point; the rest of the transfer remains visible in the sweep."
      },
      {
        "what": "Level shift",
        "expr": "V_in − V_out = V_GS1 = V_TH(V_SB) + V_ov",
        "note": "with the bulk grounded V_SB = V_out, so the threshold, and the shift, rise with the output"
      },
      {
        "what": "Body effect",
        "expr": "η = g_mb1/g_m1 = γ / (2 √(2φ_F + V_SB))",
        "note": "the body's share of the transconductance; it shrinks slowly as V_SB rises"
      },
      {
        "what": "Output resistance",
        "expr": "R_out ≈ 1 / (g_m1 + g_mb1)",
        "note": "low, which is what a buffer is for; the sink's r_o sits in parallel"
      },
      {
        "what": "Output floor",
        "expr": "V_out > V_ov(Mb)",
        "note": "below it Mb leaves saturation and stops copying I_bias"
      }
    ],
    "tradeoffs": [
      "Bulk connection: to source removes the body effect, lifting the gain towards one and flattening the shift, but needs an isolated p-well for M1.",
      "I_bias: more current raises g_m1 and lowers R_out, but increases V_ov, so the level shift grows and the output cannot go as low.",
      "W: wider lowers M1's V_ov and so the level shift, and raises g_m1, at the cost of input capacitance.",
      "L_sink: longer raises the sink's output resistance, keeping its current steadier as the output moves, but raises its V_ov at the same W_sink."
    ]
  },
  "sizing": [
    {
      "key": "W",
      "label": "W",
      "unit": "m",
      "value": 0.00002,
      "min": 1.5e-7,
      "max": 0.0001,
      "kind": "si"
    },
    {
      "key": "L",
      "label": "L",
      "unit": "m",
      "value": 5e-7,
      "min": 1.3e-7,
      "max": 0.00001,
      "kind": "si"
    },
    {
      "key": "Ib",
      "label": "I_bias",
      "unit": "A",
      "value": 0.00002,
      "min": 0.000001,
      "max": 0.0005,
      "kind": "si"
    },
    {
      "key": "Wb",
      "label": "W_sink",
      "unit": "m",
      "value": 0.00001,
      "min": 1.5e-7,
      "max": 0.0001,
      "kind": "si"
    },
    {
      "key": "Lb",
      "label": "L_sink",
      "unit": "m",
      "value": 0.000001,
      "min": 1.3e-7,
      "max": 0.00001,
      "kind": "si"
    },
    {
      "key": "bulk",
      "label": "Bulk connection",
      "unit": "",
      "value": "gnd",
      "kind": "choice",
      "choices": [
        [
          "gnd",
          "to ground (body effect)"
        ],
        [
          "src",
          "to source (isolated p-well over nBuLay)"
        ]
      ]
    }
  ],
  "testbenches": [
    {
      "id": "dc",
      "label": "DC transfer",
      "note": "",
      "measures": [
        "av",
        "shift"
      ],
      "metricKeys": [
        "gain_db",
        "shift"
      ],
      "acceptance": [
        "gain_db"
      ],
      "acceptanceRules": [
        {
          "key": "gain_db",
          "unit": "dB",
          "max": 0,
          "exclusiveMax": true,
          "classification": "simulation-limit",
          "conditions": "all requested testbench conditions",
          "outsideScope": "characterization; the measurement must still be present, unique and finite"
        }
      ],
      "cards": [
        "sg13g2_lv_tt.spice"
      ],
      "netlist": "* NMOS source follower\n.include sg13g2_lv_tt.spice\nVdd vdd 0 1.2\nXM1 vdd in out 0 sg13_lv_nmos w=20u l=500n ng=4 m=1\n* the bias sink: a mirror copying the reference current the bench supplies\nIref vdd bn 20u\nXMr bn bn 0 0 sg13_lv_nmos w=10u l=1u ng=2 m=1\nXMb out bn 0 0 sg13_lv_nmos w=10u l=1u ng=2 m=1\nVin in 0 0\n.dc Vin 0 1.2 0.004\n.end"
    }
  ],
  "measurements": {
    "gain_db": {
      "label": "Gain at V_in = 1.0 V",
      "unit": "dB",
      "spec": {
        "max": 0,
        "exclusiveMax": true
      }
    }
  },
  "recordVersion": 1,
  "authoring": {
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    "source": "this-record",
    "fields": [
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      "ports",
      "devices (except fingers/copies)",
      "intent",
      "specs",
      "explanation",
      "sizing[].label",
      "testbenches[].label",
      "testbenches[].note"
    ],
    "generated": [
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      "technology",
      "cards",
      "corners",
      "specificationPolicy",
      "sizing (except label)",
      "measurements",
      "testbenches (except label/note)",
      "diagrams",
      "provenance",
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      "devices[].copies"
    ],
    "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.",
    "sha256": "97a1f71fe17386c4a54e35e876160b81fb3d9efd3da5f45565121acbf4ebdb36"
  },
  "provenance": {
    "schema": "aisic.record-provenance/1",
    "parameterScope": "published-defaults",
    "generator": {
      "url": "/library/source-follower.js",
      "sha256": "d89dd1b2db041ca5f8c5c328376a58493030c5f1911f411e5a60095bcb119440"
    },
    "simulationFingerprints": {
      "dc": "55cdd8e584700a7a6426e80fa53659c78576d2b590cfc45570647bd8c7098b50"
    },
    "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification."
  },
  "revision": "8be4a2a24fc1d0e4516c9af1a2ebb85ed81ce60b32a90843e535f1053246b6cb",
  "diagrams": {
    "schema": "aisic.diagrams/1",
    "circuit": "source-follower",
    "parameters": {
      "W": 0.00002,
      "L": 5e-7,
      "Ib": 0.00002,
      "Wb": 0.00001,
      "Lb": 0.000001,
      "bulk": "gnd"
    },
    "parameterScope": "published-defaults",
    "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.",
    "variants": {
      "choiceParameters": [
        {
          "key": "bulk",
          "selected": "gnd",
          "choices": [
            {
              "value": "gnd",
              "label": "to ground (body effect)"
            },
            {
              "value": "src",
              "label": "to source (isolated p-well over nBuLay)"
            }
          ]
        }
      ],
      "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation."
    },
    "resourceBase": "/circuits/source-follower/",
    "graphs": [
      {
        "id": "graph-1",
        "kind": "electrical-connectivity",
        "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.",
        "root": "dut",
        "globalDefinitions": [],
        "scopes": [
          {
            "id": "dut",
            "name": "top",
            "ports": [
              {
                "name": "vdd",
                "net": "vdd",
                "kind": "supply"
              },
              {
                "name": "in",
                "net": "in",
                "kind": "input"
              },
              {
                "name": "out",
                "net": "out",
                "kind": "output"
              },
              {
                "name": "gnd",
                "net": "0",
                "kind": "ground"
              },
              {
                "name": "bn",
                "net": "bn",
                "kind": "bias"
              }
            ],
            "definitions": [],
            "devices": [
              {
                "id": "XM1",
                "displayName": "M1",
                "spiceType": "X",
                "model": "sg13_lv_nmos",
                "parametersOrValue": "w=20u l=500n ng=4 m=1",
                "source": "XM1 vdd in out 0 sg13_lv_nmos w=20u l=500n ng=4 m=1",
                "pins": [
                  {
                    "id": "d",
                    "net": "vdd"
                  },
                  {
                    "id": "g",
                    "net": "in"
                  },
                  {
                    "id": "s",
                    "net": "out"
                  },
                  {
                    "id": "b",
                    "net": "0"
                  }
                ],
                "pinMeaning": "MOS drain, gate, source, bulk"
              },
              {
                "id": "XMr",
                "displayName": "Mr",
                "spiceType": "X",
                "model": "sg13_lv_nmos",
                "parametersOrValue": "w=10u l=1u ng=2 m=1",
                "source": "XMr bn bn 0 0 sg13_lv_nmos w=10u l=1u ng=2 m=1",
                "pins": [
                  {
                    "id": "d",
                    "net": "bn"
                  },
                  {
                    "id": "g",
                    "net": "bn"
                  },
                  {
                    "id": "s",
                    "net": "0"
                  },
                  {
                    "id": "b",
                    "net": "0"
                  }
                ],
                "pinMeaning": "MOS drain, gate, source, bulk"
              },
              {
                "id": "XMb",
                "displayName": "Mb",
                "spiceType": "X",
                "model": "sg13_lv_nmos",
                "parametersOrValue": "w=10u l=1u ng=2 m=1",
                "source": "XMb out bn 0 0 sg13_lv_nmos w=10u l=1u ng=2 m=1",
                "pins": [
                  {
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                    "net": "out"
                  },
                  {
                    "id": "g",
                    "net": "bn"
                  },
                  {
                    "id": "s",
                    "net": "0"
                  },
                  {
                    "id": "b",
                    "net": "0"
                  }
                ],
                "pinMeaning": "MOS drain, gate, source, bulk"
              }
            ],
            "nets": [
              {
                "id": "vdd",
                "ground": false,
                "terminals": [
                  {
                    "device": "XM1",
                    "pin": "d"
                  }
                ],
                "ports": [
                  "vdd"
                ],
                "voltageReferences": []
              },
              {
                "id": "in",
                "ground": false,
                "terminals": [
                  {
                    "device": "XM1",
                    "pin": "g"
                  }
                ],
                "ports": [
                  "in"
                ],
                "voltageReferences": []
              },
              {
                "id": "out",
                "ground": false,
                "terminals": [
                  {
                    "device": "XM1",
                    "pin": "s"
                  },
                  {
                    "device": "XMb",
                    "pin": "d"
                  }
                ],
                "ports": [
                  "out"
                ],
                "voltageReferences": []
              },
              {
                "id": "0",
                "ground": true,
                "terminals": [
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                    "device": "XM1",
                    "pin": "b"
                  },
                  {
                    "device": "XMr",
                    "pin": "s"
                  },
                  {
                    "device": "XMr",
                    "pin": "b"
                  },
                  {
                    "device": "XMb",
                    "pin": "s"
                  },
                  {
                    "device": "XMb",
                    "pin": "b"
                  }
                ],
                "ports": [
                  "gnd"
                ],
                "voltageReferences": []
              },
              {
                "id": "bn",
                "ground": false,
                "terminals": [
                  {
                    "device": "XMr",
                    "pin": "d"
                  },
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                    "device": "XMr",
                    "pin": "g"
                  },
                  {
                    "device": "XMb",
                    "pin": "g"
                  }
                ],
                "ports": [
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                ],
                "voltageReferences": []
              }
            ]
          }
        ]
      },
      {
        "id": "graph-2",
        "kind": "electrical-connectivity",
        "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.",
        "root": "top",
        "globalDefinitions": [],
        "scopes": [
          {
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            "devices": [
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                "id": "Vdd",
                "displayName": "Vdd",
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                "model": null,
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                "source": "Vdd vdd 0 1.2",
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                "pinMeaning": "SPICE primitive terminal order"
              },
              {
                "id": "XM1",
                "displayName": "M1",
                "spiceType": "X",
                "model": "sg13_lv_nmos",
                "parametersOrValue": "w=20u l=500n ng=4 m=1",
                "source": "XM1 vdd in out 0 sg13_lv_nmos w=20u l=500n ng=4 m=1",
                "pins": [
                  {
                    "id": "d",
                    "net": "vdd"
                  },
                  {
                    "id": "g",
                    "net": "in"
                  },
                  {
                    "id": "s",
                    "net": "out"
                  },
                  {
                    "id": "b",
                    "net": "0"
                  }
                ],
                "pinMeaning": "MOS drain, gate, source, bulk"
              },
              {
                "id": "Iref",
                "displayName": "Iref",
                "spiceType": "I",
                "model": null,
                "parametersOrValue": "20u",
                "source": "Iref vdd bn 20u",
                "pins": [
                  {
                    "id": "p",
                    "net": "vdd"
                  },
                  {
                    "id": "n",
                    "net": "bn"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              },
              {
                "id": "XMr",
                "displayName": "Mr",
                "spiceType": "X",
                "model": "sg13_lv_nmos",
                "parametersOrValue": "w=10u l=1u ng=2 m=1",
                "source": "XMr bn bn 0 0 sg13_lv_nmos w=10u l=1u ng=2 m=1",
                "pins": [
                  {
                    "id": "d",
                    "net": "bn"
                  },
                  {
                    "id": "g",
                    "net": "bn"
                  },
                  {
                    "id": "s",
                    "net": "0"
                  },
                  {
                    "id": "b",
                    "net": "0"
                  }
                ],
                "pinMeaning": "MOS drain, gate, source, bulk"
              },
              {
                "id": "XMb",
                "displayName": "Mb",
                "spiceType": "X",
                "model": "sg13_lv_nmos",
                "parametersOrValue": "w=10u l=1u ng=2 m=1",
                "source": "XMb out bn 0 0 sg13_lv_nmos w=10u l=1u ng=2 m=1",
                "pins": [
                  {
                    "id": "d",
                    "net": "out"
                  },
                  {
                    "id": "g",
                    "net": "bn"
                  },
                  {
                    "id": "s",
                    "net": "0"
                  },
                  {
                    "id": "b",
                    "net": "0"
                  }
                ],
                "pinMeaning": "MOS drain, gate, source, bulk"
              },
              {
                "id": "Vin",
                "displayName": "Vin",
                "spiceType": "V",
                "model": null,
                "parametersOrValue": "0",
                "source": "Vin in 0 0",
                "pins": [
                  {
                    "id": "p",
                    "net": "in"
                  },
                  {
                    "id": "n",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              }
            ],
            "nets": [
              {
                "id": "vdd",
                "ground": false,
                "terminals": [
                  {
                    "device": "Vdd",
                    "pin": "p"
                  },
                  {
                    "device": "XM1",
                    "pin": "d"
                  },
                  {
                    "device": "Iref",
                    "pin": "p"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "0",
                "ground": true,
                "terminals": [
                  {
                    "device": "Vdd",
                    "pin": "n"
                  },
                  {
                    "device": "XM1",
                    "pin": "b"
                  },
                  {
                    "device": "XMr",
                    "pin": "s"
                  },
                  {
                    "device": "XMr",
                    "pin": "b"
                  },
                  {
                    "device": "XMb",
                    "pin": "s"
                  },
                  {
                    "device": "XMb",
                    "pin": "b"
                  },
                  {
                    "device": "Vin",
                    "pin": "n"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "in",
                "ground": false,
                "terminals": [
                  {
                    "device": "XM1",
                    "pin": "g"
                  },
                  {
                    "device": "Vin",
                    "pin": "p"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "out",
                "ground": false,
                "terminals": [
                  {
                    "device": "XM1",
                    "pin": "s"
                  },
                  {
                    "device": "XMb",
                    "pin": "d"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "bn",
                "ground": false,
                "terminals": [
                  {
                    "device": "Iref",
                    "pin": "n"
                  },
                  {
                    "device": "XMr",
                    "pin": "d"
                  },
                  {
                    "device": "XMr",
                    "pin": "g"
                  },
                  {
                    "device": "XMb",
                    "pin": "g"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              }
            ]
          }
        ],
        "uninstantiatedDefinitions": [],
        "dut": {
          "kind": "top-level-device-set",
          "scope": "top",
          "devices": [
            "XM1",
            "XMr",
            "XMb"
          ]
        }
      },
      {
        "id": "graph-3",
        "kind": "functional-graph",
        "classification": "heuristic-device-grouping",
        "electricalScope": "dut",
        "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.",
        "nodes": [
          {
            "id": "block-1",
            "label": "Follower",
            "devices": [
              {
                "scope": "dut",
                "device": "XM1"
              }
            ],
            "inferredStages": [
              1
            ]
          },
          {
            "id": "block-2",
            "label": "Bias sink",
            "devices": [
              {
                "scope": "dut",
                "device": "XMb"
              }
            ],
            "inferredStages": [
              1
            ]
          },
          {
            "id": "block-3",
            "label": "Bias mirror",
            "devices": [
              {
                "scope": "dut",
                "device": "XMr"
              }
            ],
            "inferredStages": [
              "bias"
            ]
          }
        ],
        "edges": [
          {
            "id": "net-1",
            "net": "out",
            "nodes": [
              "block-1",
              "block-2"
            ],
            "direction": "undirected-shared-net"
          },
          {
            "id": "net-2",
            "net": "bn",
            "nodes": [
              "block-3",
              "block-2"
            ],
            "direction": "undirected-shared-net"
          }
        ],
        "ports": [
          {
            "name": "vdd",
            "net": "vdd",
            "kind": "supply"
          },
          {
            "name": "in",
            "net": "in",
            "kind": "input"
          },
          {
            "name": "out",
            "net": "out",
            "kind": "output"
          },
          {
            "name": "gnd",
            "net": "0",
            "kind": "ground"
          },
          {
            "name": "bn",
            "net": "bn",
            "kind": "bias"
          }
        ],
        "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes."
      }
    ],
    "views": [
      {
        "bench": "dc",
        "source": {
          "recordField": "testbenches",
          "id": "dc",
          "field": "netlist"
        },
        "schematic": {
          "graph": "graph-1",
          "svg": {
            "url": "/circuits/source-follower/dc-schematic.svg",
            "asset": "dc-schematic.svg"
          },
          "drawingCheck": {
            "method": "checkSchematic",
            "problems": []
          },
          "sheets": [
            {
              "name": "Source follower",
              "instances": []
            }
          ]
        },
        "benchDiagram": {
          "graph": "graph-2",
          "svg": {
            "url": "/circuits/source-follower/dc-bench.svg",
            "asset": "dc-bench.svg"
          }
        },
        "blockDiagram": {
          "graph": "graph-3",
          "electricalGraph": "graph-1",
          "svg": {
            "url": "/circuits/source-follower/dc-block.svg",
            "asset": "dc-block.svg"
          }
        }
      }
    ]
  }
}