{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "strongarm", "name": "StrongARM latch comparator", "group": "Comparators", "subgroup": "Clocked", "title": "StrongARM latch comparator", "summary": "This clocked comparator decides which input voltage is higher. A small current difference starts the decision, then positive feedback drives the outputs apart. Nearly equal inputs take longer to resolve, and device mismatch can shift the decision threshold.", "reference": { "kind": "paper", "authors": "B. Razavi", "title": "The StrongARM Latch [A Circuit for All Seasons]", "publisher": "IEEE Solid-State Circuits Magazine, vol. 7, no. 2", "year": 2015, "where": "the topology, its four phases, and the regeneration time constant", "takes": "The circuit as drawn here, and the result that decision time grows as ln(1/V_id) with a time constant tau = C/gm.", "also": [ { "authors": "J. Montanaro et al.", "title": "A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor", "publisher": "IEEE Journal of Solid-State Circuits, vol. 31, no. 11", "year": 1996, "where": "the StrongARM SA-110, where this latch first appeared and from which it takes its name" } ] }, "resources": { "record": "/circuits/strongarm.json", "page": "/index.html#strongarm", "achieved": "/achieved/strongarm.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice" ], "ports": [ { "name": "inp", "kind": "input", "polarity": "+" }, { "name": "inn", "kind": "input", "polarity": "-" }, { "name": "clk", "kind": "clock", "note": "low precharges, high evaluates" }, { "name": "outp", "kind": "output" }, { "name": "outn", "kind": "output" }, { "name": "vdd", "kind": "supply", "note": "latch and precharge supply, including PMOS well connections" }, { "name": "0", "kind": "ground", "note": "tail-source and NMOS substrate return" } ], "devices": [ { "name": "Mtail", "type": "nmos", "sizedBy": [ "Wt", "L" ], "role": "tail switch, gated by the clock", "fingers": 2, "copies": 1 }, { "name": "M1", "type": "nmos", "sizedBy": [ "Wi", "L" ], "role": "input pair", "fingers": 2, "copies": 1 }, { "name": "M2", "type": "nmos", "sizedBy": [ "Wi", "L" ], "role": "input pair", "fingers": 2, "copies": 1 }, { "name": "M3", "type": "nmos", "sizedBy": [ "Wn", "L" ], "role": "cross-coupled regenerative pair", "fingers": 1, "copies": 1 }, { "name": "M4", "type": "nmos", "sizedBy": [ "Wn", "L" ], "role": "cross-coupled regenerative pair", "fingers": 1, "copies": 1 }, { "name": "M5", "type": "pmos", "sizedBy": [ "Wp", "L" ], "role": "cross-coupled regenerative pair", "fingers": 1, "copies": 1 }, { "name": "M6", "type": "pmos", "sizedBy": [ "Wp", "L" ], "role": "cross-coupled regenerative pair", "fingers": 1, "copies": 1 }, { "name": "M7", "type": "pmos", "sizedBy": [ "Wpc", "L" ], "role": "precharge", "fingers": 1, "copies": 1 }, { "name": "M8", "type": "pmos", "sizedBy": [ "Wpc", "L" ], "role": "precharge", "fingers": 1, "copies": 1 }, { "name": "M9", "type": "pmos", "sizedBy": [ "Wpc", "L" ], "role": "precharge", "fingers": 1, "copies": 1 }, { "name": "M10", "type": "pmos", "sizedBy": [ "Wpc", "L" ], "role": "precharge", "fingers": 1, "copies": 1 } ], "intent": [ { "rule": "match", "of": [ "M1", "M2" ], "why": "Input pair. In a comparator their mismatch is the offset directly, and it is the dominant term - the cross-coupled pair amplifies whatever imbalance it is handed, including its own." }, { "rule": "match", "of": [ "M3", "M4", "M5", "M6" ], "why": "The regenerative pair must be balanced or it has a preferred outcome regardless of the input." }, { "rule": "no-static-current", "of": [ "Mtail" ], "constraint": "tail gated by the clock", "why": "The clock enables brief evaluation and reset current pulses instead of an intentional continuous bias current. Device leakage remains between decisions." }, { "rule": "precharge", "of": [ "M7", "M8", "M9", "M10" ], "constraint": "reset both outputs and both drains while clk is low", "why": "Without a full reset the previous decision biases the next one - the latch remembers, and the memory looks exactly like offset." }, { "rule": "regeneration", "of": [ "M3", "M4", "M5", "M6" ], "constraint": "t_decision ~ tau*ln(1/V_id), tau = C/gm", "why": "Each decade of extra overdrive buys a roughly constant amount of time. Sizing the latch is choosing tau against the clock budget, and a smaller output capacitance is worth more than a bigger device." } ], "specs": [ { "key": "tdec", "label": "Decision time", "unit": "s", "direction": "min" }, { "key": "tau", "label": "Regeneration time constant", "unit": "s", "direction": "min" }, { "key": "istatic", "label": "Latched supply current", "unit": "A", "direction": "min", "constraint": "no intentional DC bias path; leakage is measured, with no numeric limit specified" } ], "explanation": { "idea": "This clocked comparator decides which input voltage is higher. A small current difference starts the decision, then positive feedback drives the outputs apart. Nearly equal inputs take longer to resolve, and device mismatch can shift the decision threshold.", "detail": "Decides in one clock phase which of two inputs is higher and resolves the answer to full logic levels, with no intentional static bias path; physical device leakage remains. With clk low, M7–M10 precharge both outputs and both internal drains to V_DD; when clk rises, the input pair turns V_id into a small current imbalance, and the cross-coupled inverters M3–M6 amplify it by positive feedback, approximately exponentially with time constant τ = C/g_m, until one output reaches ground. A small V_id means a long decision, possibly unfinished in time: metastability.", "lesson": { "relation": 1, "symbols": "t_dec is decision time; t_0 is the initial integration delay; τ is the regeneration time constant; ΔV_out is the required output separation; A_0 is the initial input-phase gain; V_id is the magnitude of the differential input beyond the actual threshold.", "assumptions": "The logarithmic estimate applies during approximately exponential regeneration, with fixed load and operating point. It is not a deterministic bound at zero overdrive, where mismatch and noise matter.", "exercise": { "param": "vid", "value": 0.001, "analysis": "tran", "expect": "The smaller input difference should take longer to produce a decision. Compare the output separation with the clock edge and check whether it resolves within the available time." }, "limits": "The clock must fully reset the latch before each decision. Input common mode, source impedance, kickback and output load affect operation. Ideal input sources in this bench absorb kickback; physical sources do not. Leakage and random decision errors are not zero. Decision time requires sustained resolution of the expected polarity. The overdrive sweep retains unresolved rows, and its apparent time constant is an endpoint slope over 1–200 mV, not an isolated intrinsic C/gm measurement." }, "path": [ { "part": "Precharge", "devices": "M7, M8, M9, M10", "does": "While clk is low M7–M10 pull outp, outn, dip and din to V_DD and Mtail is off, so every decision starts balanced without an intentional DC conduction path. Device leakage is not zero." }, { "part": "Input integration", "devices": "Mtail, M1, M2", "does": "When clk rises, Mtail turns on and M1 and M2 discharge dip and din at rates set by inp and inn, turning V_id into a growing voltage difference." }, { "part": "NMOS regeneration", "devices": "M3, M4", "does": "Once dip and din fall about V_thn below V_DD, M3 and M4 conduct and discharge outn and outp; their crossed gates start amplifying the difference." }, { "part": "Full regeneration", "devices": "M5, M6", "does": "When an output falls a PMOS threshold below V_DD, M5 and M6 join: the cross-coupled inverters drive outn to ground when inp > inn and restore outp to V_DD." } ], "bias": "No intentional bias current: Mtail is a switch driven by clk. The large current pulses occur during evaluation and precharge; the bench also measures the residual supply current at the end of the transient, without assuming zero leakage. The vdd and ground ports power the latch and provide its body connections. The bench holds inp and inn at V_CM ± V_id/2, 0.8 V and 10 mV by default, and loads each output with C_out, 5 fF.", "relations": [ { "what": "Regeneration", "expr": "ΔV(t) = ΔV_0·e^(t/τ), τ = C/g_m", "note": "C is an output node's capacitance, g_m the cross-coupled pair's" }, { "what": "Decision time", "expr": "t_dec ≈ t_0 + τ·ln(ΔV_out/(A_0·V_id))", "note": "A_0 is the input phase's gain; each decade less overdrive adds τ·ln 10 ≈ 2.3τ" }, { "what": "Offset", "expr": "σ_Vos ≈ A_Vt/√(W·L)", "note": "Pelgrom mismatch of M1 and M2; the latch pair's own adds, divided by A_0" }, { "what": "Kickback", "expr": "Δv_in ≈ C_gd·Δv_d/(C_gd + C_src)", "note": "dip and din swing by about V_DD; the bench's ideal sources absorb it, a floating capacitor would not" } ], "tradeoffs": [ "C_out: τ = C/g_m grows in proportion to the load, slowing every decision and widening the range of overdrives left undecided in time.", "W latch N and W latch P: widening them raises g_m, but their own capacitance loads the outputs, so τ shrinks less than proportionally.", "W input pair: a wider pair lowers offset (σ ∝ 1/√(W·L)) and raises the integration gain, but loads the inputs and raises kickback through C_gd.", "V_CM: a higher common mode discharges dip and din sooner, shortening the decision, but leaves less integration gain, so the latch pair's offset matters more." ] }, "sizing": [ { "key": "Wi", "label": "W input pair", "unit": "m", "value": 0.000008, "min": 1.5e-7, "max": 0.0001, "kind": "si" }, { "key": "Wt", "label": "W tail", "unit": "m", "value": 0.000008, "min": 1.5e-7, "max": 0.0001, "kind": "si" }, { "key": "Wn", "label": "W latch N", "unit": "m", "value": 0.000004, "min": 1.5e-7, "max": 0.0001, "kind": "si" }, { "key": "Wp", "label": "W latch P", "unit": "m", "value": 0.000004, "min": 1.5e-7, "max": 0.0001, "kind": "si" }, { "key": "Wpc", "label": "W precharge", "unit": "m", "value": 0.000002, "min": 1.5e-7, "max": 0.00005, "kind": "si" }, { "key": "L", "label": "L", "unit": "m", "value": 1.3e-7, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "CL", "label": "C_out", "unit": "F", "value": 5e-15, "min": 1e-15, "max": 2e-13, "kind": "si" }, { "key": "VCM", "label": "V_CM", "unit": "V", "value": 0.8, "min": 0.4, "max": 1.2, "kind": "si" }, { "key": "vid", "label": "Input overdrive", "unit": "V", "value": 0.01, "min": 0.0001, "max": 0.5, "kind": "si" } ], "testbenches": [ { "id": "tran", "label": "One decision", "note": "", "measures": [ "tdec", "polarity" ], "metricKeys": [ "t_dec", "istatic" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* StrongARM latch comparator\n.include sg13g2_lv_tt.spice\n* the supply, which the clock swings to as a clock driver on it would\n.param VDD=1.2\nVdd vdd 0 {VDD}\n* clock low = precharge, clock high = evaluate\nVclk clk 0 pulse(0 {VDD} 2n 50p 50p 20n 80n)\nVinp inp 0 805m\nVinn inn 0 795m\n* tail and input pair\nXMtail tail clk 0 0 sg13_lv_nmos w=8u l=130n ng=2 m=1\nXM1 dip inp tail 0 sg13_lv_nmos w=8u l=130n ng=2 m=1\nXM2 din inn tail 0 sg13_lv_nmos w=8u l=130n ng=2 m=1\n* cross-coupled regenerative pair\nXM3 outn outp dip 0 sg13_lv_nmos w=4u l=130n ng=1 m=1\nXM4 outp outn din 0 sg13_lv_nmos w=4u l=130n ng=1 m=1\nXM5 outn outp vdd vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXM6 outp outn vdd vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\n* precharge devices, on while the clock is low\nXM7 outn clk vdd vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\nXM8 outp clk vdd vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\nXM9 dip clk vdd vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\nXM10 din clk vdd vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\nCp outp 0 5f\nCn outn 0 5f\n.tran 5p 20n\n.end" }, { "id": "meta", "label": "Decision time vs overdrive", "note": "Eight positive-overdrive runs, 1–200 mV. Every requested point is retained; wrong-polarity or unresolved decisions have no valid decision time.", "measures": [ "tdec", "tau" ], "metricKeys": [ "t_dec_small", "tau" ], "acceptance": [], "acceptanceRules": [], "cards": [ "sg13g2_lv_tt.spice" ], "netlist": "* StrongARM latch comparator\n.include sg13g2_lv_tt.spice\n* the supply, which the clock swings to as a clock driver on it would\n.param VDD=1.2\nVdd vdd 0 {VDD}\n* clock low = precharge, clock high = evaluate\nVclk clk 0 pulse(0 {VDD} 4n 50p 50p 40n 160n)\nVinp inp 0 800.5m\nVinn inn 0 799.5m\n* tail and input pair\nXMtail tail clk 0 0 sg13_lv_nmos w=8u l=130n ng=2 m=1\nXM1 dip inp tail 0 sg13_lv_nmos w=8u l=130n ng=2 m=1\nXM2 din inn tail 0 sg13_lv_nmos w=8u l=130n ng=2 m=1\n* cross-coupled regenerative pair\nXM3 outn outp dip 0 sg13_lv_nmos w=4u l=130n ng=1 m=1\nXM4 outp outn din 0 sg13_lv_nmos w=4u l=130n ng=1 m=1\nXM5 outn outp vdd vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\nXM6 outp outn vdd vdd sg13_lv_pmos w=4u l=130n ng=1 m=1\n* precharge devices, on while the clock is low\nXM7 outn clk vdd vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\nXM8 outp clk vdd vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\nXM9 dip clk vdd vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\nXM10 din clk vdd vdd sg13_lv_pmos w=2u l=130n ng=1 m=1\nCp outp 0 5f\nCn outn 0 5f\n.tran 10p 40n\n.end" } ], "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "66ee69b5ad2e7ef93a3ab1e8cd5919bcbe17c298c271a98e2004e1fc00cb98ec" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/strongarm.js", "sha256": "ae7977785fe4df43108f7ea6226f913f849b06b91229d28f4171d2e541956c00" }, "simulationFingerprints": { "tran": "255b97812b72b8b03e7d9a4fb3f6abea4dc0a33d21408c68986df6905358feb2", "meta": "ebb7c55a8dca37b41ee6260f183aaa6209749e46ccfed82dd25b5a0f3a7e45c4" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "891f8c654c358cf1509b6cf149ab114845f51b38616053a4c17223a206138a33", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "strongarm", "parameters": { "Wi": 0.000008, "Wt": 0.000008, "Wn": 0.000004, "Wp": 0.000004, "Wpc": 0.000002, "L": 1.3e-7, "CL": 5e-15, "VCM": 0.8, "vid": 0.01 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/strongarm/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "top", "ports": [ { "name": "clk", "net": "clk", "kind": "clock" }, { "name": "gnd", "net": "0", "kind": "ground" }, { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "outn", "net": "outn", "kind": "output" }, { "name": "outp", "net": "outp", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" } ], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "XMtail", "displayName": "Mtail", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XMtail tail clk 0 0 sg13_lv_nmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "tail" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "0" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XM1 dip inp tail 0 sg13_lv_nmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "dip" }, { "id": "g", "net": "inp" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=8u l=130n ng=2 m=1", "source": "XM2 din inn tail 0 sg13_lv_nmos w=8u l=130n ng=2 m=1", "pins": [ { "id": "d", "net": "din" }, { "id": "g", "net": "inn" }, { "id": "s", "net": "tail" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XM3 outn outp dip 0 sg13_lv_nmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "outp" }, { "id": "s", "net": "dip" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM4", "displayName": "M4", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XM4 outp outn din 0 sg13_lv_nmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "outn" }, { "id": "s", "net": "din" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XM5 outn outp vdd vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "outp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XM6 outp outn vdd vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", 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"pin": "g" } ], "ports": [ "inn" ], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM4", "pin": "g" }, { "device": "XM5", "pin": "d" }, { "device": "XM6", "pin": "g" }, { "device": "XM7", "pin": "d" } ], "ports": [ "outn" ], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" } ], "ports": [ "outp" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "{VDD}", "source": "Vdd vdd 0 {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vclk", "displayName": "Vclk", "spiceType": "V", "model": null, "parametersOrValue": "pulse(0 {VDD} 2n 50p 50p 20n 80n)", "source": "Vclk clk 0 pulse(0 {VDD} 2n 50p 50p 20n 80n)", "pins": [ { "id": "p", "net": "clk" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vinp", "displayName": "Vinp", "spiceType": "V", "model": null, "parametersOrValue": "805m", "source": "Vinp inp 0 805m", "pins": [ { "id": "p", "net": "inp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE 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"net": "outn" }, { "id": "s", "net": "din" }, { "id": "b", "net": "0" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM5", "displayName": "M5", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XM5 outn outp vdd vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "outp" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM6", "displayName": "M6", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=4u l=130n ng=1 m=1", "source": "XM6 outp outn vdd vdd sg13_lv_pmos w=4u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "outn" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM7", "displayName": "M7", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XM7 outn clk vdd vdd sg13_lv_pmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outn" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM8", "displayName": "M8", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XM8 outp clk vdd vdd sg13_lv_pmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "outp" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM9", "displayName": "M9", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XM9 dip clk vdd vdd sg13_lv_pmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "dip" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM10", "displayName": "M10", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=2u l=130n ng=1 m=1", "source": "XM10 din clk vdd vdd sg13_lv_pmos w=2u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "din" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "Cp", "displayName": "Cp", "spiceType": "C", "model": null, "parametersOrValue": "5f", "source": "Cp outp 0 5f", "pins": [ { "id": "p", "net": "outp" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Cn", "displayName": "Cn", "spiceType": "C", "model": null, "parametersOrValue": "5f", "source": "Cn outn 0 5f", "pins": [ { "id": "p", "net": "outn" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "XM5", "pin": "s" }, { "device": "XM5", "pin": "b" }, { "device": "XM6", "pin": "s" }, { "device": "XM6", "pin": "b" }, { "device": "XM7", "pin": "s" }, { "device": "XM7", "pin": "b" }, { "device": "XM8", "pin": "s" }, { "device": "XM8", "pin": "b" }, { "device": "XM9", "pin": "s" }, { "device": "XM9", "pin": "b" }, { "device": "XM10", "pin": "s" }, { "device": "XM10", "pin": "b" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vclk", "pin": "n" }, { "device": "Vinp", "pin": "n" }, { "device": "Vinn", "pin": "n" }, { "device": "XMtail", "pin": "s" }, { "device": "XMtail", "pin": "b" }, { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "b" }, { "device": "XM3", "pin": "b" }, { "device": "XM4", "pin": "b" }, { "device": "Cp", "pin": "n" }, { "device": "Cn", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "Vclk", "pin": "p" }, { "device": "XMtail", "pin": "g" }, { "device": "XM7", "pin": "g" }, { "device": "XM8", "pin": "g" }, { "device": "XM9", "pin": "g" }, { "device": "XM10", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inp", "ground": false, "terminals": [ { "device": "Vinp", "pin": "p" }, { "device": "XM1", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "inn", "ground": false, "terminals": [ { "device": "Vinn", "pin": "p" }, { "device": "XM2", "pin": "g" } ], "ports": [], "voltageReferences": [] }, { "id": "tail", "ground": false, "terminals": [ { "device": "XMtail", "pin": "d" }, { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "s" } ], "ports": [], "voltageReferences": [] }, { "id": "dip", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" }, { "device": "XM3", "pin": "s" }, { "device": "XM9", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "din", "ground": false, "terminals": [ { "device": "XM2", "pin": "d" }, { "device": "XM4", "pin": "s" }, { "device": "XM10", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "outn", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM4", "pin": "g" }, { "device": "XM5", "pin": "d" }, { "device": "XM6", "pin": "g" }, { "device": "XM7", "pin": "d" }, { "device": "Cn", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "outp", "ground": false, "terminals": [ { "device": "XM3", "pin": "g" }, { "device": "XM4", "pin": "d" }, { "device": "XM5", "pin": "g" }, { "device": "XM6", "pin": "d" }, { "device": "XM8", "pin": "d" }, { "device": "Cp", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "top-level-device-set", "scope": "top", "devices": [ "XMtail", "XM1", "XM2", "XM3", "XM4", "XM5", "XM6", "XM7", "XM8", "XM9", "XM10" ] } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Tail switch", "devices": [ { "scope": "dut", "device": "XMtail" } ], "inferredStages": [ 1 ] }, { "id": "block-2", "label": "Input pair", "devices": [ { "scope": "dut", "device": "XM1" }, { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 1 ] }, { "id": "block-3", "label": "Cross-coupled regenerative pair", "devices": [ { "scope": "dut", "device": "XM3" }, { "scope": "dut", "device": "XM4" }, { "scope": "dut", "device": "XM5" }, { "scope": "dut", "device": "XM6" } ], "inferredStages": [ 2 ] }, { "id": "block-4", "label": "Precharge", "devices": [ { "scope": "dut", "device": "XM7" }, { "scope": "dut", "device": "XM8" }, { "scope": "dut", "device": "XM9" }, { "scope": "dut", "device": "XM10" } ], "inferredStages": [ 2, 1 ] } ], "edges": [ { "id": "net-1", "net": "tail", "nodes": [ "block-1", "block-2" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "clk", "nodes": [ "block-1", "block-4" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "dip", "nodes": [ "block-2", "block-3", "block-4" ], "direction": "undirected-shared-net" }, { "id": "net-4", "net": "din", "nodes": [ "block-2", "block-3", "block-4" ], "direction": "undirected-shared-net" }, { "id": "net-5", "net": "outn", "nodes": [ "block-3", "block-4" ], "direction": "undirected-shared-net" }, { "id": "net-6", "net": "outp", "nodes": [ "block-3", "block-4" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "clk", "net": "clk", "kind": "clock" }, { "name": "gnd", "net": "0", "kind": "ground" }, { "name": "inp", "net": "inp", "kind": "input" }, { "name": "inn", "net": "inn", "kind": "input" }, { "name": "outn", "net": "outn", "kind": "output" }, { "name": "outp", "net": "outp", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. 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