{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "super-follower", "name": "Super source follower", "group": "Amplifier stages", "subgroup": "Followers", "title": "Super source follower", "summary": "A source follower with local feedback that lowers its output resistance. A second transistor adjusts the current available to the load, keeping the output steadier. A compensation capacitor controls the loop's response; changing the load requires another stability check.", "reference": { "kind": "book", "authors": "P. R. Gray, P. J. Hurst, S. H. Lewis, R. G. Meyer", "title": "Analysis and Design of Analog Integrated Circuits", "edition": "5th ed.", "publisher": "Wiley", "year": 2009, "where": "Sec. 3.4.4 'The Super Source Follower' (p. 212)", "takes": "The topology - a follower whose drain current is held by a current source, and a feedback device driven from its drain that sinks the load's current - and the result that the loop divides the output resistance by its gain. The compensation at the follower's drain, the bias and the sizing are this library's, for SG13G2 at 1.2 V." }, "resources": { "record": "/circuits/super-follower.json", "page": "/index.html#super-follower", "achieved": "/achieved/super-follower.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "in", "kind": "input" }, { "name": "out", "kind": "output" }, { "name": "vdd", "kind": "supply" }, { "name": "vss", "kind": "ground" }, { "name": "ib", "kind": "bias", "note": "the reference current, drawn out of this pin" } ], "devices": [ { "name": "MB", "type": "pmos", "nodes": "ib ib vdd vdd", "sizedBy": [ "Wp", "Lp" ], "role": "bias reference, diode-connected", "fingers": 2, "copies": 1 }, { "name": "M3", "type": "pmos", "nodes": "x ib vdd vdd", "sizedBy": [ "Wp", "Lp", "K" ], "role": "follower current source; K copies of MB", "fingers": 2, "copies": 5 }, { "name": "M1", "type": "nmos", "nodes": "x in out vss", "sizedBy": [ "W1", "L1" ], "role": "follower", "fingers": 4, "copies": 1 }, { "name": "M2", "type": "nmos", "nodes": "out x vss vss", "sizedBy": [ "W2", "L2" ], "role": "feedback device", "fingers": 1, "copies": 1 }, { "name": "Cc", "type": "capacitor", "nodes": "x vss", "sizedBy": [ "Cc" ], "role": "loop compensation" } ], "intent": [ { "rule": "unit-copies", "of": [ "MB", "M3" ], "constraint": "M3 = K copies of MB", "why": "Repeating the same unit geometry sets the intended nominal current ratio and avoids a geometry-dependent threshold shift. Random mismatch and unequal drain voltages still cause copy error." }, { "rule": "loop-gain", "of": [ "M2", "M1", "M3" ], "constraint": "R_out ≈ 1/[(g_m1 + g_mb1)·g_m2·(r_o1 ∥ r_o3)]", "why": "The whole point of the circuit: a longer M1 raises r_o1 and the loop's gain with it, a wider M2 raises g_m2 - but see the window." }, { "rule": "window", "of": [ "M1", "M2" ], "constraint": "V_DSAT,2 < V_out < V_GS2 - V_DSAT,1", "why": "M1's drain sits at V_GS2, so V_GS2 is the ceiling of the output range. A narrow, short, strongly inverted M2 has a large V_GS - the ceiling rises - where a wide one would buy g_m2 and lose the range." }, { "rule": "compensation", "of": [ "Cc", "M2", "M1" ], "constraint": "ζ ≈ ½√[(g_m1 + g_mb1)·C_c/(g_m2·C_L)] > 1", "why": "Two poles in the loop: at x, high-impedance, and at the output, where the load sits; Cc makes the first dominant. The closed loop also has a zero at g_m2/C_c, below its natural frequency, so its step always overshoots a little: only a damping ratio above one, which Cc buys, holds that to a few per cent. Sized for the load: 3 pF for 1 pF." } ], "specs": [ { "key": "rout", "label": "Output resistance", "unit": "Ω", "direction": "min", "constraint": "<= 200 Ω", "min": null, "max": 200, "why": "The point of the circuit: a plain follower at this current offers about 1.4 kΩ, and the loop's gain, g_m2 (r_o1 ∥ r_o3), divides that by more than ten - 120 Ω at tt, and under 200 Ω at every corner, the hot ones highest." }, { "key": "gain_db", "label": "Gain at the bias point", "unit": "dB", "direction": "max", "constraint": ">= -2 dB", "min": -2, "max": null, "why": "A follower cannot reach one: the body effect of M1, whose bulk is on ground, costs 1 to 1.4 dB, and the loop does not win it back." }, { "key": "out_span", "label": "Output range", "unit": "V", "direction": "max", "constraint": ">= 0.35 V", "min": 0.35, "max": null, "why": "The output range over which the gain holds within 1 dB. Its ceiling is V_GS2 - V_DSAT1, where M1 leaves saturation: a short, strongly inverted M2, with its large V_GS, is what lifts it." }, { "key": "f3db_hz", "label": "Bandwidth, -3 dB", "unit": "Hz", "direction": "max", "constraint": ">= 50000000 Hz", "min": 50000000, "max": null, "why": "Into 1 pF: a buffer is no use slower than the stage it buffers." }, { "key": "peak_db", "label": "Peaking", "unit": "dB", "direction": "min", "constraint": "<= 1 dB", "min": null, "max": 1, "why": "The loop's closed response has a zero at g_m2/C_c below its natural frequency, so it always peaks a little: Cc holds the peak under 1 dB." }, { "key": "overshoot_pct", "label": "Overshoot", "unit": "%", "direction": "min", "constraint": "<= 10 %", "min": null, "max": 10, "why": "The step test for the same loop, in the time domain: overshoot falls only as the loop's damping rises, which Cc buys." }, { "key": "i_supply", "label": "Supply current", "unit": "A", "direction": "min", "constraint": "<= 0.00007 A", "min": null, "max": 0.00007, "why": "(K + 1)·Ib: the follower's current and its reference." } ], "explanation": { "idea": "This buffer uses local feedback to hold its output steadier when the load changes. One transistor follows the input; another adjusts the current left for the load. The feedback lowers output resistance, but its speed must be controlled to avoid ringing.", "detail": "M3 supplies an approximately fixed current to follower M1. Changes at M1's drain drive M2, which sinks more or less of that current at the output. This local loop reduces output resistance by its gain. Cc compensates the loop for the chosen capacitive load.", "lesson": { "relation": 0, "symbols": "R_out is output resistance in ohms. g_m1 and g_m2 are gate transconductances, and g_mb1 is M1's body transconductance, in siemens. r_o1 and r_o3 are device output resistances; ∥ means parallel combination.", "assumptions": "Low-frequency small-signal output resistance with the input held fixed, a large local-loop gain and saturated devices. It does not predict the high-frequency stability or large-signal load range.", "exercise": { "param": "Cc", "value": 6e-12, "analysis": "step", "expect": "Doubling Cc should reduce overshoot here. Check the measured settling time too: less ringing can improve it, while extra compensation can trade bandwidth for damping." }, "limits": "Supply the external reference current and stay within the input/output voltage range. Compensation must be checked again if the load changes." }, "path": [ { "part": "Follower", "devices": "M1", "does": "Gate on in, source on out: with its current fixed by M3 its V_GS barely changes, and out follows in a V_GS lower." }, { "part": "Current source", "devices": "MB, M3", "does": "Ib, drawn out of the ib pin, sets the diode MB; M3, K copies of it, feeds K·Ib into x, the follower's drain." }, { "part": "Feedback device", "devices": "M2", "does": "Gate on x, drain on out: when a load pulls on out, M1's current would change; x swings instead, and M2 takes up the difference." }, { "part": "Compensation", "devices": "Cc", "does": "On x, it makes the loop's first pole dominant, so the loop crosses over before the output pole, (g_m1 + g_mb1)/C_L, turns its phase." } ], "bias": "The testbench draws Ib, 10 µA, out of the ib pin; M3, five copies of MB, feeds 50 µA into x, and with no load M2 sinks all of it: 60 µA from the supply. The input sits at 0.74 V and the output follows about 0.41 V lower. M1's drain sits at V_GS2, about 0.74 V - M2 is short, narrow and strongly inverted so that its V_GS is large - which leaves both M1 and M2 saturated with margin at every corner.", "relations": [ { "what": "Output resistance", "expr": "R_out ≈ 1/[(g_m1 + g_mb1) · g_m2 (r_o1 ∥ r_o3)]", "note": "a plain follower's 1/(g_m1 + g_mb1), about 1.4 kΩ, divided by the loop's gain: 120 Ω at tt, under 200 Ω at every corner" }, { "what": "Gain", "expr": "A_v ≈ g_m1/(g_m1 + g_mb1)", "note": "M1's bulk is on ground, so the body effect still costs about 1.25 dB: the loop lowers R_out, not this" }, { "what": "Output window", "expr": "V_DSAT,2 < V_out < V_GS2 − V_DSAT,1", "note": "M1's drain sits at V_GS2, so a large V_GS2 lifts the ceiling" }, { "what": "Closed-loop response", "expr": "H(s) = A_v (1 + s/ω_z) ω_n²/(s² + 2ζω_n s + ω_n²), ω_z = g_m2/C_c", "note": "with ω_n² = (g_m1 + g_mb1) g_m2/(C_L C_c): the zero sits at ω_n/(2ζ), below ω_n, so the response always peaks a little" }, { "what": "Damping", "expr": "ζ ≈ ½ √[(g_m1 + g_mb1) C_c/(g_m2 C_L)]", "note": "above one with 3 pF: the step overshoots about 6 %, the gain peaks under 0.5 dB" } ], "tradeoffs": [ "Compensation (Cc): more generally reduces peaking and overshoot at a bandwidth cost. The numerator zero can cause overshoot even with overdamped poles, but it does not impose a fixed few-percent floor; check the response at the chosen load.", "Follower current (K): more current raises g_m1 and g_m2 and lowers R_out as 1/I, at more supply current and a larger V_GS2.", "Feedback device (W2, L2): wider raises g_m2 and lowers R_out, but lowers V_GS2 and with it the window's ceiling.", "Input level (VIN): the window is fixed by M1 and M2 and the bias belongs in it, a little high: hot corners push the output up while the ceiling falls, and the slow ones squeeze M2 from below." ] }, "sizing": [ { "key": "Ib", "label": "Reference current", "unit": "A", "value": 0.00001, "min": 0.000001, "max": 0.00005, "kind": "si" }, { "key": "K", "label": "Follower current, in Ib", "unit": "", "value": 5, "min": 1, "max": 20, "kind": "int" }, { "key": "Wp", "label": "W PMOS unit (MB, M3)", "unit": "m", "value": 0.000006, "min": 5e-7, "max": 0.00002, "kind": "si" }, { "key": "Lp", "label": "L PMOS unit", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "W1", "label": "W follower (M1)", "unit": "m", "value": 0.000016, "min": 3e-7, "max": 0.00005, "kind": "si" }, { "key": "L1", "label": "L follower", "unit": "m", "value": 0.000001, "min": 1.3e-7, "max": 0.000004, "kind": "si" }, { "key": "W2", "label": "W feedback device (M2)", "unit": "m", "value": 0.000001, "min": 1.5e-7, "max": 0.00002, "kind": "si" }, { "key": "L2", "label": "L feedback device", "unit": "m", "value": 1.3e-7, "min": 1.3e-7, "max": 0.000002, "kind": "si" }, { "key": "Cc", "label": "Compensation capacitor", "unit": "F", "value": 3e-12, "min": 5e-14, "max": 1e-11, "kind": "si" }, { "key": "CL", "label": "Load capacitance", "unit": "F", "value": 1e-12, "min": 1e-13, "max": 2e-11, "kind": "si" }, { "key": "VIN", "label": "Input level", "unit": "V", "value": 0.74, "min": 0.5, "max": 1.1, "kind": "si" } ], "testbenches": [ { "id": "op", "label": "Operating point", "note": "The stage with its input at its bias level: the current it draws and where its output sits.", "measures": [], "metricKeys": [ "i_supply", "vin_dc", "vout_dc", "shift" ], "acceptance": [ "i_supply" ], "acceptanceRules": [ { "key": "i_supply", "unit": "A", "min": null, "max": 0.00007, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Super source follower - operating point\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 dc 10u\n.subckt ssf in out vdd vss ib\n* bias: Ib into the PMOS diode MB; M3, K copies, holds the follower's current\nXMB ib ib vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\nXM3 x ib vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=5\n* the follower: gate on in, source on out, drain on x\nXM1 x in out vss sg13_lv_nmos w=16u l=1u ng=4 m=1\n* the feedback device: x drives it, and it sinks from out what M1 does not deliver to the load\nXM2 out x vss vss sg13_lv_nmos w=1u l=130n ng=1 m=1\n* the local loop's dominant pole, at x\nXCc x vss cap_cmim w=25.767u l=25.767u m=3\n.ends\nXdut in out vdd 0 ib ssf\nCl out 0 1p\nVin in 0 dc 740m\n.op\n.end" }, { "id": "dc", "label": "DC transfer", "note": "The input swept across the stage's range: the output, the gain against the output, and the output range - how far the output moves before that gain falls 1 dB from its peak.", "measures": [], "metricKeys": [ "gain_peak_db", "out_lo", "out_hi", "out_span", "in_span" ], "acceptance": [ "out_span" ], "acceptanceRules": [ { "key": "out_span", "unit": "V", "min": 0.35, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Super source follower - DC transfer\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 dc 10u\n.subckt ssf in out vdd vss ib\n* bias: Ib into the PMOS diode MB; M3, K copies, holds the follower's current\nXMB ib ib vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\nXM3 x ib vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=5\n* the follower: gate on in, source on out, drain on x\nXM1 x in out vss sg13_lv_nmos w=16u l=1u ng=4 m=1\n* the feedback device: x drives it, and it sinks from out what M1 does not deliver to the load\nXM2 out x vss vss sg13_lv_nmos w=1u l=130n ng=1 m=1\n* the local loop's dominant pole, at x\nXCc x vss cap_cmim w=25.767u l=25.767u m=3\n.ends\nXdut in out vdd 0 ib ssf\nCl out 0 1p\nVin in 0 dc 750m\n.dc Vin 300m 1.2 2m\n.end" }, { "id": "ac", "label": "Gain and bandwidth", "note": "Gain and phase at the bias point, into the circuit's load.", "measures": [], "metricKeys": [ "gain_db", "f3db_hz", "peak_db" ], "acceptance": [ "gain_db", "f3db_hz", "peak_db" ], "acceptanceRules": [ { "key": "gain_db", "unit": "dB", "min": -2, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "f3db_hz", "unit": "Hz", "min": 50000000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "peak_db", "unit": "dB", "min": null, "max": 1, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Super source follower - small-signal gain at the bias point\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 dc 10u\n.subckt ssf in out vdd vss ib\n* bias: Ib into the PMOS diode MB; M3, K copies, holds the follower's current\nXMB ib ib vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\nXM3 x ib vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=5\n* the follower: gate on in, source on out, drain on x\nXM1 x in out vss sg13_lv_nmos w=16u l=1u ng=4 m=1\n* the feedback device: x drives it, and it sinks from out what M1 does not deliver to the load\nXM2 out x vss vss sg13_lv_nmos w=1u l=130n ng=1 m=1\n* the local loop's dominant pole, at x\nXCc x vss cap_cmim w=25.767u l=25.767u m=3\n.ends\nXdut in out vdd 0 ib ssf\nCl out 0 1p\nVin in 0 dc 740m ac 1\n.ac dec 20 1 10g\n.end" }, { "id": "rout", "label": "Output resistance", "note": "A 1 A AC current into the output with the input held at its bias: the voltage it makes is the output impedance.", "measures": [], "metricKeys": [ "rout" ], "acceptance": [ "rout" ], "acceptanceRules": [ { "key": "rout", "unit": "Ω", "min": null, "max": 200, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Super source follower - output impedance at the bias point\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 dc 10u\n.subckt ssf in out vdd vss ib\n* bias: Ib into the PMOS diode MB; M3, K copies, holds the follower's current\nXMB ib ib vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\nXM3 x ib vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=5\n* the follower: gate on in, source on out, drain on x\nXM1 x in out vss sg13_lv_nmos w=16u l=1u ng=4 m=1\n* the feedback device: x drives it, and it sinks from out what M1 does not deliver to the load\nXM2 out x vss vss sg13_lv_nmos w=1u l=130n ng=1 m=1\n* the local loop's dominant pole, at x\nXCc x vss cap_cmim w=25.767u l=25.767u m=3\n.ends\nXdut in out vdd 0 ib ssf\nCl out 0 1p\nVin in 0 dc 740m\n* 1 A of AC current into the output: v(out) is the output impedance\nIout 0 out dc 0 ac 1\n.ac dec 20 1 10g\n.end" }, { "id": "step", "label": "Step response", "note": "A 50mV step at the input around its bias level: how fast the output follows, and whether it rings.", "measures": [], "metricKeys": [ "t_settle", "overshoot_pct" ], "acceptance": [ "overshoot_pct" ], "acceptanceRules": [ { "key": "overshoot_pct", "unit": "%", "min": null, "max": 10, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* Super source follower - step response\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nIb ib 0 dc 10u\n.subckt ssf in out vdd vss ib\n* bias: Ib into the PMOS diode MB; M3, K copies, holds the follower's current\nXMB ib ib vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1\nXM3 x ib vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=5\n* the follower: gate on in, source on out, drain on x\nXM1 x in out vss sg13_lv_nmos w=16u l=1u ng=4 m=1\n* the feedback device: x drives it, and it sinks from out what M1 does not deliver to the load\nXM2 out x vss vss sg13_lv_nmos w=1u l=130n ng=1 m=1\n* the local loop's dominant pole, at x\nXCc x vss cap_cmim w=25.767u l=25.767u m=3\n.ends\nXdut in out vdd 0 ib ssf\nCl out 0 1p\nVin in 0 pulse(715m 765m 20n 1n 1n 100n 400n)\n.tran 50p 200n\n.end" } ], "measurements": { "rout": { "label": "Output resistance", "unit": "Ω", "spec": { "min": null, "max": 200 } }, "gain_db": { "label": "Gain at the bias point", "unit": "dB", "spec": { "min": -2, "max": null } }, "out_span": { "label": "Output range", "unit": "V", "spec": { "min": 0.35, "max": null } }, "f3db_hz": { "label": "Bandwidth, -3 dB", "unit": "Hz", "spec": { "min": 50000000, "max": null } }, "peak_db": { "label": "Peaking", "unit": "dB", "spec": { "min": null, "max": 1 } }, "overshoot_pct": { "label": "Overshoot", "unit": "%", "spec": { "min": null, "max": 10 } }, "i_supply": { "label": "Supply current", "unit": "A", "spec": { "min": null, "max": 0.00007 } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "0656e37b0aa2f9476b1625689a0c2b4cb73d83eba00f8dbe8606db9fb17b749d" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/super-follower.js", "sha256": "54b78fe484332de88c1a17a0d72860917fa3d08bbcd9d99a1cd153bafb71b624" }, "simulationFingerprints": { "op": "e2a4ac435d745b78d2688450354591b7f8111fee02f2074bd5f0a8990bbe1673", "dc": "3b093c6099f281049fbe4c8499a0f01663edcabfc375bbfe4256693dd88901f0", "ac": "42fb9cdcb3a86b9914f2cfacaeb786d70ea4cafefc8ca56e6178046acfc047d9", "rout": "e4b1c050ec06d88c532fa2685df75c8d78f1ece5904d70b75f9c7d7c05657bd5", "step": "098a61b729367877efc55412a9610c93b80b4a568b5a0c287745e1d471c3bcd1" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "91045d459e56648fc120dc933a153fab9a85adf499a2e1d9a4ac20a62f01e9b0", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "super-follower", "parameters": { "Ib": 0.00001, "K": 5, "Wp": 0.000006, "Lp": 0.000001, "W1": 0.000016, "L1": 0.000001, "W2": 0.000001, "L2": 1.3e-7, "Cc": 3e-12, "CL": 1e-12, "VIN": 0.74 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/super-follower/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "ssf", "ports": [ { "name": "in", "net": "in", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=1u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=1u ng=2 m=5", "source": "XM3 x ib vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=5", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=16u l=1u ng=4 m=1", "source": "XM1 x in out vss sg13_lv_nmos w=16u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "in" }, { "id": "s", "net": "out" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XM2 out x vss vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "x" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCc x vss cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "x" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM3", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM1", "pin": "d" }, { "device": "XM2", "pin": "g" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "in", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "in" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" }, { "device": "XCc", "pin": "n" } ], "ports": [ "vss" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ib", "displayName": "Ib", "spiceType": "I", "model": null, "parametersOrValue": "dc 10u", "source": "Ib ib 0 dc 10u", "pins": [ { "id": "p", "net": "ib" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "ssf", "parametersOrValue": "", "source": "Xdut in out vdd 0 ib ssf", "pins": [ { "id": "in", "net": "in" }, { "id": "out", "net": "out" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" }, { "id": "ib", "net": "ib" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/ssf" }, { "id": "Cl", "displayName": "Cl", "spiceType": "C", "model": null, "parametersOrValue": "1p", "source": "Cl out 0 1p", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 740m", "source": "Vin in 0 dc 740m", "pins": [ { "id": "p", "net": "in" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Ib", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Cl", "pin": "n" }, { "device": "Vin", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "ib", "ground": false, "terminals": [ { "device": "Ib", "pin": "p" }, { "device": "Xdut", "pin": "ib" } ], "ports": [], "voltageReferences": [] }, { "id": "in", "ground": false, "terminals": [ { "device": "Xdut", "pin": "in" }, { "device": "Vin", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Cl", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/ssf", "name": "ssf", "ports": [ { "name": "in", "net": "in" }, { "name": "out", "net": "out" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" }, { "name": "ib", "net": "ib" } ], "definitions": [], "devices": [ { "id": "XMB", "displayName": "MB", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=1u ng=2 m=1", "source": "XMB ib ib vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=1", "pins": [ { "id": "d", "net": "ib" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM3", "displayName": "M3", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=6u l=1u ng=2 m=5", "source": "XM3 x ib vdd vdd sg13_lv_pmos w=6u l=1u ng=2 m=5", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "ib" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=16u l=1u ng=4 m=1", "source": "XM1 x in out vss sg13_lv_nmos w=16u l=1u ng=4 m=1", "pins": [ { "id": "d", "net": "x" }, { "id": "g", "net": "in" }, { "id": "s", "net": "out" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XM2", "displayName": "M2", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XM2 out x vss vss sg13_lv_nmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "x" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCc", "displayName": "Cc", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=25.767u l=25.767u m=3", "source": "XCc x vss cap_cmim w=25.767u l=25.767u m=3", "pins": [ { "id": "p", "net": "x" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "ib", "ground": false, "terminals": [ { "device": "XMB", "pin": "d" }, { "device": "XMB", "pin": "g" }, { "device": "XM3", "pin": "g" } ], "ports": [ "ib" ], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMB", "pin": "s" }, { "device": "XMB", "pin": "b" }, { "device": "XM3", "pin": "s" }, { "device": "XM3", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] }, { "id": "x", "ground": false, "terminals": [ { "device": "XM3", "pin": "d" }, { "device": "XM1", "pin": "d" }, { "device": "XM2", "pin": "g" }, { "device": "XCc", "pin": "p" } ], "ports": [], "voltageReferences": [] }, { "id": "in", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" } ], "ports": [ "in" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM1", "pin": "s" }, { "device": "XM2", "pin": "d" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM1", "pin": "b" }, { "device": "XM2", "pin": "s" }, { "device": "XM2", "pin": "b" }, { "device": "XCc", "pin": "n" } ], "ports": [ "vss" ], "voltageReferences": [] } ] } ], "uninstantiatedDefinitions": [], "dut": { "kind": "subcircuit-instance", "scope": "top", "device": "Xdut", "definition": "subckt/ssf" } }, { "id": "graph-3", "kind": "functional-graph", "classification": "heuristic-device-grouping", "electricalScope": "dut", "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.", "nodes": [ { "id": "block-1", "label": "Bias reference", "devices": [ { "scope": "dut", "device": "XMB" } ], "inferredStages": [ "bias" ] }, { "id": "block-2", "label": "Follower current source; K copies of MB", "devices": [ { "scope": "dut", "device": "XM3" } ], "inferredStages": [ 1 ] }, { "id": "block-3", "label": "Follower", "devices": [ { "scope": "dut", "device": "XM1" } ], "inferredStages": [ 1 ] }, { "id": "block-4", "label": "Feedback device", "devices": [ { "scope": "dut", "device": "XM2" } ], "inferredStages": [ 1 ] }, { "id": "block-5", "label": "Loop compensation", "devices": [ { "scope": "dut", "device": "XCc" } ], "inferredStages": [ 1 ] } ], "edges": [ { "id": "net-1", "net": "ib", "nodes": [ "block-1", "block-2" ], "direction": "undirected-shared-net" }, { "id": "net-2", "net": "x", "nodes": [ "block-2", "block-3", "block-4", "block-5" ], "direction": "undirected-shared-net" }, { "id": "net-3", "net": "out", "nodes": [ "block-3", "block-4" ], "direction": "undirected-shared-net" } ], "ports": [ { "name": "in", "net": "in", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" }, { "name": "ib", "net": "ib", "kind": "bias" } ], "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes." }, { "id": "graph-4", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. 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