{ "schema": "aisic.circuit/1", "entryType": "library-block", "domain": "analog", "id": "th-nmos-dummy", "name": "NMOS track-and-hold with a dummy switch", "group": "Switches and sampling", "subgroup": "Sample and hold", "title": "NMOS track-and-hold, dummy switch", "summary": "This sampling circuit uses a half-size dummy transistor to reduce the voltage error left when the main switch opens. The dummy absorbs some unwanted charge and offsets clock coupling. The cancellation is useful but depends on device matching and clock timing.", "reference": { "kind": "book", "authors": "B. Razavi", "title": "Design of Analog CMOS Integrated Circuits", "edition": "2nd", "publisher": "McGraw-Hill", "year": 2016, "where": "Switched-capacitor circuits: the MOS sampling switch, charge injection and clock feedthrough, and the dummy switch that cancels them", "takes": "The track-and-hold and its errors, and the dummy switch: half the switch's width, shorted, clocked by the complement, so that the charge and the overlap step it draws from the hold node match what the switch leaves there. The inverter that makes the complement, and the sizing, are this library's." }, "resources": { "record": "/circuits/th-nmos-dummy.json", "page": "/index.html#th-nmos-dummy", "achieved": "/achieved/th-nmos-dummy.json", "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.", "modelCards": [ { "name": "sg13g2_lv_tt.spice", "url": "/sg13g2_lv_tt.spice", "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a" }, { "name": "sg13g2_passive_tt.spice", "url": "/sg13g2_passive_tt.spice", "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc" } ], "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.", "schema": "/schemas/circuit.schema.json" }, "specificationPolicy": { "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.", "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.", "scopes": { "nominal": { "corner": "tt", "temp": 27, "vdd": 1, "temperatureUnit": "degC", "supplyMeaning": "scale of the bench's nominal supply" } }, "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim." }, "corners": { "cards": "a deck's sg13g2__tt.spice (family lv, hv, passive, hbt) becomes sg13g2__.spice", "process": [ "tt", "ss", "ff", "sf", "fs" ], "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise", "temperatures": [ -40, 27, 125 ], "supplyScale": [ 0.9, 1, 1.1 ], "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it", "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw", "sets": { "essential": [ { "corner": "tt", "temp": 27, "vdd": 1 }, { "corner": "ss", "temp": 27, "vdd": 1 }, { "corner": "ff", "temp": 27, "vdd": 1 }, { "corner": "sf", "temp": 27, "vdd": 1 }, { "corner": "fs", "temp": 27, "vdd": 1 }, { "corner": "tt", "temp": -40, "vdd": 1 }, { "corner": "tt", "temp": 125, "vdd": 1 }, { "corner": "tt", "temp": 27, "vdd": 0.9 }, { "corner": "tt", "temp": 27, "vdd": 1.1 }, { "corner": "ss", "temp": 125, "vdd": 0.9 }, { "corner": "ff", "temp": -40, "vdd": 1.1 } ], "full": "all 45 combinations" }, "montecarlo": { "cards": { "mc": "process and mismatch", "mcmm": "mismatch only", "mcproc": "process only" }, "seed": "draw k adds .options seed=k, so draws are reproducible" } }, "technology": { "id": "sg13g2", "name": "IHP SG13G2", "node": "130 nm", "corner": "tt", "vdd": 1.2, "lmin": 1.3e-7, "wmin": 1.5e-7, "models": "sg13g2_lv_tt.spice", "devices": { "nmos": "sg13_lv_nmos", "pmos": "sg13_lv_pmos", "resistor": "rppd, rhigh", "capacitor": "cap_cmim" }, "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.", "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF." }, "implementation": { "kind": "physical-device-reference", "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.", "evidence": "schematic-simulation", "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.", "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.", "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification." }, "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "ports": [ { "name": "in", "kind": "input" }, { "name": "out", "kind": "output", "note": "the hold node" }, { "name": "clk", "kind": "clock", "note": "high tracks, low holds" }, { "name": "vdd", "kind": "supply", "note": "the inverter's supply" }, { "name": "vss", "kind": "ground" } ], "devices": [ { "name": "M1", "type": "nmos", "nodes": "in clk out vss", "sizedBy": [ "W", "L" ], "role": "the sampling switch, two copies of the unit", "fingers": 1, "copies": 2 }, { "name": "MD", "type": "nmos", "nodes": "out clkb out vss", "sizedBy": [ "W", "L", "dummy" ], "role": "the dummy: one copy, shorted across the hold node, on while holding", "fingers": 1, "copies": 1 }, { "name": "MI1", "type": "nmos", "nodes": "clkb clk vss vss", "sizedBy": [ "Wi", "L", "dummy" ], "role": "the inverter that makes clkb, pull-down", "fingers": 1, "copies": 1 }, { "name": "MI2", "type": "pmos", "nodes": "clkb clk vdd vdd", "sizedBy": [ "Wi", "L", "dummy" ], "role": "the inverter that makes clkb, pull-up, twice MI1's width", "fingers": 1, "copies": 1 }, { "name": "CH", "type": "capacitor", "nodes": "out vss", "sizedBy": [ "CH" ], "role": "the hold capacitor" } ], "intent": [ { "rule": "half-size", "of": [ "MD", "M1" ], "constraint": "MD = one copy of the unit, M1 = two", "why": "M1 has total width 2W and MD has width W. If half of M1's channel charge reaches the hold node when it opens, turning on MD draws approximately that amount back. Equal-length copies preserve the intended 2:1 geometry, but do not guarantee equal charge partition or perfect matching." }, { "rule": "feedthrough", "of": [ "MD", "M1" ], "constraint": "MD's two overlaps = M1's one", "why": "M1's gate overlap at the hold node couples the clock's fall onto C_H. MD has half the width but both ends on that node, so its two overlaps approximately balance M1's one. The rising complementary clock then couples a step of the opposite sign." }, { "rule": "timing", "of": [ "MI1", "MI2", "MD" ], "constraint": "clkb rises a gate delay after clk falls", "why": "The inverter delays the dummy's turn-on relative to the falling clock. If M1 is still conducting, some charge drawn by MD comes from the input source instead of C_H. Clock slew and inverter loading therefore affect cancellation. The bench keeps its 100 ps clock fall and the inverter's sizes unchanged when the switch and capacitor are enlarged." }, { "rule": "range", "of": [ "M1" ], "constraint": "v_in ≤ 0.4 V_DD", "why": "An NMOS switch loses gate overdrive as the input rises, and body effect raises its threshold. The supported range stops at 40 % of supply, or 0.48 V at 1.2 V. A wider switch lowers resistance but does not make this a rail-to-rail sampler; higher signals need a different switch arrangement." }, { "rule": "trade", "of": [ "M1", "CH" ], "constraint": "first order: pedestal ∝ W L / C_H, bandwidth ∝ W / (L C_H)", "why": "The default W = 3.5 µm and C_H = 1.55 pF balance endpoint bandwidth and residual pedestal. Wider switches lower resistance; the larger capacitor limits voltage error and the ideal kT/C noise estimate. The costs are more switch and capacitor area, clock loading and possible leakage. At 27 °C, sqrt(kT/C_H) is about 51.7 µV rms analytically; this is not simulated sampled thermal noise." } ], "specs": [ { "key": "ron_max", "label": "On-resistance, worst over the range", "unit": "Ω", "direction": "min", "constraint": "<= 1500 Ω", "min": null, "max": 1500, "why": "M1 is two copies of the switch unit, for 7 µm total width at the default sizing. More width lowers on-resistance. As the input rises, less gate overdrive and more body effect raise the resistance. The DC bench sweeps the intended 0–40 % of V_DD range; its maximum is over sampled points, which need not land on the exact upper endpoint." }, { "key": "ped_mid", "label": "Pedestal, mid-range", "unit": "V", "direction": "target", "constraint": ">= -0.0005 V, <= 0.0005 V", "min": -0.0005, "max": 0.0005, "why": "The half-size dummy approximately cancels the main switch's released charge and clock coupling. Uneven charge partition, clock timing and mismatch leave a residual pedestal. The larger hold capacitor limits that voltage error without changing the acceptance band." }, { "key": "ped_max", "label": "Pedestal, worst sampled level", "unit": "V", "direction": "min", "constraint": "<= 0.0005 V", "min": null, "max": 0.0005, "why": "Charge cancellation changes with input level. Check the absolute residual at every sampled level, including both range endpoints; a small mid-range error alone is not enough." }, { "key": "i_leak", "label": "Off leakage, worst over the range", "unit": "A", "direction": "min", "constraint": "<= 1e-8 A", "min": null, "max": 1e-8, "why": "While holding, the main switch's off current, the dummy's gate current and the hold node's junction currents can change the sample. Wider switches can increase leakage, especially when hot, so the current limit remains a separate sizing constraint." }, { "key": "droop", "label": "Droop on the held capacitance", "unit": "V/s", "direction": "min", "constraint": "<= 10000 V/s", "min": null, "max": 10000, "why": "The estimated hold-voltage slope is the measured worst leakage divided by C_H. A larger hold capacitor reduces this estimate, but does not reduce the leakage current itself." }, { "key": "bw_min", "label": "Track bandwidth, worst sampled level", "unit": "Hz", "direction": "max", "constraint": ">= 120000000 Hz", "min": 120000000, "max": null, "why": "Track bandwidth depends on on-resistance and the held capacitance. The wider switch lowers resistance while the larger capacitor controls pedestal. The AC bench includes the exact 40 % of V_DD endpoint, where the NMOS has least gate overdrive; bandwidth alone is not a transient settling guarantee." } ], "explanation": { "idea": "This sampling circuit uses a half-size dummy transistor to reduce the voltage error left when the main switch opens. The dummy absorbs some unwanted charge and offsets clock coupling. The cancellation is useful but depends on device matching and clock timing.", "detail": "While clk is high, the NMOS switch M1 joins the input to the hold capacitor C_H. When clk falls, M1 releases channel charge and couples part of the clock step onto the held voltage. The half-size dummy MD has both ends on the hold node and turns on through the inverted clock. Its channel charge and clock coupling oppose M1's error, but cancellation is approximate. The default uses a 7 µm main switch, a 3.5 µm dummy and a 1.55 pF hold capacitor: wider switches improve endpoint tracking, while the larger capacitor limits residual pedestal. The inverter and clock timing are unchanged.", "lesson": { "relation": 1, "symbols": "ΔV_M1 is the main switch's voltage step on the hold node; (W L)_M1 uses M1's total width, twice the W unit parameter, and its channel length; C_ox is oxide capacitance per area; V_DD is clock high level; v_in is input voltage; V_th is threshold; C_H is hold capacitance; C_ov,M1 is overlap capacitance to the hold node.", "assumptions": "This first-order estimate assumes half the channel charge reaches the hold node and the input source is stiff. The dummy cancels it only approximately; charge partition, body effect, clock timing and mismatch change the residual.", "exercise": { "param": "dummy", "value": "off", "analysis": "inj", "expect": "Without the dummy, the main switch should leave a much larger negative voltage pedestal. Compare the error across the input range to see how much cancellation the dummy provides. Disabling it deliberately sacrifices that benefit, so the pedestal limits may no longer be met." }, "limits": "The intended input range ends at 40% of supply for this NMOS-only sampler. The on-core inverter generates the dummy clock, but input source impedance, clock edge shape and downstream load are bench assumptions. Leakage still causes droop, and the transient does not measure sampled thermal noise." }, "path": [ { "part": "Track", "devices": "M1, CH", "does": "With clk high, M1 conducts and C_H follows the input. M1 is two copies of the 3.5 µm unit at the default sizing. Its on-resistance rises toward the upper input limit as gate overdrive falls." }, { "part": "Sampling instant", "devices": "M1", "does": "As clk falls, some of M1's channel charge reaches C_H and its gate overlap couples a falling-clock step. The charge split depends on the input level, clock slew and source impedance." }, { "part": "Cancellation", "devices": "MD, MI1, MI2", "does": "MI1–MI2 invert clk into clkb. Turning on the half-size dummy draws charge from C_H, while its two overlaps couple a rising-clock step. Both oppose the main switch's error, without guaranteeing exact cancellation." }, { "part": "Hold", "devices": "CH", "does": "With M1 off, C_H holds the sample. Off-state, gate and junction leakage gradually change its voltage; the leakage bench estimates the worst droop as current divided by C_H." } ], "bias": "No separate bias current is required. The bench drives M1's gate from 0 to V_DD with a 100 ps fall, and the on-core inverter makes clkb from the same supply. The supported input range stops at 40 % of V_DD, or 0.48 V at 1.2 V. Wider switches reduce resistance but do not remove the NMOS headroom limit.", "relations": [ { "what": "On-resistance", "expr": "R_on ≈ 1/(µ_n C_ox (W/L)_M1 (V_DD − v_in − V_th(v_in)))", "note": "First-order trend: resistance increases as gate overdrive falls and body effect raises the threshold. Use the model sweep for numerical values." }, { "what": "Injected charge", "expr": "ΔV_M1 ≈ −(W L C_ox)_M1 (V_DD − v_in − V_th)/(2 C_H) − C_ov,M1 V_DD/C_H", "note": "Assumes half the main switch's channel charge reaches the held capacitor; actual partition and clock feedthrough depend on the circuit and timing." }, { "what": "Dummy", "expr": "ΔV_MD ≈ +(W L C_ox)_MD (V_DD − v_out − V_th)/C_H + 2 C_ov,MD V_DD/C_H", "note": "MD = M1/2 and v_out = v_in: equal and opposite, if M1's charge splits evenly" }, { "what": "Ideal sampled thermal-noise estimate", "expr": "v_n^2 = kT/C_H", "note": "For ideal settled sampling at 27 °C on the default 1.55 pF, sqrt(kT/C_H) is about 51.7 µV rms. This is an analytic estimate, not thermal noise measured by these deterministic simulations." } ], "tradeoffs": [ "W (the switch unit): wider lowers R_on, but adds switch area, clock loading and possible leakage. Both main and dummy widths increase together to preserve the 2:1 ratio.", "C_H: a larger capacitor reduces the ideal kT/C noise estimate and converts a given residual charge or leakage current into less voltage error. It costs area and slows tracking at fixed switch resistance.", "The defaults increase W from 2 to 3.5 µm and C_H from 1 to 1.55 pF. This balances bandwidth at the exact input-range endpoint against pedestal and leakage, without relaxing any limit.", "Wi (the inverter): complementary-clock delay affects cancellation. If the dummy turns on while M1 still conducts, part of its charge comes from the input instead of the hold capacitor.", "Dummy: turning it off leaves a plain NMOS track-and-hold. Compare the injection bench to see the resulting pedestal rather than assuming a fixed voltage error." ] }, "sizing": [ { "key": "dummy", "label": "Dummy switch", "unit": "", "value": "on", "kind": "choice", "choices": [ [ "on", "on" ], [ "off", "off - the plain NMOS track-and-hold" ] ] }, { "key": "W", "label": "W switch unit (M1 = 2 copies, MD = 1)", "unit": "m", "value": 0.0000035, "min": 1.5e-7, "max": 0.00002, "kind": "si" }, { "key": "L", "label": "L (switch, dummy, inverter)", "unit": "m", "value": 1.3e-7, "min": 1.3e-7, "max": 0.000001, "kind": "si" }, { "key": "Wi", "label": "W inverter NMOS (MI1; MI2 twice it)", "unit": "m", "value": 5e-7, "min": 1.5e-7, "max": 0.000005, "kind": "si" }, { "key": "CH", "label": "Hold capacitor", "unit": "F", "value": 1.55e-12, "min": 1e-13, "max": 1e-11, "kind": "si" } ], "testbenches": [ { "id": "ron", "label": "On-resistance", "note": "The switch closed, its input swept over its signal range, 0 % of V_DD to 40 % of V_DD, and its output held 10 mV below it: the current through it gives its on-resistance at every level.", "measures": [], "metricKeys": [ "ron_mid", "ron_max" ], "acceptance": [ "ron_max" ], "acceptanceRules": [ { "key": "ron_max", "unit": "Ω", "min": null, "max": 1500, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* NMOS track-and-hold with a dummy switch - on-resistance across the signal range\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVctl ctl 0 dc {VDD}\n.subckt thdummy in out clk vdd vss\n* M1: the switch, two copies of the unit, closed while clk is high\nXM1 in clk out vss sg13_lv_nmos w=3.5u l=130n ng=1 m=2\n* MD: the dummy, one copy, source and drain on the hold node, on while clk is low\nXMD out clkb out vss sg13_lv_nmos w=3.5u l=130n ng=1 m=1\n* clkb: the clock inverted, a gate delay behind it\nXMI1 clkb clk vss vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXMI2 clkb clk vdd vdd sg13_lv_pmos w=1u l=130n ng=1 m=1\n* the hold capacitor\nXCH out vss cap_cmim w=22.677u l=22.677u m=2\n.ends\nXdut in out ctl vdd 0 thdummy\nVin in 0 dc 0\n* the output held 10 mV below the input: the current is 10 mV over R_on\nEcp cp 0 in 0 1\nVt cp out dc 0.01\n.dc Vin {0*VDD+0.01} {0.4*VDD} {0.0067*VDD}\n.end" }, { "id": "inj", "label": "Pedestal", "note": "The control falls in 100 ps after tracking. Pedestal is checked at seven sampled levels including 0% and 40% VDD; this is a sampled maximum, not a continuous-range bound.", "measures": [], "metricKeys": [ "ped_mid", "ped_max" ], "acceptance": [ "ped_mid", "ped_max" ], "acceptanceRules": [ { "key": "ped_mid", "unit": "V", "min": -0.0005, "max": 0.0005, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "ped_max", "unit": "V", "min": null, "max": 0.0005, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* NMOS track-and-hold with a dummy switch - the pedestal at 20 % of V_DD\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVctl ctl 0 pwl(0 {VDD} 2n {VDD} 2.1n 0)\n.subckt thdummy in out clk vdd vss\n* M1: the switch, two copies of the unit, closed while clk is high\nXM1 in clk out vss sg13_lv_nmos w=3.5u l=130n ng=1 m=2\n* MD: the dummy, one copy, source and drain on the hold node, on while clk is low\nXMD out clkb out vss sg13_lv_nmos w=3.5u l=130n ng=1 m=1\n* clkb: the clock inverted, a gate delay behind it\nXMI1 clkb clk vss vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXMI2 clkb clk vdd vdd sg13_lv_pmos w=1u l=130n ng=1 m=1\n* the hold capacitor\nXCH out vss cap_cmim w=22.677u l=22.677u m=2\n.ends\nXdut in out ctl vdd 0 thdummy\nEin in 0 vdd 0 0.2\n.tran 10p 12n\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas tran vtrack FIND v(out) AT=1.9n\n.meas tran vheld FIND v(out) AT=12n\n.end" }, { "id": "leak", "label": "Off leakage", "note": "The switch open, its input at one end of its range and then the other, its output swept from 0 % of V_DD to 40 % of V_DD: the current that reaches the output with a real voltage across the switch.", "measures": [], "metricKeys": [ "i_leak", "droop" ], "acceptance": [ "i_leak", "droop" ], "acceptanceRules": [ { "key": "i_leak", "unit": "A", "min": null, "max": 1e-8, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" }, { "key": "droop", "unit": "V/s", "min": null, "max": 10000, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* NMOS track-and-hold with a dummy switch - open, input at 0 % of V_DD, output swept over the range\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVctl ctl 0 dc 0\n.subckt thdummy in out clk vdd vss\n* M1: the switch, two copies of the unit, closed while clk is high\nXM1 in clk out vss sg13_lv_nmos w=3.5u l=130n ng=1 m=2\n* MD: the dummy, one copy, source and drain on the hold node, on while clk is low\nXMD out clkb out vss sg13_lv_nmos w=3.5u l=130n ng=1 m=1\n* clkb: the clock inverted, a gate delay behind it\nXMI1 clkb clk vss vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXMI2 clkb clk vdd vdd sg13_lv_pmos w=1u l=130n ng=1 m=1\n* the hold capacitor\nXCH out vss cap_cmim w=22.677u l=22.677u m=2\n.ends\nXdut in out ctl vdd 0 thdummy\nEin in 0 vdd 0 0\n* the output held by a source and swept; the ammeter reads what reaches it\nVo o 0 dc 0\nVm o out dc 0\n.dc Vo {0*VDD} {0.4*VDD} {0.01*VDD}\n.end" }, { "id": "track", "label": "Track bandwidth", "note": "The closed switch drives its hold capacitance at seven sampled levels including 0% and 40% VDD. Every level must produce a finite bandwidth; missing crossings are not dropped.", "measures": [], "metricKeys": [ "bw_min" ], "acceptance": [ "bw_min" ], "acceptanceRules": [ { "key": "bw_min", "unit": "Hz", "min": 120000000, "max": null, "classification": "simulation-limit", "conditions": "all requested testbench conditions", "outsideScope": "characterization; the measurement must still be present, unique and finite" } ], "cards": [ "sg13g2_lv_tt.spice", "sg13g2_passive_tt.spice" ], "netlist": "* NMOS track-and-hold with a dummy switch - the track bandwidth at 20 % of V_DD\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\nVdd vdd 0 dc {VDD}\nVctl ctl 0 dc {VDD}\n.subckt thdummy in out clk vdd vss\n* M1: the switch, two copies of the unit, closed while clk is high\nXM1 in clk out vss sg13_lv_nmos w=3.5u l=130n ng=1 m=2\n* MD: the dummy, one copy, source and drain on the hold node, on while clk is low\nXMD out clkb out vss sg13_lv_nmos w=3.5u l=130n ng=1 m=1\n* clkb: the clock inverted, a gate delay behind it\nXMI1 clkb clk vss vss sg13_lv_nmos w=500n l=130n ng=1 m=1\nXMI2 clkb clk vdd vdd sg13_lv_pmos w=1u l=130n ng=1 m=1\n* the hold capacitor\nXCH out vss cap_cmim w=22.677u l=22.677u m=2\n.ends\nXdut in out ctl vdd 0 thdummy\nEin ina 0 vdd 0 0.2\nVac in ina dc 0 ac 1\n.ac dec 20 1meg 100g\n.end" } ], "measurements": { "ron_max": { "label": "On-resistance, worst over the range", "unit": "Ω", "spec": { "min": null, "max": 1500 } }, "ped_mid": { "label": "Pedestal, mid-range", "unit": "V", "spec": { "min": -0.0005, "max": 0.0005 } }, "ped_max": { "label": "Pedestal, worst sampled level", "unit": "V", "spec": { "min": null, "max": 0.0005 } }, "i_leak": { "label": "Off leakage, worst over the range", "unit": "A", "spec": { "min": null, "max": 1e-8 } }, "droop": { "label": "Droop on the held capacitance", "unit": "V/s", "spec": { "min": null, "max": 10000 } }, "bw_min": { "label": "Track bandwidth, worst sampled level", "unit": "Hz", "spec": { "min": 120000000, "max": null } } }, "recordVersion": 1, "authoring": { "version": 1, "source": "this-record", "fields": [ "name", "title", "group", "subgroup", "summary", "reference", "ports", "devices (except fingers/copies)", "intent", "specs", "explanation", "sizing[].label", "testbenches[].label", "testbenches[].note" ], "generated": [ "revision", "technology", "cards", "corners", "specificationPolicy", "sizing (except label)", "measurements", "testbenches (except label/note)", "diagrams", "provenance", "devices[].fingers", "devices[].copies" ], "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.", "sha256": "4f05288671408c51d9342ad0603f919dbb1bcbef68428b6efd254e613cf494a7" }, "provenance": { "schema": "aisic.record-provenance/1", "parameterScope": "published-defaults", "generator": { "url": "/library/th-nmos-dummy.js", "sha256": "66b2150ecb28f046b24fdf58aa855c0a14495fef1a87f35515ea144b05187482" }, "simulationFingerprints": { "ron": "c2a1110c94283ab2177c3a305d925722381fa8b83a2983954725dec9ddd35438", "inj": "4225bb90961602816f4ffaf2f2feee9dc0879fc4afcfdc6e1340c4fad880624a", "leak": "a4de035231d3645d0f40225f9bcb02a1608905bda2d040d446ef0f961318be20", "track": "e35f501a95c6d7a66348d6524fc3f33ca6218f34ab42ff809d5414000c6f0859" }, "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification." }, "revision": "0b17943ac4329bd03f5f30e8ef40515c4d69a2a65bfd0d4f1b652ae6742648ce", "diagrams": { "schema": "aisic.diagrams/1", "circuit": "th-nmos-dummy", "parameters": { "dummy": "on", "W": 0.0000035, "L": 1.3e-7, "Wi": 5e-7, "CH": 1.55e-12 }, "parameterScope": "published-defaults", "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.", "variants": { "choiceParameters": [ { "key": "dummy", "selected": "on", "choices": [ { "value": "on", "label": "on" }, { "value": "off", "label": "off - the plain NMOS track-and-hold" } ] } ], "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation." }, "resourceBase": "/circuits/th-nmos-dummy/", "graphs": [ { "id": "graph-1", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "dut", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "dut", "name": "thdummy", "ports": [ { "name": "in", "net": "in", "kind": "input" }, { "name": "out", "net": "out", "kind": "output" }, { "name": "clk", "net": "clk", "kind": "clock" }, { "name": "vdd", "net": "vdd", "kind": "supply" }, { "name": "vss", "net": "vss", "kind": "ground" } ], "definitions": [], "devices": [ { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.5u l=130n ng=1 m=2", "source": "XM1 in clk out vss sg13_lv_nmos w=3.5u l=130n ng=1 m=2", "pins": [ { "id": "d", "net": "in" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "out" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMD", "displayName": "MD", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.5u l=130n ng=1 m=1", "source": "XMD out clkb out vss sg13_lv_nmos w=3.5u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "out" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMI1", "displayName": "MI1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XMI1 clkb clk vss vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "clkb" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMI2", "displayName": "MI2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XMI2 clkb clk vdd vdd sg13_lv_pmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "clkb" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCH", "displayName": "CH", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=22.677u l=22.677u m=2", "source": "XCH out vss cap_cmim w=22.677u l=22.677u m=2", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "in", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" } ], "ports": [ "in" ], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XMI1", "pin": "g" }, { "device": "XMI2", "pin": "g" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM1", "pin": "s" }, { "device": "XMD", "pin": "d" }, { "device": "XMD", "pin": "s" }, { "device": "XCH", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM1", "pin": "b" }, { "device": "XMD", "pin": "b" }, { "device": "XMI1", "pin": "s" }, { "device": "XMI1", "pin": "b" }, { "device": "XCH", "pin": "n" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "XMD", "pin": "g" }, { "device": "XMI1", "pin": "d" }, { "device": "XMI2", "pin": "d" } ], "ports": [], "voltageReferences": [] }, { "id": "vdd", "ground": false, "terminals": [ { "device": "XMI2", "pin": "s" }, { "device": "XMI2", "pin": "b" } ], "ports": [ "vdd" ], "voltageReferences": [] } ] } ] }, { "id": "graph-2", "kind": "electrical-connectivity", "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.", "root": "top", "globalDefinitions": [ ".param VDD=1.2" ], "scopes": [ { "id": "top", "name": "top", "ports": [], "definitions": [ ".param VDD=1.2" ], "devices": [ { "id": "Vdd", "displayName": "Vdd", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vdd vdd 0 dc {VDD}", "pins": [ { "id": "p", "net": "vdd" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vctl", "displayName": "Vctl", "spiceType": "V", "model": null, "parametersOrValue": "dc {VDD}", "source": "Vctl ctl 0 dc {VDD}", "pins": [ { "id": "p", "net": "ctl" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Xdut", "displayName": "Xdut", "spiceType": "X", "model": "thdummy", "parametersOrValue": "", "source": "Xdut in out ctl vdd 0 thdummy", "pins": [ { "id": "in", "net": "in" }, { "id": "out", "net": "out" }, { "id": "clk", "net": "ctl" }, { "id": "vdd", "net": "vdd" }, { "id": "vss", "net": "0" } ], "pinMeaning": "Declared .subckt port order", "subcircuit": "subckt/thdummy" }, { "id": "Vin", "displayName": "Vin", "spiceType": "V", "model": null, "parametersOrValue": "dc 0", "source": "Vin in 0 dc 0", "pins": [ { "id": "p", "net": "in" }, { "id": "n", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Ecp", "displayName": "Ecp", "spiceType": "E", "model": null, "parametersOrValue": "1", "source": "Ecp cp 0 in 0 1", "pins": [ { "id": "p", "net": "cp" }, { "id": "n", "net": "0" }, { "id": "cp", "net": "in" }, { "id": "cn", "net": "0" } ], "pinMeaning": "SPICE primitive terminal order" }, { "id": "Vt", "displayName": "Vt", "spiceType": "V", "model": null, "parametersOrValue": "dc 0.01", "source": "Vt cp out dc 0.01", "pins": [ { "id": "p", "net": "cp" }, { "id": "n", "net": "out" } ], "pinMeaning": "SPICE primitive terminal order" } ], "nets": [ { "id": "vdd", "ground": false, "terminals": [ { "device": "Vdd", "pin": "p" }, { "device": "Xdut", "pin": "vdd" } ], "ports": [], "voltageReferences": [] }, { "id": "0", "ground": true, "terminals": [ { "device": "Vdd", "pin": "n" }, { "device": "Vctl", "pin": "n" }, { "device": "Xdut", "pin": "vss" }, { "device": "Vin", "pin": "n" }, { "device": "Ecp", "pin": "n" }, { "device": "Ecp", "pin": "cn" } ], "ports": [], "voltageReferences": [] }, { "id": "ctl", "ground": false, "terminals": [ { "device": "Vctl", "pin": "p" }, { "device": "Xdut", "pin": "clk" } ], "ports": [], "voltageReferences": [] }, { "id": "in", "ground": false, "terminals": [ { "device": "Xdut", "pin": "in" }, { "device": "Vin", "pin": "p" }, { "device": "Ecp", "pin": "cp" } ], "ports": [], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "Xdut", "pin": "out" }, { "device": "Vt", "pin": "n" } ], "ports": [], "voltageReferences": [] }, { "id": "cp", "ground": false, "terminals": [ { "device": "Ecp", "pin": "p" }, { "device": "Vt", "pin": "p" } ], "ports": [], "voltageReferences": [] } ] }, { "id": "subckt/thdummy", "name": "thdummy", "ports": [ { "name": "in", "net": "in" }, { "name": "out", "net": "out" }, { "name": "clk", "net": "clk" }, { "name": "vdd", "net": "vdd" }, { "name": "vss", "net": "vss" } ], "definitions": [], "devices": [ { "id": "XM1", "displayName": "M1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.5u l=130n ng=1 m=2", "source": "XM1 in clk out vss sg13_lv_nmos w=3.5u l=130n ng=1 m=2", "pins": [ { "id": "d", "net": "in" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "out" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMD", "displayName": "MD", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=3.5u l=130n ng=1 m=1", "source": "XMD out clkb out vss sg13_lv_nmos w=3.5u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "out" }, { "id": "g", "net": "clkb" }, { "id": "s", "net": "out" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMI1", "displayName": "MI1", "spiceType": "X", "model": "sg13_lv_nmos", "parametersOrValue": "w=500n l=130n ng=1 m=1", "source": "XMI1 clkb clk vss vss sg13_lv_nmos w=500n l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "clkb" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "vss" }, { "id": "b", "net": "vss" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XMI2", "displayName": "MI2", "spiceType": "X", "model": "sg13_lv_pmos", "parametersOrValue": "w=1u l=130n ng=1 m=1", "source": "XMI2 clkb clk vdd vdd sg13_lv_pmos w=1u l=130n ng=1 m=1", "pins": [ { "id": "d", "net": "clkb" }, { "id": "g", "net": "clk" }, { "id": "s", "net": "vdd" }, { "id": "b", "net": "vdd" } ], "pinMeaning": "MOS drain, gate, source, bulk" }, { "id": "XCH", "displayName": "CH", "spiceType": "X", "model": "cap_cmim", "parametersOrValue": "w=22.677u l=22.677u m=2", "source": "XCH out vss cap_cmim w=22.677u l=22.677u m=2", "pins": [ { "id": "p", "net": "out" }, { "id": "n", "net": "vss" } ], "pinMeaning": "IHP MIM model terminal order" } ], "nets": [ { "id": "in", "ground": false, "terminals": [ { "device": "XM1", "pin": "d" } ], "ports": [ "in" ], "voltageReferences": [] }, { "id": "clk", "ground": false, "terminals": [ { "device": "XM1", "pin": "g" }, { "device": "XMI1", "pin": "g" }, { "device": "XMI2", "pin": "g" } ], "ports": [ "clk" ], "voltageReferences": [] }, { "id": "out", "ground": false, "terminals": [ { "device": "XM1", "pin": "s" }, { "device": "XMD", "pin": "d" }, { "device": "XMD", "pin": "s" }, { "device": "XCH", "pin": "p" } ], "ports": [ "out" ], "voltageReferences": [] }, { "id": "vss", "ground": false, "terminals": [ { "device": "XM1", "pin": "b" }, { "device": "XMD", "pin": "b" }, { "device": "XMI1", "pin": "s" }, { "device": "XMI1", "pin": "b" }, { "device": "XCH", "pin": "n" } ], "ports": [ "vss" ], "voltageReferences": [] }, { "id": "clkb", "ground": false, "terminals": [ { "device": "XMD", "pin": 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