{
  "schema": "aisic.circuit/1",
  "entryType": "library-block",
  "domain": "analog",
  "id": "trim-triode",
  "name": "MOS-triode trim attenuator",
  "group": "Passives and trimming",
  "subgroup": "Trimming",
  "title": "MOS-triode trim attenuator",
  "summary": "This divider uses a gate voltage to adjust how much of a small reference voltage reaches its output. At enough gate overdrive, the transistor acts approximately as a resistor. The setting is nonlinear and changes with signal level and temperature, so it needs calibration.",
  "reference": {
    "kind": "book",
    "authors": "B. Razavi",
    "title": "Design of Analog CMOS Integrated Circuits",
    "edition": "2nd",
    "publisher": "McGraw-Hill",
    "year": 2016,
    "where": "Basic MOS device physics: the MOSFET in deep triode as a linear resistor its overdrive controls, R_on = 1/(µ_n C_ox (W/L)(V_GS - V_TH))",
    "takes": "The deep-triode MOSFET as a voltage-controlled resistor. A low reference voltage helps keep its drain-source voltage small, but the resistor approximation still requires enough gate overdrive. Near threshold, inspect the simulated transfer rather than assume triode behavior."
  },
  "resources": {
    "record": "/circuits/trim-triode.json",
    "page": "/index.html#trim-triode",
    "achieved": "/achieved/trim-triode.json",
    "achievedScope": "Recorded results apply to the published default design and their recorded conditions, not arbitrary sizing edits in a downloaded record.",
    "modelCards": [
      {
        "name": "sg13g2_lv_tt.spice",
        "url": "/sg13g2_lv_tt.spice",
        "sha256": "5caf9c90dc6c7e6be36ae2a098835ffe50cca0d502cb4b2a7eafb000abfcc88a"
      },
      {
        "name": "sg13g2_passive_tt.spice",
        "url": "/sg13g2_passive_tt.spice",
        "sha256": "c00886f0de9e2a3bbd746e3771812e7ffea84cd452f2dbda6cc0fb7699a539cc"
      }
    ],
    "urlBase": "Resource URLs start at this site's root. Save model cards beside exported SPICE decks using their include filenames.",
    "schema": "/schemas/circuit.schema.json"
  },
  "specificationPolicy": {
    "evidence": "Simulation evidence is not a production guarantee or completed physical signoff.",
    "defaultScope": "Numeric limits apply at every requested condition unless an explicit supported scope says otherwise.",
    "scopes": {
      "nominal": {
        "corner": "tt",
        "temp": 27,
        "vdd": 1,
        "temperatureUnit": "degC",
        "supplyMeaning": "scale of the bench's nominal supply"
      }
    },
    "characterization": "Out-of-scope results retain their numerical values and execution coverage, without a parametric-yield claim."
  },
  "corners": {
    "cards": "a deck's sg13g2_<family>_tt.spice (family lv, hv, passive, hbt) becomes sg13g2_<family>_<corner>.spice",
    "process": [
      "tt",
      "ss",
      "ff",
      "sf",
      "fs"
    ],
    "pairing": "resistors, capacitors and bipolars go to their worst-case-speed corner (wcs) with ss, their best case (bcs) with ff, and stay typical otherwise",
    "temperatures": [
      -40,
      27,
      125
    ],
    "supplyScale": [
      0.9,
      1,
      1.1
    ],
    "supply": "a deck's .param VDD, or its Vdd source, times supplyScale; a testbench that drives its supply itself keeps it",
    "held": "what a testbench gives from outside - bias currents, references - stays at its typical value at every corner and in every draw",
    "sets": {
      "essential": [
        {
          "corner": "tt",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "ss",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "ff",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "sf",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "fs",
          "temp": 27,
          "vdd": 1
        },
        {
          "corner": "tt",
          "temp": -40,
          "vdd": 1
        },
        {
          "corner": "tt",
          "temp": 125,
          "vdd": 1
        },
        {
          "corner": "tt",
          "temp": 27,
          "vdd": 0.9
        },
        {
          "corner": "tt",
          "temp": 27,
          "vdd": 1.1
        },
        {
          "corner": "ss",
          "temp": 125,
          "vdd": 0.9
        },
        {
          "corner": "ff",
          "temp": -40,
          "vdd": 1.1
        }
      ],
      "full": "all 45 combinations"
    },
    "montecarlo": {
      "cards": {
        "mc": "process and mismatch",
        "mcmm": "mismatch only",
        "mcproc": "process only"
      },
      "seed": "draw k adds .options seed=k, so draws are reproducible"
    }
  },
  "technology": {
    "id": "sg13g2",
    "name": "IHP SG13G2",
    "node": "130 nm",
    "corner": "tt",
    "vdd": 1.2,
    "lmin": 1.3e-7,
    "wmin": 1.5e-7,
    "models": "sg13g2_lv_tt.spice",
    "devices": {
      "nmos": "sg13_lv_nmos",
      "pmos": "sg13_lv_pmos",
      "resistor": "rppd, rhigh",
      "capacitor": "cap_cmim"
    },
    "defaultsScope": "vdd, lmin, wmin, models and devices above describe the core-PDK defaults, not every circuit's supply or device requirements. Use the sizing, device list, cards and testbench netlists for this implementation, including HV and bipolar devices where present.",
    "note": "Sizes are in metres (w=1u); ng is the number of gate fingers. The MOSFETs are PSP 103 and the resistors r3_cmc, Verilog-A models ngspice loads through OSDI - psp103.osdi and r3_cmc.osdi, compiled with OpenVAF."
  },
  "implementation": {
    "kind": "physical-device-reference",
    "purpose": "A reasonable SG13G2 realization for learning, reuse and technology retargeting; not a claim of globally optimal sizing.",
    "evidence": "schematic-simulation",
    "netlistBoundary": "Exported netlists are complete simulation benches, including ideal stimuli, loads, bias/reference sources and, where stated, parasitic surrogates or numerical aids; they are not fabrication netlists. Integrate and verify the physical support circuits separately.",
    "physicalSignoff": "Layout, DRC, LVS, extracted-parasitic simulation and silicon measurements are not supplied by this catalogue.",
    "retargeting": "Preserve topology, intent and interfaces; select legal devices and resize for the destination process, then repeat operating-range, PVT, mismatch and physical verification."
  },
  "cards": [
    "sg13g2_lv_tt.spice",
    "sg13g2_passive_tt.spice"
  ],
  "ports": [
    {
      "name": "in",
      "kind": "input",
      "note": "the level to be scaled: a reference, not the supply"
    },
    {
      "name": "out",
      "kind": "output"
    },
    {
      "name": "code",
      "kind": "bias",
      "note": "the trim code, 0 to V_DD from a DAC"
    },
    {
      "name": "vss",
      "kind": "ground"
    }
  ],
  "devices": [
    {
      "name": "R1",
      "type": "resistor",
      "nodes": "in out",
      "sizedBy": [
        "R"
      ],
      "role": "the divider's top leg, p+ poly"
    },
    {
      "name": "M1",
      "type": "nmos",
      "nodes": "out code vss vss",
      "sizedBy": [
        "W",
        "L"
      ],
      "role": "the divider's bottom leg: approximately resistive when gate overdrive is large beside the output voltage",
      "fingers": 1,
      "copies": 1
    }
  ],
  "intent": [
    {
      "rule": "triode",
      "of": [
        "M1"
      ],
      "constraint": "v_out ≪ V_code - V_th",
      "why": "M1 is a resistor only while the voltage across it is small next to its overdrive; with its drain on the supply's end of a divider it would sit in saturation - a current sink - for most of the code range, and the output would collapse within a few tens of millivolts of threshold. Fed from a 0.1 V reference, v_out is at most 0.1 V, and at every code above about 0.45 V M1 has at least twice that in overdrive."
    },
    {
      "rule": "transfer",
      "of": [
        "M1",
        "R1"
      ],
      "constraint": "v_out/v_in = 1/(1 + k R1 (V_code - V_th)), k = µ_n C_ox W/L",
      "why": "The factor is hyperbolic in the code: steep just above threshold, flat towards V_DD. k R1 sets how the 1.2 V of code is shared out: about 3.6 V^-1 here (2 by 4 µm against 18 kΩ), so the factor halves 0.28 V above threshold and reaches a quarter at full code. A larger k R1 crowds the whole range into the first 0.1 V of code; a smaller one never attenuates much."
    },
    {
      "rule": "temperature",
      "of": [
        "M1",
        "R1"
      ],
      "constraint": "zero-TC overdrive about 0.1 V",
      "why": "R_M1 rises with temperature through the mobility and falls through the threshold; the two cancel at an overdrive of about 0.1 V and the mobility wins above it. So a trim set near 80 % holds within about 9 % from -40 to 125 °C, and one set near 30 % drifts by more than half. R1 is p+ poly, whose resistance rises slightly with temperature and takes back a little of M1's."
    },
    {
      "rule": "level",
      "of": [
        "M1"
      ],
      "constraint": "R_M1 = 1/(k (V_ov - v_out/2))",
      "why": "M1's resistance depends on its own drain voltage: the larger the level, the higher R_M1 and the factor. At the half-way code the factor moves about 10 % from 25 mV to 0.2 V of input - fine for trimming one fixed level, not for scaling a signal."
    }
  ],
  "specs": [
    {
      "key": "att_zero",
      "label": "Factor at code 0",
      "unit": "V/V",
      "direction": "max",
      "constraint": ">= 0.99 V/V",
      "min": 0.99,
      "max": null,
      "why": "At code 0 M1 is open: the output is the input, less M1's leakage through R1."
    },
    {
      "key": "att_full",
      "label": "Factor at full code",
      "unit": "V/V",
      "direction": "min",
      "constraint": "<= 0.4 V/V",
      "min": null,
      "max": 0.4,
      "why": "At full code M1 has about 0.8 V of overdrive: R_M1 is a third of R1 and the output a quarter of the input at 27 °C, a third at 125 °C, where the channel's mobility has fallen."
    },
    {
      "key": "span",
      "label": "Code span, 90 % to 40 %",
      "unit": "V",
      "direction": "max",
      "constraint": ">= 0.2 V",
      "min": 0.2,
      "max": null,
      "why": "From 90 % to 40 % the factor takes 0.38 V of the code's 1.2 V at 27 °C, 0.25 V at -40 °C where it is steepest: M1's k R1 is chosen so the transfer is not crowded into the few tens of millivolts above threshold."
    },
    {
      "key": "step_max",
      "label": "Largest step per 10 mV of code",
      "unit": "%",
      "direction": "min",
      "constraint": "<= 3 %",
      "min": null,
      "max": 3,
      "why": "Just above threshold the transfer is steepest: under 2 % of the input per 10 mV of code, so a 7-bit DAC on the code resolves about 2 %."
    },
    {
      "key": "level_err",
      "label": "Level error, quarter to double input",
      "unit": "%",
      "direction": "min",
      "constraint": "<= 20 %",
      "min": null,
      "max": 20,
      "why": "M1 is a resistor only while v_out is small next to its overdrive: at the half-way code v_out = 50 mV against 0.25 V, and the factor moves by 10 % from a quarter of the input to twice it - 17 % at -40 °C, where that code sits nearer threshold."
    },
    {
      "key": "drift",
      "label": "Drift at half, -40 to 125 °C",
      "unit": "%",
      "direction": "min",
      "constraint": "<= 50 %",
      "min": null,
      "max": 50,
      "why": "Held at the code that halves it at 27 °C, the factor drifts by 30 % from -40 to 125 °C: the channel's mobility falls as T^-1.5 and its threshold by about 1 mV/°C, and at 0.25 V of overdrive the first wins. Set to 80 %, just above threshold, the two nearly cancel: 9 %. Set at 125 °C, the half-way code sits higher and drifts 44 %."
    }
  ],
  "explanation": {
    "idea": "This divider uses a gate voltage to adjust how much of a small reference voltage reaches its output. At enough gate overdrive, the transistor acts approximately as a resistor. The setting is nonlinear and changes with signal level and temperature, so it needs calibration.",
    "detail": "A divider whose ratio an analog trim voltage sets: R1 connects input to output, and M1 connects output to ground with the control voltage on its gate. Below threshold M1 carries little current and the output is close to the input. With sufficient gate overdrive compared with its drain voltage, M1 approaches deep triode and behaves approximately as a resistor 1/[k·(V_code − V_th)]. The divider factor then falls roughly hyperbolically as the control rises. A small input reference helps satisfy that approximation, but near threshold it fails: use the simulated transfer rather than treating the whole range as resistive.",
    "lesson": {
      "relation": 0,
      "symbols": "v_in and v_out are input and output voltages; R1 is the fixed resistor; R_M1 is the transistor's approximate resistance; V_code is its gate-control voltage; V_th is threshold; k = µ_n·C_ox·W/L combines mobility, oxide capacitance per area and transistor dimensions.",
      "assumptions": "The simple factor assumes deep triode, with v_out much smaller than V_code − V_th, negligible output loading and fixed temperature. It is not valid near cutoff and does not include all short-channel or physical resistor effects.",
      "exercise": {
        "param": "R",
        "value": 36000,
        "analysis": "transfer",
        "expect": "Doubling the fixed resistor should lower the output factor at the same above-threshold gate voltage. Compare the code that halves the input and the steepness near threshold; the usable control range also changes."
      },
      "limits": "The bench uses an ideal 0.1 V reference and an ideal swept control voltage; a physical implementation needs their sources and adequate output-load impedance. This is an analog control input, not an included digital DAC. Calibrate the factor for the intended level, process and temperature."
    },
    "path": [
      {
        "part": "Top leg",
        "devices": "R1",
        "does": "18 kΩ of p+ poly from the input to the output: the fixed arm of the divider."
      },
      {
        "part": "Cut-off",
        "devices": "M1",
        "does": "With the code below about 0.25 V, M1 carries only leakage and the output is the input: the flat start of the transfer."
      },
      {
        "part": "Triode",
        "devices": "M1",
        "does": "With enough gate overdrive compared with the drain voltage, M1 becomes approximately resistive and its resistance falls as the control rises. At the nominal design point the simulated factor halves near 0.54 V and reaches about a quarter at 1.2 V."
      }
    ],
    "bias": "The bench supplies a 0.1 V input reference and sweeps an ideal control source over 0–1.2 V. A physical circuit could use a DAC for that control; no DAC is included here. The gate requires little DC current, not exactly zero, and the reference supplies about 4 µA at full control voltage at the nominal design point.",
    "relations": [
      {
        "what": "Factor",
        "expr": "v_out/v_in = R_M1/(R_M1 + R1) = 1/(1 + k R1 (V_code − V_th))",
        "note": "k = µ_n C_ox (W/L)_M1; k R1 is about 3.6 V^(-1) here"
      },
      {
        "what": "Triode resistance",
        "expr": "R_M1 = 1/(k (V_code − V_th − v_out/2))",
        "note": "the v_out/2 term is the level dependence: 10 % from a quarter of the input to twice it at the half-way code"
      },
      {
        "what": "Zero-TC overdrive",
        "expr": "V_ov,ZTC ≈ T |dV_th/dT| / 1.5",
        "note": "about 0.1 V: below it the falling threshold wins, above it the falling mobility; the factor set to 80 % drifts 9 % from −40 to 125 °C, set to 50 % 30 %"
      },
      {
        "what": "Slope at half",
        "expr": "d(v_out/v_in)/dV_code = −k R1/4 at v_out/v_in = 1/2",
        "note": "0.9 % of the input per 10 mV of code there; steeper just above threshold, 1.9 % per 10 mV at its steepest"
      }
    ],
    "tradeoffs": [
      "R (R1) against W and L (M1): their product k R1 decides how the code's range is shared: larger crowds the transfer into the first 0.1 V above threshold, smaller never attenuates much.",
      "VIN (the level): a larger level puts more across M1 and bends the factor with the level; a smaller one keeps M1 a better resistor.",
      "Where the trim is set: near threshold it holds over temperature but each step of code moves it most; deep in triode it is fine-grained and linear but follows the channel's mobility."
    ]
  },
  "sizing": [
    {
      "key": "R",
      "label": "R1",
      "unit": "Ω",
      "value": 18000,
      "min": 2000,
      "max": 200000,
      "kind": "si"
    },
    {
      "key": "W",
      "label": "W M1",
      "unit": "m",
      "value": 0.000002,
      "min": 1.5e-7,
      "max": 0.00002,
      "kind": "si"
    },
    {
      "key": "L",
      "label": "L M1",
      "unit": "m",
      "value": 0.000004,
      "min": 1.3e-7,
      "max": 0.00002,
      "kind": "si"
    },
    {
      "key": "VIN",
      "label": "Input level",
      "unit": "V",
      "value": 0.1,
      "min": 0.01,
      "max": 0.6,
      "kind": "si"
    }
  ],
  "testbenches": [
    {
      "id": "transfer",
      "label": "Against the code",
      "note": "The input held at its level, the code swept from 0 to V_DD: the factor out/in the cell gives at every code, and how evenly the code spreads it.",
      "measures": [],
      "metricKeys": [
        "att_zero",
        "att_full",
        "code_half",
        "span",
        "step_max"
      ],
      "acceptance": [
        "att_zero",
        "att_full",
        "span",
        "step_max"
      ],
      "acceptanceRules": [
        {
          "key": "att_zero",
          "unit": "V/V",
          "min": 0.99,
          "max": null,
          "classification": "simulation-limit",
          "conditions": "all requested testbench conditions",
          "outsideScope": "characterization; the measurement must still be present, unique and finite"
        },
        {
          "key": "att_full",
          "unit": "V/V",
          "min": null,
          "max": 0.4,
          "classification": "simulation-limit",
          "conditions": "all requested testbench conditions",
          "outsideScope": "characterization; the measurement must still be present, unique and finite"
        },
        {
          "key": "span",
          "unit": "V",
          "min": 0.2,
          "max": null,
          "classification": "simulation-limit",
          "conditions": "all requested testbench conditions",
          "outsideScope": "characterization; the measurement must still be present, unique and finite"
        },
        {
          "key": "step_max",
          "unit": "%",
          "min": null,
          "max": 3,
          "classification": "simulation-limit",
          "conditions": "all requested testbench conditions",
          "outsideScope": "characterization; the measurement must still be present, unique and finite"
        }
      ],
      "cards": [
        "sg13g2_lv_tt.spice",
        "sg13g2_passive_tt.spice"
      ],
      "netlist": "* MOS-triode trim attenuator - the factor against the code\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\n* the supply the code's DAC swings to\nVdd vdd 0 dc {VDD}\nVin in 0 dc 100m\n.subckt trimtri in out code vss\n* R1: the divider's top leg\nXR1 in out vss rppd w=0.5u l=35.17u\n* M1: its bottom leg, a resistor the code sets\nXM1 out code vss vss sg13_lv_nmos w=2u l=4u ng=1 m=1\n.ends\nXdut in out code 0 trimtri\nVcode code 0 dc 0\n.dc Vcode 0 {VDD} {VDD/240}\n* Measured by this deck, so a local ngspice run reports the same figures:\n.meas dc vfull FIND v(out) AT=1.2\n.end"
    },
    {
      "id": "level",
      "label": "Against the input level",
      "note": "At the code that halves the input, the input swept from a twentieth of its level to twice it: a linear scaler gives the same factor at every level.",
      "measures": [],
      "metricKeys": [
        "level_err"
      ],
      "acceptance": [
        "level_err"
      ],
      "acceptanceRules": [
        {
          "key": "level_err",
          "unit": "%",
          "min": null,
          "max": 20,
          "classification": "simulation-limit",
          "conditions": "all requested testbench conditions",
          "outsideScope": "characterization; the measurement must still be present, unique and finite"
        }
      ],
      "cards": [
        "sg13g2_lv_tt.spice",
        "sg13g2_passive_tt.spice"
      ],
      "netlist": "* MOS-triode trim attenuator - the factor against the input level at a code of 0.600 V\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\n* the supply the code's DAC swings to\nVdd vdd 0 dc {VDD}\nVin in 0 dc 100m\n.subckt trimtri in out code vss\n* R1: the divider's top leg\nXR1 in out vss rppd w=0.5u l=35.17u\n* M1: its bottom leg, a resistor the code sets\nXM1 out code vss vss sg13_lv_nmos w=2u l=4u ng=1 m=1\n.ends\nXdut in out code 0 trimtri\nVcode code 0 dc 0.6000\n.dc Vin 5m 200m 2.5m\n.end"
    },
    {
      "id": "temp",
      "label": "Against temperature",
      "note": "The codes that give 80, 50 and 30 % found at the run's temperature and held, the temperature swept from -40 to 125 °C: how well a trim set once holds.",
      "measures": [],
      "metricKeys": [
        "drift"
      ],
      "acceptance": [
        "drift"
      ],
      "acceptanceRules": [
        {
          "key": "drift",
          "unit": "%",
          "min": null,
          "max": 50,
          "classification": "simulation-limit",
          "conditions": "all requested testbench conditions",
          "outsideScope": "characterization; the measurement must still be present, unique and finite"
        }
      ],
      "cards": [
        "sg13g2_lv_tt.spice",
        "sg13g2_passive_tt.spice"
      ],
      "netlist": "* MOS-triode trim attenuator - the factor against temperature at a code of 0.600 V\n.include sg13g2_lv_tt.spice\n.include sg13g2_passive_tt.spice\n.param VDD=1.2\n* the supply the code's DAC swings to\nVdd vdd 0 dc {VDD}\nVin in 0 dc 100m\n.subckt trimtri in out code vss\n* R1: the divider's top leg\nXR1 in out vss rppd w=0.5u l=35.17u\n* M1: its bottom leg, a resistor the code sets\nXM1 out code vss vss sg13_lv_nmos w=2u l=4u ng=1 m=1\n.ends\nXdut in out code 0 trimtri\nVcode code 0 dc 0.6000\n.dc temp -40 125 5\n.end"
    }
  ],
  "measurements": {
    "att_zero": {
      "label": "Factor at code 0",
      "unit": "V/V",
      "spec": {
        "min": 0.99,
        "max": null
      }
    },
    "att_full": {
      "label": "Factor at full code",
      "unit": "V/V",
      "spec": {
        "min": null,
        "max": 0.4
      }
    },
    "span": {
      "label": "Code span, 90 % to 40 %",
      "unit": "V",
      "spec": {
        "min": 0.2,
        "max": null
      }
    },
    "step_max": {
      "label": "Largest step per 10 mV of code",
      "unit": "%",
      "spec": {
        "min": null,
        "max": 3
      }
    },
    "level_err": {
      "label": "Level error, quarter to double input",
      "unit": "%",
      "spec": {
        "min": null,
        "max": 20
      }
    },
    "drift": {
      "label": "Drift at half, -40 to 125 °C",
      "unit": "%",
      "spec": {
        "min": null,
        "max": 50
      }
    }
  },
  "recordVersion": 1,
  "authoring": {
    "version": 1,
    "source": "this-record",
    "fields": [
      "name",
      "title",
      "group",
      "subgroup",
      "summary",
      "reference",
      "ports",
      "devices (except fingers/copies)",
      "intent",
      "specs",
      "explanation",
      "sizing[].label",
      "testbenches[].label",
      "testbenches[].note"
    ],
    "generated": [
      "revision",
      "technology",
      "cards",
      "corners",
      "specificationPolicy",
      "sizing (except label)",
      "measurements",
      "testbenches (except label/note)",
      "diagrams",
      "provenance",
      "devices[].fingers",
      "devices[].copies"
    ],
    "workflow": "Edit author-owned fields in this JSON, then run tools/export-circuits.mjs. Change executable circuit generators for numerical changes; rebuild and requalify those changes. The build preserves authored content.",
    "sha256": "687fc96efc7236639bdbe5c9a3b310d91590aece7741669c950ce723422ec6b9"
  },
  "provenance": {
    "schema": "aisic.record-provenance/1",
    "parameterScope": "published-defaults",
    "generator": {
      "url": "/library/trim-triode.js",
      "sha256": "170a5776d90f8c8b319718507bed457630160926f69aaddafe2f64da808bfdd9"
    },
    "simulationFingerprints": {
      "transfer": "a24c2ff7045da6f3306dca2d43415610f74caf4346e6de2704d8f3c9c5c7f6d1",
      "level": "b8cf89ebc1b92660d43a17680a381ce68d43b4a00f3bac271342801df28e2094",
      "temp": "f6699a5385ecf916d23daf27abe4c52865b511653f27ca8bbeb554f1512fbf1e"
    },
    "meaning": "Fingerprints identify simulation inputs, not a passing result. Follow resources.achieved for measured evidence and compare its fingerprints. Explanatory edits do not establish new physical qualification."
  },
  "revision": "32e9d8c6d8e755b00356d620bbe845db4ac1cf9ab8fb527e4b5d311462782e93",
  "diagrams": {
    "schema": "aisic.diagrams/1",
    "circuit": "trim-triode",
    "parameters": {
      "R": 18000,
      "W": 0.000002,
      "L": 0.000004,
      "VIN": 0.1
    },
    "parameterScope": "published-defaults",
    "boundary": "Electrical graphs retain physical device terminals; SVG symbols can collapse tied bipolar terminals, group transmission gates or hide passive substrates. Neither view is layout or a fabrication netlist.",
    "variants": {
      "choiceParameters": [],
      "coverage": "This bundle represents only the selected values. Declared choices can be regenerated; numeric ranges and combinations are not exhaustively qualified by diagram generation."
    },
    "resourceBase": "/circuits/trim-triode/",
    "graphs": [
      {
        "id": "graph-1",
        "kind": "electrical-connectivity",
        "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.",
        "root": "dut",
        "globalDefinitions": [
          ".param VDD=1.2"
        ],
        "scopes": [
          {
            "id": "dut",
            "name": "trimtri",
            "ports": [
              {
                "name": "in",
                "net": "in",
                "kind": "input"
              },
              {
                "name": "out",
                "net": "out",
                "kind": "output"
              },
              {
                "name": "code",
                "net": "code",
                "kind": "bias"
              },
              {
                "name": "vss",
                "net": "vss",
                "kind": "ground"
              }
            ],
            "definitions": [],
            "devices": [
              {
                "id": "XR1",
                "displayName": "R1",
                "spiceType": "X",
                "model": "rppd",
                "parametersOrValue": "w=0.5u l=35.17u",
                "source": "XR1 in out vss rppd w=0.5u l=35.17u",
                "pins": [
                  {
                    "id": "p",
                    "net": "in"
                  },
                  {
                    "id": "n",
                    "net": "out"
                  },
                  {
                    "id": "substrate",
                    "net": "vss"
                  }
                ],
                "pinMeaning": "IHP resistor model terminal order"
              },
              {
                "id": "XM1",
                "displayName": "M1",
                "spiceType": "X",
                "model": "sg13_lv_nmos",
                "parametersOrValue": "w=2u l=4u ng=1 m=1",
                "source": "XM1 out code vss vss sg13_lv_nmos w=2u l=4u ng=1 m=1",
                "pins": [
                  {
                    "id": "d",
                    "net": "out"
                  },
                  {
                    "id": "g",
                    "net": "code"
                  },
                  {
                    "id": "s",
                    "net": "vss"
                  },
                  {
                    "id": "b",
                    "net": "vss"
                  }
                ],
                "pinMeaning": "MOS drain, gate, source, bulk"
              }
            ],
            "nets": [
              {
                "id": "in",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR1",
                    "pin": "p"
                  }
                ],
                "ports": [
                  "in"
                ],
                "voltageReferences": []
              },
              {
                "id": "out",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR1",
                    "pin": "n"
                  },
                  {
                    "device": "XM1",
                    "pin": "d"
                  }
                ],
                "ports": [
                  "out"
                ],
                "voltageReferences": []
              },
              {
                "id": "vss",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR1",
                    "pin": "substrate"
                  },
                  {
                    "device": "XM1",
                    "pin": "s"
                  },
                  {
                    "device": "XM1",
                    "pin": "b"
                  }
                ],
                "ports": [
                  "vss"
                ],
                "voltageReferences": []
              },
              {
                "id": "code",
                "ground": false,
                "terminals": [
                  {
                    "device": "XM1",
                    "pin": "g"
                  }
                ],
                "ports": [
                  "code"
                ],
                "voltageReferences": []
              }
            ]
          }
        ]
      },
      {
        "id": "graph-2",
        "kind": "electrical-connectivity",
        "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.",
        "root": "top",
        "globalDefinitions": [
          ".param VDD=1.2"
        ],
        "scopes": [
          {
            "id": "top",
            "name": "top",
            "ports": [],
            "definitions": [
              ".param VDD=1.2"
            ],
            "devices": [
              {
                "id": "Vdd",
                "displayName": "Vdd",
                "spiceType": "V",
                "model": null,
                "parametersOrValue": "dc {VDD}",
                "source": "Vdd vdd 0 dc {VDD}",
                "pins": [
                  {
                    "id": "p",
                    "net": "vdd"
                  },
                  {
                    "id": "n",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              },
              {
                "id": "Vin",
                "displayName": "Vin",
                "spiceType": "V",
                "model": null,
                "parametersOrValue": "dc 100m",
                "source": "Vin in 0 dc 100m",
                "pins": [
                  {
                    "id": "p",
                    "net": "in"
                  },
                  {
                    "id": "n",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              },
              {
                "id": "Xdut",
                "displayName": "Xdut",
                "spiceType": "X",
                "model": "trimtri",
                "parametersOrValue": "",
                "source": "Xdut in out code 0 trimtri",
                "pins": [
                  {
                    "id": "in",
                    "net": "in"
                  },
                  {
                    "id": "out",
                    "net": "out"
                  },
                  {
                    "id": "code",
                    "net": "code"
                  },
                  {
                    "id": "vss",
                    "net": "0"
                  }
                ],
                "pinMeaning": "Declared .subckt port order",
                "subcircuit": "subckt/trimtri"
              },
              {
                "id": "Vcode",
                "displayName": "Vcode",
                "spiceType": "V",
                "model": null,
                "parametersOrValue": "dc 0",
                "source": "Vcode code 0 dc 0",
                "pins": [
                  {
                    "id": "p",
                    "net": "code"
                  },
                  {
                    "id": "n",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              }
            ],
            "nets": [
              {
                "id": "vdd",
                "ground": false,
                "terminals": [
                  {
                    "device": "Vdd",
                    "pin": "p"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "0",
                "ground": true,
                "terminals": [
                  {
                    "device": "Vdd",
                    "pin": "n"
                  },
                  {
                    "device": "Vin",
                    "pin": "n"
                  },
                  {
                    "device": "Xdut",
                    "pin": "vss"
                  },
                  {
                    "device": "Vcode",
                    "pin": "n"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "in",
                "ground": false,
                "terminals": [
                  {
                    "device": "Vin",
                    "pin": "p"
                  },
                  {
                    "device": "Xdut",
                    "pin": "in"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "out",
                "ground": false,
                "terminals": [
                  {
                    "device": "Xdut",
                    "pin": "out"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "code",
                "ground": false,
                "terminals": [
                  {
                    "device": "Xdut",
                    "pin": "code"
                  },
                  {
                    "device": "Vcode",
                    "pin": "p"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              }
            ]
          },
          {
            "id": "subckt/trimtri",
            "name": "trimtri",
            "ports": [
              {
                "name": "in",
                "net": "in"
              },
              {
                "name": "out",
                "net": "out"
              },
              {
                "name": "code",
                "net": "code"
              },
              {
                "name": "vss",
                "net": "vss"
              }
            ],
            "definitions": [],
            "devices": [
              {
                "id": "XR1",
                "displayName": "R1",
                "spiceType": "X",
                "model": "rppd",
                "parametersOrValue": "w=0.5u l=35.17u",
                "source": "XR1 in out vss rppd w=0.5u l=35.17u",
                "pins": [
                  {
                    "id": "p",
                    "net": "in"
                  },
                  {
                    "id": "n",
                    "net": "out"
                  },
                  {
                    "id": "substrate",
                    "net": "vss"
                  }
                ],
                "pinMeaning": "IHP resistor model terminal order"
              },
              {
                "id": "XM1",
                "displayName": "M1",
                "spiceType": "X",
                "model": "sg13_lv_nmos",
                "parametersOrValue": "w=2u l=4u ng=1 m=1",
                "source": "XM1 out code vss vss sg13_lv_nmos w=2u l=4u ng=1 m=1",
                "pins": [
                  {
                    "id": "d",
                    "net": "out"
                  },
                  {
                    "id": "g",
                    "net": "code"
                  },
                  {
                    "id": "s",
                    "net": "vss"
                  },
                  {
                    "id": "b",
                    "net": "vss"
                  }
                ],
                "pinMeaning": "MOS drain, gate, source, bulk"
              }
            ],
            "nets": [
              {
                "id": "in",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR1",
                    "pin": "p"
                  }
                ],
                "ports": [
                  "in"
                ],
                "voltageReferences": []
              },
              {
                "id": "out",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR1",
                    "pin": "n"
                  },
                  {
                    "device": "XM1",
                    "pin": "d"
                  }
                ],
                "ports": [
                  "out"
                ],
                "voltageReferences": []
              },
              {
                "id": "vss",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR1",
                    "pin": "substrate"
                  },
                  {
                    "device": "XM1",
                    "pin": "s"
                  },
                  {
                    "device": "XM1",
                    "pin": "b"
                  }
                ],
                "ports": [
                  "vss"
                ],
                "voltageReferences": []
              },
              {
                "id": "code",
                "ground": false,
                "terminals": [
                  {
                    "device": "XM1",
                    "pin": "g"
                  }
                ],
                "ports": [
                  "code"
                ],
                "voltageReferences": []
              }
            ]
          }
        ],
        "uninstantiatedDefinitions": [],
        "dut": {
          "kind": "subcircuit-instance",
          "scope": "top",
          "device": "Xdut",
          "definition": "subckt/trimtri"
        }
      },
      {
        "id": "graph-3",
        "kind": "functional-graph",
        "classification": "heuristic-device-grouping",
        "electricalScope": "dut",
        "boundary": "Automatic device-role grouping and shared-net hyperedges, not a verified behavioral signal-flow model. Shared nets do not establish direction, gain or causality; power nets are omitted here but retained in electrical connectivity. Any inferredStages values are transistor-depth hints, not gain-stage counts. The SVG shows device groups and net labels, or a separately authored functional diagram.",
        "nodes": [
          {
            "id": "block-1",
            "label": "The divider's top leg",
            "devices": [
              {
                "scope": "dut",
                "device": "XR1"
              }
            ],
            "inferredStages": [
              1
            ]
          },
          {
            "id": "block-2",
            "label": "The divider's bottom leg: approximately resistive when gate overdrive is large beside the output voltage",
            "devices": [
              {
                "scope": "dut",
                "device": "XM1"
              }
            ],
            "inferredStages": [
              "bias"
            ]
          }
        ],
        "edges": [
          {
            "id": "net-1",
            "net": "out",
            "nodes": [
              "block-1",
              "block-2"
            ],
            "direction": "undirected-shared-net"
          }
        ],
        "ports": [
          {
            "name": "in",
            "net": "in",
            "kind": "input"
          },
          {
            "name": "out",
            "net": "out",
            "kind": "output"
          },
          {
            "name": "code",
            "net": "code",
            "kind": "bias"
          },
          {
            "name": "vss",
            "net": "vss",
            "kind": "ground"
          }
        ],
        "coverage": "Every root DUT device belongs to one group; hierarchical instances refer to electrical child scopes."
      },
      {
        "id": "graph-4",
        "kind": "electrical-connectivity",
        "boundary": "Device pins and net incidence from the generated SPICE deck, including ideal bench elements. PDK/model internals are referenced, not expanded. This is not layout, extraction, DRC/LVS or silicon evidence.",
        "root": "top",
        "globalDefinitions": [
          ".param VDD=1.2"
        ],
        "scopes": [
          {
            "id": "top",
            "name": "top",
            "ports": [],
            "definitions": [
              ".param VDD=1.2"
            ],
            "devices": [
              {
                "id": "Vdd",
                "displayName": "Vdd",
                "spiceType": "V",
                "model": null,
                "parametersOrValue": "dc {VDD}",
                "source": "Vdd vdd 0 dc {VDD}",
                "pins": [
                  {
                    "id": "p",
                    "net": "vdd"
                  },
                  {
                    "id": "n",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              },
              {
                "id": "Vin",
                "displayName": "Vin",
                "spiceType": "V",
                "model": null,
                "parametersOrValue": "dc 100m",
                "source": "Vin in 0 dc 100m",
                "pins": [
                  {
                    "id": "p",
                    "net": "in"
                  },
                  {
                    "id": "n",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              },
              {
                "id": "Xdut",
                "displayName": "Xdut",
                "spiceType": "X",
                "model": "trimtri",
                "parametersOrValue": "",
                "source": "Xdut in out code 0 trimtri",
                "pins": [
                  {
                    "id": "in",
                    "net": "in"
                  },
                  {
                    "id": "out",
                    "net": "out"
                  },
                  {
                    "id": "code",
                    "net": "code"
                  },
                  {
                    "id": "vss",
                    "net": "0"
                  }
                ],
                "pinMeaning": "Declared .subckt port order",
                "subcircuit": "subckt/trimtri"
              },
              {
                "id": "Vcode",
                "displayName": "Vcode",
                "spiceType": "V",
                "model": null,
                "parametersOrValue": "dc 0.6000",
                "source": "Vcode code 0 dc 0.6000",
                "pins": [
                  {
                    "id": "p",
                    "net": "code"
                  },
                  {
                    "id": "n",
                    "net": "0"
                  }
                ],
                "pinMeaning": "SPICE primitive terminal order"
              }
            ],
            "nets": [
              {
                "id": "vdd",
                "ground": false,
                "terminals": [
                  {
                    "device": "Vdd",
                    "pin": "p"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "0",
                "ground": true,
                "terminals": [
                  {
                    "device": "Vdd",
                    "pin": "n"
                  },
                  {
                    "device": "Vin",
                    "pin": "n"
                  },
                  {
                    "device": "Xdut",
                    "pin": "vss"
                  },
                  {
                    "device": "Vcode",
                    "pin": "n"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "in",
                "ground": false,
                "terminals": [
                  {
                    "device": "Vin",
                    "pin": "p"
                  },
                  {
                    "device": "Xdut",
                    "pin": "in"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "out",
                "ground": false,
                "terminals": [
                  {
                    "device": "Xdut",
                    "pin": "out"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              },
              {
                "id": "code",
                "ground": false,
                "terminals": [
                  {
                    "device": "Xdut",
                    "pin": "code"
                  },
                  {
                    "device": "Vcode",
                    "pin": "p"
                  }
                ],
                "ports": [],
                "voltageReferences": []
              }
            ]
          },
          {
            "id": "subckt/trimtri",
            "name": "trimtri",
            "ports": [
              {
                "name": "in",
                "net": "in"
              },
              {
                "name": "out",
                "net": "out"
              },
              {
                "name": "code",
                "net": "code"
              },
              {
                "name": "vss",
                "net": "vss"
              }
            ],
            "definitions": [],
            "devices": [
              {
                "id": "XR1",
                "displayName": "R1",
                "spiceType": "X",
                "model": "rppd",
                "parametersOrValue": "w=0.5u l=35.17u",
                "source": "XR1 in out vss rppd w=0.5u l=35.17u",
                "pins": [
                  {
                    "id": "p",
                    "net": "in"
                  },
                  {
                    "id": "n",
                    "net": "out"
                  },
                  {
                    "id": "substrate",
                    "net": "vss"
                  }
                ],
                "pinMeaning": "IHP resistor model terminal order"
              },
              {
                "id": "XM1",
                "displayName": "M1",
                "spiceType": "X",
                "model": "sg13_lv_nmos",
                "parametersOrValue": "w=2u l=4u ng=1 m=1",
                "source": "XM1 out code vss vss sg13_lv_nmos w=2u l=4u ng=1 m=1",
                "pins": [
                  {
                    "id": "d",
                    "net": "out"
                  },
                  {
                    "id": "g",
                    "net": "code"
                  },
                  {
                    "id": "s",
                    "net": "vss"
                  },
                  {
                    "id": "b",
                    "net": "vss"
                  }
                ],
                "pinMeaning": "MOS drain, gate, source, bulk"
              }
            ],
            "nets": [
              {
                "id": "in",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR1",
                    "pin": "p"
                  }
                ],
                "ports": [
                  "in"
                ],
                "voltageReferences": []
              },
              {
                "id": "out",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR1",
                    "pin": "n"
                  },
                  {
                    "device": "XM1",
                    "pin": "d"
                  }
                ],
                "ports": [
                  "out"
                ],
                "voltageReferences": []
              },
              {
                "id": "vss",
                "ground": false,
                "terminals": [
                  {
                    "device": "XR1",
                    "pin": "substrate"
                  },
                  {
                    "device": "XM1",
                    "pin": "s"
                  },
                  {
                    "device": "XM1",
                    "pin": "b"
                  }
                ],
                "ports": [
                  "vss"
                ],
                "voltageReferences": []
              },
              {
                "id": "code",
                "ground": false,
                "terminals": [
                  {
                    "device": "XM1",
                    "pin": "g"
                  }
                ],
                "ports": [
                  "code"
                ],
                "voltageReferences": []
              }
            ]
          }
        ],
        "uninstantiatedDefinitions": [],
        "dut": {
          "kind": "subcircuit-instance",
          "scope": "top",
          "device": "Xdut",
          "definition": "subckt/trimtri"
        }
      }
    ],
    "views": [
      {
        "bench": "transfer",
        "source": {
          "recordField": "testbenches",
          "id": "transfer",
          "field": "netlist"
        },
        "schematic": {
          "graph": "graph-1",
          "svg": {
            "url": "/circuits/trim-triode/transfer-schematic.svg",
            "asset": "transfer-schematic.svg"
          },
          "drawingCheck": {
            "method": "checkSchematic",
            "problems": []
          },
          "sheets": [
            {
              "name": "MOS-triode trim attenuator",
              "instances": []
            }
          ]
        },
        "benchDiagram": {
          "graph": "graph-2",
          "svg": {
            "url": "/circuits/trim-triode/transfer-bench.svg",
            "asset": "transfer-bench.svg"
          }
        },
        "blockDiagram": {
          "graph": "graph-3",
          "electricalGraph": "graph-1",
          "svg": {
            "url": "/circuits/trim-triode/transfer-block.svg",
            "asset": "transfer-block.svg"
          }
        }
      },
      {
        "bench": "level",
        "source": {
          "recordField": "testbenches",
          "id": "level",
          "field": "netlist"
        },
        "schematic": {
          "graph": "graph-1",
          "svg": {
            "url": "/circuits/trim-triode/transfer-schematic.svg",
            "asset": "transfer-schematic.svg"
          },
          "drawingCheck": {
            "method": "checkSchematic",
            "problems": []
          },
          "sheets": [
            {
              "name": "MOS-triode trim attenuator",
              "instances": []
            }
          ]
        },
        "benchDiagram": {
          "graph": "graph-4",
          "svg": {
            "url": "/circuits/trim-triode/level-bench.svg",
            "asset": "level-bench.svg"
          }
        },
        "blockDiagram": {
          "graph": "graph-3",
          "electricalGraph": "graph-1",
          "svg": {
            "url": "/circuits/trim-triode/transfer-block.svg",
            "asset": "transfer-block.svg"
          }
        }
      },
      {
        "bench": "temp",
        "source": {
          "recordField": "testbenches",
          "id": "temp",
          "field": "netlist"
        },
        "schematic": {
          "graph": "graph-1",
          "svg": {
            "url": "/circuits/trim-triode/transfer-schematic.svg",
            "asset": "transfer-schematic.svg"
          },
          "drawingCheck": {
            "method": "checkSchematic",
            "problems": []
          },
          "sheets": [
            {
              "name": "MOS-triode trim attenuator",
              "instances": []
            }
          ]
        },
        "benchDiagram": {
          "graph": "graph-4",
          "svg": {
            "url": "/circuits/trim-triode/level-bench.svg",
            "asset": "level-bench.svg"
          }
        },
        "blockDiagram": {
          "graph": "graph-3",
          "electricalGraph": "graph-1",
          "svg": {
            "url": "/circuits/trim-triode/transfer-block.svg",
            "asset": "transfer-block.svg"
          }
        }
      }
    ]
  }
}
